Early pre-charge enable for peak power applications in net-zero energy devices

Abstract

Systems, apparatuses, and methods can provide early pre-charge for peak power events. By pre-charging a supercapacitor just prior to initiating a system wake-up according to a qualified system wake-up source trigger, application performance can be improved. Additionally, pre-charge of the supercapacitor can be controlled by a time-limited pre-charge period and can also be controlled by a predetermined threshold voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. nonprovisional patent application No. 15 / 682,724, filed August 22, 2017. Technical Field

[0003] In summary, the embodiments relate to power management for computing loads. More specifically, the embodiments relate to providing power management for net-zero energy (NZE) computing devices that require higher peak power during certain operations. Background Technology

[0004] For example, low-power computing solutions for NZE harvesting devices may heavily rely on the efficient use of available power. These devices can power the entire system using energy harvested from a variety of sources. In most cases, where there is a large difference between average and peak (short-term) power consumption, energy harvesting and system batteries may not be able to meet peak power requirements (e.g., due to battery chemistry and harvesting capacity), and therefore technologies such as supercapacitors (e.g., "supercapacitors") may be employed.

[0005] Supercapacitors can be connected in parallel with batteries to maintain the system's additional (e.g., peak) instantaneous charge. Traditionally, supercapacitors can be directly connected to the charging circuit, which can reduce the system's energy efficiency due to the leakage characteristics of supercapacitors. A straightforward option is to nominally discharge the supercapacitor and precharge it only for a very short time before implementing peak power depletion. This "timely" precharging of the supercapacitor while the NZE system is active can also lead to inefficiency in energy management (e.g., many circuits are powered on only while waiting for the supercapacitor to charge). Furthermore, connecting a supercapacitor in parallel with a battery means that the supercapacitor is used as a decoupling capacitor rather than for energy storage. For example, if the battery's open-circuit voltage is 3.2V, a nominally rated supercapacitor can only be charged to 3.2V and used to reduce the impedance provided by the battery. Attached Figure Description

[0006] By reading the following specification and appended claims, and referring to the following drawings, the various advantages of the embodiments will become apparent to those skilled in the art.

[0007] Figure 1 This is a block diagram of an example of a power management system according to an embodiment;

[0008] Figure 2 This is a block diagram of another example of a power management system according to an embodiment;

[0009] Figures 3A to 3DThis is a block diagram of an example power management system indicating the charging flow in various operating states according to an embodiment.

[0010] Figure 4A This is a block diagram of the digital logic section of the power management unit according to an embodiment;

[0011] Figure 4B This is a block diagram of the contents of the control and status registers used within the digital logic section of the power management unit according to an embodiment;

[0012] Figure 5 This is a flowchart illustrating the operation of the power management unit according to an example embodiment; and

[0013] Figure 6 This is an illustration of an example computing system according to an embodiment. Detailed Implementation

[0014] The techniques described herein can address the problem of timely supercapacitor pre-charging, which is constrained to minimize power consumption during pre-charging and to maximize supercapacitor efficiency or equivalently minimize supercapacitor size (e.g., charging the supercapacitor to its full nominal rated voltage).

[0015] Zero Net Energy (NZE) systems can remain in the lowest power state for as long as possible. Therefore, the transition from sleep to active state only occurs when sufficient charge is stored to perform the required task immediately upon wake-up (e.g., without waiting for the supercapacitor to charge). To effectively support the large difference between peak and average power consumption in NZE systems, the proposed IP is based on a two-fold principle: First, the supercapacitor is charged to its maximum terminal voltage (if needed), minimizing the supercapacitor size required for a given peak output energy and minimizing the charging time for the required peak energy. Second, a two-stage wake-up process can be used for supercapacitor pre-charging, where the first stage corresponds to a wake-up condition that is asynchronously activated and determined by the battery charging level, and the second stage handles timely supercapacitor pre-charging (e.g., temporarily connecting the supercapacitor to the charger while delaying wake-up until before the supercapacitor is fully charged).

[0016] The above process allows for timely pre-charging of the supercapacitor during sleep mode and immediately before transitioning to an active state. The proposed supercapacitor pre-charging can be controlled by a planned pre-charging period (e.g., adjusted for the number of recharges under worst-case conditions) or a charging state monitoring threshold (e.g., adjusted for specific charging requirements), in such a way that peak power requirements are met while maintaining a minimum power consumption state for most of the system cycle. The system's peak power requirements, the wake-up conditions for each software task expected to run during peak power events, and an estimate of the worst-case time required to charge the supercapacitor to the level required for planned control can be used to implement pre-charging control. Using this information, the power management unit (PMU) can configure the supercapacitor pre-charging level or the supercapacitor pre-charging period to control the amount of energy stored in the supercapacitor for use during peak power events.

[0017] Go to Figure 1 According to a block diagram of an example power management unit of an embodiment, PMU 101 provides electrical power to system 102 by selectively connecting a power source such as battery 103 in parallel with supercapacitor 104. PMU 101 includes analog control circuitry 110 and digital control circuitry 111 to selectively connect battery 103 and supercapacitor 104 to system 102 as needed. Analog control circuitry 110 and digital control circuitry 111 work together to charge supercapacitor 104 at appropriate times to allow supercapacitor 104 to provide additional charge to system 102 during periods of higher power demand. As described above, supercapacitor 104 can be utilized most efficiently if it is pre-charged before use to prevent wasted charge in the form of leakage current through supercapacitor 104. The terms analog control circuitry and digital control circuitry are used herein to distinguish them from each other and not to limit their meaning in any other way as described herein, wherein the terminology is based on the programmable features of digital control circuitry 111. All features and uses of these terms herein are described as their meaning as will be interpreted with respect to any embodiment.

[0018] Figure 2This is a block diagram of an example of analog control circuitry within a power management unit according to an embodiment. Analog control circuitry 110 includes a dual-input DC / DC converter 201, a three-input DC / DC converter 202, a power harvesting source 203 coupled to both the dual-input DC / DC converter 201 and the three-input DC / DC converter 202, a rechargeable battery 212 coupled to the dual-input DC / DC converter 201, a supercapacitor 211 coupled to both the dual-input DC / DC converter 201 and the three-input DC / DC converter 202, and a pair of control signals: a pre-charge enable signal 221 and a low-power state signal 222, which are coupled to both the dual-input DC / DC converter 201 and the three-input DC / DC converter 202. The two control signals 221 and 222 determine the operating modes of the dual-input DC / DC converter 201 and the three-input DC / DC converter 202 during operation. Each of these operating modes is described below in relation to... Figures 3A to 3D To describe in more detail.

[0019] In all these example modes, supercapacitor 211 is shown adjacent to both the dual-input DC / DC converter 201 and the three-input DC / DC converter 202. In reality, supercapacitor 211 is a single device, but it is shown here as two devices for convenience. When supercapacitor 211 is coupled to either of the converters 201 and 202, it is shown as coupled via a solid connecting wire. When supercapacitor 211 is not electrically coupled to either converter, the connection is shown as being disconnected as a disconnect switch. Although disconnection can be shown as a switch for illustrative purposes, disconnection is a logical construct in which supercapacitor 211 is both electrically coupled and electrically decoupled from both converters 201 and 202. The operation of the coupling mechanism for connecting and disconnecting supercapacitor 211 to converters 210 and 202 is controlled by a precharge enable signal 221 and a low-power state signal 222.

[0020] The power harvesting device 203 may include a photovoltaic cell whose terminal voltage is smoothed by using a capacitor regulated to its nominal maximum power point, or a thermoelectric generator with a similar capacitor, or any such energy harvesting device that provides a maximum power output typically much less than the system's likely requirements under high load conditions, but greater than the system's consumption during sleep. In all these modes, the battery 212 provides power at its rated terminal voltage, which can be in the range of 2.7 to 4.2 volts, for example, for the lithium-ion chemistry in a typical embodiment, where the lower limit of 2.7 volts ensures that it remains adequately charged and operates safely.

[0021] Figures 3A to 3D This is a block diagram illustrating exemplary operation of the analog control circuit within the PMU power management system according to an embodiment, indicating the charging current in various operating states. Figure 3A The diagram illustrates the operation of analog control circuitry 110 in a sleep / low power mode, during which power is being harvested from battery 212. During non-precharge sleep / low power mode, battery 212 is being charged from harvested power source 203, and system 102 is provided with sufficient power to maintain operation in sleep mode. This low power mode typically corresponds to a situation where the system uses only average power consumption (i.e., not peak power consumption) upon wake-up.

[0022] In sleep / low power mode, in this embodiment, the precharge enable signal 221 can be set to 0, and the low power state signal 222 can be set to 1. A dual-input DC / DC converter 201 is electrically coupled to the power harvester 203 to receive power 301 that can be transferred to the battery 212 as power 302. A three-input DC / DC converter 202 is electrically coupled to the battery 212 to receive power 303 that is transferred to the system 102 as power 304. In most cases, the power 302 flowing from the dual-input DC / DC converter 201 to the battery 212 is typically greater than the power 303 flowing from the battery 212 to the three-input DC / DC converter 202 because the power consumption of the system 102 is minimal during sleep / low power mode, so it is expected that the battery 212 is charging rather than discharging.

[0023] In this mode, neither the dual-input DC / DC converter 201 nor the triple-input DC / DC converter 202 is electrically coupled to the supercapacitor 211. The triple-input DC / DC converter 202 may or may not receive charge from the power source 203. Power 301 from the power source 203 is supplied by the dual-input DC / DC converter 201 to the connection between the battery 212 and the triple-input DC / DC converter 202. If the power 303 consumed by the triple-input DC / DC converter 202 is less than the power 302 supplied by the dual-input DC / DC converter 201, the battery 212 may be charging. If the power 303 consumed by the triple-input DC / DC converter 202 is greater than the power 302 supplied by the dual-input DC / DC converter 201, the battery 212 can provide the required additional power.

[0024] Figure 3B An analog control circuit 110 is shown operating in a low-power demand mode of a non-precharged active system. During this mode, battery 212 provides power 303 to three-input DC / DC converter 202, power harvester 203 also provides power 311 to the three-input DC / DC converter 202, and system 102 is supplied with sufficient power 304 by the three-input DC / DC converter 202 to maintain operation in the active low-power state. In contrast to peak power consumption, this mode supports system 102 during average power consumption, thus eliminating the need for precharging of the supercapacitor in response to wake-up events.

[0025] In this embodiment, in the non-precharge activity mode, the precharge enable signal 221 can be set to 0, and the low power state signal 222 can be set to 0. The three-input DC / DC converter 202 is electrically coupled to the battery 212 to receive power 303, and simultaneously electrically coupled to the power harvester 203 to receive power 311. The received power is transmitted to the system 102 as power source 304.

[0026] In this mode, neither the dual-input DC / DC converter 201 nor the three-input DC / DC converter 202 is electrically coupled to the supercapacitor 211. The three-input DC / DC converter 202 can also receive charge from the harvested power source 203. Although not shown, the dual-input DC / DC converter 201 can also receive power from the harvested power source 203. If the availability of the harvested power source 203 is periodically out of sync with the system energy demand, the harvested power source 203 will first supply power to the battery 212, from which the system 102 can draw power 303.

[0027] Figure 3C An analog control circuit 110 is shown operating in a pre-charge sleep / low power mode, which pre-charges the supercapacitor from the harvested power source 203 and the battery 212. In this embodiment, in the pre-charge sleep / low power mode, a pre-charge enable signal 221 can be set to 1, and a low power state signal 222 can be set to 1. A dual-input DC / DC converter 201 is electrically coupled to the harvested power source 203 to receive power 301 that can be transferred as power 322 to pre-charge the supercapacitor 211. The battery 212 is also electrically coupled to the dual-input DC / DC converter 201 to provide power 321 that can also be transferred as power 322 to pre-charge the supercapacitor 211. A three-input DC / DC converter 202 is electrically coupled to the battery 212 to receive power 303 that is transferred as power 304 to the system 102 to support the system 102 in its sleep mode.

[0028] Power 322 accumulates on supercapacitor 211 to its terminal voltage in order to provide as much charge as possible to system 102 during its active peak power mode. In this particular embodiment, the supercapacitor voltage is ΔV ≈ 0 to 5 volts.

[0029] Figure 3D An analog control circuit 110 operating in a pre-charged active peak power mode is shown. In this embodiment, in this pre-charged active peak power mode, the pre-charge enable signal 221 can be set to 1, and the low power state signal 222 can be set to 0. This pre-charged active peak power mode supports the system when peak power consumption occurs, so the supercapacitor is pre-charged to provide additional power after wake-up.

[0030] A dual-input DC / DC converter 201 is electrically coupled to a power source 203 to receive power 301 that can be transferred to a battery 212 as power 302. A three-input DC / DC converter 202 is electrically coupled to a battery 212 to receive power 303, electrically coupled to a supercapacitor 211 to receive power 303, and the power source 203 is electrically coupled to the three-input DC / DC converter 202 to provide power 311 to the three-input DC / DC converter 202. All of this power is transferred to the system 102 as power source 304.

[0031] although Figure 3D As described above, if the power source 203 can support two connections, it can simultaneously power both the battery 212 and the three-input DC / DC converter 202, which is also powered by the battery 212 and the supercapacitor 211. Alternatively, in an alternative embodiment, the power source 203 can supply power only to the battery 212, while the three-input DC / DC converter 202 is powered only by the battery 212 and the supercapacitor 211.

[0032] In this mode, all power supplies are not electrically coupled to the dual-input DC / DC converter 201. The supercapacitor 211 is also not electrically coupled to the dual-input DC / DC converter 201. In this particular embodiment, the supercapacitor voltage is ΔV ≈ 5 to 0 volts. In this mode, the maximum power output is Max... powerOut ≈Max powerIn +C super *V super 2 / Time maxload .

[0033] Figure 4A This is a block diagram of the digital logic section of the PMU according to an embodiment. Figure 4A The digital control circuit 111 of the PMU 101 shown generates the necessary PMU 101 control signals 434 to determine the current state of the PMU 101 or the mode as described above. The wake-up process of the system 102 typically occurs when a qualified system wake-up (QSW) trigger signal 436QSW0-QSW is triggered. nOne of these typically begins when an interrupt or external event explicitly identifies it. The QSW signal 436 corresponds to a signal known to system 102 and associated with one or more startup event procedures configured within the power management unit 101. The QSW signal 436 is typically mapped to entries within the PMU Control and Status Register (CSR) 401, where the power requirements of system 102 upon wake-up are known, and the corresponding power mode is defined in the CSR entries. Each entry within the PMU CSR 401 contains precharge enable indicators 450-451, configuration signals 432 based on CSR values ​​470-471, and precharge mode indicators 433 based on CSR values ​​460-461. The functions of these values ​​are referenced below. Figure 4B To describe in more detail.

[0034] Each QSW signal 436 is conditionally included / excluded from the supercapacitor precharge logic by precharge enable indicators 450-451 in their respective entries in PMU CSR 401. The QSW signals 436 included in the supercapacitor precharge logic should be those QSW signals 436 representing system wake-up conditions requiring peak power consumption after wake-up. Conditional inclusion / exclusion is performed using AND gates 426 and 427 as logic combinations. The set of all QSW signals included in the supercapacitor precharge logic uses selection logic 413 and 414 to control the generation of mode signal 433 and configuration signal 432, respectively.

[0035] The set of all QSW signals included in the supercapacitor precharge logic 440 is combined in an OR gate 424, which generates a planned precharge wake-up enable signal 437 whenever one or more QSW signals 436 signalably indicate that supercapacitor precharge is required before the system wakes up. A simple wake-up event signal 441 is created using an OR gate 423, which combines all QSW signals 436 regardless of whether they are included in the supercapacitor precharge logic. This simple wake-up event signal 441 provides indication each time at least one explicitly defined qualifying wake-up condition 436 exists (i.e., each time the system needs to wake up, regardless of whether supercapacitor precharge is present), and this simple wake-up event signal 441 is input to one of the two inputs of a multiplexer 422.

[0036] The precharge wake-up event signal 442 is the second input of multiplexer 422. The precharge wake-up event signal 442 is generated by a second multiplexer 421, which is controlled by mode selection logic 413 based on a mode signal 433 generated from an entry from PMU CSR 401. The second multiplexer 421 uses the planned precharge completion signal 443, which is the output of the precharge scheduler 403, as one of its inputs. The second multiplexer 421 uses the monitored precharge completion signal 444, which is the output of comparator 411, as its second input. Depending on the value of the mode signal 433, the second input of multiplexer 422 corresponds to either the planned precharge completion signal 443 or the monitored precharge completion signal 444.

[0037] Comparator 411 receives a supercapacitor state-of-charge (SC-SOC) signal 431 as one input and a configuration signal 432 generated by configuration selection logic 414 according to entries in PMU CSR 401 as a second input. The SC-SOC signal 431 corresponds to a signal indicating the current voltage level of the supercapacitor. Thus, the configuration signal 432 can be used to define a voltage value (threshold) such that the comparator generates a signal when the SC-SOC signal 431 is greater than the voltage defined by the configuration signal 432. When the SC-SOC threshold is met, comparator 411 generates a monitoring pre-charge completion signal 445.

[0038] The precharge scheduler 403 is a logic block that accepts configuration signal 432 as input. The precharge scheduler 403 uses the multi-bit configuration signal as a count value for a counter device within itself, which determines the precharge period for the supercapacitor 211. Thus, both inputs to the second multiplexer 421 indicate when the supercapacitor 211 has been precharged to a predetermined voltage level defined by the measured precharge level or the precharge period.

[0039] When the digital control circuit 111 is in the precharge enabled state, the output of the multiplexer 422, identified as the PMU wake-up event signal 446, is passed to the PMU finite state machine 402. The planned precharge trigger signal 437 is defined by the output of AND gate 425, which is a logical AND of the precharge enable indicator (PCEI) signal 438 generated by OR gate 424 and the low power state indicator (LPSI) signal 435 from the sleep state logic 412. The LPSI signal 435 indicates that the system 102 is currently in sleep mode. The PCEI signal 438 indicates the presence of at least one explicitly defined QSW signal 436, which requests precharging with the supercapacitor 211 before system wake-up.

[0040] LPSI signal 435 also identifies a sleep mode, during which pre-charging activity occurs, allowing the pre-charged supercapacitor 211 to provide additional power to system 102 when peak power activity occurs upon wake-up. Since LPSI signal 435 serves as the interface between digital control circuitry 111 and analog control circuitry 110, LPSI signal 435 is also... Figure 1 The analog circuit 110 is used.

[0041] Using the logic described above, when system 102 is in a sleep mode as indicated by the LPSI signal 435 (requiring pre-charging of the supercapacitor before system wake-up) and at least one explicitly defined QSW signal 436, the planned pre-charge trigger signal 437 is active. The planned pre-charge trigger signal 437 is also passed to the pre-charge scheduler 403 to indicate whether its counter should operate to count down the pre-charge period. The PCEI signal 438 can also be used in analog circuit control 110 to indicate the status of the converter used to charge the supercapacitor 211.

[0042] The PMU finite state machine 402 uses the PMU control signal 434 to control the state of the system 102. The PMU finite state machine 402 can generate the PCEI signal 438 and the LPSI signal 435. These two signals are used to set the PMU 101 to the above state. Figure 3A To one of the four operational states defined in Figure 4D. These four modes correspond to... Figure 3A Non-precharge sleep / low power mode Figure 3B Non-precharged activity system low power requirement mode, Figure 3C Precharge sleep / low power mode and Figure 3D The pre-charged active peak power mode. The PMU finite state machine 402 provides input to the sleep state logic 412 for generating its LPSI signal 435.

[0043] Figure 4B This is a block diagram of the contents of the control registers within the digital logic section of the power management unit according to an embodiment. The PMU CSR 401 includes controls for each wake-up source WSO-WS. n The three sets of values. The first set of control register values ​​corresponds to those used for WS0-WS0. n The precharge enable signals 450-451. These precharge enable signals are typically single-valued and indicate whether a specific QSW signal 436 utilizes the precharge sequence of the supercapacitor 211, which provides additional charging during peak power events. The second set of control register values ​​corresponds to those used for WS0-WS0. n The pre-charge mode signal is 460-461.

[0044] The precharge mode signal is typically a unit value, indicating whether a specific QSW signal 436 utilizes a time-based or threshold-based precharge sequence of the supercapacitor 211 to provide additional charging during peak power events. The third set of control register values ​​corresponds to WS0-WS0. n The precharge configuration signals 470-471 are used. These precharge configuration signals are typically multi-bit values ​​indicating the time period or voltage threshold value to be used in the precharge of the supercapacitor 211. These signal values ​​are used within the digital control circuitry 111 of the PMU 101 as described above. The signals can be represented as single-bit or multi-bit values ​​as needed. As described above, the PMU CSR 401 can be represented by a memory block addressed by the qualified wake-up source ID 436. The memory can be non-volatile or read-write memory to allow dynamic configuration of the wake-up sequence for a given qualified wake-up source.

[0045] Figure 5 This is a flowchart of the operation of the power management unit according to an example embodiment. The process begins at 501, and block 510 receives the QSW source trigger signal. As described above, a qualified wake-up source indicates that the source of the trigger signal is authorized to wake up system 102. Decision block 511 uses the corresponding entry in PMU CSR 401, which indicates whether pre-charging of the supercapacitor is required, to determine whether pre-charging of the supercapacitor 211 is needed. If pre-charging of the supercapacitor 211 is not needed, the process proceeds to processing block 516 to initiate the wake-up of system 102. If decision block 511 determines that pre-charging supercapacitor mode will be used, the process continues to decision block 512.

[0046] Decision block 512 determines whether the trigger signal is triggered using the charging time precharge mode or the voltage threshold precharge mode. If decision block 512 determines that the charging time precharge mode will be used, execution block 514 loads the value from the selected configuration signal 432 into a timer within the precharge scheduler 403 to define how long the charging period should be used to charge the supercapacitor 211. Processing continues to decision block 515. If decision block 512 determines that the charging time precharge mode will not be used, processing block 513 loads the value from the selected configuration signal 432 into a comparator within comparator 411 to define how the threshold voltage should be used to charge the supercapacitor 211. Processing also continues to decision block 515.

[0047] Decision block 515 determines whether supercapacitor 211 has been precharged to a specified voltage. If the precharge mode is a charging time precharge mode, decision block 515 determines whether the timer has expired. If not, decision block 515 waits. Similarly, if the precharge mode is a threshold precharge mode, decision block 515 determines whether the current voltage of supercapacitor 211 exceeds the threshold. If not, decision block 515 waits. Once the precharge condition is met, processing block 516 initiates a wake-up sequence and uses supercapacitor 211 to provide additional charging to system 102 to meet the needs during peak power mode. Once a wake-up occurs, the precharge process ends.

[0048] Figure 6 A computing system 86 is illustrated. The computing system 86 may be part of an electronic device / platform having computing functions (e.g., personal digital assistant / PDA, laptop computer, tablet computer, convertible tablet, server, HPC system), communication functions (e.g., wireless smartphone), imaging functions, media playback functions (e.g., smart TV / TV), wearable functions (e.g., watch, glasses, headwear, footwear, jewelry), vehicle functions (e.g., car, truck, motorcycle), etc., or any combination thereof. In the illustrated example, system 86 includes a processor 88 having multiple cores 90 to execute applications and an integrated memory controller (IMC) 92 capable of communicating with system memory 94. System memory 94 may include, for example, dynamic random access memory (DRAM) configured as one or more storage devices, such as dual in-line memory modules (DIMMs), small-size DIMMs (SODIMMs), etc.

[0049] The system 86 shown also includes an input / output (I / O) device 96, implemented together with a processor 88 on a semiconductor die (not shown) as a system-on-a-chip (SoC). The I / O device 96 acts as a host device and can communicate with devices such as a display 98 (e.g., a touchscreen, liquid crystal display / LCD, light-emitting diode / LED display), a network controller 70, and a mass storage device 77 (e.g., a hard disk drive / HDD, optical disk, flash memory, etc.). The processor 88 shown can execute logic 76 to obtain processor operating status information. Logic 76 can also obtain QSW signal information. Therefore, logic 76 can implement method 500 (…). Figure 5 One or more aspects of ) and may be similar to PMU 101 ( Figure 1 This logic 76 can be implemented elsewhere in system 86. Additionally, display 98 can visually present result information related to the execution of the application.

[0050] Other notes and examples:

[0051] Example 1 may include a system comprising a sleep-enabled electronic device, a supercapacitor coupled to one or more power sources, an always-on power management unit, and an analog peak power control device. The always-on power management unit includes a digital power-on device that includes first logic to receive a qualified system wake-up source trigger, initiate pre-charging of the supercapacitor, and initiate wake-up of the sleep-enabled electronic device when the supercapacitor is pre-charged to a desired charge level. The analog peak power control includes second logic to enable pre-charging of the supercapacitor and connect the supercapacitor to the sleep-enabled electronic device when the digital power-on device initiates wake-up of the sleep-enabled electronic device.

[0052] Example 2 may include the system of Example 1, wherein the second logic precharges the supercapacitor to the terminal voltage.

[0053] Example 3 may include the system of Example 1, wherein the first logic precharges the supercapacitor for a specified amount of time.

[0054] Example 4 may include the system of Example 1, wherein the first logic precharges the supercapacitor until the state of charge of the supercapacitor is greater than a specified voltage.

[0055] Example 5 may include the system of Example 1, wherein a first logic further initiates the wake-up of an electronic device that enables sleep without precharging the supercapacitor, based on a precharge configuration value having an enable indicator for triggering a qualified system wake-up source received.

[0056] Example 6 may include the system of Example 1, wherein the precharge configuration value for a received qualified system wake-up source triggering the system will further include a configuration mode value and a configuration precharge value.

[0057] Example 7 may include the system of Example 1, wherein the first logic receives one or more qualified system wake-up source triggers and maintains a precharge enable configuration value for each of the one or more qualified system wake-up source triggers.

[0058] Example 8 may include an always-on power management device including digital power-on logic, the digital power-on logic including first logic implemented at least in part in one or more of configurable logic or fixed-function hardware logic, wherein the first logic is configured to: receive a qualified system wake-up source trigger, initiate pre-charging of a supercapacitor coupled to one or more low-power sources, and initiate wake-up of an attached sleep-enabled electronic device when the supercapacitor is pre-charged to a desired charge level.

[0059] Example 10 may include the apparatus of Example 9, wherein the digital power-on device is used to precharge the supercapacitor to the terminal voltage.

[0060] Example 11 may include the apparatus of Example 9, wherein the first logic is used to precharge the supercapacitor for a specified amount of time.

[0061] Example 12 may include the apparatus of Example 9, wherein the digital power-on device precharges the supercapacitor until the state of charge of the supercapacitor is greater than a specified voltage.

[0062] Example 13 can be a device of the system of Example 9, wherein the digital power-on device further initiates the wake-up of the sleep-enabled electronic device without precharging the supercapacitor, based on a precharge configuration value having an enable indicator for the received qualified battery.

[0063] Example 14 may be a device of any of the systems in Examples 8 to 13, and the received precharge configuration value triggered by a qualified system wake-up source may also include a configuration mode value and a configuration precharge value.

[0064] Example 15 may include the apparatus of Example 8, wherein the digital power-on device receives one or more qualified system wake-up source triggers and maintains a precharge enable configuration value for each of the one or more qualified system wake-up source triggers.

[0065] Example 16 may include a method that receives a qualified system wake-up source trigger for enabling a sleep-enabled electronic device, initiates precharging of a supercapacitor coupled to one or more low-power supplies, and initiates wake-up of the sleep-enabled electronic device when the supercapacitor is precharged to a predetermined charge level.

[0066] Example 17 may include the method of Example 16, wherein the supercapacitor is precharged to the terminal voltage.

[0067] Example 18 may include the method of Example 16, wherein the supercapacitor is precharged to the terminal voltage.

[0068] Example 19 may include the method of Example 16, wherein the supercapacitor is precharged until the state of charge of the supercapacitor is greater than a specified voltage.

[0069] Example 20 may include the method of Example 16, further comprising: initiating the wake-up of a sleep-enabled electronic device without precharging the supercapacitor based on a precharge configuration value having an enable indicator for triggering a received qualified system wake-up source.

[0070] Example 21 may include the method of any of Examples 16 to 20, wherein the precharge configuration value for the received qualified system wake-up source trigger also includes a configuration mode value and a configuration precharge value.

[0071] Example 22 may include the method of Example 16, wherein a qualified system wake-up source trigger includes one or more qualified system wake-up source triggers, and each of the one or more qualified system wake-up source triggers utilizes a separate precharge enable configuration value.

[0072] Example 23 may include the method of Example 16, wherein the method further includes: connecting the supercapacitor to a sleep-enabled electronic device while the supercapacitor is being precharged.

[0073] Example 24 may include an always-on power management unit for providing additional peak power charging to a power computing device, the power management unit having a module for receiving a qualified system wake-up source trigger for enabling sleep electronic devices, a module for initiating precharging of one or more supercapacitors coupled to a low power supply, and a module for initiating wake-up of the sleep-enabled electronic devices when the supercapacitors are precharged to a predetermined charge level.

[0074] Example 25 may include the always-on power management unit of Example 24, wherein the supercapacitor is pre-charged to the terminal voltage.

[0075] Example 26 may include the always-on power management unit of Example 24, wherein the supercapacitor is pre-charged to the terminal voltage.

[0076] Example 27 may include the always-on power management unit of Example 24, wherein the supercapacitor is pre-charged until the state of charge of the supercapacitor is greater than a specified voltage.

[0077] Example 28 may include the always-on power management unit of Example 24, and further includes: initiating the wake-up of a sleep-enabled electronic device without precharging the supercapacitor based on a precharge configuration value having an enable indicator for triggering a qualified system wake-up source received.

[0078] Example 29 may include the always-on power management unit of Example 28, wherein the precharge configuration value for triggering a qualified system wake-up source received also includes a configuration mode value and a configuration precharge value.

[0079] Example 30 may include the always-on power management unit of Example 24, wherein the qualified system wake-up source triggers include one or more qualified wake-up source triggers, and each of the one or more qualified system wake-up source triggers uses a separate precharge enable configuration value.

[0080] Example 31 may include the always-on power management unit of Example 24, wherein the method further includes connecting the supercapacitor to a sleep-enabled electronic device when the supercapacitor is pre-charged.

[0081] Therefore, the technique described herein can utilize a PMU 101 that collects information not only from the cores but also from the application's performance. When operating in peak power mode, this approach allows the solution to provide additional charge to system 102. Thus, scalability could be significantly improved for future processors with, for example, hundreds of cores.

[0082] The embodiments are applicable to all types of semiconductor integrated circuit (“IC”) chips, examples of which include, but are not limited to, processors, controllers, chipset assemblies, programmable logic arrays (PLAs), memory chips, network chips, system-on-a-chip (SoCs), SSD / NAND controllers (ASICs), etc. Furthermore, in some figures, signal lines are represented by lines. Some lines may differ to represent more component signal paths, some lines may have numerical markings to represent multiple component signal paths, and / or some lines may have arrows at one or more ends to indicate the direction of the primary information flow. However, this should not be construed as limiting. Rather, it can be used in conjunction with one or more exemplary embodiments to facilitate a clearer understanding of the circuit. Any represented signal line, whether or not it carries additional information, can in practice comprise one or more signals that can propagate in multiple directions and can be implemented using any suitable type of signaling scheme, such as digital or analog lines implemented with differential pairs, fiber optic cables, and / or single-ended lines.

[0083] Examples of sizes / models / values / ranges have been given, but the embodiments are not limited thereto. As manufacturing technologies (e.g., photolithography) mature over time, it is expected that smaller devices can be manufactured. Additionally, to simplify the illustrations and discussion, and to avoid obscuring certain aspects of the embodiments, well-known power / ground connections to the IC chip and other components may or may not be shown in the figures. Furthermore, arrangements may be shown in block diagram form to avoid obscuring the embodiments, and also because the details of implementing such block diagram arrangements are highly dependent on the platform in which the embodiment is to be implemented; i.e., such details should be within the capabilities of those skilled in the art. In the context of setting forth specific details (e.g., circuitry) to describe exemplary embodiments, it will be apparent to those skilled in the art that the embodiments can be practiced without these specific details or in variations thereof. Therefore, this description should be considered illustrative rather than restrictive.

[0084] The term “coupled” may be used herein to refer to any type of direct or indirect relationship between the components under discussion, and may be applied to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Additionally, unless otherwise indicated, the terms “first,” “second,” etc., are used herein for ease of discussion only and do not have a specific temporal or chronological meaning.

[0085] From the foregoing description, those skilled in the art will understand that a wide range of techniques can be implemented in various forms. Therefore, although embodiments have been described with reference to specific examples, the true scope of the embodiments should not be so limited, as other modifications will become apparent to those skilled in the art upon examination of the drawings, specification, and appended claims.

Claims

1. A system for providing early pre-charging for peak power events, comprising: Electronic devices that have sleep mode enabled; The always-on power management unit has: A supercapacitor is disposed in an analog peak power control module and coupled to multiple power supplies, the multiple power supplies including at least a first power supply and a second power supply; The digital power-on module, including the first logic, is used for: Receive a qualified system wake-up source trigger; Initiate the pre-charging of the supercapacitor; as well as When the supercapacitor is pre-charged to the desired charge level, the wake-up of the sleep-enabled electronic device is initiated; and The simulated peak power control module includes a second logic for: Enable pre-charging of the supercapacitor; as well as When the digital power-on module initiates the wake-up of the sleep-enabled electronic device, the supercapacitor is connected to the sleep-enabled electronic device. The supercapacitor is selectively coupled to a dual-input DC / DC converter and a three-input DC / DC converter, such that a pre-charge power is obtained in the dual-input DC / DC converter by pre-charging the supercapacitor with power from the first power source and power from the second power source as inputs, and the supercapacitor discharges when the peak power event occurs, so that the pre-charge power, along with the power from the first power source and the power from the second power source, is input to the three-input DC / DC converter. The coupling between the supercapacitor and the dual-input DC / DC converter or the three-input DC / DC converter is controlled by a pair of control signals, including a pre-charge enable signal and a low-power state signal. The pre-charge enable signal and the low-power state signal are combined to define four different coupling-decoupling modes between the supercapacitor and the dual-input DC / DC converter or the three-input DC / DC converter, and the pre-charge is triggered by a logical AND of the pre-charge enable signal and the low-power state signal.

2. The system according to claim 1, wherein, The second logic is used to precharge the supercapacitor to the terminal voltage.

3. The system according to claim 1, wherein, The first logic is used to precharge the supercapacitor for a specified amount of time.

4. The system according to claim 1, wherein, The first logic is used to precharge the supercapacitor until the charging state of the supercapacitor is greater than a specified voltage.

5. The system according to claim 1, wherein, The first logic is used to further initiate the wake-up of the sleep-enabled electronic device without precharging the supercapacitor based on a precharge configuration value, the precharge configuration value having an enable indicator for triggering by a qualified system wake-up source received.

6. The system according to claim 5, wherein, The precharge configuration value used for triggering a qualified system wake-up source also includes a configuration mode value and a configuration precharge value.

7. The system according to claim 1, wherein, The first logic receives one or more qualified system wake-up source triggers and maintains a precharge enable configuration value for each of the one or more qualified system wake-up source triggers.

8. A always-on power management unit for providing early pre-charge in response to peak power events, comprising: A supercapacitor is disposed in an analog peak power control module and coupled to multiple power supplies, the multiple power supplies including at least a first power supply and a second power supply; A digital power-on module includes first logic, implemented at least in part as one or more of configurable logic or fixed-function hardware logic, wherein the first logic is used for: Receive a qualified system wake-up source trigger; Initiating the pre-charging of the supercapacitor; and When the supercapacitor is precharged to the desired charge level, the wake-up of the attached sleep-enabled electronic device is initiated. The unit further includes: The analog peak power control module includes second logic, implemented at least in part as one or more of configurable logic or fixed-function hardware logic, wherein the second logic is used for: Enable pre-charging of the supercapacitor; and When the digital power-on module initiates the wake-up of the sleep-enabled electronic device, the supercapacitor is connected to the sleep-enabled electronic device. The supercapacitor is selectively coupled to a dual-input DC / DC converter and a three-input DC / DC converter, such that a pre-charge power is obtained in the dual-input DC / DC converter by pre-charging the supercapacitor with power from the first power source and power from the second power source as inputs, and the supercapacitor discharges when the peak power event occurs, so that the pre-charge power, along with the power from the first power source and the power from the second power source, is input to the three-input DC / DC converter. The coupling between the supercapacitor and the dual-input DC / DC converter or the three-input DC / DC converter is controlled by a pair of control signals, including a pre-charge enable signal and a low-power state signal. The pre-charge enable signal and the low-power state signal are combined to define four different coupling-decoupling modes between the supercapacitor and the dual-input DC / DC converter or the three-input DC / DC converter, and the pre-charge is triggered by a logical AND of the pre-charge enable signal and the low-power state signal.

9. The unit according to claim 8, wherein, The simulated peak power control module is used to precharge the supercapacitor to the terminal voltage.

10. The unit according to claim 8, wherein, The digital power-on module is used to precharge the supercapacitor for a specified amount of time.

11. The unit according to claim 8, wherein, The digital power-on module is used to pre-charge the supercapacitor until the charging state of the supercapacitor is greater than a specified voltage.

12. The unit according to claim 8, wherein, The digital power-on module is used to further initiate the wake-up of the sleep-enabled electronic device based on a pre-charge configuration value without pre-charging the supercapacitor, the pre-charge configuration value having an enable indicator for triggering by a qualified system wake-up source received.

13. The unit according to claim 12, wherein, The precharge configuration value used for triggering a qualified system wake-up source also includes a configuration mode value and a configuration precharge value.

14. The unit according to claim 8, wherein, The digital power-on module receives one or more qualified system wake-up source triggers and maintains a precharge enable configuration value for each of the one or more qualified system wake-up source triggers.

15. A method for providing early pre-charge for peak power events, comprising: Receive a qualified system wake-up source trigger for the electronic device used to enable sleep; Initiate pre-charging of a supercapacitor coupled to multiple power sources, the multiple power sources including at least a first power source and a second power source; as well as When the supercapacitor is precharged to a predetermined charge level, the sleep-enabled electronic device is activated to wake up. The method further includes: When the pre-charging of the supercapacitor is complete, the supercapacitor is connected to the sleep-enabled electronic device, and The supercapacitor is selectively coupled to a dual-input DC / DC converter and a three-input DC / DC converter, such that in the dual-input DC / DC converter, a pre-charge power is obtained by pre-charging the supercapacitor with power from a first power source and power from a second power source as inputs, and the supercapacitor discharges when the peak power event occurs, so that the pre-charge power, along with the power from the first power source and the power from the second power source, is input to the three-input DC / DC converter. The coupling between the supercapacitor and the dual-input DC / DC converter or the three-input DC / DC converter is controlled by a pair of control signals, including a pre-charge enable signal and a low-power state signal. The pre-charge enable signal and the low-power state signal are combined to define four different coupling-decoupling modes between the supercapacitor and the dual-input DC / DC converter or the three-input DC / DC converter, and the pre-charge is triggered by a logical AND of the pre-charge enable signal and the low-power state signal.

16. The method according to claim 15, wherein, The supercapacitor is precharged to its terminal voltage.

17. The method according to claim 15, wherein, The supercapacitor is precharged for a specified amount of time.

18. The method according to claim 15, wherein, The supercapacitor is pre-charged until the state of charge of the supercapacitor is greater than a specified voltage.

19. The method of claim 15, further comprising initiating the wake-up of the sleep-enabled electronic device without precharging the supercapacitor based on a precharge configuration value having an enable indicator for triggering by a received qualified system wake-up source.

20. The method according to claim 19, wherein, The precharge configuration value used for triggering a qualified system wake-up source also includes a configuration mode value and a configuration precharge value.

21. The method according to claim 15, wherein, The qualified system wake-up source trigger includes one or more qualified system wake-up source triggers, and each of the one or more qualified system wake-up source triggers maintains a precharge enabled configuration value.

22. A always-on power management unit for providing additional peak power charging to a power computing device, comprising: A module for receiving a qualified system wake-up source trigger for an electronic device used to enable sleep; A module for initiating the pre-charging of a supercapacitor coupled to multiple power sources, the multiple power sources including at least a first power source and a second power source; A module for activating the wake-up of the sleep-enabled electronic device when the supercapacitor is precharged to a predetermined charge level; and A module for connecting the supercapacitor to the sleep-enabled electronic device when the pre-charging of the supercapacitor is complete. The supercapacitor is selectively coupled to a dual-input DC / DC converter and a three-input DC / DC converter, such that a pre-charge power is obtained in the dual-input DC / DC converter by pre-charging the supercapacitor with power from a first power source and power from a second power source as inputs, and the supercapacitor discharges upon the occurrence of a peak power event, so that the pre-charge power, along with the power from the first power source and the power from the second power source, is input to the three-input DC / DC converter. The coupling between the supercapacitor and the dual-input DC / DC converter or the three-input DC / DC converter is controlled by a pair of control signals, including a pre-charge enable signal and a low-power state signal. The pre-charge enable signal and the low-power state signal are combined to define four different coupling-decoupling modes between the supercapacitor and the dual-input DC / DC converter or the three-input DC / DC converter, and the pre-charge is triggered by a logical AND of the pre-charge enable signal and the low-power state signal.

23. The always-on power management unit according to claim 22, wherein, The supercapacitor is precharged to its terminal voltage.

24. The always-on power management unit according to claim 22, wherein, The supercapacitor is precharged for a specified amount of time.

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