Integrated circuit devices including optoelectronic components

Abstract

An integrated circuit (IC) device is provided, which includes an optical IC substrate, a local groove located inside the optical IC substrate, and an optoelectronic element, wherein the optoelectronic element includes a photoelectric conversion layer buried inside the local groove. The photoelectric conversion layer is buried inside the local groove in the optical IC substrate to form the optoelectronic element. Therefore, the IC device can suppress the warping of the optical IC substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0120610 filed on October 10, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to integrated circuit (IC) devices, and more particularly, to IC devices including optoelectronic elements (or optoelectronic devices) implemented on an optical IC substrate. Background Art

[0004] In order to meet the demand for small and high-speed electronic devices, IC devices may include optoelectronic elements for transmitting optical signals. The optoelectronic elements may include a photoelectric conversion layer or a coating layer formed to a predetermined thickness on an optical IC substrate. When the photoelectric conversion layer or the coating layer is formed to a predetermined thickness on the optical IC substrate, the IC device may suffer from a warping phenomenon when the optical IC substrate is warped during or after the manufacturing process. Summary of the invention

[0005] The present inventive concept provides an integrated circuit (IC) device including an optoelectronic device that can reduce and is not susceptible to warpage of an optical IC substrate and device.

[0006] According to one aspect of the present invention, an IC device is provided, comprising an optical IC substrate, a local groove located inside the optical IC substrate, and a photoelectric element (or device), wherein the photoelectric element (or device) comprises a photoelectric conversion layer buried inside the local groove.

[0007] According to another aspect of the present invention, an IC device is provided, which includes an optical IC substrate, a local groove located inside the optical IC substrate, a buried insulating layer buried in the local groove, and a photoelectric element, wherein the photoelectric element includes a photoelectric conversion layer formed in the buried insulating layer, and the photoelectric conversion layer is electrically insulated by the buried insulating layer.

[0008] According to another aspect of the present inventive concept, there is provided an IC device comprising: an optical IC substrate; a local groove formed in the optical IC substrate; an optoelectronic element comprising a photoelectric conversion layer buried in the local groove; and an optical waveguide layer optically coupled to the photoelectric conversion layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a top view of an integrated circuit (IC) device according to an embodiment;

[0011] Figure 2 is a cross-sectional view of a photovoltaic element according to an embodiment;

[0012] FIG. 3A to FIG. 3C According to various embodiments Figure 1 and Figure 2 A perspective view of an optical waveguide layer;

[0013] Figure 4 is a cross-sectional view of a photovoltaic element according to an embodiment;

[0014] Figure 5 is a cross-sectional view of a photovoltaic element according to an embodiment;

[0015] Figure 6 is a cross-sectional view of a photovoltaic element according to an embodiment;

[0016] Figure 7 is a cross-sectional view of a photovoltaic element according to an embodiment;

[0017] Figure 8 is a cross-sectional view of a photovoltaic element according to an embodiment;

[0018] Fig. 9 is a cross-sectional view of a photovoltaic element according to an embodiment;

[0019] Figures 10 to 13 is a cross-sectional view of the optical coupling relationship between an optical waveguide layer and an optoelectronic conversion layer that can be implemented in an IC device embodiment described herein;

[0020] Fig.14 According to the embodiment Fig.12 A cross-sectional view of an optical coupler;

[0021] Fig.15 is a top view of an IC device according to an embodiment;

[0022] Fig.16 is a diagram of an IC system including an IC device according to an embodiment; and

[0023] Fig.17 is a block diagram of a computing system including an IC device according to an embodiment. DETAILED DESCRIPTION

[0024] Figure 1 is a top view of an integrated circuit (IC) device 1000 according to an embodiment.

[0025] Specifically, the IC device 1000 may include an optical IC substrate 100 , an optical device (OD) 390 , and an optical interface 400 .

[0026] OD 390 may be formed on an optical IC substrate 100. The optical IC substrate 100 may be a silicon-on-insulator (SOI) substrate or a bulk silicon substrate. OD 390 may include an optoelectronic element (also referred to as an optoelectronic device) 300. The optoelectronic element 300 may include an optoelectronic conversion element (also referred to as an optoelectronic conversion device). The optoelectronic element 300 may include a photodetector. The optoelectronic element 300 may be a photodiode (PD). The optical device 390 may include an electro-optical element 380 or an electro-optical conversion element. The electro-optical element 380 may be a laser diode (LD).

[0027] Figure 1 A case is shown where both the optoelectronic element 300 and the electro-optical element 380 are integrated on the optical IC substrate 100. However, the electro-optical element 380 may not be integrated on the optical IC substrate 100 but may be formed on a separate substrate and formed with a separate module or system.

[0028] The optical interface 400 may be formed on one face of the optical IC substrate 100 (e.g., formed on an active surface of the optical IC substrate 100). The optical interface 400 may be optically coupled to the optical IC substrate 100. The optical interface 400 may be optically coupled to an optical waveguide layer 104 formed on the optical IC substrate 100. The optical waveguide layer 104 may be a layer in which one or more waveguides WG are formed to provide one or more paths through which light (or optical signals) are transmitted. Although the OD 390 and the optical waveguide layer 104 are Figure 1 390, however, the optical waveguide layer 104 may also be formed in the OD 390. The optical interface 400 may be an optical connector configured to physically and optically connect to one or more optical fibers 404. Figure 1 4 is shown as being on the optical IC substrate 100 , however the optical interface 400 may be positioned in contact with or separate from the optical IC substrate 100 .

[0029] The IC device 1000 may further include an electronic IC device (EICD) 200 that may be formed on the optical IC substrate 100. The EICD 200 may be located on the optical IC substrate 100 at a position spaced apart from the OD 390.

[0030] The optical IC may also include an electrical interface 500, which in some examples may be mounted on the other side of the optical IC substrate 100. The electrical interface 500 may be coupled to the EICD 200 via wiring (eg, conductive metal lines formed as part of the IC device 1000). Figure 1 Interface interconnects 503 (e.g., wiring) are shown connected to the electrical interface 500 and terminated at the electrical interface 500. At least one of the interface interconnects 503 can be connected to the EICD 200 via a first circuit interconnect 103. The electrical interface 500 can include conventional semiconductor device terminals, such as chip pads, TSVs (through substrate vias), conductive bumps (e.g., solder balls or solder pillars, etc.) forming a ball grid array (BGA), etc. The OD 390 can be electrically coupled to the EICD 200 via a second circuit interconnect 103 (e.g., wiring such as a conductive metal line). The electrical interface 500 can be located above the optical IC substrate 100 and above a portion of the active surface of the IC device 1000, or can be located on the back side of the IC device 1000 (opposite the side of the active surface) and can be in contact with the optical IC substrate. It should be understood that the interface interconnects 503 and the optical fibers 404 can be connected to the IC device 1000, however Figure 1 The other elements shown in can be integrally formed as part of the IC device 1000. When the IC device 1000 is embodied as a semiconductor chip (e.g., formed on a wafer together with other IC devices 1000 and cut (singulated) from the wafer), the circuit interconnect 103, EICD 200, optical device 390 and optical waveguide - including optical waveguide layer (WG) 104 - can be integrally formed as elements of the semiconductor chip and integrally formed with other electrical / optical circuit elements of the semiconductor chip. All or part of the optical interface 400 and the electrical interface 500 can also be formed as part of such a semiconductor chip. For example, the optical interface 400 and the electrical interface 500 can be respectively configured to be connected to an external signal transmission line (such as an interconnect 503 and an optical fiber 404) The electrical terminal (such as a chip pad) and the optical terminal (such as the end of the waveguide, for example, the end of the patterned element of the optical waveguide layer (WG) 104) are respectively connected. Hereinafter, the signal transmission relationship between the OD 390, the optical interface 400, the EICD 200, and the electrical interface 500 will be described. It should be understood that although the present description relates to a signal path of one signal, this is for illustrative purposes only, and multiple signal paths (and thus multiple electrical and optical transmission elements and conversion elements) may be formed by the IC device 1000 to operate simultaneously (e.g., in parallel) to transmit multiple signals (i.e., multiple signals may be transmitted repeatedly within the IC device 1000). Figure 1 OD 390, EICD 200, circuit interconnect lines 103 and waveguides to provide multiple signal paths between optical interface 400 and electrical interface 500).

[0031] The electrical signal transmitted through the interface interconnection line 503 connected to the electrical interface 500 may be received by the EICD 200 and the OD 390 through the circuit interconnection line 103. When the OD 390 is an electro-optical element 380 (e.g., an LD device), an optical signal may be generated by the OD 390 in response to the received electrical signal and transmitted to an external device connected to the optical fiber 404 (from the OD 390 through the optical waveguide layer 104 (as the core layer of the optical waveguide) and the optical fiber 404 connected to the optical interface 400). The portions of the optical waveguide layer 104 extending between the OD 390 and the optical interface 400 may form the core of one or more optical waveguides, wherein the cladding of the optical waveguide surrounds the core of the optical waveguide. The optical waveguide within the IC device 1000 may be formed in various configurations and provide an optical signal path between the optical interface 400 and one or both of the LD 380 and the PD 300.

[0032] The optical signal received by the optical fiber 404 through the optical interface 400 can be transmitted to the OD 390 (e.g., the optoelectronic element 300) through the optical waveguide layer 104. The optical signal can be converted into an electrical signal by the optoelectronic element 300, and the electrical signal can be transmitted from the EICD 200 and via the electrical interface 500 and the interconnection line 503 to an external device connected to the interface interconnection line 503.

[0033] Figure 2 is a cross-sectional view of a photoelectric element 300 - 1 according to an embodiment.

[0034] Photoelectric element 300-1 is Figure 1 FIG. 1 is an example of an optoelectronic element 300 of the IC device 1000. The optoelectronic element 300-1 may include a PD.

[0035] The optoelectronic element 300-1 may be formed with an optical IC substrate 302. The optical IC substrate 302 may be Figure 1 The optical IC substrate 100 of FIG. 302 may be a silicon-on-insulator (SOI) substrate including a base silicon layer 302a, a buried insulating layer 302b formed on the base silicon layer 302a, and a silicon layer 302c formed on the buried insulating layer 302b. The silicon layer 302c may be the uppermost silicon layer of the SOI substrate 302.

[0036] Each of the base silicon layer 302a and the silicon layer 302c may be a crystalline silicon layer. A region 306c formed in the upper surface of the base silicon layer 302a is doped with first conductive type impurities, for example, N-type impurities. The buried insulating layer 302b may be a silicon oxide layer.

[0037] The silicon layer 302c may be patterned and used as the optical waveguide layer WG. Specifically, the silicon layer 302c may be the optical waveguide layer 104 and have patterned elements of one or more core layers forming one or more optical waveguides. The buried insulating layer 302b formed below the silicon layer 302c may be used as a lower cladding layer of such an optical waveguide. The optical waveguide layer WG (302c) may be formed with Figure 1 The optical waveguide layer 104 is identical and forms the core of one or more waveguides. Figure 2 As shown in , the optical waveguide layer WG (104) may be patterned into portions separated from each other in its cross-sectional view (and may be patterned to form discrete pattern elements isolated from each other to form discrete optical waveguides). Figure 2 The silicon layer 302c is shown as being used as the optical waveguide layer WG, however other embodiments are possible that do not use the silicon layer 302c to form the optical waveguide.

[0038] The local trench 304 may be formed in the optical IC substrate 302. The local trench 304 may partially penetrate into the buried insulating layer 302b included in the optical IC substrate 302. The local trench 304 may have a sidewall formed by the buried insulating layer 302b, and may have a bottom formed by the base silicon layer 302a (when the trench penetrates the buried insulating layer 302b, as shown in FIG. Figure 2 ) or having a bottom formed by a lower portion of the buried insulating layer 302 b (according to other examples described herein).

[0039] The photoelectric conversion layer 306 may be buried inside the local trench 304. The photoelectric conversion layer 306 may include a plurality of semiconductor layers, for example, a first semiconductor layer 306a and a second semiconductor layer 306b. A portion of the region 306c of the base silicon layer 302a may also form the photoelectric conversion layer 306. The photoelectric conversion layer 306 may be formed of one or more silicon (Si) layers or germanium (Ge) layers or other semiconductor materials to form a PIN photodiode or a PN photodiode. The photoelectric conversion layer 306 may include one or more crystalline silicon layers and / or crystalline germanium layers. The first semiconductor layer 306a may be a crystalline germanium layer epitaxially grown using the base silicon layer 302a as a seed layer. Therefore, the photodiode semiconductor structure is formed by the photoelectric conversion layer 306, thereby including a stack of functional layers extending from a cathode formed by the N-type region 306c to an anode formed by the P-type second semiconductor layer 306b. A depletion region can be formed between the cathode and the anode, and when exposed to light, the photons can generate electron-hole pairs to cause a photocurrent and voltage across the anode and cathode (in this example, 306c and 306b, respectively). The photodiode semiconductor structure can take many forms, including conventional PN photodiodes, PIN photodiodes, metal-semiconductor-metal photodiodes, etc. Each layer of the stack of semiconductor functional layers of the photodiode semiconductor structure can be a crystalline semiconductor layer. It will be understood that the stack of doped semiconductor functional layers of the photodiode semiconductor structure can include additional semiconductor layers in the stack of its functional layers and / or be formed with other types of semiconductor materials other than the exemplary materials described herein. It should also be understood that the photodiode semiconductor structure (photoelectric conversion layer 306) can be formed so that the anode (outermost N-type functional layer) is formed as the uppermost layer of the photodiode semiconductor structure and the cathode (outermost P-type functional layer) is formed as the lowermost layer of the photodiode semiconductor structure.

[0040] In some embodiments, the first semiconductor layer 306a may be an undoped intrinsic crystalline germanium layer, and the second semiconductor layer 306b may be a crystalline silicon layer doped with impurities of a second conductivity type (e.g., P-type impurities), the second conductivity type being opposite to the first conductivity type (which is doped in region 306c of the base silicon layer 302a).

[0041] In an embodiment, the second semiconductor layer 306 b including a P-type silicon layer, the first semiconductor layer 306 a including an undoped intrinsic germanium layer, and the base silicon layer 302 a including an N-type silicon region 306 c may constitute a PIN PD.

[0042] The PIN PD may be a main component of the optoelectronic element 300 - 1 . In a narrow sense, the PIN PD may be referred to as the optoelectronic element 300 - 1 . The optoelectronic element 300 - 1 may be optically coupled to the optical waveguide layer WG.

[0043] Although the PIN PD is shown as Figure 1 The optoelectronic element 300-1 is a main component of the optoelectronic element 300-1, but the optoelectronic element 300-1 can adopt PN PD or metal-semiconductor-metal PD. Because the photoelectric conversion layer 306 (specifically, the first semiconductor layer 306a) is buried inside the local groove 304, the optoelectronic element 300-1 can be less susceptible to the warping phenomenon when the optical IC substrate 302 is warped and less likely to cause the warping of the IC device 1000.

[0044] The interlayer insulating layer 312 may be formed on the optical IC substrate 302 in which the photoelectric conversion layer 306 and the optical waveguide layer WG are formed. The interlayer insulating layer 312 may be / include a silicon oxide layer. The interlayer insulating layer 312 may be used as an upper cladding layer of an optical waveguide formed using the silicon layer 302c as a core layer of the optical waveguide. The base silicon layer 302a (specifically, the N-type silicon region 306c) may be electrically connected to the first conductive line 308 outside the local trench 304. The first conductive line 308 may include: a first contact plug (e.g., a through hole) 308a, which may be formed inside a contact hole formed in the interlayer insulating layer 312 and a contact hole formed in the buried insulating layer 302b; and a first interconnect layer 308b (e.g., a wiring extending horizontally within the IC device 1000), which may be electrically connected to the first contact plug 308a and formed in the interlayer insulating layer 312.

[0045] The second semiconductor layer 306b (e.g., a P-type silicon layer) included in the photoelectric conversion layer 306 may be electrically connected to the second conductive line 310. The second conductive line 310 may include: a second contact plug 310a, which may be formed in a contact hole extending through the interlayer insulating layer 312; and a second interconnection layer 310b (e.g., a wiring extending horizontally within the IC device 1000), which may be electrically connected to the second contact plug 310a and formed in the interlayer insulating layer 312. The first interconnection layer 308b and the second interconnection layer 310b may be wirings formed of a patterned metal layer.

[0046] In the optoelectronic element 300-1, the first conductive line 308 and the second conductive line 310 can be electrically connected to the N-type silicon region 306c and the P-type silicon layer (i.e., the second semiconductor layer 306b), respectively, and the N-type silicon region 306c and the P-type silicon layer can be located below and on the first semiconductor layer 306a including the intrinsic germanium layer, respectively, thereby forming a PIN PD.

[0047] The first conductive line 308 and the second conductive line 310 can be electrically connected to the lower part of the PIN PD (i.e., the anode formed by the N-type region 306c of the base silicon layer 302a) and the upper part of the PIN PD (i.e., the cathode formed by the P-type second semiconductor layer 306b stacked on the N-type silicon region 306c in the vertical direction). Therefore, the optoelectronic element 300-1 can be a vertical optoelectronic element.

[0048] In the optoelectronic element 300-1, the optical signal transmitted by the optical waveguide layer WG or 104 may be converted into an electrical signal by the PIN PD including the optoelectronic conversion layer 306 and transmitted to the EICD through the first interconnection layer 308b of the first conductive line 308 or the second interconnection layer 310b of the second conductive line 310 (refer to Figure 1 200 in FIG. 200). The optoelectronic element 300-1 does not need to transmit the optical signal to the PIN PD by using the waveguide of the silicon layer 302c, but can transmit the optical signal by other means. For example, the optical signal can be applied from an external source to the PIN PD including the optoelectronic conversion layer 306 and converted into an electrical signal, such as by an opening or a waveguide formed above the PIN PD.

[0049] FIG. 3A to FIG. 3C According to various embodiments Figure 1 and Figure 2 A perspective view of the optical waveguide layer.

[0050] Specifically, Figure 1 and Figure 2 The optical waveguide layer 104 (WG) may be patterned to have a FIG. 3A to FIG. 3C The optical waveguide cores 1004a, 1004b and / or 1004c are formed by the optical waveguide cores 1004a, 1004b and / or 1004c. FIG. 3A to FIG. 3C , Z represents the vertical direction, X represents the width direction of the optical waveguide core, and Y represents the length direction (along the length of the optical waveguide core corresponding to the optical signal transmission path).

[0051] refer to Figure 3A , the optical waveguide core 1004a can be formed as a core layer located on the lower cladding layer 1002a as a one-dimensional (1D) plane plate. An air layer can be used as an upper cladding layer. Alternatively, an interlayer insulating layer or other insulating layer can be used as an upper cladding layer, such as Figure 2 In operation, the refractive index changes only in the depth direction (Z), and the optical signal passing through the optical waveguide core 1004a is only reflected relative to the depth direction (Z). Figure 3A In the embodiment, an optical signal input to one side of the optical waveguide core 1004a can be output from the other side thereof. A plurality of discretely separated signals can be simultaneously transmitted between a plurality of optical devices 390 (LD 380 or PD 300) and corresponding optical fibers 404 through the slab core layer 1004a.

[0052] refer to Figure 3B , the optical waveguide core 1004b can be formed as a channel core located on the lower cladding layer 1002b. The air layer can be used as the upper cladding layer. Alternatively, the interlayer insulating layer can be used as the upper cladding layer, such as Figure 2 In this case, a change in the refractive index occurs in both the depth direction (Z) and the width direction (X) of the channel type optical waveguide core 1004b. Figure 3B In the embodiment, an optical signal input to one side of the optical waveguide core 1004b can be output from the other side thereof.

[0053] refer to Figure 3C , the optical waveguide layer 104 may include a core 1004c formed on the lower cladding layer 1002c as a branch channel type. An air layer may be used as an upper cladding layer. Alternatively, an interlayer insulating layer may be used as an upper cladding layer, such as Figure 2 As shown. Figure 3C In the embodiment, an optical signal input to one side of the core 1004c of the optical waveguide layer 104 can be output from the other side thereof. The core 1004c of the optical waveguide layer 104 can split the input optical signal into two output signals.

[0054] Figure 4 is a cross-sectional view of a photoelectric element 300 - 2 according to an embodiment.

[0055] Specifically, in addition to the optical IC substrate 302-1 being a double SOI substrate, the optoelectronic element 300-2 may be Figure 2 The photoelectric element 300-2 may include a PD. Figure 4 In the drawings, the same reference numerals are used to denote Figure 1 and Figure 2 The same elements as those in the drawings are described above, and repeated descriptions will be omitted or briefly provided.

[0056] The optical IC substrate 302-1 may be a double SOI substrate including a base silicon layer 302a-1, a first buried insulating layer 302d-1 formed on the base silicon layer 302a-1, a buried silicon layer 302e formed on the first buried insulating layer 302d-1, a second buried insulating layer 302b-1 formed on the buried silicon layer 302e, and a silicon layer 302c formed on the second buried insulating layer 302b-1. The optical IC substrate 302-1 may be an SOI substrate obtained by sequentially and repeatedly forming a silicon layer and an insulating layer.

[0057] The first buried insulating layer 302d-1 and the second buried insulating layer 302b-1 may be silicon oxide layers. The buried silicon layer 302e may be a crystalline silicon layer. The buried silicon layer 302e may be a silicon layer 306d doped with impurities of a first conductivity type (e.g., N-type impurities), and thus an N-type silicon layer. A local trench 304 may be formed in the second buried insulating layer 302b-1. The local trench 304 may have a side formed by the second buried insulating layer 302b-1 and a bottom formed by the buried silicon layer 302e.

[0058] Photoelectric conversion layer 306 may be buried inside local trench 304. Photoelectric conversion layer 306 may include first and second semiconductor layers 306a and 306b and a portion of silicon layer 302e below first semiconductor layer 306a. First semiconductor layer 306a may be a crystalline germanium layer epitaxially grown using buried silicon layer 302e as a seed layer.

[0059] As described above, the optoelectronic element 300-2 can be easily formed by epitaxially growing the first semiconductor layer 306a in the trench 304 using the buried silicon layer 302e as a seed layer. The optoelectronic element 300-2 can have the buried silicon layer 302e separated from the base silicon layer 302a-1 by the first buried insulating layer 302d-1, and the warpage of the optical IC substrate 302-1 can be further suppressed.

[0060] Figure 5 is a cross-sectional view of an optoelectronic element 300 - 3 combined with an EICD according to an embodiment.

[0061] The photoelectric element 300-3 can be connected with Figure 2 The photoelectric element 300-3 may be a PD and combined with an EICD. Figure 5 In the drawings, the same reference numerals are used to denote Figure 1 and Figure 2 The same elements as in . Figure 5 In the Figure 1 and Figure 2 Same description in .

[0062] The EICD may be integrated in the optical IC substrate 302 and include components formed in the optical IC substrate 302. The EICD may be Figure 1 The EICD 200 may include a plurality of interconnected transistors (such as Figure 5 The EICD 200 and the optoelectronic element 300-3 may be integrated in a semiconductor chip.

[0063] The source and drain regions 316 may be formed by a portion of the silicon layer 302c formed on the buried insulating layer 302b. The third conductive line 318 may be formed on the gate electrode 314 and the source and drain regions 316. Each third conductive line 318 may include: a third contact plug 318a formed inside a contact hole of the interlayer insulating layer 312; and a third interconnect layer 318b electrically connected to the third contact plug 318a and formed in the interlayer insulating layer 312. The first interconnect layer 308b, the second interconnect layer 310b, and the third interconnect layer 318b may be formed by portions of the same conductive layer.

[0064] Since the EICD is further integrated in the optical IC substrate 302 as described above, the optoelectronic element 300 - 3 can easily control the electrical signal.

[0065] Figure 6 is a cross-sectional view of a photoelectric element 300 - 4 according to an embodiment.

[0066] In addition to the optical IC substrate 302-2 being formed as a bulk silicon substrate, the optoelectronic element 300-4 may be formed with Figure 2 The photoelectric element 300-1 is the same as the photoelectric element 300-2. The photoelectric element 300-2 may be a PD. Figure 6 In the drawings, the same reference numerals are used to denote Figure 1 and Figure 2 The same elements as those in the drawings are used herein, and the same description will be omitted or briefly provided.

[0067] The optoelectronic element 300-4 may be formed on and / or within the optical IC substrate 302-2. The optical IC substrate 302-2 may be Figure 1 The optical IC substrate 100 of FIG. 302 - 2 may be a bulk silicon substrate such as a bulk crystalline silicon substrate (eg, cut from a crystalline silicon ingot).

[0068] The local trench 304a may be formed in an upper portion of the bulk silicon substrate 302-2. The local trench 304a may be formed by etching an upper portion 303a of the bulk silicon substrate 302-2 (ie, an upper portion of the bulk silicon layer 303a).

[0069] A plurality of local trenches 304a may be formed and separated from each other. Each trench may have a side and a bottom formed by the bulk silicon substrate 302-2. A buried insulating layer 320 may be formed in the local trench 304a of the bulk silicon substrate 302-2.

[0070] In an embodiment, an N-type silicon region 306e doped with impurities of a first conductivity type (e.g., N-type impurities) may be formed in one surface of the bulk silicon layer 303a located below the local trench 304a. The photoelectric conversion layer 306 may be formed inside the local trench 304a. The photoelectric conversion layer 306 may be surrounded by a buried insulating layer 320 formed inside the local trench 304a. The buried insulating layer 320 may be a silicon oxide layer.

[0071] Photoelectric conversion layer 306 may include a plurality of semiconductor layers as described elsewhere herein, for example, a first semiconductor layer 306a and a second semiconductor layer 306b. Photoelectric conversion layer 306 may include a silicon layer or a germanium layer and a portion of silicon region 306e located below first semiconductor layer 306a. Photoelectric conversion layer 306 may include a crystalline silicon layer or a crystalline germanium layer. First semiconductor layer 306a may include a germanium layer epitaxially grown using bulk silicon layer 303a as a seed layer.

[0072] In an embodiment, the first semiconductor layer 306a may be / include an undoped intrinsic germanium layer, and the second semiconductor layer 306b may be / include a P-type silicon layer doped with impurities of a second conductivity type opposite to the first conductivity type (e.g., P-type impurities). In an embodiment, the second semiconductor layer 306b including the P-type silicon layer, the first semiconductor layer 306a including the undoped intrinsic germanium layer, and the bulk silicon layer 303a including the N-type silicon layer 306e may constitute a PIN PD.

[0073] The optical waveguide layer WG may be formed on a portion of the insulating layer 320. The optical waveguide layer WG may correspond to Figure 1 The optical waveguide layer 104 may be a crystalline silicon layer, which may be formed by forming an amorphous polysilicon layer on the buried insulating layer 320 and crystallizing the amorphous polysilicon layer. Figure 6 The optical waveguide layer WG is shown in FIG. 1 , but the optical waveguide layer WG may be omitted.

[0074] The bulk silicon layer 303a (i.e., the N-type silicon layer 306e) may be electrically connected to the first conductive line 308 inside the local trench 304a. The first conductive line 308 may include: a first contact plug 308a, which may be formed inside the contact hole of the interlayer insulating layer 312 and the contact hole of the buried insulating layer 320; and a first interconnection layer 308b, which may be electrically connected to the first contact plug 308a and formed in the interlayer insulating layer 312.

[0075] The second semiconductor layer 306b (e.g., a P-type silicon layer) included in the photoelectric conversion layer 306 may be electrically connected to the second conductive line 310. The second conductive line 310 may include: a second contact plug 310a, which may be formed inside a contact hole of the interlayer insulating layer 312; and a second interconnection layer 310b, which may be electrically connected to the second contact plug 310a and formed in the interlayer insulating layer 312.

[0076] In the optoelectronic element 300-4, the first conductive line 308 may be electrically connected to the N-type silicon layer 306e which may be located below the first semiconductor layer 306a (e.g., the undoped intrinsic germanium layer), and the second conductive line 310 may be electrically connected to the P-type silicon layer (i.e., the second semiconductor layer 306b) which may be located on the first semiconductor layer 306a (e.g., the undoped intrinsic germanium layer), thereby forming a PINPD. Therefore, the optoelectronic element 300-4 may be a vertical optoelectronic element.

[0077] Figure 7 is a cross-sectional view of a photoelectric element 300 - 7 according to an embodiment.

[0078] Specifically, in addition to the photoelectric conversion layer 306 being formed in the buried insulating layer 320 (which is formed in the local trench 304a) and being electrically insulated from the bulk silicon substrate 302-2, and in addition to the photoelectric element 300-5 being formed as a metal-semiconductor-metal PD, the photoelectric element 300-5 can be Figure 8 The photoelectric element 300-6 is the same as the photoelectric element 300-7. The photoelectric element 300-7 may be a PD and may be combined with an EICD. Figure 7 In the drawings, the same reference numerals are used to denote Figure 6 The same elements as those in the drawings are used herein, and the same description will be omitted or briefly provided.

[0079] The photoelectric conversion layer 306 may be formed to be separated from the bottom 304S of the local trench 304a formed by the bulk silicon substrate 302-2. The buried insulating layer 320 may be formed on the sidewall and bottom of the local trench 304a inside the local trench 304a. The photoelectric conversion layer 306 may be formed in the buried insulating layer 320 buried inside the local trench 304a and electrically insulated from the bulk silicon substrate 302-2. The photoelectric conversion layer 306 may be spaced apart from the bottom 304S of the local trench 304a (i.e., the surface of the bulk silicon layer 303a) and inside the local trench 304a. The photoelectric conversion layer 306 includes a metal layer 306f and a first semiconductor layer 306a.

[0080] The optoelectronic element 300 - 5 may further include a first conductive line 308 electrically connected to a first portion of the metal layer 306 f and a second conductive line 310 electrically connected to a second portion of the metal layer 306 f.

[0081] Therefore, the optoelectronic element 300-5 may be a lateral optoelectronic element because the first conductive line 308 and the second conductive line 310 are formed to be spaced apart from each other on the surface of the metal layer 306f. The lateral optoelectronic element may be a metal-semiconductor-metal photodiode. The optical waveguide layer WG may be formed on the buried insulating layer 320. The optical signal applied to the optical waveguide layer WG may be converted into an electrical signal by the lateral optoelectronic element 300-7 including the optoelectronic conversion layer 306.

[0082] Figure 8 is a cross-sectional view of an optoelectronic element 300 - 6 combined with an EICD according to an embodiment.

[0083] Specifically, in addition to the optical IC substrate 302 being an SOI substrate, the optoelectronic element 300-6 may be Figure 7 The photoelectric element 300-5 is the same as the photoelectric element 300-6. The photoelectric element 300-6 can be a PD and combined with an EICD. Figure 8 In the drawings, the same reference numerals are used to denote Figure 7 The same elements as those in Figure 7 Same description in .

[0084] The optical IC substrate 302 may be an SOI substrate including a base silicon layer 302a, a buried insulating layer 302b formed on the base silicon layer 302a, and a silicon layer 302c formed on the buried insulating layer 302b. The silicon layer 302c may be patterned and used as an optical waveguide core layer WG to form one or more cores of one or more optical waveguides. The silicon layer 302c may be patterned and used as an active layer of an EICD.

[0085] The local trench 304b may be formed in the buried insulating layer 302b of the optical IC substrate 302. The bottom of the local trench 304b may be formed to be separated from the surface 302S of the base silicon layer 302a, such as by being formed by the surface of the buried insulating layer 302b or by an additional insulating layer deposited in an initial larger trench formed in the buried insulating layer 302b. The photoelectric conversion layer 306 may be spaced apart from the surface 302S of the base silicon layer 302a and buried inside the local trench 304b. The photoelectric conversion layer 306 may be spaced apart from the surface 302S of the base silicon layer 302a and buried in the buried insulating layer 302b. The optoelectronic element 300-6 may be a metal-semiconductor-metal PD. The optical signal applied to the optical waveguide layer WG may be converted into an electrical signal by the optoelectronic element 300-6 including the photoelectric conversion layer 306.

[0086] Fig. 9 is a cross-sectional view of a photoelectric element 300 - 7 according to an embodiment.

[0087] Photoelectric element 300-7 can be used with Figure 2 The photoelectric element 300-1 is the same as that of FIG. 300 and shows details of the optical waveguide layer WG optically coupled to the side surface of the photoelectric conversion layer 306. The photoelectric element 300-7 may be a PD. Fig. 9 In the drawings, the same reference numerals are used to denote Figure 2 The same elements as those in the drawings are used herein, and the same description will be omitted or briefly provided.

[0088] Photoelectric conversion layer 306 may be buried inside local trench 304 formed in optical IC substrate 302. Photoelectric conversion layer 306 may include first semiconductor layer 306a and second semiconductor layer 306b formed on first semiconductor layer 306a. Photoelectric conversion layer 306 may include one or more crystalline silicon layer and crystalline germanium layer.

[0089] The silicon layer 302c of the optical IC substrate 302 may be patterned and used as the optical waveguide layer WG. The optical waveguide layer WG may correspond to Figure 1 The optical waveguide layer 104 and a portion thereof may form one or more cores of the optical waveguide of the optoelectronic element 300-7. Fig. 9 As indicated by the region EL1 of , one side surface of the optical waveguide layer WG may be optically coupled to (and in contact with) one side surface of the photoelectric conversion layer 306 (here, one side surface of the second semiconductor layer 306b). The side surface of the optical waveguide layer WG (104) facing and in contact with the side surface of the photoelectric conversion layer 306 may form the end of an optical waveguide having the optical waveguide layer WG (104) as a core. The optical waveguide layer WG or 104 may be optically coupled to the PIN PD including the photoelectric conversion layer 306, so that an optical signal applied to the optical waveguide layer WG 104 may be transmitted to impinge on the photoelectric conversion layer 306 and be easily converted into an electrical signal.

[0090] Figures 10 to 13 is a cross-sectional view of optical coupling between the optical waveguide layer WG and the photoelectric conversion layer 306 . Figures 10 to 13 The optical coupling shows the Fig. 9 The optical waveguide layer WG ( 104 ) is located in a region corresponding to EL1 of the optical waveguide layer 306 and includes a waveguide having a waveguide core formed by an optical waveguide layer WG ( 104 ) that is adjacently terminated to the photoelectric conversion layer 306 and optically coupled to the photoelectric conversion layer 306 . Figures 10 to 13 The alternative structure can be used not only with Fig. 9 It should also be understood that the device can be used with any embodiment described herein. Figures 9 to 13An example of coupling may include an additional optical element (for example, the additional optical element may be a part of another optical transmission element, such as an insulating layer, such as 312 or 302c) disposed between the end of the waveguide and the photoelectric conversion layer 306 to optically couple the optical waveguide (having a waveguide core (104) formed by the waveguide layer WG) to the photoelectric conversion layer 306.

[0091] Specifically, if Figures 10 to 13 As indicated by EL1a, EL1b, EL1c and EL1d, Fig. 9 The optical waveguide layer WG can be easily optically coupled to the photoelectric conversion layer 306. Figures 10 to 13 Detailed Description of the Invention In the present invention, the same reference numerals are used to denote the same elements.

[0092] like Fig.10 As shown, one side surface of the optical waveguide layer WG may contact and optically couple to one side surface of the photoelectric conversion layer 306 including the first semiconductor layer 306a-1. The top surface of the optical waveguide layer WG may be located at a lower level than the top surface of the photoelectric conversion layer 306. The top surface of the photoelectric conversion layer 306 may be located at a higher level than the top surface of the optical waveguide layer WG in the vertical direction on the base silicon layer 302a of the optical IC substrate. The first semiconductor layer 306a-1 may be a crystalline silicon layer or a crystalline germanium layer. The first semiconductor layer 306a-1 may be the uppermost layer of the photoelectric conversion layer 306 and form the top surface of the photoelectric conversion layer 306, or another layer (such as a second semiconductor layer 306b (not shown)) may be formed on the top surface of the first semiconductor layer 306a-1 and form the top surface of the photoelectric conversion layer 306. In an embodiment, the first semiconductor layer 306a-1 may be a crystalline germanium layer, and the second semiconductor layer 306b (not shown) located on the first semiconductor layer 306a-1 may be a crystalline germanium layer. Fig.10 The layer (not shown) may be a crystalline silicon layer.

[0093] like Fig.11 As shown, the side surface of the optical waveguide layer WG may contact and optically couple to one side surface of the photoelectric conversion layer 306 including the semiconductor layers 306a-2 and 306b-1. The top surface of the optical waveguide layer WG may be located at a higher level than the top surface of the photoelectric conversion layer 306 and may be located higher than the entire top surface of the first semiconductor layer 306a-2. Most of the top surface of the photoelectric conversion layer 306 (and most of the top surface of the second semiconductor layer 306b-1 covering the first semiconductor layer 306a-2) may be located at a lower level than the top surface of the optical waveguide layer WG in the vertical direction on the base silicon layer 302a of the optical IC substrate.

[0094] The photoelectric conversion layer 306 may include a first semiconductor layer 306a-2 and a second semiconductor layer 306b-1, and the second semiconductor layer 306b-1 is formed on the first semiconductor layer 306a-2 and the optical waveguide layer WG. The second semiconductor layer 306b-1 may be formed on a portion of the upper surface of the optical waveguide layer WG. The photoelectric conversion layer 306 may be formed to extend on the top of the optical waveguide layer WG.

[0095] The photoelectric conversion layer 306 may include one or more crystalline silicon layers and crystalline germanium layers. In an embodiment, the first semiconductor layer 306a-2 may be a crystalline germanium layer, and the second semiconductor layer 306b-1 may include a crystalline silicon layer.

[0096] like Fig.12 As shown, one side surface of the optical waveguide layer WG may contact and optically couple to one side surface of the photoelectric conversion layer 306 including the semiconductor layers 306a and 306b. The top surface of the optical waveguide layer WG may be located at the same level as the top surface of the photoelectric conversion layer 306.

[0097] The photoelectric conversion layer 306 may include a first semiconductor layer 306a and a second semiconductor layer 306b located on the first semiconductor layer 306a. The photoelectric conversion layer 306 may include one or more crystalline silicon layers and crystalline germanium layers. In an embodiment, the first semiconductor layer 306a may be a crystalline germanium layer, and the second semiconductor layer 306b may be a crystalline silicon layer.

[0098] The optical coupler 322 may be formed in one surface of the second semiconductor layer 306b. The optical waveguide layer WG may be optically coupled to a depletion region within the photoelectric conversion layer 306 (e.g., it may be formed within the first semiconductor layer 306a) through the optical coupler 322, so that an optical signal applied to the optical waveguide layer WG may be easily converted into an electrical signal. The optical coupler 322 may be a grating formed as a series of evenly spaced grooves etched into the top surface of the second semiconductor layer 306b. The optical coupler 322 may be used to reflect light transmitted in a horizontal direction by the optical waveguide layer WG (302c) (as the core of the optical waveguide) into the first semiconductor layer 306a in a downward direction. Although the optical coupler 322 (grating) is shown as being formed in the top surface of the photoelectric conversion layer 306, the optical coupler 322 (grating) may be formed elsewhere, such as within the top surface of an optical waveguide formed to extend above the photoelectric conversion layer 306 (which may be a portion of the waveguide that is not formed by the silicon layer 302c).

[0099] like Fig.13 As shown, the optical waveguide can be optically coupled to an evanescently coupled photoelectric conversion layer 306 (eg, to form an evanescently coupled photodiode). Fig.13In the example of , the optical waveguide is formed to have a waveguide core formed by the silicon layer 302c. The side surface of the optical waveguide layer WG formed by the silicon layer 302c may contact the second semiconductor layer 306b. The lower cladding layer of the waveguide may be formed by the buried insulating layer 302b. The upper cladding layer of the optical waveguide may be the same as the upper cladding layer described elsewhere (e.g., air, interlayer dielectric 312, etc.). The optical waveguide may be optically coupled to the photoelectric conversion layer 306 including the first semiconductor layer 306a and the second semiconductor layer 306b. The top surface of the optical waveguide layer WG may be at the same level (e.g., coplanar) as the top surface of the photoelectric conversion layer 306, wherein the top surface of the photoelectric conversion layer 306 is formed by the top surface of the second semiconductor layer 306b. The bottom surface of the optical waveguide layer WG may be at the same level (e.g., coplanar) as the lower surface of the second semiconductor layer 306b.

[0100] The photoelectric conversion layer 306 may include a first semiconductor layer 306a and a second semiconductor layer 306b. An insulating layer 324 may be formed between the first semiconductor layer 306a and the second semiconductor layer 306b. The insulating layer 324 may be a silicon oxide layer. Although the second semiconductor layer 306b does not contact the first semiconductor layer 306a (isolated by the insulating layer 324), since the insulating layer 324 is made thin to provide evanescent coupling between the first semiconductor layer 306a and the second semiconductor layer 306b, photoelectric conversion may still occur in the photoelectric conversion layer 306.

[0101] Fig.14 According to the embodiment Fig.12 322 of the optical coupler.

[0102] Specifically, the optical coupler 322 may include a grating coupler. The optical coupler 322 may be implemented by forming gratings (e.g., G1 and G2) in the surface of the semiconductor layer 306b (or 302c). The optical coupler 322 may receive and transmit light by using diffraction of light encountering the gratings G1 and G2. In addition, the optical coupler 322 may filter light by adjusting the distance between the gratings G1 and G2. The gratings G1 and G2 may be used to transmit light downward into a depletion region formed in the photoelectric conversion layer 306 (e.g., downward to the first semiconductor layer 306a where the depletion region is formed).

[0103] The size (i.e., period) of the grating formed in the optical coupler 322 can be determined by the width "w" and the wave number vector (k-vector) of the incident light. Therefore, by forming an appropriate grating in the optical coupler 322, the incident light can have a high optical coupling efficiency and be optically coupled to the optical coupler 322.

[0104] Fig.15is a top view of an IC device 1100 according to an embodiment.

[0105] Specifically, in addition to the optoelectronic element 300 and the electro-optical element 380 used as the OD being further separated from each other on the optical IC substrate 100 and the light modulation device 385 being further integrated in the optical IC substrate 100, the IC device 1100 may be connected to the optical IC substrate 1100. Figure 1 The optical modulation device 385 may be a modulation (MOD) device. Fig.15 In the drawings, the same reference numerals are used to denote Figure 1 The same elements as those in the drawings are described herein, and their repeated descriptions will be omitted or briefly provided.

[0106] The electrical signal received through the interface interconnection line 503 of the electrical interface 500 may be transmitted to the EICD 200, the electro-optical element 380, and the optical modulation device 385 through the circuit interconnection line 103. The electro-optical element 380 may generate an optical signal and transmit the optical signal to the optical modulation device 385.

[0107] Optical modulation device 385 can modulate an optical signal in response to an electrical signal transmitted through circuit interconnect 103 and transmit the modulated optical signal to optical interface 400 through optical waveguide layer 104. The modulated optical signal can be transmitted to an external device through optical fiber 404 of optical interface 400. EICD 200 can control electro-optical element 380 using circuit interconnect 103 as needed.

[0108] The optical signal received through the optical fiber 404 included in the optical interface 400 may be applied to the optoelectronic element 300 through the optical waveguide layer 104. The optoelectronic element 300 may convert the optical signal into an electrical signal and transmit the electrical signal to the electrical interface 500 through the EICD 200 and the circuit interconnection line 103. The electrical signal may be transmitted to an external device through the interface interconnection line 503 of the electrical interface 500.

[0109] Fig.16 is a diagram of an IC system 2000 including IC devices 2004 and 2006 according to an embodiment.

[0110] Specifically, the IC system 2000 may include a central processing unit (CPU) 2002, which may communicate with at least one memory module 2008 via a connection system 2013. The memory module 2008 may be, for example, a dual in-line memory module (DIMM). The DIMM may be a dynamic random access memory (DRAM) module. The memory module 2008 may include a plurality of individual memory circuits (e.g., DRAM memory circuits) 2020.

[0111] In this embodiment, the CPU 2002 and the memory module 2008 may generate or process electrical signals. The connection system 2013 may include an optical communication channel 2012 (eg, optical fiber) configured to transmit optical signals between the CPU 2002 and the memory module 2008.

[0112] Because the CPU 2002 and the memory module 2008 use electrical signals, an electrical-to-optical conversion process is provided to convert the electrical signals of the CPU 2002 and the memory module 2008 into optical signals to transmit the optical signals on the optical communication channel 2012. In addition, an optical-to-electrical conversion process may be required to convert the optical signals on the optical communication channel 2012 into electrical signals for processing by the CPU 2002 and the memory module 2008.

[0113] The connection system 2013 may include IC devices 2004 and 2006 located on both sides of the optical communication channel 2012. According to an embodiment, each of the IC devices 2004 and 2006 may be implemented by any IC device described herein (e.g., Figure 1 IC devices 1000 or Fig.15 The optical communication channel 2012 may be one or more optical fibers connected to the optical interface 400 of the IC devices 2004 and 2006.

[0114] CPU 2002 can transmit electrical signals to IC device 2004 and receive electrical signals from IC device 2004 via electrical bus 2010. Memory module 2008 can transmit electrical signals to IC device 2006 and receive electrical signals from IC device 2006 via electrical bus 2014. IC devices 2004 and 2006 can send optical signals to each other and receive optical signals from each other. Electrical buses 2010 and 2014 can be connected to electrical interface 500 of IC devices 2004 and 2006.

[0115] IC device 2004 may include optoelectronic element 2016 and electro-optical element 2017. IC device 2006 may include optoelectronic element 2018 and electro-optical element 2019. Electro-optical elements 2017 and 2019 may send optical signals to optical communication channel 2012 (e.g., optical fiber). Optoelectronic elements 2016 and 2018 may receive optical signals from optical communication channel 2012. Optoelectronic elements 2016 and 2018 may correspond to Figure 1 The photoelectric element 300.

[0116] Fig.17 is a block diagram of a computing system 2200 including an IC device according to an embodiment.

[0117] Generally speaking, a computing system may include a signal processing system, a display system, a communication system, or a system capable of sending signals optically.

[0118] Specifically, in Fig.17 In an embodiment, the computing system 2200 may include a processor 2210, which may communicate with another component via an optical bus 2250. According to an embodiment, the processor 2210 may include Figure 1 IC devices 1000 or Fig.15 IC device 1100.

[0119] The semiconductor memory device 2220 may be coupled to the optical bus 2250. According to an embodiment, the semiconductor memory device 2220 may include Figure 1 IC devices 1000 or Fig.15 IC device 1100. Therefore, semiconductor memory device 2220 may communicate with another element through optical bus 2250. Power supply device 2240 may communicate with another element through optical bus 2250. User interface 2230 may receive input from a user and provide output to the user.

[0120] Although the inventive concept has been particularly shown and described with reference to the embodiments of the inventive concept, it should be understood that various changes in form and details may be made therein without departing from the spirit and scope of the claims. For example, although the substrate 302 of the IC device 1000 has been described as a bulk silicon or SOI substrate, other semiconductor crystalline materials such as bulk germanium and germanium-on-insulator substrates may be used.

Claims

1. An integrated circuit device, comprising: Optical integrated circuit substrates; a local trench formed in the optical integrated circuit substrate; a photoelectric element, the photoelectric element comprising a photoelectric conversion layer formed in the local groove; as well as an optical waveguide optically coupled to the photoelectric conversion layer of the photoelectric element, The lowermost surface of the optical waveguide is higher than the lowermost surface of the photoelectric conversion layer. wherein the lowermost surface of the photoelectric conversion layer contacts the upper surface of the optical integrated circuit substrate in the local groove, The photoelectric conversion layer includes a plurality of semiconductor layers, the plurality of semiconductor layers include a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer, the first semiconductor layer includes an undoped intrinsic semiconductor material, the second semiconductor layer includes a doped semiconductor material, and the uppermost surface of the first semiconductor layer is formed to be located at the same level as the lowermost surface of the optical waveguide or at a lower level than the lowermost surface of the optical waveguide.

2. The integrated circuit device according to claim 1, further comprising: a first conductive line electrically connected to the optical integrated circuit substrate; as well as a second conductive line, the second conductive line being electrically connected to the photoelectric conversion layer, The photovoltaic element is a vertical photovoltaic element.

3. The integrated circuit device according to claim 1, wherein: The optical integrated circuit substrate includes a silicon-on-insulator substrate including a base silicon layer, a buried insulating layer on the base silicon layer, and a silicon layer on the buried insulating layer.

4. The integrated circuit device according to claim 3, in, The local trench is formed in the buried insulating layer of the silicon-on-insulator substrate, wherein the optical waveguide comprises a core formed by the silicon layer of the silicon-on-insulator substrate, Wherein, the first semiconductor layer is located on the basic silicon layer.

5. The integrated circuit device according to claim 1, wherein: The optical integrated circuit substrate includes a bulk silicon substrate.

6. The integrated circuit device according to claim 5, in, The local trench is formed in an upper portion of the bulk silicon substrate, wherein a buried insulating layer is formed in the local trench of the bulk silicon substrate, The optical waveguide comprises a core located on the buried insulating layer, and the core comprises a silicon layer.

7. The integrated circuit device according to claim 1, wherein: The optical integrated circuit substrate comprises a double silicon-on-insulator substrate, which comprises a base silicon layer, a first buried insulating layer located on the base silicon layer, a buried silicon layer located on the first buried insulating layer, a second buried insulating layer located on the buried silicon layer, and a silicon layer located on the second buried insulating layer.

8. The integrated circuit device according to claim 7, in, The local trench is formed in the second buried insulating layer of the double silicon-on-insulator substrate, The optical waveguide comprises a core formed by the silicon layer of the double silicon-on-insulator substrate, The first semiconductor layer is located on the buried silicon layer.

9. The integrated circuit device of claim 1, further comprising an electronic integrated circuit device formed on the optical integrated circuit substrate.

10. An integrated circuit device, comprising: Optical integrated circuit substrates; a local trench formed in the optical integrated circuit substrate; a buried insulating layer formed in the local trench; an optoelectronic element, the optoelectronic element comprising a photoelectric conversion layer formed in the local trench, the optoelectronic element being located on the buried insulating layer, the photoelectric conversion layer being separated from the semiconductor portion of the optical integrated circuit substrate by the buried insulating layer; as well as an optical waveguide optically coupled to the photoelectric conversion layer of the photoelectric element, The lowermost surface of the optical waveguide is higher than the lowermost surface of the photoelectric conversion layer. wherein the lowermost surface of the photoelectric conversion layer contacts the buried insulating layer in the local trench, The photoelectric conversion layer includes a first semiconductor layer and a metal layer located on the first semiconductor layer, the first semiconductor layer includes an undoped intrinsic semiconductor material, and the uppermost surface of the first semiconductor layer is formed to be located at the same level as the lowermost surface of the optical waveguide.

11. The integrated circuit device according to claim 10, further comprising: a first conductive line electrically connected to a first portion of the metal layer of the photoelectric conversion layer; as well as a second conductive line electrically connected to a second portion of the metal layer of the photoelectric conversion layer, Wherein, the optoelectronic element is a lateral optoelectronic element.

12. The integrated circuit device according to claim 10, in, The optical integrated circuit substrate comprises a silicon-on-insulator substrate, wherein the silicon-on-insulator substrate comprises a base silicon layer, the buried insulating layer on the base silicon layer, and a silicon layer on the buried insulating layer, The optoelectronic element is separated from the upper surface of the base silicon layer by a portion of the buried insulating layer.

13. The integrated circuit device according to claim 12, in, The local trench is formed in the buried insulating layer of the silicon-on-insulator substrate, wherein the photoelectric conversion layer is formed to be in contact with the buried insulating layer of the silicon-on-insulator substrate and is electrically insulated by the buried insulating layer, wherein the optical waveguide comprises a core formed by the silicon layer of the silicon-on-insulator substrate, Wherein, the first semiconductor layer is located on the buried insulating layer.

14. The integrated circuit device according to claim 10, in, The optical integrated circuit substrate comprises a bulk silicon substrate, the local trench is formed in the bulk silicon substrate, wherein the photoelectric conversion layer is separated from the bottom of the local trench by the buried insulating layer, wherein the local trench is formed in an upper portion of the bulk silicon substrate, and a buried insulating layer is formed in the local trench of the bulk silicon substrate, The optical waveguide comprises a core located on the buried insulating layer, and the core comprises a silicon layer.

15. An integrated circuit device, comprising: Optical integrated circuit substrates; a local trench formed in the optical integrated circuit substrate; a photoelectric element including a photoelectric conversion layer formed in the local trench and in contact with one or more surfaces of the local trench or in contact with a buried insulating layer buried in the local trench; as well as an optical waveguide core layer, the optical waveguide core layer being optically coupled to the photoelectric conversion layer, The lowermost surface of the optical waveguide core layer is higher than the lowermost surface of the photoelectric conversion layer. wherein the lowermost surface of the photoelectric conversion layer contacts the upper surface of the optical integrated circuit substrate in the local groove, The photoelectric conversion layer includes a plurality of semiconductor layers, the plurality of semiconductor layers include a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer, the first semiconductor layer includes an undoped intrinsic semiconductor material, the second semiconductor layer includes a doped semiconductor material, and the uppermost surface of the first semiconductor layer is formed to be located at the same level as the lowermost surface of the optical waveguide core layer or at a lower level than the lowermost surface of the optical waveguide core layer.

16. The integrated circuit device according to claim 15, wherein: The top surface of the photoelectric conversion layer is formed on the optical integrated circuit substrate at a higher level in a vertical direction than the top surface of the optical waveguide core layer.

17. The integrated circuit device according to claim 15, in, The top surface of the photoelectric conversion layer is formed on the optical integrated circuit substrate at a level lower than the top surface of the optical waveguide core layer in a vertical direction, Wherein, the photoelectric conversion layer is formed to extend on the optical waveguide core layer.

18. The integrated circuit device according to claim 15, in, The top surface of the photoelectric conversion layer is formed on the optical integrated circuit substrate in a vertical direction at the same level as the top surface of the optical waveguide core layer, Wherein, a grating is formed on the top surface of the photoelectric conversion layer.

19. The integrated circuit device according to claim 15, in, An insulating layer is formed between the first semiconductor layer and the second semiconductor layer of the photoelectric conversion layer, The first semiconductor layer is evanescently coupled with the second semiconductor layer.

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