Method for reducing dark current of back-illuminated image sensor and back-illuminated image sensor

Abstract

The present invention provides a method for reducing the dark current of a back-illuminated image sensor. Instead of using the method of connecting the substrate through P-type heavily doped vias, a deep P-type doped region is used to connect the P-type doped well regions of adjacent pixel units, thereby reducing the connection resistance between pixel units, realizing the connection of the upper and lower rows of the pixel array, and then being able to cancel the substrate connection in the middle of the array, eliminating the influence of the dark current of the ground contact in the pixel array. The imaging quality is optimized through experimental data verification, and the overall performance of the image sensor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular, to a method for reducing dark current of a back-illuminated image sensor and a back-illuminated image sensor. Background Art

[0002] CMOS image sensors have the advantages of simple process, easy integration with other devices, small size, light weight, low power consumption, low cost, etc. Therefore, with the development of technology, CMOS image sensors are increasingly replacing CCD image sensors and being applied to various electronic products. Currently, CMOS image sensors have been widely used in static digital cameras, camera phones, digital video cameras, medical imaging devices (such as gastroscopes), vehicle imaging devices, etc.

[0003] CMOS image sensors can be divided into front-illuminated image sensors and back-illuminated image sensors according to the order of the device layers through which light irradiates. In existing back-illuminated image sensors, dark current is an important factor affecting the performance of pixel units.

[0004] In an image sensor, a pixel array is the core unit of the device. In order to isolate MOS transistor devices in existing back-illuminated image sensors, one way is to choose to make a shallow trench isolation structure (STI) in the surrounding area of the device. However, STI surface isolation results in a relatively large resistance. If a ground voltage is connected outside the array, an obvious ground voltage drop will be generated in the pixel array, and thus a "black pot" phenomenon that varies with the distance of the pixel from the array boundary will be reflected in the imaging pattern. For this reason, based on STI surface isolation, the method of making substrate contacts in the pixel array can alleviate or eliminate the "black pot" phenomenon. In addition, the STI region is filled with silicon oxide as an insulating isolation layer. Although it can better isolate device current, as the pixel size gradually decreases, the requirement for light absorption utilization also gradually increases. Designing to remove STI and instead using a co-grounded p-type doped region for isolation can improve the area utilization rate of silicon. However, the too large substrate resistance makes it impossible to remove the ground electrode in the array. Therefore, the performance of the sensor will be affected by the dark current generated by the ground electrode. The magnitude of this dark current varies with the actual voltage of the ground electrode, so it will bring a "white pot" phenomenon of uneven regional distribution to imaging. Please continue to refer to Figure 1 、 Figure 2 , Figure 1 which is a schematic diagram of the pixel structure of the CMOS image sensor of the prior art of the present invention, Figure 2 is Figure 1 a side cross-sectional view along the A-A direction.

[0005] Figure 1It is a pixel unit structure in which four photosensitive units share a floating diffusion region (FD) 130 respectively. The illustrated pixel array structure does not adopt the STI method in design, but uses a P-type doped region 131 with a common ground in the middle area for isolation. Figure 2 It shows a side cross-sectional view of the P-type doped region. As described above, an excessive substrate resistance will cause the grounding electrode of the pixel array to be unable to be removed, resulting in a serious dark current phenomenon, which will further affect the imaging effect of the image sensor. Summary of the Invention

[0006] The purpose of the present invention is to provide a method for reducing the dark current of a back-illuminated image sensor.

[0007] The back-illuminated image sensor cancels the grounded P-type doped through hole, and uses a deep P-type doped region to connect the P-type doped well regions of adjacent pixel units, reducing the connection resistance between pixel units and realizing the connection of the upper and lower rows of the pixel array; furthermore, the substrate connection of the pixel array can be cancelled, eliminating or reducing the influence of the dark current of the ground contact in the pixel array. Preferably, according to the method for reducing the dark current of a back-illuminated image sensor described in claim 1, it is characterized in that a surface P-type doped region is used to connect the pinned layer regions of adjacent pixel units, thereby reducing the connection resistance between pixel units and reducing the dark current.

[0008] Preferably, it is characterized in that the scheme is applied to a structure with STI isolation or without STI isolation.

[0009] Preferably, when there is no STI structure in the pixel structure, a negative voltage is provided on the isolation MOS transistor between pixel units, so that the MOS transistor channel enters the accumulation state, thereby reducing the channel resistance and enhancing the substrate connection ability on both sides of the isolation transistor.

[0010] Preferably, the depth of the deep P-type doped region is 0.05um - 1um.

[0011] Preferably, the depth of the surface P-type doped region does not exceed 0.1um.

[0012] Preferably, the negative voltage depends on the electric field intensity on both sides of the isolation MOS transistor and is 0 to -3.3V.

[0013] A back-illuminated image sensor.

[0014] The back-illuminated image sensor includes: a pixel array having a plurality of pixel units.

[0015] There is a deep P-type doped region between the pixel units, and the deep P-type doped region connects the P-type well regions of adjacent pixel units.

[0016] A surface P-type doped region, a pinned layer region adapted to connect adjacent pixel units;

[0017] Preferably, the pixel array further includes: an isolation MOS transistor that provides a negative pressure between pixel units;

[0018] Preferably, the negative pressure depends on the electric field intensity on both sides of the isolation MOS transistor and is 0 to -3.3V;

[0019] Preferably, the depth of the deep P-type doped region is 0.05um to 1um.

[0020] The present invention does not adopt the method of connecting the substrate through P-type heavily doped vias, but adopts a deep P-type doped region to connect the P-type doped well regions of adjacent pixel units to achieve the connection between the upper and lower rows of the pixel array; adopts a surface P-type doped region to connect the pinned layer structures of adjacent pixel units; when there is no STI structure in the pixel structure, a negative voltage is provided on the isolation MOS transistor between pixel units, so that the MOS transistor channel enters the accumulation state to reduce the connection resistance between pixel units, eliminating the influence of the dark current of the ground contact in the array. The imaging quality is optimized through experimental data verification, improving the overall performance of the image sensor. Description of the Drawings

[0021] Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0022] Figure 1 It is a schematic diagram of the pixel structure of a prior art CMOS image sensor;

[0023] Figure 2 For Figure 1 A side cross-sectional view along the A-A direction;

[0024] Figure 3 It is a schematic diagram of the pixel structure of a CMOS image sensor according to an embodiment of the present invention;

[0025] Figure 4 For Figure 3 A side cross-sectional view of 230 in the vertical direction;

[0026] Figure 5 For Figure 3 A side cross-sectional view of 250 in the horizontal direction in;

[0027] Figure 6 For Figure 3 A side cross-sectional view of 240 in the horizontal direction in;

[0028] Figure 7 For Figure 3 A comparison diagram of the connection resistance values of adjacent pixel units in the solution with the prior art.

[0029] In the figures, throughout the different views, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed implementation mode

[0030] To solve the problems in the above-mentioned prior art, the present invention provides a method for reducing the dark current of a back-illuminated image sensor. The back-illuminated image sensor cancels the grounded P-type doped vias and uses a deep P-type doped region to connect the P-type doped well regions of adjacent pixel units, reducing the connection resistance between pixel units and realizing the connection of the upper and lower rows of the pixel array; thereby, the substrate connection of the pixel array can be cancelled, and the influence of the dark current of the ground contact in the pixel array can be eliminated or reduced.

[0031] In the following detailed description of the preferred embodiments, reference will be made to the accompanying drawings which form a part of the present invention. The accompanying drawings illustrate, by way of example, specific embodiments that can implement the present invention. The exemplary embodiments are not intended to exhaust all embodiments according to the present invention. It can be understood that other embodiments can be utilized without departing from the scope of the present invention, and structural or logical modifications can also be made. Therefore, the following detailed description is not restrictive, and the scope of the present invention is defined by the appended claims.

[0032] Figure 3 Schematic diagram of the pixel structure of a CMOS image sensor according to an embodiment of the present invention;

[0033] As Figure 3 shown, there are four pixel units shown in the figure, and the four pixel units respectively have a photosensitive unit 260 and a transfer transistor 270. In the layout design of the pixel units, there are N-type wells (NWELL) 210, 220 between the upper and lower pixel units; please refer to Figure 4 , Figure 4 is Figure 3 a side cross-sectional view along the vertical direction of 230 in ; on some boundaries between pixel units, an active follower transistor (SF) or a reset transistor (RST) and the corresponding source-drain electrode n+ regions are often placed. Due to the need for threshold voltage adjustment, these MOS transistor channels are often n-type doped. To protect the performance of these devices, the p-type conductive connection between pixels needs to bypass the surface n-doped region. Therefore, a deep p-type doped region (PWELL) 230 is used here to connect the pixel regions on both sides. In this embodiment, the original n-type doped region is bypassed to connect the deep p-type doped well regions, so it may also be used to connect the two sides of any n-type doped region. In this embodiment, the connection resistance between pixel units is reduced, and the connection of the upper and lower rows of the pixel array is realized; thereby, the substrate connection of the pixel array can be cancelled, and the depth of the deep P-type doped region is 0.05 um - 1 um. Figure 4Among them, 410 is a MOS transistor (cross-section in the vertical channel direction), 420 is the n-type region in the MOS transistor channel, 430 is the p-type passivation region on the pixel surface, and 440 is the deep P-type doped region PWELL doping channel in this embodiment.

[0034] Please continue to refer to Figure 3 and Figure 5 , Figure 5 is Figure 3 a side cross-sectional view of 250 in the horizontal direction in Figure 5 This is another method for reducing the dark current of a back-illuminated image sensor in an embodiment of the present invention. Figure 5 is the pinning layer located in the surface area of the photosensitive unit 270 in the pixel unit. In order to avoid dark current generated by silicon wafer surface defects during pixel reading, a relatively thick surface p-type doped region passivation is performed on the shallow surface in the process. With the help of this surface p-type doped region passivation, conductive connections can also be made between adjacent pixels. The surface P-type doped region connects the pinning layer structures of adjacent pixel units, thereby reducing the resistance between pixel units and reducing the dark current. This solution is mainly used for connecting adjacent pixels without device separation. Figure 5 is a schematic diagram of this solution. In the figure, 510 is the original p-type pinning layer structure on the pixel surface, and 520 is the surface p-type doped region in this embodiment. The depth of the surface P-type doped region does not exceed 0.1 um. Since there is no depth difference between this doping and both sides, the surface p-type doped region passivation doping can be directly used to complete the connection in one time in the design.

[0035] It should be noted that Figure 4 , Figure 5 the specific implementation method in

[0036] Please continue to refer to Figure 3 and Figure 6 , Figure 6 is Figure 3 a side cross-sectional view of 240 in the horizontal direction in Figure 6 This is yet another method for reducing the dark current of a back-illuminated image sensor in an embodiment of the present invention. Figure 6In a pixel, in a pixel array structure applied to a non-STI design, since there is an N-type MOS isolation transistor 240 with unregulated doping of the threshold voltage in the pixel unit, the channel is p-type doped. Such MOS transistors are generally used to isolate different signal electrodes. For the N-type MOS isolation transistor 240, a negative voltage is applied to its gate, and the negative voltage depends on the electric field strength on both sides of the N-type MOS isolation transistor. In this embodiment, it is 0 to -3.3V. An excessive voltage will cause a sharp increase in noise; applying a negative voltage within the range of this embodiment can make the channel enter the accumulation state, improve the p-type doping degree, thereby reducing the channel resistance and enhancing the substrate connection ability on both sides of the N-type MOS isolation transistor. Figure 6 This is a schematic diagram of the solution. In the figure, 610 is an N-type MOS isolation transistor (cross-section in the vertical channel direction), and 620 is the p-type doping regions on both sides of the N-type MOS isolation transistor. After applying a negative voltage at the gate of 610, an accumulated hole layer 630 will be induced in the channel. The hole layer 630 reduces the resistance at this position, so the resistance between the two p-type doping regions on both sides decreases accordingly. The accumulated holes in the N-type MOS isolation transistor form a connection between the two sides.

[0037] Please continue to refer to Figure 7 , Figure 7 is Figure 3 a comparison graph of the connected resistance values of adjacent pixel units in the solution with the prior art.

[0038] In the pixel array, Figure 4 , Figure 5 , Figure 6 By comprehensively using the design solutions, the connected resistance of the pixel array can be significantly reduced. Figure 7 This is the connected resistance value of adjacent pixels obtained by using computer-aided semiconductor process simulation. The application of this solution significantly reduces the adjacent pixel resistance to about one-tenth, which is significantly beneficial to the performance of the pixel array's peripheral grounding and reduces the non-uniformity of the working state caused by the grounding distance.

[0039] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, in any case, the embodiments should be regarded as exemplary and non-limiting. In addition, obviously, the word "including" does not exclude other elements and steps, and the term "one" does not exclude a plurality. A plurality of elements stated in the apparatus claims can also be implemented by one element. The words first, second, etc. are used to denote names and do not denote any specific order.

Claims

1. A method for reducing the dark current of a back-illuminated image sensor, characterized in that, the back-illuminated image sensor cancels the grounded P-type doped vias, transistors are placed on part of the boundaries between the pixel units of the image sensor, the transistors have n-type doped regions, a deep P-type doped region is used to connect the P-type doped well regions of adjacent pixel units, the deep P-type doped region bypasses the n-type doped region, reduces the connection resistance between pixel units, and realizes the connection between the upper and lower rows of the pixel array; furthermore, the substrate connection of the pixel array is cancelled, and the influence of the dark current of the grounded contacts in the pixel array is eliminated or reduced.

2. The method for reducing the dark current of a back-illuminated image sensor according to claim 1, characterized in that, a surface P-type doped region is used to connect the pinned layer structures of adjacent pixel units, thereby reducing the resistance between pixel units and reducing the dark current.

3. The method for reducing the dark current of a back-illuminated image sensor according to any one of claims 1 or 2, characterized in that, the solution of using a surface P-type doped region to connect the pinned layer structures of adjacent pixel units is applied to a structure with STI isolation or without STI isolation.

4. The method for reducing the dark current of a back-illuminated image sensor according to claim 1, characterized in that, when there is no STI structure in the pixel structure, a negative voltage is provided on the isolation MOS transistor between pixel units, so that the isolation MOS transistor channel enters the accumulation state; thereby reducing the channel resistance and enhancing the connection ability of the substrates on both sides of the isolation transistor.

5. The method for reducing the dark current of a back-illuminated image sensor according to claim 1, characterized in that, the depth of the deep P-type doped region is 0.05 um - 1 um.

6. The method for reducing the dark current of a back-illuminated image sensor according to claim 2, characterized in that, the depth of the surface P-type doped region does not exceed 0.1 um.

7. The method for reducing the dark current of a back-illuminated image sensor according to claim 4, characterized in that, the negative voltage depends on the electric field intensity on both sides of the isolation MOS transistor and is 0 to -3.3 V.

8. A back-illuminated image sensor, characterized in that, the back-illuminated image sensor includes: a pixel array having a plurality of pixel units; transistors are placed on part of the boundaries between the pixel units, the transistors have n-type doped regions, there is a deep P-type doped region between the pixel units, the deep P-type doped region connects the P-type well regions of adjacent pixel units, the deep P-type doped region is not grounded, and the deep P-type doped region bypasses the n-type doped region; a surface P-type doped region, suitable for connecting the pinned layer structures of adjacent pixel units.

9. The back-illuminated image sensor according to claim 8, characterized in that, the pixel array further includes: an isolation MOS transistor between pixel units that provides a negative voltage.

10. The back-illuminated image sensor according to claim 9, characterized in that, the negative voltage depends on the electric field intensity on both sides of the isolation MOS transistor and is 0 to -3.3 V.

11. The back-illuminated image sensor according to claim 8, characterized in that, The depth of the deep P-type doping region is from 0.05 um to 1 um.

12. The back-illuminated image sensor according to claim 8, wherein, the depth of the surface P-type doping region does not exceed 0.1 um.

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