Semiconductor device and method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: a semiconductor substrate as a body region; a doped region extending from the first surface of the body region into the body region; a gate stack located on the first surface of the body region; a conductive channel comprising a groove penetrating the body region along the thickness direction of the body region and a conductive material filled in the groove, and the conductive channel is separated from the doped region; and a drain electrode in contact with the conductive channel on the second surface of the body region, wherein the gate stack receives a control voltage, and the drain electrode is connected to the doped region through the conductive channel and the channel between the doped region and the conductive channel. Since the conductive channel of the semiconductor device connects the first surface and the second surface of the body region, and the drain electrode is in contact with the conductive channel on the second surface, after the device is turned on, the original epitaxial layer and substrate are omitted, thereby reducing the on-resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and more specifically, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Trench VDMOS (vertical double-diffused metal oxide semiconductor field effect transistor) forms a gate by growing a gate dielectric layer on the sidewall of the trench and filling it with conductive materials. This trench gate structure greatly improves the utilization efficiency of the planar area of ​​the power device, allowing a larger device unit channel width and current density per unit area, thereby enabling the device to obtain a greater current conduction capability. Currently, trench VDMOS has been widely used in many fields such as motor speed regulation, inverters, power supplies, electronic switches, audio, and automotive electrical appliances.

[0003] Trench VDMOS is also called UMOS because it contains a U-shaped trench structure. Figure 1 FIG. 2 shows a schematic diagram of the structure of a UMOS device in the prior art. Figure 1 As shown, a typical UMOS device includes a substrate 10, an epitaxial layer 11, a body region 12, a U-shaped trench, a source region 15, a contact hole 16 and a channel 17. A gate dielectric layer 13 is formed on the sidewall of the U-shaped trench, and a conductive material as a gate conductor 14 is filled in the U-shaped trench.

[0004] The on-resistance of a conventional UMOS device includes: substrate resistance Rsub, epitaxial resistance Repi, accumulation region resistance Racc, channel resistance Rch, source resistance Rsc, and hole contact resistance Rcon. After the device is turned on, the vertically flowing current (arrow direction) needs to pass through the entire device, especially through a high resistance region, the epitaxial layer 11, and the resistance of the epitaxial resistance Repi is very large, resulting in a very high on-resistance problem for the device. Summary of the invention

[0005] In view of this, the present invention provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device has a smaller on-resistance.

[0006] According to one aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate as a body region, having a first surface and a second surface relative to each other; a doped region, extending from the first surface of the body region into the body region; a gate stack, located on the first surface of the body region; a conductive channel, comprising a groove penetrating the body region along the thickness direction of the body region and a conductive material filled in the groove, and the conductive channel is separated from the doped region; and a drain electrode, contacting the conductive channel on the second surface of the body region, wherein the body region is of a first doping type, the doped region and the conductive channel are of a second doping type, the first doping type is opposite to the second doping type, the gate stack receives a control voltage, and the drain electrode is connected to the doped region through the conductive channel and the channel between the doped region and the conductive channel.

[0007] Preferably, the channel is close to the first surface of the body region.

[0008] Preferably, the gate stack comprises: a gate dielectric layer covering a first surface of the body region; and a gate conductor layer located on the gate dielectric layer, wherein the gate conductor layer at least corresponds to the body region between the doped region and the conductive channel.

[0009] Preferably, it also includes: an interlayer dielectric layer, covering the gate dielectric layer and the gate conductor layer; a first conductive plug, passing through the interlayer dielectric layer and the gate dielectric layer, and contacting the doped region and the body region respectively; a second conductive plug, passing through the interlayer dielectric layer and contacting the gate conductor layer; a source electrode, located on the surface of the interlayer dielectric layer and contacting the first conductive plug; and a gate electrode, located on the surface of the interlayer dielectric layer and contacting the second conductive plug.

[0010] Preferably, an isolation layer is further included, which is located between the second surface of the body region and the drain electrode, wherein the conductive path passes through the isolation layer to contact the drain electrode, or the drain electrode passes through the isolation layer to contact the conductive path.

[0011] Preferably, in a cross section perpendicular to the thickness direction of the body region, a plurality of the doped regions are arranged in an array in the body region, each of the doped regions is surrounded by the conductive channel, wherein a channel between each of the doped regions and the conductive channel is in the shape of a U-shaped rectangle; or, in a cross section perpendicular to the thickness direction of the body region, a plurality of the doped regions are rectangular and are arranged in parallel in the body region along the long side direction of the rectangle, and at least one conductive channel is spaced between two adjacent doped regions, wherein a channel between each of the doped regions and the conductive channel is in the shape of a rectangle.

[0012] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: utilizing a semiconductor substrate as a body region, the body region having a first surface and a second surface relative to each other; forming a doped region extending from the first surface of the body region to the body region; forming a gate stack on the first surface of the body region; forming a conductive channel penetrating the body region along a thickness direction of the body region, the conductive channel being separated from the doped region; and forming a drain electrode, the drain electrode being in contact with the conductive channel on the second surface of the body region, wherein the body region is of a first doping type, the doped region and the conductive channel are of a second doping type, the first doping type is opposite to the second doping type, the gate stack receives a control voltage, and the drain electrode is connected to the doped region through the conductive channel and a channel between the doped region and the conductive channel.

[0013] Preferably, the step of forming the gate stack includes: forming a gate dielectric layer covering a first surface of the body region; and forming a gate conductor on the gate dielectric layer, wherein the gate conductor corresponds to at least the body region between the doped region and the conductive channel.

[0014] Preferably, it also includes: forming an interlayer dielectric layer covering the gate dielectric layer and the gate conductor layer; forming a first conductive plug passing through the interlayer dielectric layer, the gate dielectric layer and the doped region, the first conductive plug being in contact with the doped region; forming a second conductive plug passing through the interlayer dielectric layer, the second conductive plug being in contact with the gate conductor layer; forming a source electrode on the surface of the interlayer dielectric layer, the source electrode being in contact with the first conductive plug; and forming a gate electrode on the surface of the interlayer dielectric layer, the gate electrode being in contact with the second conductive plug.

[0015] Preferably, the method further comprises forming an isolation layer between the second surface of the body region and the drain electrode, wherein the conductive path passes through the isolation layer and contacts the drain electrode.

[0016] Preferably, the step of forming the conductive channel includes: forming a first trench extending from the first surface of the body region into the body region; filling the first trench with a conductive material; forming a second trench extending from the surface of the isolation layer into the body region, the second trench exposing a portion of the conductive material in the first trench; and filling the second trench with a conductive material, wherein the first trench contacts the conductive material in the second trench to form the conductive channel, or, trench etches the body region to form a through hole passing through the body region; and filling the through hole with a conductive material to form the conductive channel.

[0017] The semiconductor device and the manufacturing method thereof provided by the present invention use a semiconductor substrate as the body region of the device, and form a conductive channel penetrating the body region in the body region, and the drain electrode contacts the conductive channel on the second surface of the body region, so when the device is turned on, the drain electrode and the channel are directly connected through the conductive channel. Compared with the UMOS device in the prior art, the epitaxial layer and the substrate resistance are no longer used as components of the on-resistance, that is, the epitaxial resistance Repi and the substrate resistance Rsub originally connected in series in the traditional UMOS device are all removed, thereby reducing the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments are briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0019] Figure 1 The figure shows a schematic structural diagram of a UMOS device in the prior art.

[0020] Figure 2a A schematic structural diagram of a semiconductor device according to an embodiment of the present invention is shown.

[0021] Figure 2b Shows Figure 2a Schematic cross-sectional view of a semiconductor device in FIG.

[0022] Figure 2c Schematic cross-sectional views of semiconductor devices according to other embodiments of the present invention are shown.

[0023] Figures 3a to 3n 1 and 2 show cross-sectional views at various stages of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

[0024] Figures 4a to 4d A cross-sectional view showing a partial stage of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0026] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0027] If the purpose is to describe the situation of being directly on another layer or another area, this article will use the expression "directly on..." or "on... and adjacent to...".

[0028] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0029] The present invention may be embodied in various forms, some examples of which will be described below.

[0030] Figure 2a A schematic structural diagram of a semiconductor device according to an embodiment of the present invention is shown.

[0031] like Figure 2a As shown, the semiconductor device provided by the embodiment of the present invention includes: a body region 120, a conductive channel 130, a gate stack 140, a doped region 150, an interlayer dielectric layer 160, a first conductive plug 171, a second conductive plug 172, a source electrode 181, a gate electrode 182, a drain electrode 183 and an isolation layer 109b.

[0032] The semiconductor substrate can be directly used as the body region 120, and the body region 120 has a first surface and a second surface opposite to each other. The drain electrode 183 is located on the second surface of the body region 120, and the isolation layer 109b is located between the drain electrode 183 and the second surface of the body region 120. The conductive channel 130 includes a groove and a conductive material filled in the groove, wherein the groove extends from the first surface of the body region 120 to the second surface of the body region 120 and penetrates the body region 120, so that the conductive channel 130 passes through the body region 120 and contacts the drain electrode 183. The depth of the conductive channel 130 is not less than the thickness of the semiconductor substrate. In this embodiment, the conductive channel 130 also passes through the isolation layer 109b. In some other embodiments, the conductive channel 130 only extends to the second surface of the body region 120, that is, the depth of the conductive channel 130 is equal to the thickness of the semiconductor substrate, and the drain electrode 183 passes through the isolation layer 109b and contacts the conductive channel 130. The doped region 150 extends from the first surface of the body region 120 into the body region 120 , and the conductive channel 130 and the doped region 150 are separated by the body region 120 .

[0033] The body region 120 is of a first doping type, the conductive channel 130 and the doping region 150 are of a second doping type, the first doping type is opposite to the second doping type, wherein the second doping type is selected from one of P-type doping and N-type doping, and the first doping type is selected from the other of P-type doping and N-type doping.

[0034] In this embodiment, the first doping type is selected from P-type doping, and the second doping type is selected from N-type doping. In other embodiments, the first doping type is selected from N-type doping, and the second doping type is selected from P-type doping.

[0035] The gate stack 140 specifically includes a gate dielectric layer 141 and a gate conductor layer 142 which are stacked, wherein the gate dielectric layer 141 covers the first surface of the body region 120, and the gate conductor layer 142 is located on the gate dielectric layer 141. The gate conductor layer 142 is located above the conductive channel 130, and extends along the gate dielectric layer 141 to both sides of the conductive channel 130 to cover the body region 120 between the doped region 150 and the conductive channel 130. The gate stack 140, or more precisely, the gate conductor layer 142 receives a control voltage, and a channel 190 is formed between the doped region 150 and the conductive channel 130. The drain electrode 183 is connected to the doped region 150 through the conductive channel 130 and the channel 190. The channel 190 is adjacent to the gate dielectric layer 141 and close to the surface of the body region 120.

[0036] The interlayer dielectric layer (ILD) 160 covers the gate dielectric layer 141 and the gate conductor layer 142. The first conductive plug 171 passes through the interlayer dielectric layer 160 and the gate dielectric layer 141, and contacts the doped region 150 and the body region 120 at the same time. That is, the first conductive plug 171 passes through the interlayer dielectric layer 160, the gate dielectric layer 141 and the doped region 150, and contacts the body region 120 below the doped region 150. The second conductive plug 172 passes through the interlayer dielectric layer 160 and contacts the gate conductor layer 142. In this embodiment, the second conductive plug 172 passes through the interlayer dielectric layer 160 and contacts the surface of the gate conductor layer 142 away from the body region 120; in other embodiments, the second conductive plug 172 passes through the interlayer dielectric layer 160 and enters the gate conductor layer 142.

[0037] The source electrode 181 is located on the surface of the interlayer dielectric layer 160 and contacts the first conductive plug 171. The gate electrode 182 is located on the surface of the interlayer dielectric layer 160 and contacts the second conductive plug 172. Of course, the source electrode 181 and the gate electrode 182 are not in direct contact with each other.

[0038] Figure 2b Shows Figure 2a A schematic cross-sectional view of a semiconductor device in FIG. 1 , wherein the cross-sectional view corresponding to the source connection region S is Figure 2aThe cross-sectional view corresponding to the gate connection region G is taken along the position indicated by arrow A in FIG. Figure 2a The image is taken along the position indicated by arrow B.

[0039] like Figure 2a and 2b As shown, in a cross section perpendicular to the thickness direction of the body region 120, a plurality of doped regions 150 are arranged in an array in the body region 120, and each doped region 150 is surrounded and enclosed by a conductive channel 130. Among them, the channel 190 between each doped region 150 and the conductive channel 130 is in a U-shaped shape, so as to increase the current density. The plurality of doped regions 150 are connected to the same source electrode 181 through the first conductive plug 171. The gate conductor layer 142 is connected to the same gate electrode 182 through the plurality of second conductive plugs 172, and the plurality of conductive channels 130 are connected to the same drain electrode 183.

[0040] It should be noted that Figure 2b In the embodiment, there are 4 doping regions 150, which are arranged in a 2×2 array. In the specific implementation process, the number of doping regions 150 in each cell can reach hundreds of thousands or even millions, and the arrangement method can be reasonably set according to the product performance requirements, which will not be repeated here.

[0041] like Figure 2c As shown, in some other embodiments, in a cross section perpendicular to the thickness direction of the body region 120, the multiple doping regions 150 are rectangular, arranged in parallel in the body region 120 along the long side direction of the rectangle, and at least one conductive channel 130 is spaced between two adjacent doping regions 150. Among them, the channel 190 between each doping region 150 and the conductive channel 130 is rectangular. Each doping region 150 is connected to multiple uniformly arranged first conductive plugs 171, and multiple doping regions 150 are connected to the same source electrode 181 through the first conductive plugs 171. Multiple gate conductor layers 142 are connected to the same gate electrode 182 through corresponding second conductive plugs 172, and multiple conductive channels 130 are connected to the same drain electrode 183.

[0042] It should be noted that Figure 2c In the embodiment, there are two doping regions 150 arranged in parallel. In the specific implementation process, the number of doping regions 150 in each cell can reach hundreds of thousands or even millions, and the arrangement method can be reasonably set according to the product performance requirements, which will not be repeated here. Figures 3a to 3n The cross-sectional views of the method for manufacturing a semiconductor device according to the first embodiment of the present invention at various stages are shown. Figures 3a to 3n The method for manufacturing the semiconductor device of the present invention will be described in detail.

[0043] The method of the first embodiment of the present invention starts with a substrate, wherein the substrate is a P-type doped single crystal silicon substrate, which serves as the body region 120 of the semiconductor device of this embodiment. Figure 3a shown.

[0044] In this embodiment, the P-type doping impurity is boron (B), and the doping concentration of the body region 120 can be flexibly adjusted according to the breakdown voltage requirement of the device. However, the embodiment of the present invention is not limited thereto, and those skilled in the art can select a semiconductor substrate with an appropriate resistivity as required.

[0045] Since the channel 190 is formed in the body region 120 and close to the surface of the body region 120 when the device is formed and turned on, there is no need to consider the longitudinal concentration gradient of the doped impurities in the body region 120. It is only necessary to control the uniformity of the doped impurities on the surface of the body region 120, thereby reducing the difficulty of the doping process and making the channel resistance Rch and the threshold voltage Vt stable and easy to control after the device is turned on.

[0046] Furthermore, isolation layers 109a and 109b are formed on the first surface and the second surface of the body region 120, respectively. Figure 3b shown.

[0047] In this step, for example, the isolation layers 109a and 109b are formed by a thin film growth process. The isolation layers 109a and 109b have a high etching selectivity with the body region 120. In this embodiment, the isolation layers 109a and 109b are made of insulating materials such as silicon oxide and silicon nitride, and the thickness of the isolation layers 109a and 109b is not less than 100 angstroms.

[0048] However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings for the material and thickness of the isolation layers 109 a and 109 b as needed.

[0049] Furthermore, the isolation layer 109a on the first surface of the body region 120 is patterned to form a mask, such as Figure 3c shown.

[0050] In this step, the isolation layer 109 a is patterned by an etching process to form a mask having a plurality of windows 102 , wherein the plurality of windows 102 expose the first surface of the body region 120 .

[0051] Furthermore, the body region 120 is anisotropically etched through the window 102 to form a first trench 104a, such as Figure 3d shown.

[0052] In this step, the anisotropic etching is, for example, ion milling etching, plasma etching, reactive ion etching, or laser ablation. By controlling the etching time and etching rate, the first trench 104a extends from the first surface of the body region 120 to a predetermined depth in the body region 120. In this embodiment, the first trench 104a may be a U-shaped trench in a current UMOS.

[0053] Since in the subsequent steps, a conductive material will be filled in the first groove 104a to form a conductive channel, the on-resistance of the device mainly depends on the resistance of the conductive material in the conductive channel 130, and the shape and edge flatness of the first groove 104a will not have a significant impact on the quality of the device. Therefore, in the step of forming the first groove 104a, the inner surface of the first groove 104a does not need to be deliberately required to be very flat. In traditional UMOS devices, the device performance depends on the shape of the groove and the roughness of the groove sidewalls, so there are very high requirements for the manufacturing process of the groove. In summary, the device structure of this embodiment reduces the difficulty of controlling the groove etching process.

[0054] Furthermore, a conductive material is filled in the first trench 104a to form a first polysilicon layer 105a. Figure 3e shown.

[0055] In this step, for example, the first polysilicon layer 105a is formed by a CVD process. Thermal diffusion, ion implantation and subsequent annealing can be used to dope the first polysilicon layer 105a with a concentration not less than E18cm -3 In this embodiment, the first polysilicon layer 105a is, for example, in-situ N-type doped, with an impurity concentration of 1E19cm -3 After the first polysilicon layer 105 a is deposited, the mask (isolation layer 109 a ) is removed to expose the first surface of the body region 120 again. The first polysilicon layer 105 a extends from the first surface of the body region 120 into the body region 120 .

[0056] However, the embodiments of the present invention are not limited thereto, and those skilled in the art may flexibly adjust the parameters of the first polysilicon layer 105 a according to the filling effect of the first trench 104 a .

[0057] Furthermore, a gate dielectric layer 141 is formed on the first surface of the body region 120, such as Figure 3f shown.

[0058] In this step, for example, a thin film growth process is used to form the gate dielectric layer 141. The material of the gate dielectric layer 141 includes but is not limited to silicon oxide, and the thickness is not less than 50 angstroms.

[0059] However, the embodiments of the present invention are not limited thereto, and those skilled in the art may flexibly adjust the thickness of the gate dielectric layer 141 according to different requirements for the device threshold voltage Vt.

[0060] Further, the isolation layer 109b is patterned to form a mask, such as Figure 3f shown.

[0061] In this step, the isolation layer 109 b is patterned by an etching process to form a mask having a plurality of windows 103 , wherein the plurality of windows 103 expose the second surface of the body region 120 .

[0062] Furthermore, the body region 120 is anisotropically etched through the window 103 to form a second trench 104b, such as Figure 3g shown.

[0063] In this step, the anisotropic etching is, for example, ion milling etching, plasma etching, reactive ion etching, and laser ablation. By controlling the etching time, the second groove 104b is extended from the second surface of the body region 120 to a predetermined depth in the body region 120, and a portion of the first polysilicon layer 105a in the first groove 104a is exposed. In this embodiment, the shape of the second groove 104b can also be a U-shaped groove in the current UMOS.

[0064] It is easy to understand that in order to obtain the conductive channel 130 penetrating the body region 120 , the opening positions of the first trench 104 a and the second trench 104 b should remain opposite to each other.

[0065] Since in the subsequent steps, the conductive material will also be filled in the second groove 104b to form the conductive channel 130, and the shape and edge flatness of the second groove 104b will not have a significant impact on the quality of the device. Therefore, in the step of forming the second groove 104b, the inner surface of the second groove 104b does not need to be deliberately required to be very flat, thereby reducing the difficulty of controlling the etching process. In addition, since the shape of the conductive channel will not have a significant impact on the quality of the device, the positions of the first groove 104a and the second groove 104b can be roughly aligned, further reducing the process difficulty.

[0066] Furthermore, a second polysilicon layer 105b is formed in the second trench 104b, and a third polysilicon layer 105c is formed on the surface of the gate dielectric layer 141. Figure 3h shown.

[0067] In this step, for example, a CVD process is used to simultaneously deposit polysilicon material in the second trench 104b, on the surface of the gate dielectric layer 141, and on the surface of the isolation layer 109b. Thermal diffusion, ion implantation followed by annealing, etc. can also be used to simultaneously dope the second polysilicon layer 105b and the third polysilicon layer 105c with a concentration not less than E18cm-3 In this embodiment, the second polysilicon layer 105b and the third polysilicon layer 105c are, for example, in-situ N-type doped, and the impurity concentration is 1E19cm -3 The first polysilicon layer 105 a contacts the second polysilicon layer 105 b to form a conductive channel 130 .

[0068] The present invention does not particularly limit the doping concentrations of the first polysilicon layer 105 a and the second polysilicon layer 105 b to be completely consistent. In fact, the two can be reasonably adjusted and determined according to the resistance of the final conductive channel 130 .

[0069] However, the embodiments of the present invention are not limited thereto, and those skilled in the art may flexibly adjust the parameters of the second polysilicon layer 105 b according to the filling effect of the second trench 104 b .

[0070] Further, the polysilicon material on the surface of the isolation layer 109b is removed to expose the isolation layer 109b again, such as Figure 3i shown.

[0071] In this step, the second polysilicon layer 105b is planarized by, for example, etching or chemical mechanical polishing (CMP) processes. Preferably, annealing is performed before planarization so that a good PN junction is formed between the conductive channel 130 reused as the device drain region and the body region 120, and the doping impurities in the conductive channel 130 are more evenly distributed.

[0072] Furthermore, a gate conductor layer 142 is formed on the surface of the gate dielectric layer 141. Figure 3i shown.

[0073] In this step, for example, the third polysilicon layer 105 c is patterned by using photolithography and etching processes to form a gate conductor layer 142 . The gate dielectric layer 141 and the gate conductor layer 142 constitute a gate stack 140 .

[0074] In this embodiment, the gate conductor layer 142 is located above the conductive channel 130 and extends along the gate dielectric layer 141 to both sides of the conductive channel 130 by a preset length, so that the gate conductor layer 142 covers the channel 190 and the conductive channel 130 .

[0075] However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings for the thickness and doping concentration of the polysilicon layer as needed.

[0076] Furthermore, a doped region 150 extending from the surface of the body region 120 to the body region 120 is formed, such as Figure 3j shown.

[0077] In this step, a self-aligned implantation process is first used to implant N-type doping impurities from the first surface of the body region 120 into the body region 120. The gate conductor layer 142 made of polysilicon is used as a masking layer. After annealing, the doping impurities are diffused from the first surface of the body region 120 into the body region 120 to form a doping region 150. In this embodiment, the doping region 150 serves as the source region of the device, and the N-type doping impurity is arsenic (As), and the implantation dose is not less than E15cm -2 .

[0078] However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings for the doping impurities and doping concentration of the doping region 150 as needed, and reasonably adjust the annealing conditions according to actual needs.

[0079] Furthermore, an interlayer dielectric layer 160 is formed to cover the gate dielectric layer 141 and the gate conductor layer 142. Figure 3k shown.

[0080] In this step, for example, a thin film growth process is first used to deposit an insulating material, such as silicon oxide, silicon nitride, etc., on the surface of the gate dielectric layer 141 and the gate conductor layer 142. Then, for example, a CMP process is used to planarize the insulating material to form an interlayer dielectric layer 160. In this embodiment, the thickness of the planarized interlayer dielectric layer 160 is not less than 1000 angstroms.

[0081] However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings for the material and thickness of the interlayer dielectric layer 160 as needed.

[0082] Furthermore, an anisotropic etching process is used to form a first contact hole 106 passing through the interlayer dielectric layer 160 and the gate dielectric layer 141, and a second contact hole 107 passing through the interlayer dielectric layer 160 is formed. Figure 3l shown.

[0083] In this step, anisotropic etching is, for example, ion milling etching, plasma etching, reactive ion etching, and laser ablation. By controlling the etching rate and etching time, the bottom of the first contact hole 106 passes through the doped region 150 and enters the body region 120; similarly, by controlling the etching rate and etching time, the bottom of the second contact hole 107 reaches the gate conductor layer 142, or passes through the gate conductor layer 142. When forming the second contact hole 107, the gate dielectric layer 141 can be used as an etching stop layer, and the second contact hole 107 may also pass through the surface of the gate dielectric layer 141 to the middle of the gate dielectric layer 141.

[0084] Further, a first conductive plug 171 is formed through the interlayer dielectric layer 160, the gate dielectric layer 141 and the doped region 150, and a second conductive plug 172 is formed through the interlayer dielectric layer 160, such as Figure 3m shown.

[0085] In this step, for example, a CVD or PVD process is used to fill metal materials, such as titanium, titanium nitride, tungsten, and copper, in the first contact hole 106 and the second contact hole 107. The first conductive plug 171 extends through the doped region 150 to the body region 120 below the doped region 150. The bottom of the second conductive plug 172 reaches the gate conductor layer 142, and can also pass through the gate conductor layer 142 to reach the surface or middle of the gate dielectric layer 141.

[0086] Further, a source electrode 181 and a gate electrode 182 are formed on the surface of the interlayer dielectric layer 160, and a drain electrode 183 is formed on the surface of the isolation layer 109b. Figure 3n The source electrode 181 contacts the first conductive plug 171 , the gate electrode 182 contacts the second conductive plug 172 , and the drain electrode 183 contacts the conductive channel 130 .

[0087] In this step, for example, a PVD process is first used to deposit metal layers on the surfaces of the interlayer dielectric layer 160 and the isolation layer 109b, and the material of the metal layers is, for example, aluminum, copper, silver, aluminum-copper alloy, aluminum-silicon-copper alloy, etc. Then, an etching process is used to form an opening 108, so that the metal layer located on the surface of the interlayer dielectric layer 160 is separated into a source electrode 181 and a gate electrode 182.

[0088] A control voltage is applied to the gate electrode 182, the gate conductor layer 142 receives the control voltage, and a channel 190 is formed between the doped region 150 and the conductive channel 130. The drain electrode 183 is connected to the doped region 150 through the conductive channel 130 and the channel 190. The current flows sequentially through the drain electrode 183, the longitudinal conductive channel 130 (drain region), the channel 190, the doped region 150 (source region), and the longitudinal first conductive plug 171 to reach the source electrode 181, as shown in FIG. Figure 2a shown.

[0089] Figures 4a to 4d The cross-sectional view of a method for manufacturing a semiconductor device according to the second embodiment of the present invention at some stages is shown, wherein the similarities with the manufacturing method of the first embodiment are not repeated in the following.

[0090] The difference from the manufacturing method of the first embodiment is that after the isolation layer 109a is patterned, the body region 120 is anisotropically etched through the etching window to form a through hole 104 passing through the body region 120, such as Figure 4a As shown, the etching stops when the isolation layer 109b is reached. Further, a conductive material is filled in the through hole 104 to form a conductive channel 130, as shown in FIG. Figure 4b shown.

[0091] After forming the gate dielectric layer 141, the gate conductor layer 142, the doped region 150 and the interlayer dielectric layer 160, a portion of the isolation layer 109b is removed to expose the conductive channel 130, such as Figure 4c shown.

[0092] Further, a source electrode 181 and a gate electrode 182 are formed on the surface of the interlayer dielectric layer 160, and a drain electrode 183 covering the isolation layer 109b is formed. Figure 4d As shown, the drain electrode 183 passes through the isolation layer 109b and contacts the conductive channel 130.

[0093] The manufacturing method of the semiconductor device mentioned in the embodiment of the present invention is particularly suitable for manufacturing low-voltage (operating voltage not more than 100V) NMOS devices. The manufacturing principle of the PMOS device is the same, and the doping type in the corresponding structure is directly switched. However, the N-type doping and P-type doping methods of polysilicon are different. The N-type mostly adopts in-situ polycrystalline doping, that is, growing N-type doped polycrystalline silicon. P-type doping is limited by the processing means. Generally, polysilicon is deposited first, and then boron is injected and annealed to achieve P-type doping. In addition, the formation of N-type polysilicon can also be carried out by phosphorus injection plus annealing, and in-situ N-type polycrystalline deposition is the preferred solution.

[0094] According to an embodiment of the present invention, a semiconductor device and a method for manufacturing the same are provided. Figure 2a As shown, by using a semiconductor substrate as the body region 120, forming a conductive channel 130 connecting the first surface and the second surface of the body region 120, and the drain electrode 183 contacts the conductive channel 130 at the second surface of the body region 120. After the device is turned on, the epitaxial layer and the substrate in the traditional UMOS device will no longer be components of the on-resistance, that is, the epitaxial resistance Repi and the substrate resistance Rsub originally connected in series in the traditional UMOS device will be completely eliminated, thereby reducing the on-resistance.

[0095] Since the material of the conductive channel 130 is in-situ doped polysilicon, and the conductive channel 130 only serves as a low-resistance conductive path to conduct current from the drain electrode 183 on the back of the device to the source electrode 181 on the front, the functional characteristic of the vertical flow of current between the source electrode 181 and the drain electrode 183 of the VDMOS is not changed, thereby ensuring the efficient utilization of the device's planar area.

[0096] Since the gate stack 140 is formed on the first surface of the body region 120 and replaces the trench gate structure in the prior art, the problem of the roughness of the U-shaped trench profile and the sidewall affecting the gate oxidation quality is avoided.

[0097] Furthermore, since the gate dielectric layer 141 is only formed on the first surface of the body region 120, the thickness uniformity and quality of the gate dielectric layer 141 are better controlled; in addition, the body region 120 is a semiconductor material with a single crystal orientation, so the thickness uniformity and quality of the gate dielectric layer 141 can be better controlled, thereby making the threshold voltage Vt more stable and the on-resistance value easier to control.

[0098] Furthermore, since the gate stack 140 is a planar gate structure, the channel 190 is adjacent to the gate dielectric layer 141 and close to the first surface of the body region 120, thereby making the resistance of the channel 190 more uniform and easier to control, avoiding the resistance of the channel 190 being easily affected by the longitudinal concentration gradient of impurities in the body region 120, thereby making the channel resistance Rch stable and easy to control, and at the same time making the on-resistance and threshold voltage Vt of the device more stable.

[0099] In addition, since the semiconductor device according to the embodiment of the present invention omits the epitaxial layer in the conventional process, the overall thickness of the device is reduced, so that the device is further miniaturized.

[0100] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0101] The embodiments of the present invention are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate as a body region having a first surface and a second surface opposite to each other; a doped region extending from the first surface of the body region into the body region; A gate stack located on a first surface of the body region; a conductive channel, comprising a groove penetrating the body region along a thickness direction of the body region and a conductive material filled in the groove, wherein the conductive channel is separated from the doped region; as well as a drain electrode, contacting the conductive channel at the second surface of the body region, The body region is of a first doping type, the doping region and the conductive channel are of a second doping type, and the first doping type is opposite to the second doping type. The gate stack receives a control voltage, and the drain electrode and the doped region are connected through the conductive channel and a channel between the doped region and the conductive channel.

2. The semiconductor device according to claim 1, wherein: The channel is adjacent to the first surface of the body region.

3. The semiconductor device according to claim 1 or 2, characterized in that: The gate stack comprises: a gate dielectric layer covering the first surface of the body region; and a gate conductor layer, located on the gate dielectric layer, The gate conductor layer at least corresponds to the body region between the doped region and the conductive channel.

4. The semiconductor device according to claim 3, characterized in that Also includes: an interlayer dielectric layer, covering the gate dielectric layer and the gate conductor layer; a first conductive plug, passing through the interlayer dielectric layer and the gate dielectric layer, and contacting the doped region and the body region respectively; a second conductive plug, passing through the interlayer dielectric layer and contacting the gate conductor layer; A source electrode, located on a surface of the interlayer dielectric layer and in contact with the first conductive plug; as well as The gate electrode is located on the surface of the interlayer dielectric layer and contacts the second conductive plug.

5. The semiconductor device according to claim 4, characterized in that It also includes an isolation layer located between the second surface of the body region and the drain electrode, The conductive channel passes through the isolation layer to contact the drain electrode, or the drain electrode passes through the isolation layer to contact the conductive channel.

6. The semiconductor device according to claim 1 or 2, characterized in that: In a cross section perpendicular to the thickness direction of the body region, a plurality of the doped regions are arranged in an array in the body region, each of the doped regions is surrounded by the conductive channel, wherein a channel between each of the doped regions and the conductive channel is in a U-shape; or, In a cross section perpendicular to the thickness direction of the body region, the multiple doped regions are rectangular and are arranged in parallel in the body region along the long side direction of the rectangle, and at least one conductive channel is spaced between two adjacent doped regions, wherein the channel between each doped region and the conductive channel is rectangular.

7. A method for manufacturing a semiconductor device, characterized in that: include: Using a semiconductor substrate as a body region, the body region having a first surface and a second surface opposite to each other; forming a doped region extending from the first surface of the body region into the body region; forming a gate stack on a first surface of the body region; forming a conductive channel penetrating the body region along a thickness direction of the body region, wherein the conductive channel is separated from the doped region; as well as forming a drain electrode, the drain electrode being in contact with the conductive channel at the second surface of the body region, The body region is of a first doping type, the doping region and the conductive channel are of a second doping type, and the first doping type is opposite to the second doping type. The gate stack receives a control voltage, and the drain electrode and the doped region are connected through the conductive channel and a channel between the doped region and the conductive channel.

8. The manufacturing method according to claim 7, characterized in that: The step of forming the gate stack comprises: forming a gate dielectric layer covering the first surface of the body region; and forming a gate conductor on the gate dielectric layer, The gate conductor at least corresponds to a body region between the doped region and the conductive channel.

9. The manufacturing method according to claim 8, characterized in that: Also includes: forming an interlayer dielectric layer covering the gate dielectric layer and the gate conductor layer; forming a first conductive plug passing through the interlayer dielectric layer, the gate dielectric layer and the doped region, wherein the first conductive plug contacts the doped region; forming a second conductive plug passing through the interlayer dielectric layer, wherein the second conductive plug contacts the gate conductor layer; forming a source electrode on the surface of the interlayer dielectric layer, wherein the source electrode is in contact with the first conductive plug; forming a gate electrode on the surface of the interlayer dielectric layer, wherein the gate electrode is in contact with the second conductive plug; as well as forming an isolation layer between the second surface of the body region and the drain electrode, The conductive channel passes through the isolation layer and contacts the drain electrode.

10. The manufacturing method according to claim 9, characterized in that: The step of forming the conductive channel includes: forming a first trench extending from the first surface of the body region into the body region; filling the first trench with a conductive material; forming a second trench extending from the surface of the isolation layer into the body region, the second trench exposing a portion of the conductive material in the first trench; and filling the second trench with a conductive material, wherein the first trench contacts the conductive material in the second trench to form the conductive channel. or, The body region is trench-etched to form a through hole passing through the body region; and a conductive material is filled in the through hole to form the conductive channel.

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