Structured light based three-dimensional image sensor
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SAMSUNG ELECTRONICS CO LTD
- Filing Date
- 2019-10-17
- Publication Date
- 2026-06-16
Smart Images
Figure CN111081726B_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0124583, filed on October 18, 2018 with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field
[0003] The present invention relates to a three-dimensional (3D) image sensor, and more specifically, to a 3D image sensor based on structured light (SL). Background Technology
[0004] Regarding methods for realizing or measuring objects in 3D images, there are passive methods that use natural light without a separate light source and active methods that use an active light source. In stereo vision systems, which are one type of passive method, parallax occurs due to the distance between two sensors capturing two or more images, and 3D depth information is calculated by using parallax. On the other hand, in the case of the SL method, which is one type of active method, depth information is calculated by analyzing the degree of deformation of the specific pattern according to the surface shape of the target object after illuminating the target object with a laser beam of a specific pattern. Summary of the Invention
[0005] The present invention provides a structured light (SL) based three-dimensional (3D) image sensor, which has a structure in which the manufacturing process of the wiring layer can be simplified and / or the area of the bottom pads of the capacitor can be increased.
[0006] According to one aspect of the present invention, a structured light (SL) based three-dimensional (3D) image sensor is provided, the 3D image sensor comprising: a pixel region including a photodiode in a semiconductor substrate, the pixel region including a gate group including a plurality of gates on top of and around the photodiode; a multiple wiring layer on the upper portion of the pixel region, the multiple wiring layer including at least two wiring layers electrically connected to the semiconductor substrate and at least one of the plurality of gates; and a capacitor structure located between a first wiring layer and a second wiring layer, the first wiring layer being the lowest wiring layer in the multiple wiring layers, the second wiring layer being on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors located between the top pad and the top pad, wherein the bottom pad is connected to the first wiring layer.
[0007] According to another aspect of the present invention, a structured light (SL) based three-dimensional (3D) image sensor is provided, the 3D image sensor comprising: a charge generation region at a central portion of a pixel on a semiconductor substrate; a gate group including a plurality of gates configured to transmit charges generated in the charge generation region; a multiple wiring layer including at least two wiring layers on the pixel and electrically connected to the semiconductor substrate and at least one of the plurality of gates; and a capacitor structure located between two adjacent wiring layers of the multiple wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors located between the bottom pad and the top pad, wherein there is no wiring layer at the horizontal height at which the bottom pad is disposed.
[0008] According to another aspect of the present invention, a structured light (SL) based three-dimensional (3D) image sensor is provided, the 3D image sensor comprising: a pixel region including a photodiode in a semiconductor substrate, the pixel region including a gate group including a plurality of gates on top of and around the photodiode; a multiple wiring layer on the upper portion of the pixel region, the multiple wiring layer including at least two wiring layers electrically connected to the semiconductor substrate and at least one of the plurality of gates; and a capacitor structure located between a first wiring layer and a second wiring layer, the first wiring layer being the lowest wiring layer in the multiple wiring layers, the second wiring layer being on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors located between the bottom pad and the top pad, wherein the bottom pad is connected to the first wiring layer, and at least two bottom pads of the bottom pad are spaced apart from each other corresponding to the pixel region. Attached Figure Description
[0009] The various embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:
[0010] Figure 1A This is a cross-sectional view of a structured light (SL) based three-dimensional (3D) image sensor according to some embodiments. Figure 1B and Figure 1C Is with Figure 1A The equivalent circuit diagram corresponding to the 3D image sensor, and Figure 1D yes Figure 1A A plan view of the 3D image sensor at the horizontal height of the top surface of the bottom pad;
[0011] Figure 2 It is shown Figure 1A A magnified view of region A of the capacitor structure of the 3D image sensor;
[0012] Figures 3A to 3C Is it separate from Figure 1D A corresponding plan view of the SL-based 3D image sensor at the horizontal height of the top surface of the bottom pad, according to some embodiments;
[0013] Figure 4A This is a cross-sectional view of a SL-based 3D image sensor according to some embodiments, and Figure 4B yes Figure 4A A plan view of the 3D image sensor at the horizontal height of the top surface of the bottom pad;
[0014] Figure 5A and Figure 5B These are cross-sectional views of a SL-based 3D image sensor according to some embodiments; and
[0015] Figure 6 This is a schematic structural diagram of an electronic device including a 3D image sensor according to some embodiments. Detailed Implementation
[0016] In the following, various embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same constituent elements, and repeated descriptions thereof will be omitted.
[0017] Figure 1A This is a cross-sectional view of a structured light (SL) based three-dimensional (3D) image sensor 100 according to some embodiments. Figure 1B and Figure 1C yes Figure 1A The equivalent circuit diagram of the 3D image sensor 100, and Figure 1D yes Figure 1A A plan view of the 3D image sensor 100 at the horizontal height of the top surface of the bottom pad.
[0018] Reference Figures 1A to 1D According to some embodiments, a SL-based 3D image sensor 100 (hereinafter referred to as "3D image sensor") may include a semiconductor substrate 101, a photodiode (PD) 103, a gate group 110, a capacitor structure 120, an interlayer insulating layer 130, and / or a multilayer wiring layer 140.
[0019] Semiconductor substrate 101 may include, for example, a p-type semiconductor substrate. However, semiconductor substrate 101 is not limited to this. Multiple pixels may be located on semiconductor substrate 101 in a two-dimensional array structure, and each pixel may include a PD region (PA) and a transistor (TR) region (TA). A p-type well region may be formed in the top region of semiconductor substrate 101. Gate group 110 may be located on the p-type well region to construct various TRs. Microlens 107 may be located on the bottom surface of semiconductor substrate 101. Light can be incident on the bottom surface of semiconductor substrate 101 through microlens 107. Therefore, the 3D image sensor 100 of some embodiments may have a back illumination (BSI) structure. According to some embodiments, a color filter may be present between semiconductor substrate 101 and microlens 107.
[0020] A PD 103 can be formed in a semiconductor substrate 101. The PD 103 may include n-type doped regions and p-type doped regions. The PD 103 can be in the PA of the pixel. On the other hand, multiple TRs for charge transport can be on top of the PD 103 in the PA and in the TA adjacent to the PA. Figure 1A As shown, PA and TA can be separated by an isolation structure 105. The isolation structure 105 may include, for example, a deep trench isolation (DTI) structure. However, the isolation structure 105 is not limited thereto. For example, according to some embodiments, the isolation structure 105 may include a shallow trench isolation (STI) structure. Furthermore, according to some embodiments, the isolation structure 105 may be omitted between PA and TA. On the other hand, according to embodiments, a metal shielding layer may be formed on the bottom surface of the semiconductor substrate 101 corresponding to TA to block light incident into TA.
[0021] For reference, in some embodiments, the 3D image sensor 100 may use a light illuminator (see [reference]). Figure 6 The SL (light intensity) of 200 can employ a global shutter scheme. SL can refer to light in the form of a one-dimensional or two-dimensional lattice. A global shutter scheme can be a concept where all pixels are reset simultaneously and the light signal is accumulated, and can be the opposite of a rolling shutter scheme that controls pixel operation on a row-by-row basis.
[0022] According to some embodiments, the 3D image sensor 100 may include a capacitor structure 120 as described below, which serves as a charge storage structure for storing charges generated by receiving SL reflected from a target object.
[0023] Gate group 110 may include a transfer gate 112, a reset gate 114, a first source follower gate 116-1, a second source follower gate 116-2, a precharge gate 115, a sampling gate 117, a calibration gate 119, and / or a select gate 118. The transfer gate 112, reset gate 114, first source follower gate 116-1, second source follower gate 116-2, precharge gate 115, sampling gate 117, calibration gate 119, and / or select gate 118 may respectively constitute a transfer TR TX, a reset TRRX, a first source follower TR SF1, a second source follower TR SF2, a precharge TR PRE, a sampling TR SAMP, a calibration TR CAL, and a select TR SEL. Figure 1B As can be understood from the equivalent circuit diagram, the floating diffuse (FD) region 109 is located between the transfer gate 112 and the reset gate 114, and is electrically connected to the first source follower gate 116-1. Although in Figure 1A Only the transfer gate 112, FD region 109, and first source follower gate 116-1 are shown in the PA, but other gates may be located at different positions in the second direction (y direction) of the PA, or may be in the TA. Furthermore, in Figure 1A In the diagram, only one gate is shown, but multiple gates can be present in the second direction (y-direction). See reference... Figure 1B The equivalent circuit diagram is provided, briefly describing the operation of the 3D image sensor in some embodiments.
[0024] First, the transmission TR TX and reset TR RX can be turned on, thus resetting PD 103 for all pixels. Next, the transmission TR TX and reset TR RX can be turned off, and charge accumulation for all pixels can begin. Subsequently, the reset TR RX can be turned on, resetting FD region 109, and simultaneously, the calibration TR CAL can be turned on to reset the first capacitor 124-1. Furthermore, when the sampling TR SAMP is turned on and the voltage at the other end of the second capacitor 124-2 is reset due to the calibration voltage Vcal, the sampling TR SAMP can simultaneously begin sampling and holding the voltage at the other end of the second capacitor 124-2. Next, the reset TR RX can be turned off, thus terminating the reset of FD region 109, and the calibration TR CAL can be turned off, thus terminating the reset of the first capacitor 124-1. At this point, the second capacitor 124-2 can lock onto the first voltage (the voltage after the reset of FD region 109) corresponding to the amplified signal output from the first source follower TR 116-1. Subsequently, the transfer TR TX can be turned on, and the charge stored in PD 103 can be transferred to FD region 109 via the transfer TR TX and stored in FD region 109. Next, the transfer TR TX can be turned off, and subsequently the sampling TR SAMP can be turned off. Therefore, the sampling and holding of the voltage at the other end of the second capacitor 124-2 can be terminated. At this time, the second capacitor 124-2 can hold a second voltage (the voltage after charge accumulation in FD region 109) corresponding to the amplified signal from the output of the first source follower TR 116-1. Subsequently, the reset TR TX can be turned on, and the selection TR SEL can be turned on, so the voltage Vout corresponding to the charge stored in the first capacitor 124-1 can be output.
[0025] The charge generated in PD 103, corresponding to the voltage change caused by the operation of the second capacitor 124-2 and the sampling TR SAMP, can be accumulated in the first capacitor 124-1. Furthermore, this operation can remove reset noise caused by the operation of the reset TRRX, noise caused by the circuit threshold deviation of the first source follower TR SF1, etc. The operation of the second capacitor 124-2 and the sampling TR SAMP can correspond to the correlated double sampling (CDS) operation.
[0026] exist Figure 1C In the case of an equivalent circuit, the second capacitor 124-2 can be located between the calibration TR CAL and the first capacitor 124-1. Figure 1C The equivalent circuit is similar to the one in overall operation. Figure 1BThe equivalent circuit is not significantly different. However, by increasing the capacitance of the second capacitor 124-2, the noise generated when the calibration TR CAL is turned off can be reduced.
[0027] Furthermore, according to some embodiments, in Figure 1B In the equivalent circuit, the calibration TR CAL can be located between the sampling TR SAMP and the second capacitor 124-2, instead of between the sampling TR SAMP and the first capacitor 124-1. Furthermore, according to some embodiments, the second capacitor 124-2 and / or the calibration TR CAL can be omitted. When the second capacitor 124-2 is omitted, it can be omitted... Figure 1A The second bottom pad 122-2 in the capacitor structure 120. Furthermore, according to some embodiments, where three or more bottom pads can be arranged, the pixel region may include three or more capacitors.
[0028] The transfer gate 112 may have a recessed structure. The transfer gate 112 may be formed such that the top of the semiconductor substrate 101 is recessed to a specific depth, and the top of the recess is filled with polysilicon. For example... Figure 1A As shown, the bottom surface of the transfer gate 112 can extend towards the top of the PD 103. The transfer gate 112 with such a recessed structure can be referred to as a vertical transfer gate. A gate oxide layer 113 can be located between the transfer gate 112 and the semiconductor substrate 101.
[0029] When a voltage is applied to the transmission gate 112, such as Figure 1A As shown, the charge (e.g., electrons) generated by PD 103 can be transferred to FD region 109 through a channel formed on the bottom surface of transmission gate 112. On the other hand, holes in the charge generated in PD 103 can be discharged to the outside via isolation structure 105. Therefore, a conductive material can be placed inside the isolation structure 105, and a negative (-) voltage or a ground voltage can be applied to the conductive material.
[0030] On the other hand, the gates (114, 115, 116-1, 116-2, 117, 118, and 119) other than the transfer gate 112 may have a horizontal structure comprising polysilicon on the semiconductor substrate 101. According to some embodiments, the gates (112, 114, 115, 116-1, 116-2, 117, 118, and 119) may comprise metal.
[0031] The interlayer insulating layer 130 and the multiple wiring layer 140 may be located above the semiconductor substrate 101 and the gate group 110. In addition, the capacitor structure 120 may be located in the interlayer insulating layer 130 between two adjacent wiring layers in the multiple wiring layer.
[0032] A multi-layer wiring layer 140, comprising multiple wiring layers, may be located in the interlayer insulating layer 130 above the semiconductor substrate 101 and the gate group 110. For example, the multi-layer wiring layer 140 may include a first wiring layer M1 to a fifth wiring layer M5.
[0033] The first wiring layer M1, which is the lowest wiring layer among the multiple wiring layers 140, may be adjacent to the semiconductor substrate 101. The first wiring layer M1 may include multiple wirings and / or pads, and may be located at a first horizontal height L1 in the vertical direction (i.e., the third direction (z-direction)) of the semiconductor substrate 101. The pads of the first wiring layer M1 may be connected via a first vertical direct contact Vc1 to the conductive material of the semiconductor substrate 101, the gates (112, 114, 115, 116-1, 116-2, 117, 118, and 119), and the isolation structure 105. On the other hand, as... Figure 1A As shown, one of the pads in the first wiring layer M1 can be connected downward to the semiconductor substrate 101 and upward to the bottom pad 122 of the capacitor structure 120.
[0034] The second wiring layer M2 may be located above the first wiring layer M1 and may include multiple wirings and / or multiple pads. The second wiring layer M2 may be connected to the first wiring layer M1 via a second vertical direct contact Vc2 and an additional second vertical direct contact Vc2'. Figure 1A As shown, the additional second vertical direct contact Vc2' can be located on the second vertical direct contact Vc2. The additional second vertical direct contact Vc2' can be formed by a damascene process. However, according to some embodiments, the additional second vertical direct contact Vc2' can be omitted.
[0035] The third wiring layer M3 to the fifth wiring layer M5 may be located above the second wiring layer M2 and connected to other wiring layers at other horizontal heights via corresponding vertical direct contacts. Alternatively, the fifth wiring layer M5 may include a shielding plate formed on its uppermost portion to block external noise. According to some embodiments, at least one of the fourth wiring layer M4 and the fifth wiring layer M5 may be omitted.
[0036] The first wiring layer M1, the first vertical direct contact Vc1, and the second vertical direct contact Vc2 may comprise tungsten (W), and the additional second vertical direct contact Vc2' and the second wiring layer M2 to the fifth wiring layer M5 may comprise copper (Cu). However, the materials of the first wiring layer M1 to the fifth wiring layer M5, the first vertical direct contact Vc1, the second vertical direct contact Vc2, and the additional second vertical direct contact Vc2' are not limited thereto. At least one barrier metal layer may be located at the boundary between the first wiring layer M1 to the fifth wiring layer M5, the first vertical direct contact Vc1, the second vertical direct contact Vc2, the additional second vertical direct contact Vc2', and the interlayer insulating layer 130.
[0037] The capacitor structure 120 may be located between the first wiring layer M1 and the second wiring layer M2 of the multi-wiring layer 140. The capacitor structure 120 may include a bottom pad 122, a top pad 126, and / or a capacitor 124. Two bottom pads 122 may correspond to one pixel PX. By arranging two bottom pads 122 in one capacitor structure 120, the capacitor structure 120 can function as two capacitors. For example, the bottom pads 122 may include a first bottom pad 122-1 and a second bottom pad 122-2, and the first bottom pad 122-1 and the second bottom pad 122-2 may be respectively connected to... Figure 1B or Figure 1C The first capacitor 124-1 and the second capacitor 124-2 shown correspond to each other. As described above, CDS can be performed using the second capacitor 124-2 and the sampling TR SAMP.
[0038] The first bottom pad 122-1 can be directly contacted via the bottom vertical contact V. Wl The second bottom pad 122-2 is connected to the corresponding pad of the first wiring layer M1, and can be connected to the corresponding pad of the second wiring layer M2 via the second vertical direct contact Vc2 and an additional second vertical direct contact Vc2'. The second vertical direct contact Vc2 connected to the second bottom pad 122-2 can be shorter than the second vertical direct contact Vc2 connected to the pad of the first wiring layer M1. The top pad 126 can be connected to the corresponding pad of the second bottom pad 122-2 via the second vertical direct contact Vc2'. Wh and additional top vertical direct contact V Cu Connect to the corresponding pads on the second wiring layer M2. Bottom pad 122, bottom vertical direct contact V Wl and top vertical direct contact piece V Wh This may include, for example, W. An additional top vertical direct contact V. Cu It can be formed by an inlay process (as with the addition of a second vertical direct contact Vc2'), can include Cu, and can be omitted depending on the embodiment. However, the bottom pad 122 and the bottom vertical direct contact Vc2' are not included. Wl Top vertical direct contact V Whand additional top vertical direct contact V Cu The materials are not limited to these.
[0039] like Figure 1D As shown, when the horizontal cross-section of pixel PX has a structure of a first rectangle Re1, the bottom pad 122 can be wide at the center portion of the first rectangle Re1. For example, each of the first bottom pad 122-1 and the second bottom pad 122-2 can have a structure of a second rectangle Re2 extending in a second direction (y direction). The first bottom pad 122-1 and the second bottom pad 122-2 can be adjacent to each other in the center portion of the first rectangle Re1, while being symmetrical with respect to the centerline CL passing through the center of the first rectangle Re1.
[0040] Each of the first bottom pad 122-1 and the second bottom pad 122-2 may have a first width W1 in a first direction (x-direction). The first width W1 may be less than approximately half the width of the first rectangle Re1 in the first direction (x-direction). Therefore, a vertical direct contact area Avc may be allocated to the peripheral portion of the first rectangle Re1 outside the bottom pad 122. A plurality of second vertical direct contacts Vc2 may be located within the vertical direct contact area Avc. For reference, Figure 1D This is a plan view of pixel PX as seen from the top horizontal plane Lbp of the bottom pad 122; therefore, the second vertical direct contact Vc2 is shown as being horizontally cut at the top horizontal plane Lbp. Although the vertical direct contact area Avc is assigned to the two outer portions of the first rectangle Re1 in the first direction (x-direction), the assignment position of the vertical direct contact area Avc is not limited to this. For example, the vertical direct contact area Avc can be additionally assigned to the two outer portions of the first rectangle Re1 in the second direction (y-direction), and the second vertical direct contact Vc2 can be located within this additionally assigned vertical direct contact area Avc in the first direction (x-direction).
[0041] Multiple capacitors 124 may be located between the bottom pad 122 and the top pad 126. The top pad 126 may be located above the capacitors 124 as a structure covering all capacitors 124, and may be integrally formed (unlike the bottom pad 122). See reference. Figure 2 A more detailed description of capacitor structure 120 is given.
[0042] In some embodiments of the 3D image sensor 100, the first wiring layer M1 may be located at a first horizontal height L1 in the vertical direction (i.e., the third direction (z-direction)) relative to the semiconductor substrate 101, and the second wiring layer M2 may be located at a third horizontal height L3 in the third direction (z-direction). The bottom pad 122 may be located at a second horizontal height L2 between the first horizontal height L1 and the third horizontal height L3 in the third direction (z-direction). Since the bottom pad 122 is located between the first horizontal height L1 and the third horizontal height L3, it can have the following advantages. First, the pads of the second wiring layer M2 and the bottom pad 122 can be easily formed. Second, short-circuit faults between the pads of the second wiring layer M2 and the bottom pad 122 can be reduced. Third, when the pixel size is reduced in the future, the area of the bottom pad 122 can be more easily secured.
[0043] For reference, in conventional 3D image sensors, the bottom pad can be at the same horizontal level as the pads of the second wiring layer M2. For example, in conventional 3D image sensors, a small first pad and a large bottom pad can be formed together in the second wiring layer M2. Therefore, in the case of conventional 3D image sensors, the process of forming the second wiring layer M2 may be more difficult, and thus, the process time may be increased. To form a pattern, typically, firstly, a mask corresponding to the corresponding pattern can be fabricated by optical proximity correction (OPC) operation, and then a photolithography process can be performed using the mask to form a photoresist pattern. Subsequently, an etching process can be performed using the photoresist pattern. However, when first pads and bottom pads of different sizes and shapes coexist in the second wiring layer M2, the OPC process, photolithography process, and etching process may become more complex, the number of processes may increase, and the completeness may be significantly reduced. In addition, due to insufficient space in the second wiring layer M2 and the low completeness of pattern formation, short-circuit faults between the first pad and the bottom pad may increase.
[0044] Typically, the bottom pad can be located in the center of pixel PX, and the first pad can be located on the outer periphery of pixel PX. For example, in Figure 1D In this configuration, the first pad may be located on the outer periphery of the first rectangle Re1, outside the bottom pad 122. On the other hand, the bottom pad may be needed to secure some area for ensuring the capacitance of the capacitor. Therefore, in a conventional 3D image sensor structure where the first pad and the bottom pad are formed together in the second wiring layer M2, it may be difficult to secure a sufficient area for the bottom pad when the pixel size decreases.
[0045] On the other hand, in some embodiments of the 3D image sensor 100, one or more of the above-mentioned problems can be solved by arranging the bottom pad 122 at a horizontal height between the first wiring layer M1 and the second wiring layer M2. In other words, the pads of the second wiring layer M2 and the bottom pad 122 can be easily formed, short-circuit faults between the pads of the second wiring layer M2 and the bottom pad 122 can be reduced, and / or the area of the bottom pad 122 can be sufficiently guaranteed even if the pixel size is reduced in the future.
[0046] Figure 2 It is shown Figure 1A A magnified view of region A of the capacitor structure 120 of the 3D image sensor 100.
[0047] Reference Figure 2 In some embodiments of the 3D image sensor 100, the capacitor structure 120 may include a bottom pad 122 located at its bottom portion, a top pad 126 located at its top portion, and / or a plurality of capacitors 124 located between the bottom pad 122 and the top pad 126.
[0048] Bottom pad 122 can be directly contacted via bottom vertical contacts (see...) Figure 1A V in Wl The first bottom pad 122-1 is connected to the pads of the first wiring layer M1, and therefore can be connected to the semiconductor substrate 101. For example, the first bottom pad 122-1 can be connected to the source region of the sampling TR SAMP via the pads of the first wiring layer M1. Therefore, the first capacitor including the first bottom pad 122-1 (see...) Figure 1B or Figure 1C 124-1 in the capacitor can store a charge corresponding to the voltage fixed to the second capacitor 124-2.
[0049] The capacitor 124 may have a cylindrical structure and may include a first metal layer 124m1, a dielectric layer 124d, and / or a second metal layer 124m2. In some embodiments, the cylindrical structure may refer only to the portion of the first metal layer 124m1, the dielectric layer 124d, and the second metal layer 124m2 formed perpendicular to the top surface of the bottom pad 122. The first metal layer 124m1 and the second metal layer 124m2 may include, for example, titanium nitride (TiN). However, the materials of the first metal layer 124m1 and the second metal layer 124m2 are not limited thereto.
[0050] On the other hand, dielectric layer 124d may comprise a high-dielectric (high-k) material with a dielectric constant of about 10 to about 25. For example, dielectric layer 124d may comprise metal oxides such as hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), and aluminum oxide (Al2O3), their silicates, or their aluminates. Furthermore, dielectric layer 124d may comprise metal nitride oxides such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), and yttrium oxynitride (YON), their silicates, or their aluminates.
[0051] The top pad 126 can be formed to cover all of the plurality of capacitors 124 and can include, for example, silicon germanium (SiGe). However, the material of the top pad 126 is not limited thereto.
[0052] The capacitor structure 120 can be formed by the following process. First, a bottom pad 122 can be formed at a second horizontal height L2 above the semiconductor substrate 101. Next, an interlayer insulating layer 130 covering the bottom pad 122 can be formed and planarized, and then a trench can be formed in the portion where the capacitor structure 120 will be formed. The bottom pad 122 can be exposed at the bottom surface of the trench. Thereafter, material layers for the first metal layer 124m1, dielectric layer 124d, and second metal layer 124m2 can be formed sequentially, and a material layer for the top pad 126, such as a SiGe layer, can be formed on the material layer of the second metal layer 124m2. Finally, the capacitor structure 120 can be completed by forming the first metal layer 124m1, dielectric layer 124d, second metal layer 124m2, and top pad 126 through a patterning process.
[0053] Subsequently, a top vertical direct contact V can be formed on the capacitor structure 120. Wh and additional top vertical direct contact V Cu Furthermore, the top pad 126 can be directly contacted via the top vertical V-shaped pin. Wh and additional top vertical direct contact V Cu Electrically connected to the corresponding pad on the second wiring layer M2.
[0054] Figures 3A to 3C Is it separate from Figure 1D Plan view at the horizontal height of the top surface of the bottom pads 122a, 122b, and 122c of the corresponding SL-based 3D image sensors 100a, 100b, and 100c according to some embodiments. Brief description or omission has been referenced. Figures 1A to 2 The given description.
[0055] Reference Figure 3AAccording to some embodiments, the 3D image sensor can be positioned in the form of the bottom pad 122a of the capacitor 120a and the location of the second vertical direct contact Vc2. Figure 1D The 3D image sensor shown is different. Figure 1D In the 3D image sensor 100, the bottom pad 122 of the capacitor structure 120 may have a rectangular structure extending in the second direction (y direction). On the other hand, in some embodiments of the 3D image sensor 100a, the bottom pad 122a may have a rectangular structure extending in the second direction (y direction), while also including a step S on the outer portion of the first rectangle Re1. Due to the step S, the bottom pad 122a may have an L-shaped appearance. The two bottom pads (122a-1 and 122a-2) may have a structure symmetrical with respect to the center point CP of the first rectangle Re1. For example, by forming a step S on the first bottom pad 122a-1 pointing downwards in the second direction (y direction) and a step S on the second bottom pad 122a-2 pointing upwards in the second direction (y direction), the step S of the first bottom pad 122a-1 and the step S of the second bottom pad 122a-2 can be symmetrical with respect to the center point CP of the first rectangle Re1.
[0056] The bottom pad 122a can have two widths in a first direction (x-direction). In other words, the bottom pad 122a can have a second width W2 in the portion where the step S is not formed, and a third width W3 smaller than the second width W2 in the portion where the step S is formed. The second width W2 of the bottom pad 122a can be greater than... Figure 1D The bottom pad 122 of the 3D image sensor 100 has a first width W1, and a third width W3 may be smaller than the first width W1. Therefore, as Figure 3A As shown, the vertical direct contact area Avca can be assigned to the outer portion of the first rectangle Re1 that forms the step S, and the second vertical direct contact Vc2 can be assigned to such a vertical direct contact area Avca.
[0057] Reference Figure 3B In some embodiments, the 3D image sensor 100b can be positioned in the form of the bottom pad 122b of the capacitor structure 120b and the location of the second vertical direct contact Vc2. Figure 1DThe 3D image sensor 100b differs from other 3D image sensors. In some embodiments of the 3D image sensor 100b, the bottom pad 122b may have a rectangular structure extending in a second direction (y-direction) and an external recess Cout outside the central portion in the second direction (y-direction). Due to the external recess Cout, the bottom pad 122b may have a shape similar to a 'U'. On the other hand, the first bottom pad 122b-1 and the second bottom pad 122b-2 may have a structure symmetrical with respect to the center line CL of the first rectangle Re1. For example, the external recess Cout of the first bottom pad 122b-1 may be formed on the right outer side in the first direction (x-direction), and the external recess Cout of the second bottom pad 122b-2 may be formed on the left outer side in the first direction (x-direction). Therefore, the external recesses Cout of the first bottom pad 122b-1 and the second bottom pad 122b-2 may be symmetrical with respect to the center line CL of the first rectangle Re1.
[0058] The bottom pad 122b may have two widths in a first direction (x-direction). In other words, the bottom pad 122b may have a second width W2' at the two peripheral portions in a second direction (y-direction) where the external recess Cout is not formed, and a third width W3' smaller than the second width W2' in the central portion in the second direction (y-direction) where the external recess Cout is formed. The second width W2' of the bottom pad 122b may be greater than... Figure 1D The bottom pad 122 of the 3D image sensor 100 has a first width W1, and a third width W3' can be smaller than the first width W1. Therefore, as Figure 3B As shown, the vertical direct contact area Avcb can be assigned to the outer portion of the first rectangle Re1 that forms the outer recess Cout, and the second vertical direct contact Vc2 can be assigned to such a vertical direct contact area Avcb.
[0059] The second width W2' and the third width W3' can be approximately equal to Figure 3A The 3D image sensor 100a has a second width W2 and a third width W3 for the bottom pad 122a. However, according to some embodiments, the second width W2' and the third width W3' may be different from the second width W2 and the third width W3, respectively.
[0060] Reference Figure 3C In some embodiments, the 3D image sensor 100c can be positioned in the form of the bottom pad 122c of the capacitor structure 120c and the location of the second vertical direct contact Vc2. Figure 1DThe 3D image sensor 100 shown is different. In some embodiments of the 3D image sensor 100c, the bottom pad 122c may have a rectangular structure extending in the second direction (y direction), while having an inner recess Cin on the inner side of the central portion in the second direction (y direction). Due to the inner recess Cin, the bottom pad 122c may have a shape similar to a 'U', as... Figure 3B The bottom pad 122b of the 3D image sensor 100b. In some embodiments of the 3D image sensor 100c, when the bottom pad 122b is... Figure 3B When comparing the bottom pads 122b of the 3D image sensor 100b, the following differences exist: the inner recess Cin and the outer recess Cout are arranged on opposite sides in the first direction (x direction). For example, the outer recess Cout of the first bottom pad 122b-1 may be located on the right side of the first bottom pad 122b-1, while the inner recess Cin of the first bottom pad 122c-1 may be located on the left side of the first bottom pad 122c-1.
[0061] The bottom pad 122c can have two widths in a first direction (x-direction). In other words, the bottom pad 122c can have a second width W2” in the two peripheral portions of the unformed inner recess Cin in a second direction (y-direction), and a third width W3” smaller than the second width W2” in the central portion of the formed inner recess Cin in the second direction (y-direction). The second width W2” of the bottom pad 122c can be greater than… Figure 1D The bottom pad 122 of the 3D image sensor 100 has a first width W1, and a third width W3" can be smaller than the first width W1. Therefore, as Figure 3C As shown, the vertical direct contact area Avcc can be assigned to the central portion of the inner recess Cin of the first rectangle Re1, and the second vertical direct contact Vc2 can be assigned to such a vertical direct contact area Avcc.
[0062] The second width W2” and the third width W3” can be approximately equal to Figure 3A The second width W2 and the third width W3 of the bottom pad 122a in the 3D image sensor. However, according to some embodiments, the second width W2” and the third width W3” may be different from the second width W2 and the third width W3, respectively.
[0063] Figure 4A This is a cross-sectional view of an SL-based 3D image sensor 100d according to some embodiments. Figure 4B yes Figure 4A A plan view of the top surface of the bottom pad 122d of the 3D image sensor 100d at a horizontal height. (Briefly provided or omitted from reference.) Figures 1A to 3CThe given description.
[0064] Reference Figure 4A and Figure 4B In some embodiments, the 3D image sensor 100d can be integrated with the capacitor structure 120d. Figure 1A The 3D image sensor 100d differs from the 3D image sensor 100d in some embodiments. In the 3D image sensor 100d of some embodiments, the second bottom pad 122d-2 of the bottom pad 122d may include a protrusion 122p that protrudes toward the left outer boundary in a first direction (x direction), and the protrusion 122p may be connected to the corresponding pad of the second wiring layer M2 via a second vertical direct contact Vc2 and an additional second vertical direct contact Vc2'.
[0065] In some embodiments of the 3D image sensor 100d, the capacitor structure 120d can be located between the first wiring layer M1 and the second wiring layer M2. Therefore, the process for forming the pads of the second wiring layer M2 and the bottom pad 122d can be simpler, potential short-circuit faults can be reduced, and / or the area of the bottom pad 122d can be easily secured even if the pixel size is reduced in the future. Furthermore, as... Figure 4B As shown, the second vertical direct contact Vc2 can be arranged in the second direction (y direction) at a position corresponding to the protrusion 122p of the bottom pad 122d, and the second vertical direct contact Vc2 can be connected to the semiconductor substrate 101 or the gate on the semiconductor substrate 101 via the corresponding pad of the first wiring layer M1. The corresponding pad of the first wiring layer M1 corresponding to the gate is located below the bottom pad 122d, therefore... Figure 4B It is not shown in the document.
[0066] In some embodiments of the 3D image sensor 100d, the vertical direct contact area Avc' can be sufficiently ensured by including the protrusion 122p. Furthermore, because the vertical direct contact area Avc' is sufficiently ensured, a sufficient area for the bottom pad 122d can be guaranteed even if the pixel size is reduced in the future.
[0067] Figure 5A and Figure 5B These are cross-sectional views of SL-based 3D image sensors 100e and 100f according to some embodiments, where only the charge generation region in the semiconductor substrate 101 is shown, while the capacitor structure, interlayer insulating layer, and multiple wiring layers covering the semiconductor substrate 101 are omitted. Briefly provided or omitted information already referenced... Figures 1A to 4B The given description.
[0068] Reference Figure 5AIn some embodiments of the 3D image sensor 100e, a separate photodiode (PD) may not be formed in the semiconductor substrate 101. Instead of the PD, a photogate 150 may be formed on the semiconductor substrate 101. When a high voltage is applied to the photogate 150, a field can be formed in the semiconductor substrate 101, and light incident through the bottom surface of the semiconductor substrate 101 can be converted into electron-hole pairs near the field, thus generating an electric charge.
[0069] The photogate 150 can generate charge and simultaneously function as a transport gate. Therefore, a separate transport gate may not be necessary. However, according to some embodiments, a separate transport gate may be present around and together with the photogate 150.
[0070] In some embodiments of the 3D image sensor 100e, the capacitor structure (reference) Figure 1A The capacitor structure 120 can be located above the semiconductor substrate 101, and the capacitor structure 120 can be located in the first wiring layer (see reference). Figure 1A M1 in the middle) and the second wiring layer (reference) Figure 1A Between M2 in the capacitor structure 120. In other words, the bottom pad of the capacitor structure 120 (refer to M2) Figure 1A 122) can be formed separately at a different horizontal height than the second wiring layer M2. Therefore, the 3D image sensor of some embodiments can also have, as for... Figure 1A The effect described by the 3D image sensor 100.
[0071] Reference Figure 5B In some embodiments, the 3D image sensor 100f can be used with... Figure 5A The 3D image sensor 100f differs from the 3D image sensor 100e in that the PD 103a is additionally disposed within the semiconductor substrate 101. In the 3D image sensor 100f of this embodiment, the PD 103a can be additionally formed below the photogate 150, thus allowing for a deeper field to be formed. Therefore, the 3D image sensor 100f of this embodiment can generate more charge by using a combined structure of the photogate 150 and the PD 103a.
[0072] In some embodiments of the 3D image sensor 100f, the capacitor structure (reference) Figure 1A The capacitor structure 120 can be located above the semiconductor substrate 101, and the capacitor structure 120 can be located in the first wiring layer (see reference). Figure 1A M1 in the middle) and the second wiring layer (reference) Figure 1A Between M2). Therefore, the 3D image sensor 100f in some embodiments may also have, as for... Figure 1A The effect described by the 3D image sensor 100.
[0073] Although the structural and functional characteristics of capacitor structures have been primarily described for SL-based 3D image sensors, these characteristics are not limited to this. For example, the structural and functional characteristics of capacitor structures can also be applied to other types of 3D image sensors, such as time-of-flight (TOF) based 3D image sensors. Furthermore, the structural and functional characteristics of capacitor structures can also be applied to traditional 2D image sensors.
[0074] Figure 6 This is a schematic structural diagram of an electronic device 1000 including a 3D image sensor 100 according to some embodiments. Briefly provided or omitted from reference. Figures 1A to 5B The given description.
[0075] Reference Figure 6 In some embodiments, the electronic device 1000 may include a 3D image sensor 100, a light illuminator 200, a lens 300, a controller 400, and / or a signal processor 500. The 3D image sensor 100 may be, for example... Figure 1A The 3D image sensor 100 is described. However, the 3D image sensor 100 is not limited to this and can be used in electronic devices 1000 in some embodiments. Figures 3A to 3C , Figure 4A , Figure 5A and Figure 5B 3D image sensors 100a to 100f.
[0076] The light illuminator 200 can generate light and illuminate the object 10. The light illuminator 200 can generate infrared light and illuminate the object 10 with infrared light. However, the embodiment is not limited to this. The light illuminator 200 can generate near-infrared (NIR) light, ultraviolet (UV) light, visible light, etc., and can illuminate the object 10 with them. The light illuminator 200 can be implemented by an array of light-emitting diodes (LEDs), a laser amplification device for stimulated emission, etc. As described above, the light illuminator 200 can generate structured light Li and illuminate the object 10 with structured light Li. On the other hand, in Figure 6 Even though a 1DSL is shown, a 2DSL can be generated and illuminated.
[0077] Lens 300 can converge structured light Lr reflected from object 10 and transmit the converged structured light to 3D image sensor 100. Controller 400 typically controls 3D image sensor 100, light illuminator 200, and signal processor 500. Signal processor 500 can generate a depth image of object 10, i.e., a 3D image, using a signal processing module based on the amount of charge measured according to the SL method in 3D image sensor 100.
[0078] The controller 400 and / or signal processor 500 may include processing circuitry, including but not limited to a processor, central processing unit (CPU), controller, arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-a-chip (SoC), programmable logic unit, microprocessor, or any other device capable of responding to and executing instructions in a defined manner. In some example embodiments, the controller 400 and / or signal processor 500 may be at least one of application-specific integrated circuit (ASIC) and / or ASIC chip.
[0079] By executing computer-readable program code stored on a storage device, the controller 400 and / or signal processor 500 can be configured as a special-purpose machine. The program code may include programs or computer-readable instructions, software elements, software modules, data files, data structures, etc., that can be implemented by one or more hardware devices (e.g., one or more instances of the controller 400 and / or signal processor 500 described above). Examples of program code include machine code generated by a compiler and high-level program code executed using an interpreter.
[0080] The controller 400 and / or signal processor 500 may include one or more storage devices. The one or more storage devices may be tangible or non-transitory computer-readable storage media, such as random access memory (RAM), read-only memory (ROM), permanent mass storage devices (such as disk drives), solid-state (e.g., NAND flash memory) devices, and / or any other similar data storage institution capable of storing and recording data. The one or more storage devices may be configured to store computer programs, program code, instructions, or combinations thereof for use with one or more operating systems and / or for implementing the exemplary embodiments described herein. Computer programs, program code, instructions, or combinations thereof may also be loaded from a separate computer-readable storage medium into one or more storage devices, and / or into one or more computer processing devices using a drive mechanism or capable of transmitting data. Such a separate computer-readable storage medium may include a USB flash drive, memory stick, Blu-ray / DVD / CD-ROM drive, memory card, and / or other similar computer-readable storage media. Computer programs, program code, instructions, or combinations thereof may be loaded from a remote data storage device into one or more storage devices, and / or one or more computer processing devices via a network interface rather than via a local computer-readable storage medium. Additionally, computer programs, program code, instructions, or combinations thereof can be loaded from a remote computing system configured to transmit and / or distribute computer programs, program code, instructions, or combinations thereof over a network into one or more storage devices and / or one or more processors.
[0081] The SL-based 3D image sensor according to the technical concept of the present invention may include a capacitor structure for storing charges generated in the PD, and the bottom pad of the capacitor structure may be located above the semiconductor substrate at a second horizontal height in the vertical direction, between a first horizontal height of the first wiring layer and a third horizontal height of the second wiring layer. Because the bottom pad is located between the first horizontal height of the first wiring layer and the third horizontal height of the second wiring layer, the pads of the second wiring layer and the bottom pad can be formed more easily, and short-circuit faults between the pads of the second wiring layer and the bottom pad can be reduced. Furthermore, the area of the bottom pad can be sufficiently ensured when the pixel size is reduced in the future.
[0082] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.
Claims
1. A structured light-based three-dimensional image sensor, the three-dimensional image sensor comprising: A pixel region including a photodiode in a semiconductor substrate, the pixel region including a gate group including a plurality of gates on top of and around the photodiode; A multiple wiring layer is located on the upper part of the pixel region, the multiple wiring layer comprising at least two wiring layers electrically connected to the semiconductor substrate and at least one of the plurality of gates; as well as A capacitor structure is located between a first wiring layer and a second wiring layer, wherein the first wiring layer is the lowest wiring layer in the multiple wiring layers, and the second wiring layer is on the first wiring layer. The capacitor structure includes a bottom pad layer, a top pad, and a plurality of capacitors located between the bottom pad layer and the top pad. The top pad is formed as a single unit, and the bottom pad layer includes two bottom pads horizontally spaced apart from each other, with each of the two bottom pads corresponding to a pixel. One of the two bottom pads includes a protrusion that extends in the width direction away from the outer boundary of the other bottom pad, and the protrusion is connected to the corresponding pad of the second wiring layer via a second vertical direct contact and an additional second vertical direct contact; and The other of the two bottom pads is connected to the first wiring layer.
2. The three-dimensional image sensor as described in claim 1, wherein, There is no wiring layer at the horizontal height where the bottom pad layer is located.
3. The three-dimensional image sensor as described in claim 1, wherein, The pixel region has a rectangular shape, and the two bottom pads are formed in the pixel region.
4. The three-dimensional image sensor as described in claim 1, wherein, Each of the capacitors has a cylindrical structure.
5. The three-dimensional image sensor as described in claim 4, wherein, The bottom pad layer comprises tungsten, and the top pad comprises silicon-germanium.
6. The three-dimensional image sensor as described in claim 4, wherein, The top pad is located below the second wiring layer and is connected to the second wiring layer via a top vertical direct contact and an additional top vertical direct contact, the top vertical direct contact comprising tungsten and the additional top vertical direct contact comprising copper.
7. The three-dimensional image sensor as described in claim 1, wherein, The transmission gates of the gate group are formed in a recess in the semiconductor substrate.
8. A structured light-based three-dimensional image sensor, the three-dimensional image sensor comprising: The charge generation region is located at the center of the pixel on the semiconductor substrate; A gate group configured to transmit the charge generated in the charge generation region, the gate group comprising a plurality of gates; A multi-layer wiring system comprising at least two wiring layers on the pixel and electrically connected to the semiconductor substrate and at least one of the plurality of gates; as well as A capacitor structure is located between the first and second wiring layers of the multi-layer wiring system. The capacitor structure includes a bottom pad layer, a top pad, and multiple capacitors located between the bottom pad layer and the top pad. Specifically, there is no wiring layer at the horizontal height where the bottom pad layer is located. The top pads are formed as a single unit, and the bottom pad layer includes two bottom pads horizontally spaced apart from each other, with each bottom pad corresponding to a pixel. One of the two bottom pads includes a protrusion that extends in the width direction away from the outer boundary of the other bottom pad, and the protrusion is connected to the corresponding pad of the second wiring layer via a second vertical direct contact and an additional second vertical direct contact; and The other of the two bottom pads is connected to the first wiring layer.
9. The three-dimensional image sensor as claimed in claim 8, wherein, The first wiring layer is the lowest wiring layer in the multiple wiring layers, the second wiring layer is above the first wiring layer, and the bottom pad layer is electrically connected to the semiconductor substrate via the first wiring layer.
10. The three-dimensional image sensor as claimed in claim 8, wherein, The charge generation region includes one of a photodiode structure, a photogate structure, or a combination thereof.
11. A structured light-based three-dimensional image sensor, the three-dimensional image sensor comprising: A pixel region including a photodiode in a semiconductor substrate, the pixel region including a gate group including a plurality of gates on top of and around the photodiode; A multiple wiring layer is located on the upper part of the pixel region, the multiple wiring layer comprising at least two wiring layers electrically connected to the semiconductor substrate and at least one of the plurality of gates; as well as A capacitor structure is located between a first wiring layer and a second wiring layer, wherein the first wiring layer is the lowest wiring layer in the multiple wiring layers, and the second wiring layer is on the first wiring layer. The capacitor structure includes at least two bottom pads, a top pad, and a plurality of capacitors located between the at least two bottom pads and the top pad. The top pad is formed as a single unit, and the at least two bottom pads are horizontally spaced apart from each other and correspond to a pixel. The at least two bottom pads are respectively connected to the first wiring layer and the second wiring layer. One of the at least two bottom pads includes a protrusion that extends in the width direction away from the outer boundary of the other bottom pad, and the protrusion is connected to a corresponding pad of the second wiring layer via a second vertical direct contact and an additional second vertical direct contact; and The other bottom pad of the at least two bottom pads is connected to the first wiring layer.
12. The three-dimensional image sensor as claimed in claim 11, wherein, The transmission gate of the gate group is on the photodiode, and the bottom pad connected to the first wiring layer is electrically connected to the source or drain region of the gate surrounding the photodiode via the first wiring layer and vertical direct contacts.