Display Devices

Abstract

A display device having a display area and a pad area is provided, the display device comprising: a base substrate; a thin film transistor located on the base substrate in the display area; an insulating layer located on the base substrate and the thin film transistor; a conductive pattern layer located on the insulating layer, the conductive pattern layer comprising a pad electrode located in the pad area; and a via insulating layer located on the insulating layer, exposing at least a portion of an upper surface of the pad electrode and covering an edge of the pad electrode, wherein, in the pad area, the insulating layer comprises a groove having a certain depth, and the pad electrode is located in the groove.

Description

Technical Field

[0001] Embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0002] Recently, display devices with light weight and small size have been manufactured. Cathode ray tube (CRT) display devices have been used due to performance and competitive price. However, CRT display devices have disadvantages in size or portability. Therefore, display devices such as plasma display devices, liquid crystal display devices and organic light emitting display devices have been highly valued due to small size, light weight and low power consumption. Summary of the invention

[0003] An embodiment can be implemented by providing a display device having a display area and a pad area, the display device comprising: a base substrate; a thin film transistor located on the base substrate in the display area; an insulating layer located on the base substrate and the thin film transistor; a conductive pattern layer located on the insulating layer, the conductive pattern layer including a pad electrode located in the pad area; and a via insulating layer located on the insulating layer, exposing at least a portion of an upper surface of the pad electrode and covering an edge of the pad electrode, wherein, in the pad area, the insulating layer includes a groove having a certain depth, and the pad electrode is located in the groove.

[0004] The thickness of the conductive pattern layer may be greater than the depth of the groove.

[0005] The insulating layer may include an inorganic insulating material.

[0006] The via insulating layer may include an organic insulating material.

[0007] The via insulating layer may have a first height in the display region and a second height in the pad region, the second height being smaller than the first height.

[0008] The groove may have a first width at an upper surface of the insulating layer, and the pad electrode may have a second width smaller than the first width.

[0009] The thin film transistor may include: an active pattern located on the base substrate; a gate electrode located on the active pattern; and a source electrode and a drain electrode included in the conductive pattern layer.

[0010] The display device may further include a light emitting structure on the via insulating layer and electrically connected to the drain electrode.

[0011] The display device may also include: a first gate insulating layer located between the insulating layer and the base substrate; and a first gate pattern located between the first gate insulating layer and the insulating layer and including a first signal line located in the pad area, wherein a thickness of the insulating layer on the first signal line is less than a thickness of the insulating layer adjacent to the first signal line.

[0012] An upper surface of the insulating layer on the first signal line may be flat.

[0013] The display device may further include a first insulating layer between the insulating layer and the base substrate, wherein the groove of the insulating layer is an opening passing through the insulating layer, the opening exposing the first insulating layer.

[0014] The thickness of the via insulating layer in the pad region may be about 0.2 μm to 1.1 μm.

[0015] The thickness of the pad electrode may be about 0.2 μm to 1.2 μm.

[0016] The insulating layer may include multiple layers comprising different materials.

[0017] The display device may further include: a conductive film located on the pad electrode and including a conductive ball; and a driver located on the conductive film, the driver being electrically connected to the pad electrode.

[0018] An embodiment can be implemented by providing a method for manufacturing a display device having a display area and a pad area, the method comprising the following steps: forming an active pattern of a thin film transistor on a base substrate; forming an insulating layer on the active pattern; forming a contact hole and a groove in the insulating layer so that the contact hole exposes the active pattern and the groove is located in the pad area; forming a conductive pattern layer, the conductive pattern layer including a drain electrode located in the contact hole and a pad electrode located in the groove; and forming a via insulating layer on the insulating layer so that the via insulating layer exposes the drain electrode and the pad electrode.

[0019] The method may further include: forming a first electrode on the via insulating layer so that the first electrode is electrically connected to the drain electrode; forming a light emitting layer on the first electrode; and forming a second electrode on the light emitting layer.

[0020] The method may further include: before forming the insulating layer, forming a first insulating layer on the base substrate, wherein the groove is an opening formed through the insulating layer and exposing the first insulating layer.

[0021] The method may further include forming a gate pattern including a gate electrode and a signal line on the base substrate before forming the insulating layer, wherein in the step of forming the contact hole and the groove, a step of an upper surface of the insulating layer formed on the signal line is removed.

[0022] The groove may have a first width at an upper surface of the insulating layer, and the pad electrode may have a second width smaller than the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Features will be apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0024] Figure 1 shows a plan view of a display device according to an exemplary embodiment;

[0025] Figure 2 Shown along Figure 1 A cross-sectional view taken along line II-I' and line II-II';

[0026] Figure 3 The drive unit is connected to the Figure 1 A cross-sectional view showing a state of a pad electrode of a display device;

[0027] Figure 4 A cross-sectional view showing a pad region and a display region of a display device according to an exemplary embodiment;

[0028] Figure 5 A cross-sectional view showing a pad region and a display region of a display device according to an exemplary embodiment;

[0029] Figure 6 A cross-sectional view showing a pad region and a display region of a display device according to an exemplary embodiment;

[0030] Figure 7 A cross-sectional view showing a pad region and a display region of a display device according to an exemplary embodiment;

[0031] Figure 8 A cross-sectional view showing a pad region and a display region of a display device according to an exemplary embodiment;

[0032] 9A to 9E Shows the manufacturing Figure 2 cross-sectional views showing stages of the method of the apparatus;

[0033] FIG. 10A to FIG. 10C Shows the manufacturing Figure 4 cross-sectional views showing stages of the method of the apparatus;

[0034] FIG. 11A to FIG. 11D Shows the manufacturing Figure 5 cross-sectional views showing stages of the method of the apparatus;

[0035] FIG. 12A to FIG. 12D Shows the manufacturing Figure 6 cross-sectional views showing stages of the method of the apparatus;

[0036] FIG. 13A to FIG. 13C Shows the manufacturing Figure 8 cross-sectional views showing stages of the method of the apparatus;

[0037] Fig.14 shows a block diagram of an electronic device according to an example embodiment;

[0038] Fig.15A It shows Fig.14 FIG. 10 is a diagram of an example in which the electronic device is implemented as a television; and

[0039] Fig. 15B It shows Fig.14 FIG. 1 is an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0040] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, example embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art.

[0041] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It will also be understood that when a layer or element is referred to as being "on" another layer or element, the layer or element may be directly on the other layer or element, or there may also be intermediate layers or intermediate elements. In addition, it will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may also be one or more intermediate elements. The same reference numerals represent the same elements throughout.

[0042] Figure 1 A plan view of a display device according to an exemplary embodiment is shown.

[0043] Reference Figure 1 The display device may include a display area DA (displaying an image), a peripheral area PA (as a non-display area adjacent to the display area DA and surrounding the display area DA), a pad (or "pad") area PADA (adjacent to the peripheral area PA) and a folding area FA (located between the peripheral area PA and the pad area PADA).

[0044] The display area DA may be on a plane formed by the first direction D1 and the second direction D2 perpendicular to the first direction D1. In an embodiment, the display area DA may be rectangular. In an embodiment, the display area DA may have various shapes such as a circular shape, an elliptical shape, a polygonal shape, or a polygonal shape with rounded corners.

[0045] In the display area DA, a plurality of pixels may be arranged in a matrix to display an image. The display area DA may further include a thin film transistor and a signal line therein.

[0046] The peripheral area PA is a non-display area and may surround an edge of the display area DA while being adjacent to the display area DA. A circuit structure for driving pixels of the display area DA may be located in the peripheral area PA.

[0047] A pad portion PAD may be located in the pad area PADA. The pad portion PAD may include a portion for electrically connecting to the driving unit (see Figure 3 DR) of multiple pads (or "pads") electrodes (refer to Figure 3 The driving unit is used to apply a driving signal, voltage, etc. to the display device.

[0048] The folding area FA may be a portion where the display device is bent. The display device may include a flexible substrate, and the folding area FA may be bent. For example, the pad area PADA may be located at the rear of the display area DA, thereby reducing the frame width.

[0049] Figure 2 Shown along Figure 1 The cross-sectional view taken along line II' and line II-II' is a view of a display area DA of the display device, and the cross-sectional view taken along line II-II' is a view of a pad area PADA of the display device.

[0050] Reference Figure 1 and Figure 2 , the display device may include a base substrate 100 , a thin film transistor TFT, an insulating layer 140 , a conductive pattern layer, a via insulating layer 150 , a light emitting structure 180 , a pixel defining layer PDL, and a thin film encapsulation layer TFE.

[0051] The base substrate 100 may include a transparent or opaque insulating material. In an embodiment, the base substrate 100 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc. In an embodiment, the base substrate 100 may include a flexible transparent material such as a flexible transparent resin substrate (e.g., a polyimide substrate). In this case, the polyimide substrate may include a first polyimide layer, a barrier film layer, a second polyimide layer, etc. For example, the polyimide substrate may have a first polyimide layer, a barrier film layer, and a second polyimide layer stacked on a rigid glass substrate.

[0052] The thin film transistor TFT may be located on the base substrate 100 in the display area DA. The thin film transistor TFT may be an amorphous silicon thin film transistor, a polysilicon thin film transistor, an oxide thin film transistor, or the like.

[0053] The insulating layer 140 may be located on the base substrate 100 on which the thin film transistor TFT is disposed. The insulating layer 140 may fully cover the thin film transistor TFT on the base substrate 100 and may have a substantially flat upper surface without generating steps around the thin film transistor TFT. In an embodiment, the insulating layer 140 may cover the thin film transistor TFT on the base substrate 100 and may have substantially the same thickness along the contour of the thin film transistor TFT. The insulating layer 140 may include an inorganic insulating material such as a silicon compound or an insulating metal oxide.

[0054] The conductive pattern layer may be on the insulating layer 140. The conductive pattern layer may include a drain electrode DE electrically connected to the thin film transistor TFT in the display area DA and a pad electrode PADE in the pad area PADA. In an implementation, the pad electrode PADE may have a thickness of, for example, 0.2 μm to 1.2 μm.

[0055] For example, the drain electrode DE may be electrically connected to the active pattern of the thin film transistor TFT through a contact hole formed through the insulating layer 140 .

[0056] A groove GR (having a depth t1) may be formed on or in the upper surface of the insulating layer 140. For example, the groove GR may be recessed from the upper surface of the insulating layer 140 by a depth t1. The pad electrode PADE may be located in the groove GR. The thickness t2 of the pad electrode PADE may be greater than the depth t1. For example, the upper surface of the pad electrode PADE may protrude from the upper surface of the adjacent insulating layer 140 by a difference of the thickness t2 and the depth t1 or be higher than the upper surface of the adjacent insulating layer 140 by a difference of the thickness t2 and the depth t1.

[0057] The via insulating layer 150 may be located on the insulating layer 140 on which the conductive pattern layer is disposed. The via insulating layer 150 may expose at least a portion of the upper surface of the pad electrode PADE (e.g., the central area of ​​the upper surface of the pad electrode PADE), and may cover the edge of the pad electrode PADE. In an embodiment, the via insulating layer 150 may have a single-layer structure, or may have a multi-layer structure including at least two insulating layers. The via insulating layer 150 may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane-based resin, etc.

[0058] The via insulating layer 150 may have a first height h1 (e.g., measured in a direction orthogonal to the surface of the insulating layer 140) in the display area DA, and may have a second height h2 (less than the first height h1) in the pad area PADA. For example, the via insulating layer 150 may have a sufficient thickness in the display area DA and may have a desired minimum thickness in the pad area PADA, so that the pad electrode PADE and the conductive film (see Figure 3 Keeping the thickness of the via insulating layer 150 in the pad area PADA sufficiently thin can help ensure that the adhesion between the pad electrode PADE and the conductive film is good. Keeping the thickness of the via insulating layer 150 in the display area DA sufficiently thick can help prevent undesirable warping at the edge of the pad electrode PADE. In an embodiment, the second thickness h2 of the via insulating layer 150 may be 0.2 μm to 1.1 μm.

[0059] In an embodiment, the via insulating layer 150 may have different thicknesses in the display area DA and the pad area PADA. In an embodiment, the thickness of the via insulating layer 150 in the display area DA and the thickness of the via insulating layer 150 in the pad area PADA may be the same.

[0060] The light emitting structure 180 may include a first electrode 181 , an emission layer 182 , and a second electrode 183 .

[0061] The first electrode 181 may be located on the via insulating layer 150. The first electrode 181 may include a reflective material or a transmissive material according to the emission type of the display device. In an embodiment, the first electrode 181 may have a single-layer structure or a multi-layer structure that may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0062] The pixel defining layer PDL may be located on the via insulating layer 150 on which the first electrode 181 is disposed. The pixel defining layer PDL may be formed using an organic material. For example, the pixel defining layer PDL may include a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, and the like. In an embodiment, an opening exposing the first electrode 181 may be formed by etching the pixel defining layer PDL. The emission region and the non-emission region of the display device may be defined by the opening of the pixel defining layer PDL. For example, a portion of the opening of the pixel defining layer PDL may correspond to the emission region, and the non-emission region may correspond to a portion adjacent to the opening of the pixel defining layer PDL.

[0063] The light emitting layer 182 may be located on the first electrode 181 exposed by the opening of the pixel defining layer PDL. In an embodiment, the light emitting layer 182 may extend on the sidewall of the opening of the pixel defining layer PDL. In an embodiment, the light emitting layer 182 may include an organic light emitting layer (EL), a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), an electron injection layer (EIL), etc. In an embodiment, the hole injection layer, the hole transport layer, the electron transport layer and the electron injection layer (for example, a layer other than the organic light emitting layer) may be formed in common to correspond to a plurality of pixels. In an embodiment, a plurality of organic light emitting layers may be formed using light emitting materials for generating light of different colors such as red light, green light and blue light according to the color pixels of the display device. In an embodiment, the organic light emitting layer of the light emitting layer 182 may include a plurality of stacked light emitting materials for generating red light, green light and blue light, thereby emitting white light. For example, the elements of the light emitting layer 182 may be formed in common to correspond to a plurality of pixels, and each pixel may be divided by a color filter layer.

[0064] The second electrode 183 may be located on the pixel defining layer PDL and the light emitting layer 182. The second electrode 183 may include a transmissive material or a reflective material according to the emission type of the display device. In an embodiment, the second electrode 183 may also have a single-layer structure or a multi-layer structure that may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film and / or a transparent conductive film.

[0065] The thin film encapsulation layer TFE may be located on the second electrode 183. The thin film encapsulation layer TFE may help prevent moisture and oxygen from penetrating from the outside. The thin film encapsulation layer TFE may include at least one organic layer and at least one inorganic layer. The at least one organic layer and the at least one inorganic layer may be stacked alternately with each other. In an embodiment, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer located between the two inorganic layers. In an embodiment, a sealing substrate for shielding external air and moisture from penetrating into the display device may be provided to replace the thin film encapsulation layer TFE.

[0066] Figure 3 The driving unit DR is connected to the Figure 1 A cross-sectional view of a state of a pad electrode PADE of a display device.

[0067] Reference Figures 1 to 3 , the conductive film ACF may be located on the pad electrode PADE of the display device and the via insulating layer 150. The conductive film ACF may be an anisotropic conductive film including the conductive balls B.

[0068] A driving unit or driver DR electrically connected to the pad electrode PADE may be located on the conductive film ACF. The driving unit DR may be electrically connected to the pad electrode PADE through a conductive ball B of the conductive film ACF. The driving unit DR may apply a driving signal, voltage, etc. to the display device through the pad electrode PADE.

[0069] The pad electrode PADE may be located in the groove GR of the insulating layer 140 (compared to the case where the groove GR is not formed), and the step between the upper surface of the insulating layer 140 and the upper surface of the pad electrode PADE may be reduced. For example, while forming the pad electrode PADE to be sufficiently thick, it can help prevent damage to the via insulating layer 150 due to the step difference.

[0070] In addition, the thickness of the via insulating layer 150 around the pad electrode PADE may be thinner than the thickness of the via insulating layer 150 in the display area DA, so that the adhesion of the conductive film ACF to the pad electrode PADE may be improved.

[0071] Figure 4 A cross-sectional view illustrating a pad area PADA and a display area DA of a display device according to an exemplary embodiment.

[0072] Reference Figure 1 and Figure 4 In addition to the pad electrode PADE, the display device can be Figure 2 Therefore, repeated explanations may be omitted.

[0073] The display device may include a base substrate 100 , a thin film transistor TFT, an insulating layer 140 , a conductive pattern layer (including a drain electrode DE and a pad electrode PADE), a via insulating layer 150 , a light emitting structure 180 , a pixel defining layer PDL, and a thin film encapsulation layer TFE.

[0074] A groove having a certain depth may be formed on or in the upper surface of the insulating layer 140. For example, the groove may be recessed from the upper surface of the insulating layer 140. The pad electrode PADE may be located in the groove. The thickness t2 of the pad electrode PADE may be greater than the depth of the groove.

[0075] The groove may have a first width W1 measured at an upper surface of the insulating layer 140. The pad electrode PADE may have a second width W2 smaller than the first width W1. For example, the pad electrode PADE may be located in the groove.

[0076] In an embodiment, the width of the lower surface or bottom surface of the groove and the second width W2 may be equal to each other. In an embodiment, the second width W2 may be smaller than the first width W1 and larger than the width of the bottom surface of the groove so that the side surface of the pad electrode PADE can be formed on the side surface (e.g., sidewall) of the groove.

[0077] Figure 5 A cross-sectional view illustrating a pad area PADA and a display area DA of a display device according to an exemplary embodiment.

[0078] Reference Figure 1 and Figure 5 The display device may include a base substrate 100, a buffer layer 110, an active pattern ACT, a gate insulating layer 120, a first gate pattern, a first insulating layer 130, a second gate pattern, a second insulating layer 140, a conductive pattern layer, a via insulating layer 150, a light emitting structure 180, a pixel defining layer PDL, and a thin film encapsulation layer TFE.

[0079] In an embodiment, the base substrate 100 may be made of a transparent or opaque material. In an embodiment, the base substrate 100 may be made of a transparent resin substrate having flexibility.

[0080] The buffer layer 110 may be entirely located on the base substrate 100 (eg, located in the display area DA and the pad area PADA). The buffer layer 110 may include a silicon oxide (SiO x ), silicon nitride (SiN x ) and other inorganic insulating materials.

[0081] The active pattern ACT may be located on the buffer layer 110 in the display area DA. The active pattern ACT may include polysilicon. The active pattern ACT may include a drain region and a source region doped with impurities and a channel region between the source region and the drain region.

[0082] The gate insulating layer 120 may cover the active pattern ACT on the buffer layer 110 and may have a substantially uniform thickness along a contour of the active pattern ACT. The gate insulating layer 120 may include an inorganic insulating material such as a silicon compound or an insulating metal oxide.

[0083] The first gate pattern may be located on the gate insulating layer 120. The first gate pattern may include a signal line such as a gate line and a gate electrode GE overlapping the active pattern ACT. The first gate pattern may also include a first signal line SL1 located in the pad area PADA. The first gate pattern may be formed using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.

[0084] The first insulating layer 130 may be located on the gate insulating layer 120 on which the first gate pattern is disposed. The first insulating layer 130 may cover the first gate pattern on the gate insulating layer 120 and may have a substantially uniform thickness along a contour of the first gate pattern. The first insulating layer 130 may include an inorganic insulating material such as a silicon compound or an insulating metal oxide.

[0085] The second gate pattern may be located on the first insulating layer 130. The second gate pattern may include a storage electrode CE. The storage electrode CE may overlap the gate electrode GE to form a storage capacitor. The second gate pattern may also include a second signal line SL2 located in the pad area PADA. The second signal line SL2 may be adjacent to the first signal line SL1. The second gate pattern may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0086] The second insulating layer 140 may be located on the first insulating layer 130 on which the second gate pattern is disposed. The second insulating layer 140 may cover the second gate pattern on the first insulating layer 130 and may have a substantially uniform thickness along a contour of the second gate pattern. The second insulating layer 140 may include an inorganic insulating material such as silicon oxide or an insulating metal oxide.

[0087] The conductive pattern layer may be located on the second insulating layer 140. The conductive pattern layer may include a source electrode SE and a drain electrode DE located in the display area DA and a pad electrode PADE located in the pad area PADA. The conductive pattern layer may be formed using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.

[0088] The source electrode SE and the drain electrode DE may be electrically connected to the active pattern ACT through contact holes formed through the second insulating layer 140 , the first insulating layer 130 , and the gate insulating layer 120 .

[0089] A groove having a certain depth may be formed on or in the upper surface of the second insulating layer. For example, the groove may be recessed inwardly by a certain depth from the upper surface of the second insulating layer 140. The pad electrode PADE may be located in the groove. The thickness of the pad electrode PADE may be greater than the depth of the groove.

[0090] The via insulating layer 150 may be located on the second insulating layer 140 on which the conductive pattern layer is disposed. The via insulating layer 150 may have a height h1 in the display area DA, and may have a second height h2 less than the first height h1 in the pad area PADA.

[0091] In an embodiment, the second insulating layer 140 may include silicon nitride (SiN x ) layer and silicon oxide (SiO x) layer, and may have a thickness of about 0.5 μm. In an embodiment, the pad electrode PADE may have a thickness of about 0.7 μm. In an embodiment, the step difference between the upper surface of the second insulating layer 140 and the upper surface of the pad electrode PADE may be about 0.2 μm. When the second height h2 of the via insulating layer 150 is about 0.2 μm to 1.1 μm, the stress applied to the via insulating layer 150 may be reduced by the reduced step difference compared to the case where the groove is not formed. For example, the via insulating layer 150 around the pad electrode PADE will not be cracked or lifted.

[0092] The light emitting structure 180 may include a first electrode 181, a light emitting layer 182, and a second electrode 183. The first electrode 181 may be located on the via insulating layer 150. The pixel defining layer PDL may be located on the via insulating layer 150 on which the first electrode 181 is disposed. The light emitting layer 182 may be located on the first electrode 181 exposed through an opening of the pixel defining layer PDL. The second electrode 183 may be located on the pixel defining layer PDL and the light emitting layer 182. The thin film encapsulation layer TFE may be located on the second electrode 183.

[0093] Here, the via insulating layer 150, the light emitting structure 180, the pixel defining layer PDL and the thin film encapsulation layer TFE may be Figure 2 The via insulating layer 150 , the light emitting structure 180 , the pixel defining layer PDL, and the thin film encapsulation layer TFE of the display device are substantially the same. Therefore, repeated explanations may be omitted.

[0094] Figure 6 A cross-sectional view illustrating a pad area PADA and a display area DA of a display device according to an exemplary embodiment.

[0095] Reference Figures 1 to 6 , except that an opening may be formed in the second insulating layer 140 (eg, completely through the second insulating layer 140) instead of a groove (eg, only partially penetrating the second insulating layer 140) and the pad electrode PADE may be located in the opening, the display device and Figure 5 The display devices of the present invention are basically the same. Therefore, repeated descriptions can be omitted.

[0096] The display device may include a base substrate 100, a buffer layer 110, an active pattern ACT, a gate insulating layer 120, a first gate pattern including a gate electrode GE and a first signal line SL1, a first insulating layer 130, a second gate pattern including a storage electrode CE and a second signal line SL2, a second insulating layer 140, a conductive pattern layer including a source electrode SE, a drain electrode DE and a pad electrode PADE, a via insulating layer 150, a light emitting structure 180, a pixel defining layer PDL and a thin film encapsulation layer TFE.

[0097] An opening through the second insulating layer 140 to expose the first insulating layer 130 may be formed in the pad area PADA. The pad electrode PADE may be located in the opening. The pad electrode PADE may be located in the opening formed through the second insulating layer 140, and the upper surface of the pad electrode PADE may protrude from the upper surface of the adjacent second insulating layer 140 or be higher than the upper surface of the adjacent second insulating layer 140 by only the difference between the thickness of the pad electrode PADE and the thickness of the second insulating layer 140 to form a step. For example, damage such as warping of the via insulating layer 150 can be prevented.

[0098] Figure 7 A cross-sectional view illustrating a pad area PADA and a display area DA of a display device according to an exemplary embodiment.

[0099] Reference Figures 1 to 7 In addition to the pad electrode PADE, the display device can be Figure 6 Therefore, repeated explanations may be omitted.

[0100] The display device may include a base substrate 100, a buffer layer 110, an active pattern ACT, a gate insulating layer 120, a first gate pattern including a gate electrode GE and a first signal line SL1, a first insulating layer 130, a second gate pattern including a storage electrode CE and a second signal line SL2, a second insulating layer 140, a conductive pattern layer including a source electrode SE, a drain electrode DE and a pad electrode PADE, a via insulating layer 150, a light emitting structure 180, a pixel defining layer PDL and a thin film encapsulation layer TFE.

[0101] An opening may be formed in the pad area PADA through the second insulating layer 140 to expose the first insulating layer 130. The pad electrode PADE may be located in the opening.

[0102] The opening may have a first width W1 measured at an upper surface of the second insulating layer 140, and the pad electrode PADE may have a second width W2 smaller than the first width W1. For example, the pad electrode PADE may be located in the opening.

[0103] In an embodiment, the width of the lower surface of the opening (e.g., the width of the exposed upper surface of the first insulating layer 130) and the second width W2 may be the same. In an embodiment, the second width W2 may be smaller than the first width W1 and larger than the width of the lower surface of the opening so that the side surface of the pad electrode PADE may be located on the side surface (e.g., sidewall) of the opening.

[0104] Figure 8 A cross-sectional view illustrating a pad area PADA and a display area DA of a display device according to an exemplary embodiment.

[0105] Reference Figure 1 and Figure 8 , except that the upper surface of the second insulating layer 140a located on the first signal line SL1 and the second signal line SL2 is flat, the display device can be Figure 5 Therefore, repeated explanations may be omitted.

[0106] The display device may include a base substrate 100, a buffer layer 110, an active pattern ACT, a gate insulating layer 120, a first gate pattern including a gate electrode GE and a first signal line SL1, a first insulating layer 130, a second gate pattern including a storage electrode CE and a second signal line SL2, a second insulating layer 140a, a conductive pattern layer including a source electrode SE, a drain electrode DE and a pad electrode PADE, a via insulating layer 150, a light emitting structure 180, a pixel defining layer PDL, and a thin film encapsulation layer TFE.

[0107] The second insulating layer 140a may have a substantially uniform thickness along the contour of the structure below the second insulating layer 140a in the display area DA. For example, the upper surface of the second insulating layer 140a may not be flat, and a step may be formed in the display area DA.

[0108] The second insulating layer 140a may have a flat upper surface on the first signal line SL1 and the second signal line SL2 in the pad area PADA. For example, the thickness of the second insulating layer 140a located on the first signal line SL1 and the second signal line SL2 may be less than the thickness of the second insulating layer 140a adjacent to the first signal line SL1 and the second signal line SL2. Steps on the second insulating layer 140a caused by the first signal line SL1 and the second signal line SL2 are not formed in the pad area PADA, thereby helping to prevent damage or warping of the via insulating layer 150 that would otherwise occur due to the steps.

[0109] 9A to 9E Shows the manufacturing Figure 2 Cross-sectional views of the apparatus showing stages in the method.

[0110] Reference Fig. 9A , a thin film transistor TFT may be formed on the base substrate 100. An insulating layer 140 may be formed on the base substrate 100 on which the thin film transistor TFT is formed. The insulating layer 140 may be formed by a chemical vapor deposition process, a spin coating process, a plasma enhanced chemical vapor deposition process, a sputtering process, a vacuum deposition process, a high density plasma chemical vapor deposition process, a printing process, or the like.

[0111] Reference Fig. 9B, the insulating layer 140 may be partially removed to form a contact hole CNT (exposing the thin film transistor TFT) and a groove GR (located in the pad area PADA). The groove may have a depth t1. For example, after a photoresist layer is formed on the insulating layer 140, a mask having a pattern corresponding to the contact hole CNT and the groove GR may be used to expose and develop the photoresist layer to form a photoresist pattern. The insulating layer 140 may be etched using the photoresist pattern to form the contact hole CNT and the groove GR. In an embodiment, the size and depth of the groove GR and the contact hole CNT may be adjusted to a desired degree by using a halftone mask or the like.

[0112] Reference Fig. 9C , a conductive pattern layer (including a drain electrode DE and a pad electrode PADE) may be formed on the insulating layer 140. The conductive pattern layer may be formed on the insulating layer 140 by patterning the conductive layer formed on the insulating layer 140 using a photolithography process or by using an etching process using an additional etching mask. In an embodiment, the conductive layer may be formed using a printing process, a sputtering process, a chemical vapor deposition process, a pulsed laser deposition (PLD) process, a vacuum deposition process, an atomic layer deposition (ALD) process, or the like.

[0113] In an implementation, the conductive pattern layer may have a thickness t2, and the thickness t2 may be greater than the depth t1 of the groove GR.

[0114] Reference Fig.9D , a via insulating layer 150 may be formed on the insulating layer 140 having the conductive pattern layer formed thereon. The via insulating layer 150 may be formed by forming a photoresist layer on the insulating layer 140 and then exposing and developing the photoresist layer. In an embodiment, by using a half-tone mask or the like, the via insulating layer 150 may have a second height h2 (in the pad area PADA) less than the first height h1 (in the display area DA), and the pad electrode PADE and the drain electrode DE may be exposed.

[0115] Reference Fig.9E , a first electrode 181, a pixel defining layer PDL, a light emitting layer 182, a second electrode 183, and a thin film encapsulation layer TFE may be formed on the via insulating layer 150 to manufacture a display device. The first electrode 181, the pixel defining layer PDL, the light emitting layer 182, the second electrode 183, and the thin film encapsulation layer TFE may be formed in a suitable manner.

[0116] In an embodiment, a conductive film and a driver may be attached to the exposed upper surface of the pad electrode PADE (refer to Figure 3 ).

[0117] FIG. 10A to FIG. 10C Shows the manufacturing Figure 4Cross-sectional views of the apparatus showing stages in the method.

[0118] Reference Fig. 10A , a thin film transistor TFT may be formed on the base substrate 100. An insulating layer 140 may be formed on the base substrate 100 on which the thin film transistor TFT is formed. The insulating layer 140 may be partially removed to form a contact hole CNT exposing the thin film transistor TFT in the display area DA and to form a groove GR in the pad area PADA. The groove GR may have a depth t1. The groove GR may have a first width W1 on the upper surface of the insulating layer 140.

[0119] Reference Fig. 10B , a conductive pattern layer (including the drain electrode DE and the pad electrode PADE) may be formed on the insulating layer 140. In an embodiment, the pad electrode PADE may be located in the groove GR, and the pad electrode PADE may have a second width W2 that is smaller than the first width W1. For example, the width of the lower surface of the pad electrode PADE may be smaller than the width of the upper surface of the groove GR (e.g., the width of the groove GR at the upper surface of the insulating layer 140).

[0120] Reference Fig. 10C , a via insulating layer 150, a first electrode 181, a pixel defining layer PDL, a light emitting layer 182, a second electrode 183, and a thin film encapsulation layer TFE may be formed on the insulating layer 140 (on which the conductive pattern layer is formed) to manufacture a display device. The via insulating layer 150, the first electrode 181, the pixel defining layer PDL, the light emitting layer 182, the second electrode 183, and the thin film encapsulation layer TFE may be formed by a suitable method.

[0121] FIG. 11A to FIG. 11D Shows the manufacturing Figure 5 Cross-sectional views of the apparatus showing stages in the method.

[0122] Reference Fig.11A , a buffer layer 110 may be formed on the base substrate 100. An active pattern ACT may be formed on the buffer layer 110. A gate insulating layer 120 may be formed on the buffer layer 110 on which the active pattern ACT is formed. A first gate pattern including a gate electrode GE and a first signal line SL1 may be formed on the gate insulating layer 120. A first insulating layer 130 may be formed on the gate insulating layer 120 on which the first gate pattern is formed. A second gate pattern including a storage electrode CE and a second signal line SL2 may be formed on the first insulating layer 130. A second insulating layer 140 may be formed on the first insulating layer 130 on which the second gate pattern is formed.

[0123] Reference Fig. 11B, the second insulating layer 140 may be partially removed to form a contact hole CNT (exposing the thin film transistor TFT) and a groove GR. The groove GR may have a depth t1.

[0124] Reference Fig. 11C , a conductive pattern layer (including the drain electrode DE, the source electrode SE, and the pad electrode PADE) may be formed on the second insulating layer 140. A conductive layer may be formed on the second insulating layer 140, and then the conductive layer may be patterned into a conductive pattern layer using a photolithography process or an etching process using an additional etching mask.

[0125] Reference Fig.11D , a via insulating layer 150, a first electrode 181, a pixel defining layer PDL, a light emitting layer 182, a second electrode 183, and a thin film encapsulation layer TFE may be formed on the second insulating layer 140 on which the conductive pattern layer is formed, so that a display device may be manufactured. The via insulating layer 150, the first electrode 181, the pixel defining layer PDL, the light emitting layer 182, the second electrode 183, and the thin film encapsulation layer TFE may be formed by a suitable method.

[0126] FIG. 12A to FIG. 12D Shows the manufacturing Figure 6 Cross-sectional views of the apparatus showing stages in the method.

[0127] Reference Fig. 12A A buffer layer 110 , an active pattern ACT, a gate insulating layer 120 , a first gate pattern including a gate electrode GE and a first signal line SL1 , a first insulating layer 130 , a second gate pattern including a storage electrode CE and a second signal line SL2 , and a second insulating layer 140 may be formed on a base substrate 100 .

[0128] Reference Fig. 12B , the second insulating layer 140, the first insulating layer 130, and the gate insulating layer 120 may be partially removed to form a contact hole CNT exposing the active pattern ACT. In addition, in the pad area PADA, the second insulating layer 140 may be partially removed to form an opening OP, thereby exposing the first insulating layer 130. In an embodiment, the opening OP and the contact hole CNT may be simultaneously formed using a half-tone mask or the like.

[0129] Reference Fig. 12C , a conductive pattern layer (including the drain electrode DE, the source electrode SE, and the pad electrode PADE) may be formed on the second insulating layer 140. A conductive layer may be formed on the second insulating layer 140, and then the conductive layer may be patterned into a conductive pattern layer using a photolithography process or an etching process using an additional etching mask.

[0130] Reference Fig.12D, a via insulating layer 150, a first electrode 181, a pixel defining layer PDL, a light emitting layer 182, a second electrode 183, and a thin film encapsulation layer TFE may be formed on the second insulating layer 140 on which the conductive pattern layer is formed, so that a display device may be manufactured. The via insulating layer 150, the first electrode 181, the pixel defining layer PDL, the light emitting layer 182, the second electrode 183, and the thin film encapsulation layer TFE may be formed by a suitable method.

[0131] also, Figure 7 Manufacturing method of a display device with respect to an opening of a first width W1 and a pad electrode PADE of a second width W2 and Figures 10A to 10C The manufacturing method of the groove GR with the first width W1 and the pad electrode PADE with the second width W2 is similar, and Figure 7 The other stages of the method for manufacturing a display device may be related to Figures 12A to 12D The corresponding stages of the manufacturing method are similar. Therefore, a detailed explanation thereof may be omitted.

[0132] FIG. 13A to FIG. 13C Shows the manufacturing Figure 8 Cross-sectional views of the apparatus showing stages in the method.

[0133] Reference Fig.13A A buffer layer 110, an active pattern ACT, a gate insulating layer 120, a first gate pattern including a gate electrode GE and a first signal line SL1, a first insulating layer 130, a second gate pattern including a storage electrode CE and a second signal line SL2, and a second insulating layer 140a may be formed on a base substrate 100.

[0134] A photoresist pattern PR may be formed on the second insulating layer 140a. A photoresist layer may be formed on the second insulating layer 140a, and then the photoresist layer may be exposed and developed using a halftone mask to form the photoresist pattern PR. In an embodiment, a portion where a contact hole is to be formed may correspond to the full-tone region FT, an upper portion of the first signal line SL1 and the second signal line SL2 may correspond to the first halftone region HT1, and a portion where a groove is to be formed may correspond to the second halftone region HT2. Therefore, the photoresist pattern PR may have an opening in the full-tone region FT, and recesses (e.g., depressions) having different depths may be formed in the first halftone region HT1 and the second halftone region HT2.

[0135] Reference Fig. 13B, the second insulating layer 140a may be patterned using the photoresist pattern PR. For example, the second insulating layer 140a, the first insulating layer 130, and the gate insulating layer 120 may be etched to form a contact hole CNT exposing the active pattern ACT in the full-tone region FT. In addition, in the first half-tone region HT1, a stepped portion of the second insulating layer 140a may be removed to form a flat upper surface F. In addition, in the second half-tone region HT2, a portion of the second insulating layer 140a may be removed to form a groove GR having a depth t1. Then, the photoresist pattern PR may be removed.

[0136] Reference Fig. 13C A conductive pattern layer including a drain electrode DE, a source electrode SE, and a pad electrode PADE may be formed on the second insulating layer 140a. A conductive layer may be formed on the second insulating layer 140a, and then the conductive layer may be patterned into a conductive pattern layer using a photolithography process or an etching process using an additional etching mask.

[0137] A via insulating layer 150, a first electrode 181, a pixel defining layer PDL, a light emitting layer 182, a second electrode 183, and a thin film encapsulation layer TFE may be formed on the second insulating layer 140a on which the conductive pattern layer is formed, so that a display device may be manufactured. The via insulating layer 150, the first electrode 181, the pixel defining layer PDL, the light emitting layer 182, the second electrode 183, and the thin film encapsulation layer TFE may be formed by a suitable method.

[0138] Fig.14 A block diagram of an electronic device according to an example embodiment is shown. Fig.15A It shows Fig.14 FIG. 1 is a diagram of an example in which the electronic device is implemented as a television. Fig. 15B It shows Fig.14 FIG. 1 is an example in which the electronic device is implemented as a smart phone.

[0139] Reference Figures 14 to 15B , the electronic device 500 may include a processor 510, a memory device 520, a storage device 530, an input / output (I / O) device 540, a power supply 550, and a display device 560. Here, the display device 560 may correspond to Figure 1 In addition, the electronic device 500 may also include multiple ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. In an embodiment, as Fig.15A As shown in , the electronic device 500 may be implemented as a television. Fig. 15BAs shown in , the electronic device 500 can be implemented as a smart phone. In an embodiment, the electronic device 500 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop computer, a head mounted display (HMD), etc.

[0140] The processor 510 may perform various computing functions. The processor 510 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 510 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 510 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. The memory device 520 may store data for the operation of the electronic device 500. For example, the memory device 520 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc. and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc. The storage device 530 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 540 may include an input device such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc. and an output device such as a printer, a speaker, etc. The power supply 550 may provide power for the operation of the electronic device 500.

[0141] The display device 560 may be coupled to other components via a bus or other communication link. In an embodiment, the display device 560 may be included in the I / O device 540. As described above, the pad electrode may be located in a groove or opening formed in the insulating layer, and the step difference from the upper surface of the insulating layer to the upper surface of the pad electrode may be reduced, so that the via insulating layer on the insulating layer can be prevented from warping. Therefore, it is possible to improve the adhesion of the conductive film for bonding the driver, reduce defects, and improve display quality.

[0142] The embodiments can be applied to organic light-emitting display devices and various electronic devices including the organic light-emitting display devices. For example, the embodiments can be applied to mobile phones, smart phones, video phones, smart tablets, smart watches, tablet PCs, car navigation systems, televisions, computer monitors, notebook computers, etc.

[0143] By way of summary and review, a display device may include a structure such as a plurality of conductive pattern layers and a plurality of insulating layers. Due to structural problems, process problems, etc., the structure may be damaged. Therefore, image quality may be degraded.

[0144] One or more embodiments may provide a display device capable of reducing defects.

[0145] One or more embodiments may provide a display device capable of reducing defects and improving display quality.

[0146] According to an exemplary embodiment, a groove having a certain depth on the insulating layer may be formed in the pad region of the display device, and the pad electrode may be located in the groove, so that the step difference between the pad electrode and the insulating layer may be reduced. According to the reduced step difference, the stress applied to the via insulating layer on the insulating layer may be reduced compared to a case where the groove is not formed. Therefore, it is possible to help prevent the via insulating layer around the pad electrode from being damaged or lifted.

[0147] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and will be interpreted only in a general and descriptive sense, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments as of the time of filing this application, unless otherwise specifically stated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device having a display area and a pad area, the display device comprising: base substrate; A thin film transistor, located on the base substrate in the display area; An insulating layer, located on the base substrate and the thin film transistor; a conductive pattern layer located on the insulating layer, the conductive pattern layer comprising a pad electrode located in the pad region; as well as a via insulating layer, located on the insulating layer, exposing at least a portion of the upper surface of the pad electrode and covering an edge of the pad electrode, wherein, in the pad region, the insulating layer comprises a groove having a certain depth, the pad electrode is located in the groove, and The groove has a first width at the upper surface of the insulating layer, and the pad electrode has a second width not greater than the first width.

2. The display device according to claim 1, wherein: The thickness of the conductive pattern layer is greater than the certain depth of the groove.

3. The display device according to claim 2, wherein: The insulating layer includes an inorganic insulating material.

4. The display device according to claim 3, wherein: The via insulating layer comprises an organic insulating material, and The via insulating layer has a first height in the display area and a second height in the pad area, and the second height is smaller than the first height.

5. The display device according to claim 1, wherein: The second width is smaller than the first width.

6. The display device according to claim 1, wherein: The second width is equal to the first width.

7. The display device according to claim 1, wherein: The thin film transistor comprises: An active pattern, located on the base substrate; a gate electrode located on the active pattern; and A source electrode and a drain electrode are included in the conductive pattern layer, and Wherein, the display device further includes a light emitting structure located on the via insulating layer and electrically connected to the drain electrode.

8. The display device according to claim 1, further comprising: A first gate insulating layer, located between the insulating layer and the base substrate; as well as a first gate pattern located between the first gate insulating layer and the insulating layer and including a first signal line located in the pad region, The thickness of the insulating layer on the first signal line is smaller than the thickness of the insulating layer adjacent to the first signal line, and Wherein, an upper surface of the insulating layer on the first signal line is flat.

9. The display device according to claim 1, further comprising a first insulating layer located between the insulating layer and the base substrate, in, The groove of the insulating layer is an opening passing through the insulating layer, and the opening exposes the first insulating layer.

10. The display device according to claim 1, wherein: The thickness of the via insulating layer in the pad region is 0.2 μm to 1.1 μm, and Wherein, the thickness of the pad electrode is 0.2 μm to 1.2 μm.

11. The display device according to claim 1, further comprising: a conductive film located on the pad electrode and including conductive balls; and a driver located on the conductive film, the driver being electrically connected to the pad electrode, The insulating layer includes a plurality of layers, and the plurality of layers include different materials.

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