Semiconductor packaging and manufacturing methods

Abstract

The present invention provides a semiconductor package structure comprising a patterned conductive layer having a front surface, a rear surface, and a side surface connecting the front surface and the rear surface. The semiconductor package structure further comprises: a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer; a first encapsulant covering at least the rear surface of the patterned conductive layer; and a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first encapsulant and the second encapsulant.

Description

Technical Field

[0001] This disclosure relates to a semiconductor packaging structure and a method for manufacturing a semiconductor packaging structure, and more particularly to a semiconductor packaging structure with an encapsulant covering a patterned conductive layer and a method for manufacturing the same. Background Technology

[0002] In recent years, with increasingly higher demands on the electronics market and advanced processing technologies, more and more 3C products emphasize portability and mass appeal. Conventional signal chip packaging technologies can no longer meet these new market requirements. A well-known product trend is to design and produce products that are lightweight, thin, short, small, with increased packaging density, and low cost. Therefore, under the premise of being lightweight, thin, short, and small, integrating various integrated circuits (ICs) with different functions through various stacking packaging methods to reduce package size and thickness is the mainstream approach in market research for various packaged products. Summary of the Invention

[0003] Some embodiments of the present invention provide a semiconductor package structure comprising a patterned conductive layer having a front surface, a rear surface, and a side surface connecting the front and rear surfaces. The semiconductor package structure further comprises: a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer; a first encapsulant covering at least the rear surface of the patterned conductive layer; and a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first and second encapsulants.

[0004] Some embodiments of the present invention provide a semiconductor substrate comprising a patterned conductive layer having a front surface, a rear surface, and a side surface connecting the front and rear surfaces. The semiconductor substrate further comprises an encapsulant covering the rear and side surfaces of the patterned conductive layer.

[0005] Some embodiments of the present invention provide a method for manufacturing a semiconductor package structure. The method includes providing a carrier and forming a patterned conductive layer over the carrier. The patterned conductive layer has a front surface, a rear surface, and a side surface connecting the front and rear surfaces of the carrier. A first encapsulation is formed over the patterned conductive layer, covering the rear and side surfaces of the first encapsulation, and the carrier is removed to expose the front surface of the patterned conductive layer. Attached Figure Description

[0006] The various aspects of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the features may not be drawn to scale. In fact, for clarity of explanation, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1A A cross-section of a semiconductor package according to some comparative embodiments of the present invention is shown.

[0008] Figure 1B A cross-section of a semiconductor package according to some comparative embodiments of the present invention is shown.

[0009] Figures 2A to 2E A cross-section of a semiconductor substrate during intermediate manufacturing operations is shown, according to some comparative embodiments of the invention.

[0010] Figure 3A A cross-section of a chip-scale package (CSP) having a single embedded trace substrate (ETS) is shown according to some embodiments of the present invention.

[0011] Figure 3B A cross-section of a grid array (LGA) package having a single embedded trace substrate (ETS) is shown according to some embodiments of the present invention.

[0012] Figures 4A to 4G The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 3A The cross-section of a semiconductor package.

[0013] Figure 5A Some embodiments according to the present invention are shown. Figure 4B The cross-section of the semiconductor substrate.

[0014] Figure 5B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 4C The cross-section of the semiconductor substrate.

[0015] Figures 6A to 6F The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 3B The cross-section of a semiconductor package.

[0016] Figures 7A to 7E A cross-section of a semiconductor package during intermediate manufacturing operations is shown according to some embodiments of the present invention.

[0017] Figure 8A Some embodiments according to the present invention are shown. Figure 7A The cross-section of the semiconductor substrate.

[0018] Figure 8B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 7B The cross-section of the semiconductor substrate.

[0019] Figure 9AA cross-section of a chip-scale package (CSP) having two embedded trace substrates (ETS) is shown according to some embodiments of the present invention.

[0020] Figure 9B A cross-section of a grid array (LGA) package having two embedded trace substrates (ETS) is shown according to some embodiments of the present invention.

[0021] Figures 10A to 10G The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 9A The cross-section of a semiconductor package.

[0022] Figure 10CA , Figure 10CB , Figure 10CC Figure 10CD This is a cross-section of a semiconductor package during intermediate manufacturing operations according to some embodiments of the present invention.

[0023] Figure 11A Some embodiments according to the present invention are shown. Figure 10B The cross-section of the semiconductor substrate.

[0024] Figure 11B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 10C The cross-section of the semiconductor substrate.

[0025] Figures 12A to 12E The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 9A The cross-section of a semiconductor package.

[0026] Figure 13A Some embodiments according to the present invention are shown. Figure 12A The cross-section of the semiconductor substrate.

[0027] Figure 13B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 12B The cross-section of the semiconductor substrate.

[0028] Figures 14A to 14F The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 9B The cross-section of a semiconductor package.

[0029] Figure 15A Some embodiments according to the present invention are shown. Figure 14B The cross-section of the semiconductor substrate.

[0030] Figure 15B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 14C The cross-section of the semiconductor substrate.

[0031] Figure 16A , Figure 16B and Figure 16C A cross section of a chip-scale package (CSP) having a two-layer embedded trace substrate (ETS) integrated with a passive device is shown according to some embodiments of the present invention.

[0032] Figure 17A A cross-section of a chip-scale package (CSP) having a single-layer molded interconnect substrate (MIS) is shown according to some embodiments of the present invention.

[0033] Figure 17B A cross-section of a grid array (LGA) having a single-layer molded interconnect substrate (MIS) is shown according to some embodiments of the present invention.

[0034] Figures 18A to 18G The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 17A The cross-section of a semiconductor package.

[0035] Figure 18AA , Figure 18BB , Figure 18CC , Figure 18DD , Figure 18EE , Figure 18FF and Figure 18GG A cross-section of a semiconductor package with two-layer MIS is shown during intermediate manufacturing operations according to some embodiments of the present invention.

[0036] Figure 18AA '、 Figure 18BB '、 Figure 18CC 'and Figure 18DD A cross-section of a semiconductor package having two layers of resin-coated copper (RCC) ETS during intermediate manufacturing operations is shown, according to some embodiments of the present invention.

[0037] Figure 18AA "、 Figure 18BB "、 Figure 18CC "and Figure 18DD "A cross-section of a semiconductor package having two printable dielectric ETSs during intermediate manufacturing operations is shown according to some embodiments of the present invention."

[0038] Figure 19A Some embodiments according to the present invention are shown. Figure 18B The cross-section of the semiconductor substrate.

[0039] Figure 19B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 18C The cross-section of the semiconductor substrate.

[0040] Figure 20AA cross-section of a core semiconductor package with vertically molded boundaries is shown according to some embodiments of the present invention.

[0041] Figure 20B A cross-section of a core semiconductor package with horizontally molded boundaries is shown according to some embodiments of the present invention.

[0042] Figures 21A to 21D The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 20A The cross-section of the core semiconductor package.

[0043] Figures 22A to 22E The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 20B The cross-section of the core semiconductor package.

[0044] Figures 23A to 23E The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 20B The cross-section of the core semiconductor package. Detailed Implementation

[0045] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. These are, of course, merely examples and are not intended to be limiting. In this invention, references to the formation of a first feature on or over a second feature in the following description may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0046] Electronic packaging for automotive applications tends towards compact / thin package configurations and high reliability. In the aforementioned electronic packaging, the carrier comprises a leadframe and an organic substrate. Compared to its organic substrate-based counterpart, leadframe-based products offer higher reliability but are thicker and less versatile in wiring. On the other hand, organic substrate-based products can have one or more wiring layers to exhibit versatility in wiring. However, when the thickness of an organic substrate-based package is less than 100 micrometers or even 50 micrometers, carrier attachment and removal operations are required during the packaging process to compensate for the substrate's weak mechanical strength.

[0047] Carrier attachment and removal operations increase the cost of the packaging process. Additionally, during molding, the attached substrate is prone to peeling off from the carrier and can cause the popcorn effect during high-temperature processing. Finally, in the final packaged product, the organic substrate (dielectric material) is directly exposed to the surrounding environment and can pose reliability issues due to its high hygroscopicity (moisture absorption).

[0048] What is urgently needed is a thin package structure (e.g., a substrate thinner than 100 micrometers) that has adequate reliability during the packaging process and a protective layer that mitigates the consequences of moisture absorption at the substrate.

[0049] This invention provides a packaging structure having a first molded article encapsulating a conductor layer (e.g., dielectric, conductor, solder bumps) and a second molded article encapsulating a die bonded to the conductor layer. The first molded article is then ground to expose the solder bumps. The invention also provides a packaging structure having a first molded article encapsulating a conductor layer (e.g., dielectric, conductors) and a second molded article encapsulating a die bonded to the conductor layer. The first molded article is then laser-drilled to expose a portion of the conductor layer and implanted solder bumps thereon. During packaging, the first molded article is manipulated to provide mechanical support for the conductor layer, covering the bottom and side surfaces of the conductor layer to mitigate moisture absorption issues.

[0050] refer to Figure 1A , Figure 1A A cross-section of a flip-chip semiconductor package having a single embedded trace substrate (ETS) 100 and a semiconductor die 110 bonded to the top surface of the ETS 100, according to some comparative embodiments of the invention, is shown. A molding compound 120 encapsulates the top and sides of the semiconductor die 110 and the top surface of the ETS 100. In the current comparative embodiment, the molding compound 120 does not cover the sides 100S of the ETS 100. In some embodiments, the sides 100S of the ETS 100 are exposed to the environment, and the exposed sides 100S may be composed of an organic dielectric material such as BT (bismaleimide-triazine) resin or epoxy resin.

[0051] refer to Figure 1B , Figure 1BA cross-section of a flip-chip semiconductor package having two layers of embedded trace substrates (ETS) 101 and a semiconductor die 111 bonded to the top surface of the ETS 101, according to some comparative embodiments of the invention, is shown. A molding compound 120 encapsulates the top and sides of the semiconductor die 111 and the top surface of the ETS 101. In the current comparative embodiment, the molding compound 120 does not cover the sides 101S of the multilayer ETS 101. In some embodiments, the sides 101S of the multilayer ETS 101 are exposed to the environment, and the exposed sides 101S may be composed of an organic dielectric material such as BT (bismaleimide-triazine) resin or epoxy resin.

[0052] As discussed earlier, organic materials are directly exposed to the surrounding environment and, due to their high hygroscopicity (moisture absorption), can cause reliability issues. Therefore, Figure 1A and Figure 1B The reliability of the semiconductor package shown can be greatly affected by the hygroscopicity of the organic substrate material used.

[0053] Figures 2A to 2E Cross-sections of thin semiconductor substrates during intermediate manufacturing operations according to some comparative embodiments of the invention are shown. In some comparative embodiments, the manufactured semiconductor substrates have a thickness of less than 100 μm. Figure 2A In this embodiment, a first carrier 201 coated with a copper layer 211 is provided. A patterned layer 211' (e.g., a photoresist layer) is disposed over the copper layer 211 to allow for... Figure 2B A patterned copper layer 212 is formed in the middle. Figure 2C A solder mask 213 is then formed and patterned on a patterned copper layer 212. A second carrier 202 having a copper layer 215 coated on at least one surface is laminated to the first carrier 201 via the patterned solder mask 213 by a pressing operation, as follows: Figure 2D As explained in [the document]. Subsequently in [the document / document]... Figure 2E A carrier removal operation is performed to remove the first carrier 201 from the second carrier 202 and the laminated layers thereon, followed by copper flash etching to expose the surface of the solder mask 213 away from the copper layer 215. Figure 2E A portion of the first conductive trace 217 in the thin substrate is formed by the support of the second carrier 202, and other conductive traces can be further stacked on the first conductive trace 217 by similar carrier attachment and decarrier operations before the mechanical strength of the thin substrate is sufficient for various manufacturing processes.

[0054] As previously discussed, carrier attachment and removal operations increase the cost of the packaging process, and the attached substrate is easily peeled off from the carrier and causes the cornflower effect during high-temperature processing.

[0055] refer to Figure 3A, Figure 3A A cross-section of a chip-scale package (CSP) 30A having a single embedded trace substrate (ETS) according to some embodiments of the present invention is shown. The CSP 30A includes a patterned conductive layer 301, for example, a single conductive trace embedded in an organic dielectric layer. The patterned conductive layer 301 has a front surface 301F and a rear surface 301B opposite to the front surface 301F. The front surface 301F is closer to the semiconductor chip 302 than the rear surface 301B. In some embodiments, the front surface 301F exposes a portion of the embedded trace to form an electrical connection between the patterned conductive layer 301 and the semiconductor chip 302.

[0056] CSP 30A further includes a first encapsulation 303A placed on the rear surface 301B of the patterned conductive layer 301. (As...) Figure 3A As shown, a first encapsulant 303A covers the rear surface 301B and side surface 301S of the patterned conductive layer 301. Because the side surface 301S of the patterned conductive layer 301 can be composed of a highly hygroscopic organic dielectric material, the coverage of the first encapsulant 303A at the side surface 301S may reduce water absorption at the organic dielectric material and prevent degradation of the patterned conductive layer 301. The CSP 30A further includes a second encapsulant 303B placed on the front surface 301F of the patterned conductive layer 301. The second encapsulant 303B covers the top, sides, and bottom of the semiconductor chip 302, as well as the front surface 301F of the patterned conductive layer 301. At the edge of the CSP 30A, the first encapsulant 303A and the second encapsulant 303B are in direct contact, and the boundary between the two encapsulants can be observed. For example, in CSP 30A, a horizontal boundary that is substantially flush with the front surface 301F of the patterned conductive layer 301 can be observed.

[0057] Figure 3A The CSP 30A further includes a conductive element 305 disposed on the rear surface 301B of the patterned conductive layer 301 and electrically connected to embedded traces in the patterned conductive layer 301. In some embodiments, the conductive element 305 is partially surrounded by a first encapsulation 303A. For example, such as Figure 3AAs depicted, the conductive element 305 includes a first portion 305A laterally encapsulated by a first encapsulant 303A and a second portion 305B extending from the surface of the first encapsulant 303A. The first portion 305A and the second portion 305B are physically bonded and may be composed of the same or different materials. For example, the first portion 305A may be composed of solder or copper in the form of solder pillars or copper pillars. The second portion 305B may be composed of solder bumps or solder balls. In some embodiments, the first portion 305A has a first surface in direct contact with embedded traces in the patterned conductive layer 301 and a second surface opposite to the first surface. The second surface is coplanar with the bottom surface of the first encapsulant 303A. The bottom surface of the first encapsulant 303A is farther from the semiconductor chip 302 than the top surface of the first encapsulant 303A.

[0058] The first encapsulant 303A of CSP 30A may consist of epoxy resin and filler for enhanced thermal conductivity. The filler may be spherical or cylindrical. In some embodiments, incomplete filler may be observed at such bottom surfaces due to a planarization operation, for example, filler in broken spheres or broken cylinders. To prevent water absorption at the organic dielectric material of the patterned conductive layer 301, the first encapsulant 303A may have a water absorption rate lower than, for example, less than or equal to 0.5% of the encapsulated organic material. The first encapsulant 303A may be selected from dielectric materials having a Young's modulus greater than or equal to 15 GPa to provide sufficient mechanical support for the patterned conductive layer 301 during its fabrication and processing.

[0059] The second encapsulant 303B may be composed of the same or different materials as the first encapsulant 303A. For example, the second encapsulant 303B may or may not be composed of epoxy resin and fillers, or incomplete fillers. The second encapsulant 303B may or may not have a water absorption rate of less than or equal to 0.5% or a Young's modulus of greater than or equal to 15 GPa.

[0060] Figure 3B A lattice array (LGA) package 30B with a single embedded trace substrate (ETS) is shown according to some embodiments of the present invention. Figure 3B and Figure 3A The same numerical markings in the diagram indicate similar elements or their equivalents, and will not be repeated here for the sake of brevity. The conductive element 305 in the LGA package 30B may consist of solder pillars that are laterally surrounded by a first encapsulation 303A. The bottom of the solder pillars may be coplanar with the bottom surface of the first encapsulation 303A.

[0061] Figures 4A to 4G The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 3A The cross-section of CSP30A. In Figure 4A In this process, a patterned conductive layer 301 (e.g., a single-layer embedded trace structure) is formed on a carrier 400. The patterned conductive layer 301 has a front surface 301F in contact with the carrier 400 and a rear surface 301B opposite to the front surface 301F. Side surfaces 301S of the patterned conductive layer 301 connect the front surface 301F and the rear surface 301B. In some embodiments, the organic dielectric material is patterned to expose a portion of the conductive traces. Figure 4B In this process, a first portion 305A of the conductive element (e.g., a copper pillar or solder pillar) is connected to the conductive trace via an opening previously exposed from the organic dielectric material, for example, through a photolithography operation. The first portion 305A of the conductive element extends from the rear surface 301B of the patterned conductive layer 301. A first encapsulation layer 303A' is formed to cover the first portion 305A of the conductive element, the rear surface 301B of the patterned conductive layer 301, and the side surfaces 301S, as shown. Figure 4C As shown in the diagram. Prior to the monomerization operation, multiple patterned conductive layer units can be formed on the carrier 400 until... Figure 4C Operations within, such as... Figure 5A and Figure 5B As discussed in the text.

[0062] Figure 4D A carrier removal operation is illustrated, wherein the carrier 400 detaches from the patterned conductive layer 301 and the first encapsulation layer 303A', exposing the front surface 301F of the patterned conductive layer 301. The semiconductor chip 302 is a flip chip bonded to the conductive traces exposed at the front surface 301F of the patterned conductive layer 301 and subsequently encapsulated by the second encapsulation layer 303B'. Figure 4E As shown, the second encapsulation layer 303B' covers the semiconductor chip 302, the front surface 301F of the patterned conductive layer 301, and the first encapsulation layer 303A'. Figure 4F This is a planarization or thinning operation, wherein the first encapsulation layer 303A' is planarized or thinned until a first portion 305A of the conductive element is exposed or a coplanar surface is formed consisting of the first encapsulation layer 303A and the first portion 305A of the conductive element. The second encapsulation layer 303B' may optionally be thinned at the current or previous operation to obtain a second encapsulation layer 303B with a desired thickness. Figure 4G In this configuration, the second portion 305B of the conductive element (e.g., a solder ball or solder bump) is connected to the first portion 305A and electrically connected to the patterned conductive layer 301 and the semiconductor chip 302.

[0063] Figure 5A Some embodiments according to the present invention are shown. Figure 4B The cross-section of the semiconductor substrate 50A, and Figure 5BPreparation for monomerization according to some embodiments of the present invention is shown. Figure 4C The cross-section of the semiconductor substrate 50B. As previously described, prior to the monomerization operation, multiple patterned conductive layer units 500A, 500B, 500C, and 500D are formed on the carrier 400, such as... Figure 5A As shown in the diagram. Subsequently, a first encapsulation layer 303A' is formed over a plurality of patterned conductive layer units 500A, 500B, 500C, and 500D, filling the gaps 500AB, 500BC, and 500CD between adjacent patterned conductive layer units. The semiconductor substrate 50B is then die-cut into a plurality of monomeric substrate chips for subsequent packaging operations. Each of the monomeric substrate chips has a side surface 301S covered by the first encapsulation layer 303A', as shown in the diagram. Figure 4C As explained in the text.

[0064] Figures 6A to 6F The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 3B The cross-section of the LGA package 30B. Figure 6A In this process, a patterned conductive layer 301 (e.g., a single-layer embedded trace structure) is formed on the carrier 600. The patterned conductive layer 301 has a front surface 301F in contact with the carrier 600 and a rear surface 301B opposite to the front surface 301F. Side surfaces 301S of the patterned conductive layer 301 connect the front surface 301F and the rear surface 301B. In some embodiments, the organic dielectric material is patterned to expose a portion of the conductive traces. Figure 6B In this configuration, a conductive element 305 (e.g., a solder bump or solder ball) is connected to a conductive trace via an opening previously exposed from the organic dielectric material. A first portion 305A of the conductive element extends from the rear surface 301B of the patterned conductive layer 301. A first encapsulation layer 303A' is formed to cover the conductive element 305, the rear surface 301B of the patterned conductive layer 301, and the side surfaces 301S, as shown. Figure 6C As shown in the diagram. Prior to the monomerization operation, multiple patterned conductive layer units can be formed on the carrier 600 until... Figure 6C The operations within.

[0065] Figure 6D A carrier removal operation is illustrated, wherein the carrier 600 detaches from the patterned conductive layer 301 and the first encapsulation layer 303A', exposing the front surface 301F of the patterned conductive layer 301. The semiconductor chip 302 is a flip chip bonded to the conductive traces exposed at the front surface 301F of the patterned conductive layer 301 and subsequently encapsulated by the second encapsulation layer 303B'. Figure 6E As shown, the second encapsulation layer 303B' covers the semiconductor chip 302, the front surface 301F of the patterned conductive layer 301, and the first encapsulation layer 303A'. Figure 6F The first encapsulation layer 303A' is planarized or thinned until the conductive element 305 is exposed, forming a coplanar surface composed of the first encapsulation layer 303A and the conductive element 305. The second encapsulation layer 303B' may optionally be thinned at the current operation or a previous operation to obtain a second encapsulation layer 303B with a desired thickness.

[0066] Figures 7A to 7E A cross-section of a semiconductor package during intermediate manufacturing operations is shown, according to some embodiments of the present invention. Figure 7A In this process, a patterned conductive layer 301 (e.g., a single-layer embedded trace structure) is formed on the carrier 700. The patterned conductive layer 301 has a front surface 301F in contact with the carrier 700 and a rear surface 301B opposite to the front surface 301F. Side surfaces 301S of the patterned conductive layer 301 connect the front surface 301F and the rear surface 301B. In some embodiments, the organic dielectric material is patterned to expose a portion of the conductive traces. Figure 7B In this process, the first encapsulation layer 303A' is formed to cover the patterned conductive layer 301 and the carrier 700. Multiple patterned conductive layer units can be formed on the carrier 700 prior to the monomerization operation. Figure 7B Operations within, such as... Figure 8A and Figure 8B As described in the text.

[0067] Figure 7C A carrier removal operation is illustrated, wherein the carrier 700 detaches from the patterned conductive layer 301 and the first encapsulation layer 303A', exposing the front surface 301F of the patterned conductive layer 301. The semiconductor chip 302 is a flip chip bonded to conductive traces exposed at the front surface 301F of the patterned conductive layer 301 and subsequently encapsulated by a second encapsulation layer 303B'. The second encapsulation layer 303B' covers the semiconductor chip 302, the front surface 301F of the patterned conductive layer 301, and the first encapsulation layer 303A'. Optionally, the first encapsulation layer 303A' may be planarized or thinned until the first encapsulation 303A has a desired thickness. Figure 7D In this process, a portion of the first encapsulation 303A is removed to expose conductive traces in the patterned conductive layer 301 via an opening 303C. In some embodiments, the opening 303C is formed by machining, laser etching, or photolithography. The type of laser includes carbon dioxide lasers, YAG (yttrium aluminum garnet) lasers, excimer lasers, etc., with carbon dioxide lasers being preferred. In some embodiments, the size of the opening is determined based on the size of the conductive element 305 (e.g., solder balls or solder paste). Figure 7EAs shown, conductive element 305 can be placed or filled into opening 303C, followed by appropriate reflow operation. Conductive element 305 can protrude from the bottom surface of first encapsulation 303A.

[0068] Figure 8A Some embodiments according to the present invention are shown. Figure 7A The cross-section of the semiconductor substrate 80A, and Figure 8B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 7B The cross-section of the semiconductor substrate 80B. As previously described, prior to the monomerization operation, multiple patterned conductive layer units 800A, 800B, 800C, and 800D are formed on the carrier 700, such as... Figure 8A As shown in the diagram. Subsequently, a first encapsulation layer 303A' is formed over a plurality of patterned conductive layer units 800A, 800B, 800C, and 800D, filling the gaps 500AB, 500BC, and 500CD between adjacent patterned conductive layer units. The semiconductor substrate 80B is then die-cut into a plurality of monomeric substrate chips for subsequent packaging operations. Each of the monomeric substrate chips has a side surface 301S covered by the first encapsulation layer 303A', as shown in the diagram. Figure 7B As explained in the text.

[0069] refer to Figure 9A , Figure 9A A cross-section of a chip-scale package (CSP) 90A having a two-layer embedded trace substrate (ETS) is shown according to some embodiments of the present invention. The CSP 90A includes a patterned conductive layer 901, for example, two conductive traces at least partially embedded in an organic dielectric layer 9010. For example, the two conductive traces include a first conductive layer 9011 near a front surface 901F, a second conductive layer 9012 near a rear surface 901B, and a conductive via 9013 connecting the first conductive layer 9011 and the second conductive layer 9012. The second conductive layer 9012 may be exposed from the organic dielectric layer 9010. The patterned conductive layer 901 has a front surface 901F and a rear surface 901B opposite to the front surface 901F. The front surface 901F is closer to the semiconductor chip 902 than the rear surface 901B. In some embodiments, the front surface 901F exposes a portion of the embedded traces to form an electrical connection between the patterned conductive layer 901 and the semiconductor chip 902.

[0070] CSP 90A further includes a first encapsulation 903A placed at the rear surface 901B of the patterned conductive layer 901. As... Figure 9AAs shown, a first encapsulant 903A covers the rear surface 901B and side surface 901S of the patterned conductive layer 901. Because the side surface 901S of the patterned conductive layer 901 can be composed of a highly hygroscopic organic dielectric material, the coverage of the first encapsulant 903A at the side surface 901S may reduce water absorption at the organic dielectric material and prevent degradation of the patterned conductive layer 901. The CSP 90A further includes a second encapsulant 903B placed on the front surface 901F of the patterned conductive layer 901. The second encapsulant 903B covers the top, sides, and bottom of the semiconductor chip 902, as well as the front surface 901F of the patterned conductive layer 901. At the edge of the CSP 90A, the first encapsulant 903A and the second encapsulant 903B are in direct contact, and the boundary between the two encapsulants can be observed. For example, in CSP 90A, a horizontal boundary that is substantially flush with the front surface 901F of the patterned conductive layer 901 can be observed.

[0071] Figure 9A The CSP 90A further includes a conductive element 905 disposed at the rear surface 901B of the patterned conductive layer 901 and electrically connected to embedded traces in the patterned conductive layer 901. In some embodiments, the conductive element 905 is partially surrounded by a first encapsulation 903A. For example, such as Figure 9A As depicted, the conductive element 905 includes a first portion 905A laterally encapsulated by a first encapsulant 903A and a second portion 905B extending from the surface of the first encapsulant 903A. The first portion 905A and the second portion 905B are physically bonded and may be composed of the same or different materials. For example, the first portion 905A may be composed of solder or copper in the form of solder pillars or copper pillars. The second portion 905B may be composed of solder bumps or solder balls. In some embodiments, the first portion 905A has a first surface in direct contact with embedded traces in the patterned conductive layer 901 and a second surface opposite to the first surface. The second surface is coplanar with the bottom surface of the first encapsulant 903A. The bottom surface of the first encapsulant 903A is farther from the semiconductor chip 902 than the top surface of the first encapsulant 903A.

[0072] The first encapsulant 903A of the CSP 90A may consist of epoxy resin and filler for enhanced thermal conductivity. The filler may be spherical or cylindrical. In some embodiments, incomplete filler may be observed at such bottom surfaces due to a planarization operation at the bottom surface of the first encapsulant 903A, for example, filler in broken spheres or broken cylinders. To prevent water absorption at the organic dielectric material of the patterned conductive layer 901, the first encapsulant 903A may have a water absorption rate lower than, for example, less than or equal to 0.5% of the encapsulated organic material. The first encapsulant 903A may be selected from dielectric materials having a Young's modulus greater than or equal to 15 GPa to provide sufficient mechanical support for the patterned conductive layer 901 during its fabrication and processing.

[0073] The second encapsulant 903B may be composed of the same or different materials as the first encapsulant 903A. For example, the second encapsulant 903B may or may not be composed of epoxy resin and fillers, or incomplete fillers. The second encapsulant 903B may or may not have a water absorption rate of less than or equal to 0.5% or a Young's modulus of greater than or equal to 15 GPa.

[0074] Figure 9B A lattice array (LGA) package 90B with a single-layer embedded trace substrate (ETS) is shown according to some embodiments of the present invention. Figure 9B and Figure 3A The same numerical markings in the diagram indicate similar elements or their equivalents, and will not be repeated here for the sake of brevity. The conductive element 905 in the LGA package 90B may consist of solder pillars laterally surrounded by a first encapsulation 903A. The bottom of the solder pillars may be coplanar with the bottom surface of the first encapsulation 903A.

[0075] Figures 10A to 10G The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 9A The cross-section of CSP 90A. In Figure 10A In this process, a patterned conductive layer 901 (e.g., a two-layer embedded trace structure) is formed on the carrier 1000. The patterned conductive layer 901 has a front surface 901F in contact with the carrier 1000 and a rear surface 901B opposite to the front surface 901F. The side surfaces 901S of the patterned conductive layer 901 connect the front surface 901F and the rear surface 901B. A continuous conductive layer 9011' covers the top surface of the carrier 1000 and connects the individual patterns of the first conductive layer 9011. Figure 10BIn this process, a first portion 905A of the conductive element (e.g., a copper pillar or solder pillar) is connected to the conductive trace via an opening previously exposed from the organic dielectric material, for example, through a photolithography operation. The first portion 905A of the conductive element extends from the rear surface 901B of the patterned conductive layer 901. A first encapsulating layer 903A' is formed to cover the first portion 905A of the conductive element, the rear surface 901B of the patterned conductive layer 901, and the side surfaces 901S, as shown. Figure 10C As shown in the figure. Prior to the monomerization operation, multiple patterned conductive layer units can be formed on the carrier 1000 until... Figure 10C Operations within, such as... Figure 11A and Figure 11B As discussed in the text.

[0076] Figure 10D The diagram illustrates a carrier removal operation, in which the carrier 1000 detaches from the patterned conductive layer 901 and the first encapsulation layer 903A', exposing the front surface 901F of the patterned conductive layer 901. The continuous conductive layer 9011' is removed in this operation by a flash etching operation. The semiconductor chip 902 is a flip chip bonded to the conductive traces exposed at the front surface 901F of the patterned conductive layer 901 and subsequently encapsulated by the second encapsulation layer 903B'. Figure 10E As shown, the second encapsulation layer 903B' covers the semiconductor chip 902, the front surface 901F of the patterned conductive layer 901, and the first encapsulation layer 903A'. Figure 10F This is a planarization or thinning operation, wherein the first encapsulation layer 903A' is planarized or thinned until a first portion 905A of the conductive element is exposed or a coplanar surface is formed consisting of the first encapsulation layer 903A and the first portion 905A of the conductive element. The second encapsulation layer 903B' may optionally be thinned at the current or previous operation to obtain a second encapsulation layer 903B having a desired thickness. Figure 10G In this configuration, a second portion 905B of the conductive element (e.g., a solder ball or solder bump) is connected to a first portion 905A and electrically connected to a patterned conductive layer 901 and a semiconductor chip 902.

[0077] Figure 10CA , Figure 10CB , Figure 10CC , Figure 10CD This is a cross-section of the CSP 90A during intermediate manufacturing operations according to some embodiments of the present invention. Figure 10CA In Figure 10C Following the operation, the probe hole 9030 can be opened by aligning with the first portion 905A of the conductive element 905, supported mechanically by the first encapsulation layer 903A'. The probe hole 9030 can be formed using various techniques, including (but not limited to) within... Figure 7D The technology described in [the document]. Figure 10CBThis is a carrier removal operation, whereby the carrier 1000 can be detached from the patterned conductive layer 901. Figure 10CC In this process, the continuous conductive layer 9011' can be removed via a flash etch operation. Figure 10CD In this configuration, test probe 1010B can access the first portion 905A of conductive element 905 from the rear surface 901B to perform various electrical tests. Similarly, test probe 1010F can access the first conductive layer 9011 of the conductive two-layer embedded trace structure from the front surface 901F to perform various electrical tests. In some embodiments, performing electrical tests using both test probes 1010B and 1010F simultaneously can provide early screening of defective patterned conductive layer cells and further reduce die loss rate after package assembly.

[0078] In a single-layer embedded trace structure, optical inspection is used for early screening of defective patterned conductive layer cells. However, in two- or more-layer embedded trace structures, this invention allows electrical testing to be performed early in the fabrication of thin substrates (e.g., substrates thinner than 100 μm). By forming a first encapsulation layer 903A' over the carrier 1000, subsequent processing of the thin substrate can be supported solely by the first encapsulation layer 903A' and avoid the application of a second carrier, as in... Figures 2A to 2E The comparative examples described herein.

[0079] Figure 11A Some embodiments according to the present invention are shown. Figure 10B The cross-section of the semiconductor substrate 110A, and Figure 11B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 10C The cross-section of the semiconductor substrate 110B. As previously described, prior to the monomerization operation, a plurality of patterned conductive layer units 1100A, 1100B, and 1100C are formed on the carrier 1000, such as... Figure 11A As shown in the diagram. Subsequently, a first encapsulation layer 903A' is formed over a plurality of patterned conductive layer units 1100A, 1100B, and 1100C, filling the gaps 1100AB and 1100BC between adjacent patterned conductive layer units. The semiconductor substrate 110B is then die-cut into a plurality of monomeric substrate chips for subsequent packaging operations. Each of the monomeric substrate chips has a side surface 901S covered by the first encapsulation layer 903A', as shown in the diagram. Figure 10C As explained in the text.

[0080] Figures 12A to 12E The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 9A The cross-section of CSP 90A. In Figure 12AIn this process, a patterned conductive layer 901 (e.g., a two-layer embedded trace structure) is formed on the carrier 1200. The patterned conductive layer 901 has a front surface 901F in contact with the carrier 1200 and a rear surface 901B opposite to the front surface 901F. The side surfaces 901S of the patterned conductive layer 901 connect the front surface 901F and the rear surface 901B. A continuous conductive layer 9011' covers the top surface of the carrier 1000 and connects the individual patterns of the first conductive layer 9011. Figure 12B In this process, the first encapsulation layer 903A' is formed to cover the rear surface 901B and side surface 901S of the patterned conductive layer 901. Multiple patterned conductive layer units can be formed on the carrier 1200 prior to the monomerization operation. Figure 12B Operations within, such as... Figure 13A and Figure 13B As discussed in the text.

[0081] Figure 12C A carrier removal operation is illustrated, in which the carrier 1200 detaches from the patterned conductive layer 901 and the first encapsulation layer 903A', exposing the front surface 901F of the patterned conductive layer 901. The continuous conductive layer 9011' is removed in the current operation by a flash etching operation. The semiconductor chip 902 is a flip chip bonded to the conductive traces exposed at the front surface 901F of the patterned conductive layer 901 and subsequently encapsulated by the second encapsulation layer 903B'. Figure 12C As shown, the second encapsulation layer 903B' covers the semiconductor chip 902, the front surface 901F of the patterned conductive layer 901, and the first encapsulation layer 903A'. The first encapsulation layer 903A' can be thinned to a desired thickness in current or previous operations to obtain the first encapsulation 903A. Figure 12D In this process, a portion of the first encapsulation 903A is removed to expose a portion of the second conductive layer 9012. The removal of the first encapsulation 903A forms an opening 903C within the first encapsulation 903A aligned with the conductive traces of the second conductive layer 9012. Solder paste or solder balls are placed in the opening 903C and filled by a proper reflow operation to form a conductive element 905 extending from the bottom surface of the first encapsulation 903A.

[0082] Figure 13A Some embodiments according to the present invention are shown. Figure 12A The cross-section of the semiconductor substrate 130A, and Figure 13B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 12B The cross-section of the semiconductor substrate 130B. As previously described, prior to the monomerization operation, a plurality of patterned conductive layer units 1300A, 1300B, and 1300C are formed on the carrier 1200, such as... Figure 13AAs shown in the diagram. Subsequently, a first encapsulation layer 903A' is formed over a plurality of patterned conductive layer units 1300A, 1300B, and 1300C, filling the gaps 1300AB and 1300BC between adjacent patterned conductive layer units. The semiconductor substrate 130B is then die-cut into a plurality of monomeric substrate chips for subsequent packaging operations. Each of the monomeric substrate chips has a side surface 901S covered by the first encapsulation layer 903A', as shown in the diagram. Figure 12B As explained in the text.

[0083] Figures 14A to 14F The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 9B The cross-section of the LGA 90B package. Figure 14A In this process, a patterned conductive layer 901 (e.g., a two-layer embedded trace structure) is formed on the carrier 1400. The patterned conductive layer 901 has a front surface 901F in contact with the carrier 1400 and a rear surface 901B opposite to the front surface 901F. A side surface 901S of the patterned conductive layer 901 connects the front surface 901F and the rear surface 901B. A solder mask layer 9010' is patterned through an opening above a second conductive layer 9012 of the patterned conductive layer 901. Figure 14B In this process, solder balls or solder paste are placed at the openings exposing the second conductive layer 9012, followed by a proper reflow operation to form the conductive element 905. The conductive element 905 may extend from the solder mask layer 9010'. Figure 14C In this process, the first encapsulation layer 903A' is formed to cover the rear surface 901B and side surface 901S of the patterned conductive layer 901. Multiple patterned conductive layer units can be formed on the carrier 1400 prior to the monomerization operation. Figure 14C Operations within, such as... Figure 15A and Figure 15B As discussed in the text.

[0084] Figure 14D A carrier removal operation is illustrated, wherein the carrier 1400 detaches from the patterned conductive layer 901 and the first encapsulation layer 903A', exposing the front surface 901F of the patterned conductive layer 901. The semiconductor chip 902 is a flip chip bonded to the conductive traces exposed at the front surface 901F of the patterned conductive layer 901 and subsequently encapsulated by the second encapsulation layer 903B'. Figure 14E As shown, the second encapsulation layer 903B' covers the semiconductor chip 902, the front surface 901F of the patterned conductive layer 901, and the first encapsulation layer 903A'. The first encapsulation layer 903A' is then thinned in the current operation to a desired thickness to obtain a first encapsulation 903A to expose the conductive element 905 from the first encapsulation 903A, as... Figure 14FAs shown in the figure. In some embodiments, the bottom surface of the first encapsulation 903A and the exposed surface of the conductive element 905 are coplanar.

[0085] Figure 15A Some embodiments according to the present invention are shown. Figure 14B The cross-section of the semiconductor substrate 150A, and Figure 15B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 14C The cross-section of the semiconductor substrate 150B. As previously described, prior to the monomerization operation, a plurality of patterned conductive layer units 1500A, 1500B, and 1500C are formed on the carrier 1400, such as... Figure 15A As shown in the diagram. Subsequently, a first encapsulation layer 903A' is formed over a plurality of patterned conductive layer units 1500A, 1500B, and 1500C, filling the gaps 1500AB and 1500BC between adjacent patterned conductive layer units. The semiconductor substrate 150B is then die-cut into a plurality of monomeric substrate chips for subsequent packaging operations. Each of the monomeric substrate chips has a side surface 901S covered by the first encapsulation layer 903A', and the side surface of the solder mask layer 9010' is also covered by the first encapsulation layer 903A', as shown in the diagram. Figure 14C As explained in the text.

[0086] Figure 16A , Figure 16B and Figure 16C Cross-sections of chip-scale packages (CSPs) 160A, 160B, and 160C with two-layer embedded trace substrates (ETS) integrated with passive devices are shown. Figure 16A In this context, a passive device 907, such as a resistor, capacitor, or inductor, is disposed on the rear surface 901B of a patterned conductive layer 901 and encapsulated by a first encapsulant 903A. In, for example, the currently used... Figure 14B The passive device 907 shown in the diagram can be integrated into the patterned conductive layer 901 and electrically connected to the semiconductor chip 902 via the patterned conductive layer 901.

[0087] exist Figure 16B In this configuration, multiple passive devices 907 are exposed at the front surface 901F of the patterned conductive layer 901 and encapsulated by a second encapsulant 903B. An additional semiconductor chip 908 is a flip chip bonded to the rear surface 901B, encapsulated by a first encapsulant 903A, and electrically coupled to conductive traces in the patterned conductive layer 901. In, for example, in the current application... Figure 14E The operation shown can integrate multiple passive devices 907 into the patterned conductive layer 901. For example, in the current application... Figure 14B The additional semiconductor chip 908 shown in the diagram can be integrated into the patterned conductive layer 901. Figure 16C The CSP160C in the middle is similar to that in Figure 16B The difference between the CSP 160B and the CSP 160B is that the additional semiconductor chip 908 is wire-bonded to the back surface 901B, encapsulated by the first encapsulant 903A, and electrically coupled to conductive traces in the patterned conductive layer 901.

[0088] refer to Figure 17A , Figure 17A A cross-section of a chip-scale package (CSP) having a single-layer molded interconnect substrate (MIS) is shown according to some embodiments of the present invention. CSP 170A includes a patterned conductive layer 1701, for example, a single layer of conductive traces embedded in a first encapsulation 1703A. Optionally, a solder mask layer 1701A' is disposed on the conductive traces 1701A. The patterned conductive layer 1701 has a front surface 1701F and a rear surface 1701B opposite to the front surface 1701F. The front surface 1701F is closer to the semiconductor chip 1702 than the rear surface 1701B. In some embodiments, the front surface 1701F exposes a portion of the embedded traces to form an electrical connection between the patterned conductive layer 1701 and the semiconductor chip 1702.

[0089] CSP 170A further includes a first encapsulation 1703A placed at the rear surface 1701B of the patterned conductive layer 1701. As... Figure 17A As shown, the first encapsulant 1703A covers the rear surface 1701B and side surface 1701S of the patterned conductive layer 1701. The CSP 170A further includes a second encapsulant 1703B placed at the front surface 1701F of the patterned conductive layer 1701. The second encapsulant 1703B covers the top, sides, and bottom of the semiconductor chip 1702, as well as the front surface 1701F of the patterned conductive layer 1701. At the edge of the CSP 170A, the first encapsulant 1703A and the second encapsulant 1703B are in direct contact, and a boundary between the two encapsulants can be observed. For example, a horizontal boundary substantially flush with the front surface 1701F of the patterned conductive layer 1701 can be observed in the CSP 170A.

[0090] Figure 17A The CSP 170A further includes a conductive element 1705 disposed on the rear surface 1701B of the patterned conductive layer 1701 and electrically connected to the conductive trace 1701A in the patterned conductive layer 1701. In some embodiments, the conductive element 1705 is partially surrounded by a first encapsulation 1703A. For example, Figure 3A As depicted, the conductive element 305 is surrounded by and extends from the first encapsulation 1703A portion.

[0091] The first encapsulant 1703A of CSP 170A may consist of epoxy resin and filler for enhanced thermal conductivity. The filler may be spherical or cylindrical. In some embodiments, incomplete filler may be observed at such bottom surfaces due to a planarization operation at the bottom surface of the first encapsulant 1703A, for example, filler in a broken sphere or broken cylinder. The first encapsulant 303A may be selected from dielectric materials having a Young's modulus greater than or equal to 15 GPa to provide sufficient mechanical support during the fabrication and processing of the patterned conductive layer 1701.

[0092] The second encapsulant 1703B may be composed of the same or different materials as the first encapsulant 1703A. For example, the second encapsulant 1703B may or may not be composed of epoxy resin and fillers, or incomplete fillers. The second encapsulant 1703B may or may not have a Young's modulus greater than or equal to 15 GPa.

[0093] Figure 17B A lattice array (LGA) package 170B with a single-layer molded interconnect substrate (MIS) is shown according to some embodiments of the present invention. Figure 17B and Figure 17A The same numerical markings in the diagram indicate similar elements or their equivalents, and will not be repeated here for the sake of brevity. The conductive element 1705 in the LGA package 170B may consist of solder pillars that are laterally surrounded by a first encapsulation 1703A. The bottom of the solder pillars may be coplanar with the bottom surface of the first encapsulation 1703A.

[0094] Figures 18A to 18G The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 17A CSP 170A and Figure 17B The cross-section of the LGA package 170B. Figure 18A In this process, a patterned conductive layer 1701 (e.g., a conductive trace 1701A and optionally a solder mask layer 1701A') is formed on a carrier 1800. An open-ended patterned solder mask layer 1701A' is disposed above the conductive trace 1701A. The patterned conductive layer 1701 has a front surface 1701F in contact with the carrier 1800 and a rear surface 1701B opposite to the front surface 1701F. A side surface 1701S of the patterned conductive layer 1701 connects the front surface 1701F and the rear surface 1701B. Figure 18B In this context, conductive elements 1705, such as solder balls or solder paste, are connected to conductive traces 1701A via openings previously exposed from the solder mask layer 1701A'. Figure 18B In other embodiments not shown, the conductive element 1705 may be a copper pillar or a solder pillar, as previously described. Figure 10BAs described herein. The conductive element 1705 extends from the rear surface 1701B of the patterned conductive layer 1701. A first encapsulation layer 1703A' is formed to cover the conductive element 1705, the rear surface 1701B of the patterned conductive layer 1701, and the side surfaces 1701S, as described above. Figure 18C As shown in the diagram, conductive trace 1701A and the first encapsulation layer 1703A' together form a molded interconnect substrate (MIS). Multiple patterned conductive layer units can be formed on the carrier 1800 prior to the monomerization operation. Figure 18C Operations within, such as... Figure 19A and Figure 19B As discussed in the text.

[0095] Figure 18D A carrier removal operation is illustrated, wherein the carrier 1800 detaches from the patterned conductive layer 1701 and the first encapsulation layer 1703A', exposing the front surface 1701F of the patterned conductive layer 1701. The semiconductor chip 1702 is a flip chip bonded to the conductive traces exposed at the front surface 1701F of the patterned conductive layer 1701 and subsequently encapsulated by the second encapsulation layer 1703B'. Figure 18E As shown, the second encapsulation layer 1703B' covers the semiconductor chip 1702, the front surface 1701F of the patterned conductive layer 1701, and the first encapsulation layer 1703A'. Figure 18F The first encapsulation layer 1703A' is planarized or thinned until the conductive element 1705 is exposed, or a coplanar surface consisting of the first encapsulation layer 1703A and the conductive element 1705 is formed. The second encapsulation layer 1703B' can optionally be thinned at the current or previous operation to obtain a second encapsulation layer 1703B with a desired thickness. An LGA package with a single-layer MIS is formed on... Figure 18F In the middle. Alternatively, in Figure 18G In this context, the conductive element 1705 may be a solder ball connected to the conductive trace 1701A in the MIS via an opening in a laser-drilled hole in the first encapsulation 1703A, as can be seen from the previously described... Figure 12D and Figure 12E .exist Figure 18G A CSP with a single layer of MIS is formed in the middle.

[0096] Figure 18AA , Figure 18BB , Figure 18CC , Figure 18DD , Figure 18EE , Figure 18FF and Figure 18GG A cross-section of a semiconductor package with two-layer MIS is shown during intermediate manufacturing operations according to some embodiments of the present invention. Figure 18AAIn this structure, a patterned conductive layer 1801 (e.g., a two-layer MIS structure having a first portion 1805A of conductive elements 1805 and a first encapsulation layer 1803A') is formed above the carrier 1800. The patterned conductive layer 1801 has a front surface 1801F close to the carrier 1800 and a rear surface 1801B away from the carrier. Figure 18BB In this process, a plurality of test holes 1801' are formed in the first encapsulation layer 1803A', wherein alignment with the conductive traces of the patterned conductive layer 1801 is achieved through (but not limited to) previously... Figure 10CA The method described herein can be formed and referenced Figure 10CA . Figure 18CC This is a carrier removal operation, in which the carrier 1800 is detached from the patterned conductive layer 1801 followed by a copper flash etching operation. Figure 18DD In this configuration, test probe 1810B can approach the first portion 1805A of conductive element 1805 from the rear surface 1801B to perform various electrical tests. Similarly, test probe 1810F can approach the conductive traces of the MIS from the front surface 1801F to perform various electrical tests. In some embodiments, performing electrical tests using both test probes 1810B and 1810F simultaneously can provide early screening of defective MIS cells and further reduce die loss rates after package assembly.

[0097] exist Figure 18EE In the process, after electrical testing, the semiconductor chip 1802 is a flip chip bonded from the front surface 1801F to the exposed conductive traces of the patterned conductive layer 1801. The second encapsulation layer 1803B' covers the semiconductor chip 1802, the front surface 1801F of the patterned conductive layer 1801, and the first encapsulation layer 1803A'. Figure 18FF This is a planarization or thinning operation, wherein the first encapsulation layer 1803A' is planarized or thinned until a first portion 1805A of the conductive element 1805 is exposed, or a coplanar surface is formed consisting of the first encapsulation layer 1803A and the first portion 1805A of the conductive element 1805. The second encapsulation layer 1803B' may optionally be thinned at the current or previous operation to obtain a second encapsulation layer 1803B having a desired thickness. Figure 18GG In this configuration, the second portion 1805B of the conductive element 1805 (e.g., a solder ball) can be positioned to align with the first portion 1805A of the conductive element 1805. Figure 18GG A CSP with two patterned conductive layers 1801 can be obtained.

[0098] Figure 18AA '、 Figure 18BB '、 Figure 18CC 'and Figure 18DDThe illustration shows a cross-section of a semiconductor package having two layers of resin-coated copper (RCC) embedded trace substrate (ETS) during intermediate manufacturing operations according to some embodiments of the present invention. Figure 18AA '、 Figure 18BB '、 Figure 18CC 'and Figure 18DD Similar to Figure 18AA , Figure 18BB , Figure 18CC and 18DD The difference lies in that the patterned conductive layer 1801 consists of two layers of RCC ETS. A first portion 1805A of the conductive element 1805 is formed over the patterned conductive layer 1801 and is also encapsulated by a first encapsulant 1803A' (e.g., RCC dielectric). Since the RCC dielectric may not be glass fiber reinforced, a copper layer 1804A' is coated onto the RCC dielectric to enhance its stability. Figure 18BB In the first encapsulation layer 1803A, a plurality of test holes 1801 are formed, wherein alignment with the conductive traces of the patterned conductive layer 1801 is achieved through (but not limited to) the previously formed conductive traces in the patterned conductive layer 1801. Figure 10CA The method described in [the document] can be referenced. Figure 10CA . Figure 18CC 'This is a carrier removal operation, in which the carrier 1800 is detached from the patterned conductive layer 1801 and subsequently subjected to a copper flash etching operation.' Figure 18DD In this configuration, test probe 1810B can approach the first portion 1805A of conductive element 1805 from the rear surface 1801B to perform various electrical tests. Similarly, test probe 1810F can approach the conductive traces of the patterned conductive layer 1801 from the front surface 1801F to perform various electrical tests. In some embodiments, performing electrical tests using both test probes 1810B and 1810F simultaneously can provide early screening of defective RCC ETS cells and further reduce die loss rate after package assembly.

[0099] Figure 18AA "、 Figure 18BB "、 Figure 18CC "and Figure 18DD "A cross-section of a semiconductor package having two printable dielectric ETSs during intermediate manufacturing operations is shown according to some embodiments of the present invention." Figure 18AA "、 Figure 18BB "、 Figure 18CC "and Figure 18DD Similar to Figure 18AA , Figure 18BB , Figure 18CC and 18DDThe difference lies in that the patterned conductive layer 1801 consists of two layers of ETS. A first portion 1805A of the conductive element 1805 is formed above the patterned conductive layer 1801 and is also encapsulated by a first encapsulant 1803A' (e.g., a printable dielectric). Figure 18AA As shown, the printable dielectric has a conformal surface that follows the morphology of the conductive element and the patterned conductive layer 1801. Figure 18BB In this structure, a plurality of test holes 1801' are formed in the first encapsulation layer 1803A', wherein alignment with the conductive traces of the patterned conductive layer 1801 is achieved through (but not limited to) previously... Figure 10CA The method described in [the document] can be referenced. Figure 10CA . Figure 18CC "It is a carrier removal operation, in which the carrier 1800 is detached from the patterned conductive layer 1801 and then a copper flash etching operation is performed. In Figure 18DD In this configuration, test probe 1810B can approach the first portion 1805A of the conductive element from the rear surface 1801B to perform various electrical tests. Similarly, test probe 1810F can approach the conductive traces of the patterned conductive layer 1801 from the front surface 1801F to perform various electrical tests. In some embodiments, performing electrical tests using both test probes 1810B and 1810F simultaneously can provide early screening of defective ETS cells and further reduce die loss rates after package assembly.

[0100] Figure 19A Some embodiments according to the present invention are shown. Figure 18B The cross-section of the semiconductor substrate 190A, and Figure 19B Preparation for monomerization according to some embodiments of the present invention is shown. Figure 18C The cross-section of the semiconductor substrate 190B. As previously described, prior to the monomerization operation, a plurality of patterned conductive layer units 1900A, 1900B, and 1900C are formed on the carrier 1800, such as... Figure 19A As shown in the diagram. Subsequently, a first encapsulation layer 1703A' is formed over a plurality of patterned conductive layer units 1900A, 1900B, and 1900C, filling the gaps 1900AB and 1900BC between adjacent patterned conductive layer units. The semiconductor substrate 190B is then die-cut into a plurality of monomeric substrate chips for subsequent packaging operations. Each of the monomeric substrate chips has a side surface 1701S covered by the first encapsulation layer 1703A', as shown in the diagram. Figure 18C As explained in the text.

[0101] Figure 20AA cross-section of a core semiconductor package 200A with a vertically molded boundary is shown according to some embodiments of the present invention. The core semiconductor package 200A includes a core substrate 2001 having a front surface 2001F and a rear surface 2001B. The core substrate 2001 may be an organic substrate formed of a core layer made of glass fiber reinforced BT (bismaleimide-triazine) resin or FR-4 glass fiber reinforced epoxy resin. In some embodiments, the front surface 2001F exposes a portion of the embedded traces to form an electrical connection between the core substrate 2001 and a semiconductor chip 2002. The core semiconductor package 200A further includes a first encapsulant 2003A disposed at the rear surface 2001B of the core substrate 2001. Figure 20A As shown, the first encapsulant 2003A covers the rear surface 2001B of the core substrate 2001, and the second encapsulant 2003B covers the front surface 2001F and side surface 2001S of the core substrate 2001. Because the side surface 2001S of the patterned conductive layer 301 can be composed of an organic dielectric material with high hygroscopicity, the coverage of the second encapsulant 2003B at the side surface 2001S reduces the water absorption rate at the organic dielectric material and prevents the core substrate 2001 from degrading. The second encapsulant 2003B covers the top, sides, and bottom of the semiconductor chip 2002 and the front surface 2001F of the core substrate 2001. At the edge of the core semiconductor package 200A, the first encapsulant 2003A and the second encapsulant 2003B are in direct contact, and the boundary between the two encapsulants can be observed. For example, in the core semiconductor package 200A, a vertical boundary 2003AB can be observed that is substantially aligned with the side surface 2001S of the core substrate 2001.

[0102] Figure 20B A cross-section of a core semiconductor package 200B with a horizontally molded boundary is shown according to some embodiments of the present invention. The core semiconductor package 200B is similar to the core semiconductor package 200A, except that a first encapsulator 2003A covers the rear surface 2001B and side surface 2001S of the core substrate 2001, while a second encapsulator 2003B covers the top surface 2001F of the core substrate 2001 and the edge portion of the first encapsulator 2003A. At the edge of the core semiconductor package 200B, the first encapsulator 2003A and the second encapsulator 2003B are in direct contact, and a boundary between the two encapsulators can be observed. For example, a horizontal boundary 2003AB substantially flush with the front surface 2001F of the core substrate 2001 can be observed in the core semiconductor package 200B.

[0103] Figures 21A to 21D The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 20AThe cross-section of the core semiconductor package 200A. Figure 21A In this process, a known good substrate 200A' is selected and attached to the first encapsulation layer 2003A' at the rear surface 2001B and placed over the strip 2004. In some embodiments, a conductive element 2005 at the rear surface 2001B of the core substrate 200 is pressed into the first encapsulation layer 2003A'. Figure 21A The operation shown is a substrate reconstruction operation. Figure 21B In this process, semiconductor chip 2002 is a flip chip bonded to the front surface 2001F of core substrate 2001. Subsequently, a second encapsulation layer 2003B' is formed by filling the gap between adjacent known good substrates 200A' to encapsulate the front surface 2001F and side surface 2001S of core substrate 2001. Figure 21C In this process, strip 2004 is removed from the first encapsulation layer 2003A' and a thinning operation is performed to thin the first encapsulation layer 2003A' to a desired thickness. In some embodiments, conductive elements 2005 are exposed from the first encapsulation layer 2003A' after the thinning operation. Figure 21D In this process, solder balls are attached to the exposed conductive element 2005 and a spherical grid array is formed at the rear surface 2001B of the core substrate 2001. A die-cutting operation is then performed to monolithize the semiconductor package into multiple core semiconductor packages 200A, such as... Figure 20A As shown in the image.

[0104] Figures 22A to 22E The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 20B The cross-section of the core semiconductor package 200B. Figure 22A In this process, a known good substrate 200A' is attached to a strip 2004 on the front surface 2001F by a selection and placement operation. The known good substrate 200A' is then molded by a first encapsulation layer 2003A'. The first encapsulation layer 2003A' covers the rear surface 2001B and side surfaces 2001S of the core substrate 2001. Figure 22A The operation shown is a substrate reconstruction operation. Figure 22B In the process, strip 2004 is removed from the molded substrate. Figure 22C In this process, semiconductor chip 2002 is a flip chip bonded to the front surface 2001F of core substrate 2001. Subsequently, a second encapsulation layer 2003B' is formed to encapsulate the front surface 2001F of core substrate 2001 and semiconductor chip 2002. Figure 22D In this process, a thinning operation is performed to thin the first encapsulation layer 2003A' to a desired thickness. In some embodiments, after the thinning operation, the conductive element 2005 is exposed from the first encapsulation layer 2003A'. Figure 22EIn this process, solder balls are attached to the exposed conductive element 2005 and a spherical grid array is formed at the rear surface 2001B of the core substrate 2001. A die-cutting operation is then performed to monolithize the semiconductor package into multiple core semiconductor packages 200B, such as... Figure 20B As shown in the image.

[0105] Figures 23A to 23E The following are illustrated during intermediate manufacturing operations according to some embodiments of the present invention. Figure 20B The cross-section of the core semiconductor package 200B. Figure 23A In this process, a known good substrate 200A' is attached to a strip 2004 on the front surface 2001F by a selection and placement operation. The known good substrate 200A' is then molded by a first encapsulation layer 2003A'. The first encapsulation layer 2003A' covers the rear surface 2001B and side surfaces 2001S of the core substrate 2001. Figure 23A The operation shown is a substrate reconstruction operation. Figure 23B In the next stage, strip 2004 is removed from the molded substrate. A thinning operation can then be performed to thin the first encapsulation layer 2003A' to the desired thickness. Figure 23C In this process, semiconductor chip 2002 is a flip chip bonded to the front surface 2001F of core substrate 2001. Subsequently, a second encapsulation layer 2003B' is formed to encapsulate the front surface 2001F of core substrate 2001 and semiconductor chip 2002. Figure 23D In this structure, multiple openings are formed in the first encapsulation 2003A, aligned with conductive traces on the core substrate 2001. Figure 23E In this process, solder balls or solder paste are placed in the opening 2003C and a spherical grid array is formed on the rear surface 2001B of the core substrate 2001 through a proper reflow operation. A die-cutting operation is then performed to monolithize the semiconductor package into multiple core semiconductor packages 200B, such as... Figure 20B As shown in the image.

[0106] The embodiments of the present invention have been described in detail above. However, it should be understood that the present invention provides many applicable concepts that can be implemented in a wide variety of specific situations. The specific embodiments described are merely illustrative and do not limit the scope of the invention.

[0107] Additionally, spatially relative terms used herein, such as “below,” “below,” “lower,” “above,” “upper,” “lower,” “left,” “right,” and the like, are used to facilitate the description of the relationship between one element or feature and another element or feature as illustrated in the figures. Apart from the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to said other element, or there may be an intermediate element.

[0108] The numerical ranges and parameters that define the broad scope of the invention are approximate values ​​and are reported as precisely as possible for any particular instance. However, some values ​​may contain certain errors necessarily caused by the standard deviation found in their respective test measurements. And, as used herein, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of a given value or range. Alternatively, when considered by a person skilled in the art, the term “about” means within an acceptable standard error of the average. Except in operational / working instances, or unless otherwise expressly specified, all numerical ranges, quantities, values, and percentages (e.g., those used for quantities of material, durations, temperatures, operating conditions, ratios of quantities, and the like disclosed herein) should be understood to be modified by the term “about” in all cases. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the invention and the appended claims are variable approximations. Each numerical parameter should be interpreted at least according to the number of significant figures reported and by applying general rounding techniques. A range may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term “substantially coplanar” may refer to two surfaces located along the same plane within a few micrometers (μm), for example, within 10 μm, 5 μm, 1 μm, or 0.5 μm along the same plane. When referring to “substantially” identical numerical values ​​or characteristics, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0109] The foregoing outlines several embodiments and detailed features of the present invention. The embodiments described herein can readily serve as the basis for designing or modifying other processes and structures for performing the same or similar purposes and / or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the invention, and various changes, substitutions, and variations can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor package structure comprising: A patterned conductive layer has a front surface, a rear surface, and a side surface connecting the front surface and the rear surface, and the patterned conductive layer includes an organic dielectric layer and conductive traces embedded in the organic dielectric layer. A first semiconductor chip is located on the front surface and electrically connected to the patterned conductive layer; A first encapsulation material covers the rear surface and the side surface of the patterned conductive layer; as well as A second encapsulation covers the front surface of the patterned conductive layer, and the organic dielectric layer is covered by the first and second encapsulations. The organic dielectric layer has high hygroscopicity, and the first encapsulant has a water absorption rate of less than or equal to 0.5%.

2. The semiconductor packaging structure according to claim 1, wherein the conductive traces do not contact the first encapsulant.

3. The semiconductor package structure of claim 1, further comprising a conductive element on the rear surface of the patterned conductive layer and surrounded by the organic dielectric layer and the first encapsulant.

4. The semiconductor packaging structure according to claim 1, wherein the rear surface and the side surface of the patterned conductive layer are composed of the organic dielectric layer, and the first encapsulant covers the rear surface and the side surface of the patterned conductive layer.

5. The semiconductor packaging structure according to claim 4, wherein the Young's modulus of the first encapsulant is greater than or equal to 15 GPa.

6. The semiconductor packaging structure according to claim 1, wherein the first encapsulant, the conductive trace, and the organic dielectric layer form a coplanar surface.

7. The semiconductor packaging structure of claim 6, wherein the boundary intersects the coplanar surface and the second encapsulant.

8. A semiconductor substrate comprising: A patterned conductive layer has a front surface, a rear surface, and a side surface connecting the front surface and the rear surface. The patterned conductive layer includes an organic dielectric layer, a first conductive layer, a second conductive layer, and a conductive via electrically connecting the first conductive layer and the second conductive layer. The first conductive layer is embedded in the organic dielectric layer. An encapsulation covering the side surface of the patterned conductive layer, wherein the side surface is composed of the organic dielectric layer. The organic dielectric layer has high hygroscopicity, and the encapsulant has a water absorption rate of less than or equal to 0.5%.

9. The semiconductor substrate of claim 8, wherein the conductive via tapers from the rear surface toward the front surface.

10. The semiconductor substrate of claim 8, further comprising a solder resist layer above the rear surface of the patterned conductive layer, the side surfaces of the solder resist layer being covered by the encapsulant.

11. The semiconductor substrate of claim 8, wherein the encapsulant covers the back surface of the patterned conductive layer, and the back surface is composed of the organic dielectric layer.

12. A method for manufacturing a semiconductor package structure, comprising: Provide a carrier; An embedded trace structure is formed above the carrier; An organic dielectric layer with an embedded trace structure is patterned to expose a portion of the conductive trace to form a patterned conductive layer, the patterned conductive layer having a front surface and a rear surface that contact the carrier, and a side surface that connects the front surface and the rear surface; A first encapsulation is formed over the patterned conductive layer, covering the rear surface and the side surface of the organic dielectric layer; as well as Removing the carrier thereby exposes the front surface of the patterned conductive layer. The organic dielectric layer has high hygroscopicity, and the first encapsulant has a water absorption rate of less than or equal to 0.5%.

13. The method of claim 12, further comprising: After the carrier is removed, a semiconductor chip is placed on the front surface; as well as A second encapsulation is formed covering the semiconductor chip, the organic dielectric layer, and the first encapsulation.

14. The method of claim 12, further comprising forming a coplanar surface of the first encapsulation, the conductive trace, and the organic dielectric layer.

15. The method of claim 12, further comprising forming a conductive element extending from the rear surface of the organic dielectric layer prior to forming the first encapsulation.

16. The method of claim 15, further comprising removing a portion of the first encapsulation and a portion of the conductive element to form a coplanar surface comprising the first encapsulation and the conductive element.

17. The method of claim 15, further comprising forming a solder resist layer on the organic dielectric layer, wherein the sides of the solder resist layer are covered by the first encapsulant.

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