Semiconductor packaging and manufacturing methods

Abstract

This application provides a semiconductor package and a method for manufacturing the semiconductor package. The semiconductor package includes a semiconductor die, a capping layer, conductive terminals, and a dam structure. The semiconductor die has a first surface. The capping layer is located above the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminals penetrate the capping layer and are electrically connected to the semiconductor die. The dam structure is located between the semiconductor die and the capping layer and surrounds a portion of the conductive terminals between the first surface and the second surface, thereby forming a gap between the capping layer and the semiconductor die.

Description

Technical Field

[0001] This application relates to a semiconductor package and a method for manufacturing a semiconductor package, and more specifically, to wafer-level chip-scale packaging, chip-to-wafer packaging, or wafer-to-wafer packaging. Background Technology

[0002] There has been a persistent desire to reduce the size of semiconductor packages (e.g., planar grid array (LGA) packages). It has also been a persistent desire to prevent contaminants generated during the formation of conductive terminals from entering the active areas of the semiconductor die in flip-chip packages (e.g., bump packages). Therefore, there is a need to provide semiconductor packages that mitigate contamination issues while simultaneously meeting miniaturization requirements. Summary of the Invention

[0003] In one aspect, a semiconductor package includes a semiconductor die, a capping layer, conductive terminals, and a dam structure. The semiconductor die has a first surface. The capping layer is located above the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminals penetrate the capping layer and are electrically connected to the semiconductor die. The dam structure is located between the semiconductor die and the capping layer and surrounds a portion of the conductive terminals between the first and second surfaces, thereby forming a gap between the capping layer and the semiconductor die.

[0004] In one aspect, a method of manufacturing a semiconductor package includes: patterning a cover wafer to form a through opening connecting a first surface and a second surface of the cover wafer; patterning a bonding layer at the second surface of the cover wafer; bonding the cover wafer to a semiconductor wafer; and dicing the cover wafer and the semiconductor wafer. Attached Figure Description

[0005] Figure 1 A cross-sectional view illustrating a semiconductor package according to an embodiment of this application.

[0006] Figure 2A Explanation for example Figure 1 The diagram shows a quarter-perspective view of a complete semiconductor package.

[0007] Figure 2B Explanation for example Figure 1 The diagram shows a quarter-perspective view of a complete semiconductor package.

[0008] Figure 3 A cross-sectional view illustrating a semiconductor package according to an embodiment of this application.

[0009] Figure 4 A cross-sectional view illustrating a semiconductor package according to an embodiment of this application.

[0010] Figure 5A A cross-sectional view illustrating a semiconductor package according to an embodiment of this application.

[0011] Figure 5B Explanation for example Figure 5A The diagram shows a quarter-perspective view of a complete semiconductor package.

[0012] Figure 6 A cross-sectional view illustrating a semiconductor package according to an embodiment of this application.

[0013] Figure 7 A cross-sectional view illustrating a semiconductor package according to an embodiment of this application.

[0014] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 8F , Figure 8G , Figure 8H , Figure 8I , Figure 8J , Figure 8K , Figure 8L and Figure 8M Instructions for use in manufacturing, for example Figure 1 The semiconductor packaging method.

[0015] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 8F , Figure 8G , Figure 8H , Figure 8I , Figure 8J , Figure 8K , Figure 8N , Figure 8O , Figure 8P and Figure 8Q Instructions for use in manufacturing, for example Figure 3 The semiconductor packaging method.

[0016] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G , Figure 9H and Figure 9I This application describes a method for manufacturing a semiconductor package according to embodiments thereof.

[0017] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I , Figure 10J and Figure 10K This application describes a method for manufacturing a semiconductor package according to embodiments thereof.

[0018] Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A Instructions for use in manufacturing, for example Figure 5A The semiconductor packaging method.

[0019] Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A This application describes a method for manufacturing a semiconductor package according to embodiments thereof.

[0020] Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B Explain each Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A The corresponding perspective view.

[0021] Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 17G , Figure 17H and Figure 17I Instructions for use in manufacturing, for example Figure 6 The semiconductor packaging method. Detailed Implementation

[0022] Unless otherwise stated, spatial descriptions of orientation shown in the figures, such as "above," "top," and "bottom," are used. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in any orientation or manner, provided that such arrangement does not depart from the advantages of the embodiments of this application.

[0023] In some embodiments, this application provides a semiconductor package comprising a semiconductor die and a protective structure in the form of a capping layer protecting the active regions of the semiconductor die. The semiconductor package disclosed herein may be without wire bonding structures, capping structures, or die seals such as epoxy resin, thus offering advantages in reducing package size and preventing contamination. The semiconductor package disclosed herein can be fabricated using wafer-level chip-scale packaging, chip-to-wafer packaging, or wafer-to-wafer packaging.

[0024] Unlike wafer-level packaging, semiconductor packaging, such as planar grid array (LGA) packaging or flip-chip packaging (e.g., bump packaging), is performed in a one-to-one manner. Each semiconductor die is first individualized, picked up, and placed on substrate 110, followed by wire bonding or solder reflow operations. In some embodiments of this application, the semiconductor package is manufactured using wafer-level chip-scale packaging (WLCSP) technology, where processed wafers are bonded together before being diced into individual chips.

[0025] Figure 1 A cross-sectional view illustrating a semiconductor package 100 according to an embodiment of this application. Figure 1 The semiconductor package 100 includes: a semiconductor die 101, a capping layer 103, conductive terminals 105, and dam structures 107a and 107b.

[0026] Semiconductor die 101 may be a chip (e.g., a communication chip, a microprocessor chip, a graphics chip, or a microelectromechanical system (MEMS) chip diced from a wafer), a package, an insert, or a combination thereof. In some embodiments, the MEMS chip may include, for example, micro-sized electromechanical components (e.g., optical devices, switches, mirrors, filters, transducers, accelerometers, microphones, capacitive sensors, sensors, or actuators, etc.).

[0027] Semiconductor die 101 has a first die surface 101a and a second die surface 101b, the second die surface 101b being opposite to the first die surface 101a. Semiconductor die 101 may include an active region 109 disposed adjacent to the first die surface 101a. In some embodiments, the active region 109 is disposed near the center of semiconductor die 101. Semiconductor die 101 may include at least one bonding pad 111 disposed adjacent to the first die surface 101a. In some embodiments, the bonding pad 109 is disposed around the active region 109. In some embodiments, the bonding pad 109 is directly disposed (e.g., in physical contact) on the first die surface 101a of semiconductor die 101. The bonding pad 109 may include, for example, copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc, or one or a combination of other metals or metal alloys.

[0028] A capping layer 103 is disposed over the semiconductor die 101. The capping layer 103 has a first capping surface 103a and a second capping surface 103b opposite to the first capping surface 103a. The capping layer 103 may define at least one first through-hole 103c corresponding to a respective bonding pad 109. The capping layer 103 may comprise, for example, one or a combination of silicon, high-resistivity silicon, or glass. In some embodiments where the semiconductor die 101 is an optical device, the capping layer 103 comprises a glass material.

[0029] The conductive terminal 105 penetrates the capping layer 103. The conductive terminal 105 may be disposed in a first through-hole 103c of the capping layer 103. The conductive terminal 105 may be disposed on the bonding pad 111 and electrically connected to the semiconductor die 101. Alternatively, the conductive terminal 105 may be isolated from the semiconductor die 101. The conductive terminal 105 may be, for example, a solder ball.

[0030] In some embodiments, a bonding pad 111 is disposed on a first die surface 101a of the semiconductor die 101, and a conductive terminal 105 is disposed in a first through-hole 103c of the capping layer 103 and on the bonding pad 111, with the semiconductor die 101 electrically connected to the conductive terminal 105. By disposing of the conductive terminal 105 penetrating the capping layer 103, a shorter path for transmitting electrical signals to the semiconductor die 101 can be provided, which can increase signal transmission speed.

[0031] Dam structures 107a and 107b are disposed between semiconductor die 101 and capping layer 103. Dam structures 107a and 107b may be disposed adjacent to the first die surface 101a of semiconductor die 101. Dam structures 107a and 107b may be disposed adjacent to bonding pad 111. Dam structures 107a and 107b may be disposed around the first through opening 103c of capping layer 103. Dam structures 107a and 107b may surround bonding pad 111. Dam structures 107a and 107b may surround and be spaced apart from bonding pad 111. Dam structures 107a and 107b may surround a portion of the conductive terminal 105 between the first die surface 101a of semiconductor die 101 and the second capping surface 103b of capping layer 103. In some embodiments, dam structures 107a and 107b are disposed around the first through opening 103c of the capping layer 103. In some embodiments, dam structures 107a and 107b are located between the semiconductor die 101 and the capping layer 103 and surround the bonding pad 111, thereby forming a gap between the capping layer 103 and the semiconductor die 101. Therefore, when the conductive terminal 105 is disposed on the bonding pad 111, the space between the dam structures 107a and 107b, the capping layer 103 and the semiconductor die 101 can accommodate the conductive terminal 105 and prevent solder from overflowing to the vicinity and contaminating the active area 109.

[0032] In some embodiments, a conductive terminal 105 is disposed in a first through-hole 103c of the capping layer 103 and electrically connected to the semiconductor die 101, and dam structures 107a, 107b surround a portion of the conductive terminal 105. By placing the dam structures 107a, 107b around the location where the conductive terminal 105 is disposed, contamination that may result from the placement of the conductive terminal can be reduced by confining it to a limited space. The dam structures 107a, 107b may comprise, for example, a photoresist material (e.g., SU-8), a polymer material (e.g., benzocyclobutene (BCB)), an epoxy resin, or a metallic material (e.g., a eutectic alloy, including but not limited to Au-In, Cu-Sn, Au-Sn, Au-Ge, Au-Si, Al-Ge, Al-Si). Eutectic alloys have greater bonding strength than their polymer counterparts while occupying a smaller area between the capping layer 103 and the semiconductor die 101.

[0033] In some embodiments (e.g.) Figure 1In the embodiments described herein, the semiconductor package 100 may further include bonding structures 113a, 113b disposed between the semiconductor die 101 and the capping layer 103. The bonding structures 113a, 113b are disposed around the semiconductor die 101. In some embodiments, the bonding structures 113a, 113b are disposed at the periphery of the semiconductor die 101. In some embodiments, the bonding structures 113a, 113b are disposed adjacent to a dicing edge used to individualize the semiconductor die 101. The capping layer 103 can be bonded to the semiconductor die 101 via the bonding structures 113a, 113b.

[0034] In some embodiments where the bonding structures 113a and 113b are positioned adjacent to the dicing edge of the semiconductor die 101, the bonding structures 113a and 113b can prevent the semiconductor die 101 from being contaminated by debris generated during the dicing process (e.g., a singlet process). The bonding structures 113a and 113b may comprise, for example, photoresist materials, polymeric materials (e.g., benzocyclobutene (BCB)), epoxy resins, metals, or combinations thereof. The materials and dimensions (e.g., height and / or width) of the bonding structures 113a and 113b and the materials and dimensions (e.g., height and / or width) of the dam structures 107a and 107b may be the same or different.

[0035] In some embodiments (e.g.) Figure 1 In the embodiments described herein, the semiconductor package 100 may further include an isolation layer 115 disposed between the conductive terminal 105 and the capping layer 103. In some embodiments, the isolation layer 115 is aligned with the sidewall of the first through-opening 103c of the capping layer 103. In some embodiments, the isolation layer 115 is aligned with the sidewall of the first through-opening 103c of the capping layer 103 and defines an area for housing the conductive terminal 105 by covering a portion of the bonding pad 111. The isolation layer 115 may comprise, for example, a polymeric material (e.g., polybenzoxazole (PBO)). The isolation layer 115 can provide better wetting properties of the conductive terminal 105 and thus better adhesion properties between the conductive terminal 105 and the capping layer 103. Alternatively, when the capping layer 103 is made of high-resistivity silicon or glass, the isolation layer 115 may be omitted.

[0036] In some embodiments (e.g.) Figure 1 In the embodiments described herein, the semiconductor package 100 may further include a first passivation layer 117 disposed between the cap layer 103 and the dam structures 107a, 107b. In some embodiments, the first passivation layer 117 is disposed adjacent to a second cap surface 103b of the cap layer 103. In some embodiments, the first passivation layer 117 is disposed on the second cap surface 103b of the cap layer 103 and is in direct contact with the dam structures 107a, 107b.

[0037] For the purposes of description, Figure 2A Explain the partitioning along two axes of symmetry (e.g., X and Y). Figure 1 The image shows a quarter-perspective view of a complete semiconductor package. Figure 2A In this configuration, a capping layer 103 is stacked on a semiconductor die 101, with a bonding structure 113a between the capping layer and the semiconductor die. A conductive terminal 105 protrudes from a first capping surface 103a of the capping layer 103 and is electrically connected to a bonding pad 111 of the semiconductor die 101 through a first through-opening 103c penetrating the capping layer 103. An insulating layer 115 is lined throughout the first through-opening 103c of the capping layer 303 located between the conductive terminal 105 and the capping layer 103, and extends above the first capping surface 103a of the capping layer 103. The conductive terminal 105 is disposed on the insulating layer 115.

[0038] For the purposes of description, Figure 2B The cap layer, divided along two axes of symmetry (e.g., X and Y), is shown after removal, for example... Figure 1 The image shows a quarter-perspective view of a complete semiconductor package. Figure 2B In this package, the active region 109 of the semiconductor die 101 is positioned close to the center of the entire semiconductor package. A bonding pad 111, configured to receive conductive terminals 105 from the capping layer 103, is positioned close to a corner of the complete semiconductor package. Dam structures 107a and 107b surround the bonding pad 111 from all four sides. Bonding structures 113a and 113c are lining the sides of the complete semiconductor package. In some embodiments, similar to bonding structures 113a and 113c, the dam structures 107a and 107b are used to bond the semiconductor die 101 to the capping layer 103 and can be patterned over the semiconductor die 101 in the same manner as the patterned bonding structures 113a and 113b. Those skilled in the art will understand that the layout of the active area 109, the bonding structures 113a, 113c, the dam structures 107a, 107b, and the bonding pad 111 can be varied depending on the packaging layout, as can the conductive terminal 105 and the insulating layer 115.

[0039] Figure 3 A cross-sectional view illustrating a semiconductor package 300 according to an embodiment of this application is shown. The semiconductor package 300 is similar to... Figure 1The semiconductor package described herein differs in that a metal layer 319 is disposed between the conductive terminal 105 and the isolation layer 115. In some embodiments, the metal layer 319 is disposed on the isolation layer 115 and the bonding pad 111. In some embodiments, the metal layer 310 liners the isolation layer 115 and covers the surface of the bonding pad 111. By providing the metal layer 319 together with the isolation layer 115, better wetting properties of the conductive terminal 105 are provided, and therefore better adhesion between the conductive terminal 105 and the isolation layer 115.

[0040] Figure 4 A cross-sectional view of a semiconductor package 400 according to an embodiment of this application is shown. Figure 4 The semiconductor package 400 includes: a semiconductor die 401, a capping layer 403, a conductive terminal 405, and dam structures 407a and 407b.

[0041] Semiconductor die 401 may be a chip (e.g., a communication chip, a microprocessor chip, a graphics chip, or a microelectromechanical system (MEMS) chip diced from a wafer), a package, an insert, or a combination thereof. In some embodiments, the MEMS chip may include, for example, micro-sized electromechanical components (e.g., optical devices, switches, mirrors, filters, transducers, accelerometers, microphones, capacitive sensors, sensors, or actuators, etc.). Semiconductor die 401 has a first die surface 401a and a second die surface 401b, the second die surface being opposite to the first die surface 401a. Semiconductor die 401 may include at least one bonding pad 411 disposed adjacent to the first die surface 401a of semiconductor die 401. In some embodiments, the bonding pad 411 is directly disposed (e.g., in physical contact) on the first die surface 401a of semiconductor die 401. The bonding pad 411 may comprise, for example, one or a combination of copper, gold, indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, or zinc, or other metals or metal alloys. A second passivation layer 421 may be disposed adjacent to the first die surface 401a of the semiconductor die 401. The second passivation layer 421 is disposed to expose the bonding pad 411. In some embodiments, the passivation layer 421 is in direct contact with the first die contact surface 401a of the semiconductor die 401.

[0042] A capping layer 403 is disposed over the semiconductor die 401. The capping layer 403 has a first capping surface 403a and a second capping surface 403b opposite to the first capping surface 403a. The capping layer 403 may define at least one first through-hole 403c corresponding to a respective bonding pad 411. The capping layer 403 may comprise, for example, one or a combination of silicon, high-resistivity silicon, or glass. In some embodiments where the semiconductor die 401 is an optical device, the capping layer 403 comprises a glass material.

[0043] The conductive terminal 405 penetrates the capping layer 403. The conductive terminal 405 may be disposed in a first through-hole 403c of the capping layer 103. The conductive terminal 405 may be disposed on the bonding pad 411. The conductive terminal 405 may be, for example, a solder ball or a pillar structure, which may include an under-bump metallization (UBM) layer, a pillar, a barrier layer, a solder layer, or a combination of both or more thereof. The UBM layer may contain, for example, solder material. The pillar may contain, for example, copper. The barrier layer may contain, for example, nickel. In some embodiments, the conductive terminal 405 is a solder ball.

[0044] In some embodiments, a bonding pad 411 is disposed on a first die surface 401a of the semiconductor die 401 and surrounded by a second passivation layer 421, and a conductive terminal 405 is disposed in a first through-hole 403c of the capping layer 403 and on the bonding pad 411, and the semiconductor die 401 is electrically connected to the conductive terminal 405. By disposing of the conductive terminal 405 that penetrates the capping layer 403, a shorter path for transmitting electrical signals to the semiconductor die 401 can be provided, which can increase the signal transmission speed.

[0045] Dam structures 407a and 407b are disposed between semiconductor die 401 and capping layer 403. Dam structures 407a and 407b may be disposed adjacent to a first die surface 401a of semiconductor die 401. Dam structures 407a and 407b may be disposed adjacent to a second passivation layer 421. Dam structures 407a and 407b may be disposed adjacent to a bonding pad 411. Dam structures 407a and 407b may be disposed around a first through-hole 403c of capping layer 403. Dam structures 407a and 407b may surround the bonding pad 411. In some embodiments, dam structures 407a and 407b are disposed on the second passivation layer 421 and surround the bonding pad 411. The space between dam structures 407a and 407b and the bonding pad 411 can accommodate a conductive terminal 405 and prevent it from laterally extending into the vicinity and contaminating the active area. Dam structures 407a and 407b may surround a portion of the conductive terminal 405 between the first die surface 401a of the semiconductor die 401 and the second cover surface 403b of the cover layer 403. In some embodiments, dam structures 407a and 407b are disposed around the first through opening 403c of the cover layer 403.

[0046] In some embodiments, the conductive terminal 405 is disposed in a first through-hole 403c of the capping layer 403, and dam structures 407a, 407b surround a portion of the conductive terminal 405. By placing the dam structures 407a, 407b around the location where the conductive terminal 405 is disposed, contamination that may result from the placement of the conductive terminal can be reduced by confining it to a limited space. The dam structures 407a, 407b may comprise, for example, photoresist materials, polymeric materials (e.g., benzocyclobutene (BCB)), epoxy resins, or metallic materials (e.g., eutectic alloys, including but not limited to Au-In, Cu-Sn, Au-Sn, Au-Ge, Au-Si, Al-Ge, Al-Si). Eutectic alloys have greater bonding strength than their polymer counterparts while occupying a smaller area between the capping layer 403 and the semiconductor die 401.

[0047] Figure 5A A cross-sectional view illustrating a semiconductor package 500 according to an embodiment of this application is shown. The semiconductor package 500 is similar to... Figure 4 The semiconductor package described herein differs in that a bonding structure 513 is disposed between the semiconductor die 401 and the capping layer 503, and the dam structure around the conductive terminals 405 may be omitted. The bonding structure 513 is disposed around the semiconductor die 401. In some embodiments, the bonding structure 513 is disposed at the periphery of the semiconductor die 401. In some embodiments, the bonding structure 513 is disposed adjacent to a dicing edge used to individualize the semiconductor die 401. In some embodiments, the capping layer 503 defines a second via 503d, and the bonding structure 513 is disposed in the second via 503d of the capping layer 503. The capping layer 503 can be bonded to the semiconductor die 401 via the bonding structure 513. In some embodiments where the bonding structure 513 is disposed adjacent to the dicing edge of the semiconductor die 401, the bonding structure 513 can prevent the semiconductor die 401 from contamination by debris generated during the dicing process (e.g., a dicing process). The bonding structure 513 may include, for example, a photoresist material, a polymer material (e.g., benzocyclobutene (BCB)), an epoxy resin, a metal, or a combination thereof.

[0048] For the purposes of description, Figure 5B Explain the partitioning along two axes of symmetry (e.g., X and Y). Figure 5A The image shows a quarter-perspective view of a complete semiconductor package. Figure 5B In this configuration, a capping layer 503 is stacked on a semiconductor die 401, and a bonding structure 513 is provided between the capping layer and the semiconductor die. Conductive terminals 405 protrude from a first capping surface 503a of the capping layer 503 and pass through a first through-hole 403c penetrating the capping layer 503. Figure 5A(As shown in the image) The bonding pad 411 is electrically connected to the semiconductor die 401. Figure 5A (As shown in the image). The bonding structure 513 is positioned adjacent to the dicing edge of the semiconductor die 401 and separates the different semiconductor dies.

[0049] Figure 6 A cross-sectional view illustrating a semiconductor package 600 according to an embodiment of this application is shown. The semiconductor package 600 is similar to... Figure 1 The semiconductor package described herein differs in that the conductive terminal 605 is a pillar structure, which may include an under bump metal (UBM) layer 605a, a pillar 605b, a barrier layer 605c and a solder layer 605d, and at least one cavity 623a, 623b disposed at the second cover surface 603b of the cover layer 603.

[0050] UBM layer 605a may contain, for example, solder material. Pillar 605b may contain, for example, copper. Barrier layer 605c may contain, for example, nickel. Solder layer 605d may contain, for example, solder balls.

[0051] Cavities 623a and 623b are formed at the second cover surface 603b of the capping layer 603 and correspond to the respective active regions 609a and 609b of the semiconductor die 601, for accommodating the active regions 609a and 609b, respectively. Cavities 623a and 623b are formed to compensate for the height loss between the capping layer 603 and the semiconductor die 601 due to the conductive terminal 605 being arranged as a pillar structure. In other words, in some embodiments where the conductive terminal 605 is arranged as a pillar structure, cavities 623a and 623b may be necessary to provide sufficient space to accommodate the active regions 609a and 609b of the semiconductor die 601.

[0052] Figure 7 A cross-sectional view illustrating a semiconductor package 700 according to an embodiment of this application is shown. The semiconductor package 700 is similar to... Figure 6 The semiconductor package described herein differs in that an isolation layer 715 is disposed between the conductive terminal 605 and the cap layer 603. In some embodiments, the isolation layer 715 is aligned with the sidewall of the first through-hole opening 603c of the cap layer 603. In some embodiments, the isolation layer 715 is aligned with the sidewall of the first through-hole opening 603c and extends over the first cap surface 603a of the cap layer 603. The isolation layer 715 may comprise, for example, a polymeric material (e.g., polybenzoxazole (PBO)). The isolation layer 715 can provide better wetting properties for the conductive terminal 605 and thus better adhesion properties between the conductive terminal 605 and the cap layer 603. Alternatively, when the cap layer 603 is made of high-resistivity silicon or glass, the isolation layer 715 may be omitted.

[0053] Figures 8A to 8M Instructions for use in manufacturing, for example Figure 1 A method for semiconductor packaging 100.

[0054] refer to Figure 8A A capping layer 800 is provided. The capping layer 800 has a first capping surface 800a and a second capping surface 800b, the second capping surface being opposite to the first capping surface 800a. The capping layer 800 can be a semiconductor wafer. The semiconductor wafer 800 can be made of silicon, high-resistivity silicon (undoped silicon), or other III-V compound materials.

[0055] refer to Figure 8B Passivation layers 801a and 801b are formed above the first cover surface 800a and the second cover surface 800b of the capping layer 800, respectively. In some embodiments, the passivation layers 801a and 801b are formed by thermal oxidation, low-pressure chemical vapor deposition of nitrides, or a combination thereof.

[0056] refer to Figure 8C An opening 801' is formed at a passivation layer 801a on a first cover surface 800a of the cover layer 800, which exposes the underlying cover layer 800. In some embodiments, a photolithography process and an etching process are performed to remove a predetermined portion of the passivation layer 801a to form the opening 801'.

[0057] refer to Figure 8D Cavity 800' is formed by opening 801' of capping layer 800. In some embodiments, a wet etching process is performed to form cavity 800'. Due to the type of etching process selected, a portion of passivation layer 801a may be retained and protrude over cavity 800'.

[0058] refer to Figure 8E The bonding layer 807 is formed adjacent to the second cover surface 800b of the cover layer 800, for example, on the passivation layer 801b. In some embodiments, the bonding layer 807 includes bonding structures 807a, 807b and dam structures 807c, 807d. The dam structures 807c, 807d are closer to the cavity 800' than the bonding structures 807a, 807b. In some embodiments, the bonding layer 807 may be made of a photoresist material (e.g., SU-8), a polymer material (e.g., benzocyclobutene (BCB)), epoxy resin, etc., and the bonding layer 807 may be directly patterned on the passivation layer 801b on the second cover surface 800b of the cover layer 800. In some embodiments, the bonding layer 807 may be made of a metallic material such as a eutectic alloy (including but not limited to Au-In, Cu-Sn, Au-Ge, Au-Si, Al-Ge, Al-Si) and deposited, sputtered or electroplated on the second cover surface 800b of the cover layer 800.

[0059] refer to Figure 8FThe capping layer 800 is bonded to the semiconductor wafer 900 via a bonding layer 807. The semiconductor wafer 900 has a first wafer surface 900a and a second wafer surface 900b, the second wafer surface being opposite to the first wafer surface 900a. The semiconductor wafer 900 may include at least one semiconductor die, such as a communication chip, a microprocessor chip, a graphics chip, or a MEMS chip. A bonding pad 111 is provided on the first wafer surface 900a of the semiconductor wafer 900, aligned with the cavity 800', and configured to receive conductive terminals passing through the capping layer 800. Dam structures 807c and 807d are closer to the bonding pad 111 than bonding structures 807a and 807b.

[0060] refer to Figure 8G ,Will Figure 8F The passivation layer 801a shown is removed, and the total thickness of the capping layer 800 is reduced to, for example, 20 μm. In some embodiments, the thickness of the passivation layer 801a and the capping layer 800 can be removed by grinding.

[0061] refer to Figure 8H The portion of the capping layer 800 below the cavity 800' is removed until the passivation layer 801b is exposed. In some embodiments, the removal of the portion of the capping layer 800 can be performed using a dry etching process.

[0062] refer to Figure 8I A portion of the passivation layer 801b exposed by the cavity 800' is removed. In some embodiments, the removal of the portion of the passivation layer 801b is performed by a self-aligned etching process, such as reactive ion etching (RIE). Subsequently, a first through-hole 800" may be formed in the capping layer 800.

[0063] refer to Figure 8J The isolation material 815' is placed in the first through opening 800" and above the first cover surface 800a of the cover layer 800. The isolation material 815' can fill the space between the dam structures 807c and 807d and cover the joint liner 111. The isolation material 815' can be placed by spin coating or spraying.

[0064] refer to Figure 8K A portion of the insulating material 815' is removed, thereby exposing a portion of the surface of the bonding pad 111 and forming the insulating layer 115 and the second through opening 803". In some embodiments, the horizontal portion of the insulating material 815' is removed. In some embodiments, the removal of a portion of the insulating material 815' is performed by a combination of photolithography and etching techniques.

[0065] refer to Figure 8LThe conductive terminal 805 is formed in the second through-hole 803" of the semiconductor wafer 900. In some embodiments, the conductive terminal 805 is a solder layer, which can be formed by solder ball placement technology or solder paste printing technology.

[0066] refer to Figure 8M In some embodiments where the conductive terminal 805 is a solder layer, solder balls can be formed by a reflow process, which are electrically connected to the bonding pad 111. Subsequently, it is possible to obtain, for example... Figure 1 The semiconductor package described herein.

[0067] Figure 8A to 8K and Figure 8N to 8Q Instructions for use in manufacturing, for example Figure 3 The semiconductor packaging method of semiconductor package 300.

[0068] Figure 8A to 8K The explanation is consistent with the above text. Figure 8A to 8K The process described herein is the same as that described elsewhere, and therefore will not be repeated here for the sake of brevity.

[0069] refer to Figure 8N A metal layer 819' is disposed in the second through opening 803" of the capping layer 800. In some embodiments, the metal layer 819' is disposed in accordance with the insulating layer 115, covering a portion of the surface of the bonding pad 111, and at least a portion of the first cover surface 800a of the capping layer 800. The metal layer 819' can be disposed using a physical vapor deposition (PVD) technique. The metal layer 819' provides better wetting properties for the subsequently formed conductive terminal 805.

[0070] refer to Figure 8O The conductive terminal 805 is formed in the second through opening 803". In some embodiments, the conductive terminal 805 is a solder layer, which can be formed by solder ball placement technology or solder paste printing technology.

[0071] refer to Figure 8P In some embodiments where the conductive terminal 805 is a solder layer, solder balls can be formed by a reflow process.

[0072] refer to Figure 8Q The portion of the metal layer 819' not covered by the solder ball 805 is removed. In some embodiments, the portion of the metal layer 819' can be removed using a wet etching technique. In some embodiments, the removal range of the conductive terminal 805 by the wet etching technique is negligible compared to the metal layer 819'. Subsequently, for example, a [structure / object] can be obtained. Figure 3 The semiconductor package described herein.

[0073] Figures 9A to 9IThis application describes a method for manufacturing a semiconductor package according to embodiments thereof.

[0074] Referring to 9A, a capping layer 900 and a semiconductor wafer 902 are provided. The capping layer 900 has a first capping surface 900a and a second capping surface 900b, the second capping surface being opposite to the first capping surface 900a. In some embodiments, the capping layer 900 is a semiconductor wafer. The semiconductor wafer 900 may be made of silicon, high-resistivity silicon (undoped silicon), or other III-V compound materials. The capping layer 900 is provided with a passivation layer 901 disposed adjacent to the second capping surface 900b of the capping layer 900, and a bonding layer 907 disposed adjacent to the surface of the passivation layer 901. In some embodiments, the bonding layer 907 includes dam structures 907a, 907b and bonding structures 907c, 907d. The capping layer 900 also has a first alignment mark 922a disposed at the first capping surface 900a of the capping layer 900, the first alignment mark 922a corresponding to an alignment bond 924 on the semiconductor wafer 902 to be bonded.

[0075] Semiconductor wafer 902 has a first wafer surface 902a and a second wafer surface 902b, the second wafer surface being opposite to the first wafer surface 902a. Semiconductor wafer 900 may include at least one semiconductor die, such as a communication chip, microprocessor chip, graphics chip, or MEMS chip. A bonding pad 911 is disposed on the first wafer surface 902a of semiconductor wafer 902 and configured to receive conductive terminals passing through capping layer 900. Alignment keys 924 are disposed adjacent to the first wafer surface 902a of semiconductor wafer 902 for alignment with a first alignment mark 922a.

[0076] refer to Figure 9B The capping layer 900 is bonded to the semiconductor wafer 902 via bonding structures 907c and 907d. In some embodiments, the dam structures 907a and 907b are partially deformed by bonding pads 911. In other words, the dam structures 907a and 907b may cover a portion of the bonding pads 911.

[0077] refer to Figure 9C A second alignment mark 922b is placed on the second wafer surface 902b of the semiconductor wafer 902 to assist in alignment.

[0078] refer to Figure 9D A thinning process is performed from the first cover surface 900a of the cover layer 900 to reduce the thickness of the cover layer 900 to, for example, 20 μm. In some embodiments, the thinning process is performed by, for example, a polishing technique. Since the first alignment mark 922a is removed when the cover layer 900 is thinned, the second alignment mark 922b formed on the second wafer surface 902b of the semiconductor wafer 902 can facilitate wafer identification in subsequent processes.

[0079] refer to Figure 9E An opening 900' is formed in the capping layer 900 by, for example, a dry etching technique.

[0080] refer to Figure 9F Then, a portion of the passivation layer 901 is removed by, for example, a self-aligned dry etching operation.

[0081] Figure 9G to 9I The explanation is consistent with the above text. Figure 8K , Figure 8L and Figure 8M The processes described herein are the same as those described elsewhere, and therefore will not be repeated here for the sake of brevity.

[0082] Figures 10A to 10K This application describes a method for manufacturing a semiconductor package according to embodiments thereof.

[0083] refer to Figure 10A A capping layer 1000 is provided. The capping layer 1000 has a first capping surface 1000a and a second capping surface 1000b, the second capping surface 1000b being opposite to the first capping surface 1000a. The capping layer 1000 can be a semiconductor wafer. The semiconductor wafer 1000 can be made of silicon, high-resistivity silicon (undoped silicon), or other III-V compound materials.

[0084] refer to Figure 10B Passivation layers 1001a and 1001b are formed above the first cover surface 1000a and the second cover surface 1000 of the capping layer 1000, respectively. In some embodiments, the passivation layers 1001a and 1001b are formed by thermal oxidation, low-pressure chemical vapor deposition of nitrides, or a combination thereof.

[0085] refer to Figure 10C An opening 1001a' is formed at the passivation layer 1001a on the first cover surface 1000a of the cover layer 1000, which exposes the underlying cover layer 1000. In some embodiments, a photolithography process and an etching process are performed to remove a predetermined portion of the passivation layer 1001a to form the opening 1001a'.

[0086] refer to Figure 10D An opening 1001b' is formed at the passivation layer 1001b on the second cover surface 1000b of the cover layer 1000, which exposes the underlying cover layer 1000. In some embodiments, a photolithography process and an etching process are performed to remove a predetermined portion of the passivation layer 1001b to form the opening 1001b'.

[0087] refer to Figure 10EThrough-holes 1000 are formed in capping layer 1000 by, for example, wet etching techniques. In some embodiments where capping layer 1000 is made of silicon, KOH wet etching or tetramethylammonium hydroxide (TMAH) wet etching techniques may be used.

[0088] refer to Figure 10F The bonding layer 1007 is formed with a second cover surface 1000b adjacent to the cover layer 1000 and is patterned such that it may include dam structures 1007a, 1007b and bonding structures 1007c, 1007d. In some embodiments, the bonding layer 1007 is disposed on the passivation layer 1001b.

[0089] Referring to 10G, the capping layer 1000 is bonded to the semiconductor wafer 1002 via a bonding layer 1007. The semiconductor substrate 1002 includes bonding pads 1011 disposed adjacent to a first wafer surface 1002a of the semiconductor wafer 1002. Through-holes 1000 in the semiconductor wafer 1000 expose the bonding pads 1011 on the semiconductor wafer 1002.

[0090] refer to Figure 10H The capping layer 1000 is thinned to a predetermined thickness by, for example, a grinding process, and the passivation layer 1001a is removed.

[0091] refer to Figure 10I The isolation material 1015' is placed in the through hole 1000" and is located above the first cover surface 1000a of the cover layer 1000. The isolation material 1015' can fill the space between the dam structures 1007a and 1007b and cover the joint liner 1011. The isolation material 1015' can be placed by spin coating or spraying.

[0092] refer to Figure 10J A portion of the insulating material 1015' is removed, thereby exposing a portion of the surface of the bonding pad 1011 and forming the insulating layer 1015 and the second through opening 1003". In some embodiments, the horizontal portion of the insulating material 1015' is removed. In some embodiments, the removal of a portion of the insulating material 1015' is performed by a combination of photolithography and etching techniques.

[0093] refer to Figure 10K Conductive terminals 1005 are formed in the second through opening 1003" of the capping layer 900. In some embodiments, the conductive terminals 1005 are solder balls or solder layers, which can be formed by solder ball placement technology or solder paste printing technology. Subsequently, solder balls electrically connected to the bonding pads 1011 can be formed by a reflow process.

[0094] Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A Instructions for use in manufacturing, for example Figure 5A The semiconductor packaging method of 500 semiconductor packaging. Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A This application describes a method for manufacturing a semiconductor package according to embodiments thereof. Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B Explain each Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A The corresponding perspective view.

[0095] refer to Figure 11A and Figure 11B The capping layer 1100 has a plurality of through openings 1100". The capping layer 1100 can be a semiconductor wafer. Compared with chip-to-wafer embodiments, a wafer-to-wafer method can be used when the rigidity of the capping wafer is deemed unsuitable for performing on-band dicing operations. In other words, if the rigidity of the capping wafer is sufficient to perform on-band dicing operations, a chip-to-wafer method can be used. The semiconductor wafer 1100 can be made of silicon, high-resistivity silicon (undoped silicon), or other III-V compound materials. The through openings 1100" can be formed by, for example, laser drilling technology. Note that laser drilling processes can be performed on silicon wafers and glass wafers without additional wet or dry etching. In some embodiments, the width of the through openings 1100" is in the range of about 100 μm to about 200 μm.

[0096] refer to Figure 12A and Figure 12B Conductive terminals 1205 are formed in the through opening 1100" of the capping layer 1100. In some embodiments, the conductive terminals 1205 are solder vias, which can be formed, for example, by printing solder paste followed by a reflow process. The solder vias are configured to bond the capping layer 1100 or subsequently individualized capping layers to another wafer.

[0097] refer to Figure 13A and Figure 13B A cap layer 1100 with solder through-holes 1205 is mounted to a strip 1300, which is configured to support the cap layer 1100 during cutting operations. (As in...) Figure 13A and Figure 13BAs shown, a cutting operation is performed to separate cap 1100 into at least two separate caps 1100a and 1100b. A saw groove 1308 is located between the adjacent separate caps 1100a and 1100b held by the belt 1300.

[0098] refer to Figure 14A and Figure 14B Each of the individual cap layers 1100a and 1100b is picked up via a chip-to-wafer bonding operation and placed on the semiconductor wafer 1400. The conductive terminals 1205a and 1205b on the cap layers 1100a and 1100b are aligned with corresponding bonding pads 1411a and 1411b on the semiconductor wafer 1400 and bonded via a reflow operation. A protective layer 1402 may be disposed around the conductive pads 1411a and 1411b.

[0099] refer to Figure 15A and Figure 15B The joining structure 1500 is disposed in the saw groove 1308 between adjacent cap layers 1100a and 1100b. Subsequently, for example, [the following can be obtained]. Figure 5A The semiconductor package described herein is a semiconductor package. In some embodiments, a bonding structure 1500 is disposed by distributing a sealing gel over a saw groove 1308 adjacent to the cap layers 1100a, 1100b, filling the saw groove 1308, and overfilling the surfaces of the cap layers 1100a, 1100b. In some embodiments, the bonding structure 1500 bonds the individual cap layers 1100a, 1100b and the semiconductor wafer 1400 together. The bonding structure 1500 may protrude from the top of the sawn cap layers 1100a, 1100b. The bonding structure 1500 is applied to prevent contaminants from entering the space between the sawn cap layer 1100 and the sawn semiconductor wafer 1400 during subsequent individualization operations.

[0100] refer to Figure 16A and Figure 16B A unitization or dicing process is performed on the bonding structure 1500 of the semiconductor package to separate the semiconductor package into individual semiconductor packages 1600a, 1600b. In some embodiments, the unitization or dicing process is performed, for example, by a sawing process. Each of the semiconductor packages 1600a, 1600b includes sawn semiconductor wafers 1400a, 1400b and individual capping layers 1100a, 1100b. The bonding structure 1500 may optionally be removed after the dicing or unitization process.

[0101] Figures 17A to 17I Instructions for use in manufacturing, for example Figure 6 The semiconductor packaging method of 600 semiconductor packaging.

[0102] refer to Figure 17AA capping layer 1700 is provided. The capping layer 1700 has a first capping surface 1700a and a second capping surface 1700b, the second capping surface 1700b being opposite to the first capping surface 1700a. The capping layer 1700 can be a semiconductor wafer. The semiconductor wafer 1700 can be made of silicon, high-resistivity silicon (undoped silicon), or other III-V compound materials. Passivation layers 1701a and 1701b are formed over the first capping surface 1700a and the second capping surface 1700, respectively. In some embodiments, the passivation layers 1701a and 1701b are formed by thermal oxidation, low-pressure chemical vapor deposition of nitrides, or a combination thereof.

[0103] refer to Figure 17B Cavities 1723a and 1723b are formed at the second cover surface 1700b of the capping layer 1700 for active regions of the respective semiconductor dies. Cavities 1723a and 1723b can be formed, for example, by laser drilling technology.

[0104] refer to Figure 17C Perform a single-layer or cutting process to separate cap 1700 into individual caps 1708a and 1708b.

[0105] refer to Figure 17D Each of the individual cap layers 1708a and 1708b is picked up via a chip-to-wafer bonding operation and placed on a carrier 1704. The carrier 1704 includes a metal seed layer 1706 disposed adjacent to a surface 1704a of the carrier 1704. The metal seed layer 1706 is exposed through cavities 1723a and 1723b of the respective cap layers 1708a and 1708b and openings 1700c defined by the adjacent cap layers 1708a and 1708b.

[0106] refer to Figure 17E The conductive terminal 1705 may be formed from an exposed portion of a metal seed layer 1706, the exposed portion being defined by an opening 1700c defined by adjacent capping layers 1708a, 1708b. In some embodiments, the conductive terminal 1705 is a pillar structure, which may include an under-bump metal (UBM) layer 1705a, a pillar 1705b, a barrier layer 1705c, and a solder layer 1705d. In some embodiments, the conductive terminal 1705 is formed by a combination of processes such as physical vapor deposition, electroplating, photolithography, etching, solder reflow, or other suitable processes.

[0107] refer to Figure 17F ,Will Figure 17EThe carrier 1704, passivation layer 1701b, and metal seed layer 1706 shown are removed. In some embodiments, the top surface 1710 of the conductive terminal 1705 protrudes from the first cover surface 1700a of the cover layer 1700, and the bottom surface 1706 of the conductive terminal 1705 protrudes from the second cover surface 1700b of the cover layer 1700.

[0108] refer to Figure 17G The bonding layer 1707 is formed adjacent to a second cover surface 1700b of the capping layer 1700. In some embodiments, the bonding layer 1707 includes dam structures 1707c and 1707d. The dam structures 1707c and 1707d are closer to the cavity 1723b. In some embodiments, the bonding layer 1707 may be composed of a photoresist material (e.g., SU-8), a polymer material (e.g., benzocyclobutene (BCB)), epoxy resin, etc. In some embodiments, the bonding layer 1707 may be composed of a metallic material such as a eutectic alloy (including but not limited to Au-In, Cu-Sn, Au-Sn, Au-Ge, Au-Si, Al-Ge, Al-Si) and deposited, sputtered, or electroplated on the second cover surface 1700b of the capping layer 1700.

[0109] refer to Figure 17H The capping layer 1700 is bonded to the semiconductor wafer 1702 via a bonding layer 1707, wherein cavities 1723a and 1723b correspond to corresponding active regions of the corresponding semiconductor dies of the semiconductor wafer 1702, and conductive terminals 1705 are electrically connected to corresponding bonding pads 1711 of the semiconductor wafer 1702. The semiconductor wafer 1702 may include at least one active region 1709a and 1709b corresponding to the corresponding semiconductor die, including, for example, a communication chip, a microprocessor chip, a graphics chip, or a MEMS chip.

[0110] refer to Figure 17I In some embodiments where the conductive terminal 1705 is a cylindrical structure including a solder layer 1705d, solder balls can be formed by a reflow process. Subsequently, for example, [the desired result can be obtained]. Figure 6 The semiconductor package described herein.

[0111] As used herein and unless otherwise defined, the terms "substantially" and "approximately" are used to describe and account for small variations. When used in conjunction with events or situations, the terms may encompass examples of events or situations that exactly occur as well as examples of events or situations that approximately occur. For example, when used in conjunction with numerical values, the terms may encompass a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a line or plane may be substantially flat if its peak or trough values ​​are no greater than 5 μm, no greater than 1 μm, or no greater than 0.5 μm.

[0112] As used herein, unless the context clearly indicates otherwise, the singular terms “a”, “an”, and “the” may include plural objects. In the description of some embodiments, providing a component “on” or “above” another component may encompass situations where the latter component is directly on (e.g., in physical contact with) the former component, and situations where one or more intervening components may be located between the former and the latter component.

[0113] While the invention has been described and illustrated with reference to specific examples, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and equivalents can be made without departing from the true spirit and scope of the invention as defined in the appended claims. Illustrations need not be drawn to scale. Due to manufacturing processes and limitations, there may be differences between the intricate representations of the invention and actual devices. Other embodiments of the invention not specifically described may exist. The description and drawings should be considered illustrative rather than limiting. Modifications can be made to adapt particular situations, materials, compositions of substances, methods, or processes to the purpose, spirit, and scope of the invention. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limiting.

Claims

1. A semiconductor package comprising: A semiconductor die having a first surface, the semiconductor die having a bonding pad and an active region formed on the first surface; A capping layer, which is above the semiconductor die, has a second surface facing the first surface and a third surface relative to the second surface; A conductive terminal that penetrates the capping layer and is electrically connected to the semiconductor die; A dam structure located between the semiconductor die and the capping layer, surrounding a portion of the conductive terminal between the first surface of the semiconductor die and the second surface of the capping layer, thereby forming a gap between the capping layer and the semiconductor die; and An isolation layer, which lined the sidewalls of the through-opening of the capping layer and was surrounded by the dam structure, completely covered the side surface of the bonding pad on the first surface of the semiconductor die and partially covered the upper surface of the bonding pad. The dam structure is positioned between the bonding pad and the active region of the semiconductor die. The insulating layer comprises a polymer material to ensure wetting properties of the conductive terminals and adhesive properties between the conductive terminals and the capping layer.

2. The semiconductor package of claim 1, further comprising a bonding structure between the semiconductor die and the capping layer, wherein the capping layer comprises a glass material and the semiconductor die is an optical chip.

3. The semiconductor package of claim 2, wherein the bonding structure is spaced apart from the dam structure, wherein the dam structure comprises a photoresist material, a polymer material, an epoxy resin, or a eutectic alloy material.

4. The semiconductor package of claim 1, wherein the conductive terminal contacts the bonding pad of the semiconductor die, and the dam structure surrounds a plurality of sides of the bonding pad.

5. The semiconductor package of claim 1, wherein the extension portion of the isolation layer extends on the third surface of the capping layer, wherein the extension portion of the isolation layer overlaps with the projection area of ​​the dam structure on the semiconductor die, and the extension portion of the isolation layer does not overlap with the projection area of ​​the active region on the semiconductor die.

6. The semiconductor package of claim 5, further comprising a conductive layer lining the isolation layer, wherein the capping layer further has a side surface between the second surface and the third surface, wherein the side surface of the capping layer has a first portion and a second portion, the first portion being inclined relative to the third surface and the second portion being substantially perpendicular to the second surface.

7. The semiconductor package of claim 5, further comprising a passivation layer between the cap layer and the dam structure, wherein the passivation layer directly contacts the isolation layer, the dam structure, and the second surface of the cap layer.

8. The semiconductor package of claim 1, wherein the dam structure is spaced apart from the conductive terminal.

9. The semiconductor package of claim 2, wherein the capping layer, the bonding structure, and the semiconductor die form a cavity for receiving the active region of the semiconductor die, the active region being spaced apart from the bonding pad by the dam structure.

10. The semiconductor package of claim 9, wherein the conductive terminal comprises an under-bump metal (UBM) layer, a pillar, a barrier layer, and a solder layer, wherein the UBM layer comprises solder material and the pillar comprises copper, and wherein the active region and the dam structure are laterally spaced apart by a distance on the same plane of the semiconductor die.

11. A method for manufacturing a semiconductor package, comprising: Patterning the cover wafer to form a through opening connecting the first surface and the second surface of the cover wafer; An isolation layer is formed to line the sidewalls of the through-opening of the cover wafer; Conductive terminals are formed in the through opening; A bonding layer is patterned on the second surface of the cover wafer; The cover wafer is bonded to a semiconductor wafer, the semiconductor wafer having an upper surface and bonding pads and active regions formed on the upper surface; and Cut the cap wafer and the semiconductor wafer. The patterning of the bonding layer includes: A dam structure is formed around the through opening from the second surface; and A bonding structure is formed at the second surface. The dam structure is positioned between the bonding pad and the active region of the semiconductor wafer. The isolation layer is surrounded by the dam structure, and the isolation layer completely covers the side surface of the bonding pad on the upper surface of the semiconductor wafer and partially covers the upper surface of the bonding pad. The isolation layer comprises a polymer material to ensure wetting properties of the conductive terminals and adhesion properties between the conductive terminals and the cover wafer.

12. The method of claim 11, wherein the cover wafer comprises a glass material and the semiconductor wafer comprises an optical chip, wherein an extension of the isolation layer extends on the first surface of the cover wafer, wherein the extension of the isolation layer overlaps with the projection area of ​​the dam structure on the semiconductor wafer, and the extension of the isolation layer does not overlap with the projection area of ​​the active region on the semiconductor wafer.

13. The method of claim 11, further comprising placing solder material in the through-opening of the cover wafer after bonding the cover wafer to the semiconductor wafer, wherein the dam structure surrounds a plurality of sides of the bonding pad.

14. The method of claim 11, wherein patterning the cap wafer to form a through-hole comprises: Before bonding the cover wafer to the semiconductor wafer, a first etching is performed on the first surface; and A second etching is performed after the cover wafer is bonded to the semiconductor wafer to form the through opening.

15. The method of claim 12, wherein patterning the cap wafer to form a through-hole comprises: After the cap wafer is bonded to the semiconductor wafer, etching is performed from the first surface. The dam structure comprises photoresist materials, polymer materials, epoxy resins, or eutectic alloy materials.

16. The method of claim 11, wherein patterning the cap wafer to form a through-hole comprises: Before bonding the cover wafer to the semiconductor wafer, etching is performed from the first surface and the second surface.

17. The method of claim 12, wherein patterning the cap wafer to form a through opening includes forming a passivation layer on the first surface and the second surface, wherein the passivation layer directly contacts the isolation layer, the dam structure, and the cap wafer.

18. The method of claim 12, further comprising forming a conductive layer lining the insulating layer.

19. The method of claim 11, wherein forming the conductive terminal in the through opening is performed before patterning the bonding layer on the second surface, wherein the active region and the dam structure are laterally spaced apart by a distance on the same plane of the semiconductor wafer.

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