Semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate of a first conductivity type and a vertical Hall element disposed on the semiconductor substrate. The vertical Hall element comprises: a semiconductor layer of a second conductivity type disposed on the semiconductor substrate; an impurity diffusion layer of the second conductivity type disposed on the upper part of the semiconductor layer and having a higher concentration compared to the semiconductor layer; a plurality of electrodes composed of impurity regions of the second conductivity type disposed on the surface of the impurity diffusion layer and arranged in a straight line, wherein the impurity regions of the second conductivity type have a higher concentration compared to the impurity diffusion layer; a plurality of electrode separation diffusion layers of the first conductivity type disposed between each of the plurality of electrodes, thereby separating the plurality of electrodes; and a buried layer composed of impurity regions of the second conductivity type disposed between the semiconductor substrate and the semiconductor layer, wherein the impurity regions of the second conductivity type have a higher concentration compared to the semiconductor layer and a lower concentration compared to the impurity diffusion layer.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor devices having a vertical Hall element for detecting a magnetic field in the horizontal direction. Background Technology

[0002] Generally, it is more difficult to improve the sensitivity of vertical Hall elements compared to horizontal Hall elements.

[0003] Therefore, Patent Document 1 (with particular reference) Figure 3 In this paper, a structure is proposed in which an electrode composed of an N-type diffusion layer and an electrode separation diffusion layer (P-well) separating adjacent electrodes are provided in a magnetic sensing part (N-well) formed on a P-type substrate. The magnetic sensing part has a concentration distribution that is highest at the substrate surface and gradually decreases in concentration as it goes deeper from the surface. According to this structure, the width of the depletion layer formed around the electrode separation diffusion layer and the width of the electrode separation diffusion layer that narrows as it goes deeper from the substrate surface are complementary, which can suppress the current expansion in the magnetic sensing part and relatively increase the current component flowing in the direction perpendicular to the substrate, thereby improving the sensitivity.

[0004] However, in the structure of Patent Document 1, when current is supplied between the two electrodes of the clamping electrode separation diffusion layer, the current flows from one electrode on the substrate surface toward the back side of the substrate (downward), then flows in the lower part of the electrode separation diffusion layer in a direction parallel to the substrate, and from there flows to the other electrode on the substrate surface (upward).

[0005] At this point, the current flowing in the direction parallel to the substrate in the lower part of the electrode separation and diffusion layer is particularly concentrated in the region with the lowest resistance (highest concentration) within the magnetic sensing section of the lower electrode separation and diffusion layer, that is, directly below the electrode separation and diffusion layer. Furthermore, the magnetic sensing section becomes highly resistant as it extends towards the back side of the substrate; therefore, the region of the magnetic sensing section near the back side of the substrate in the lower part of the electrode separation and diffusion layer experiences almost no current flow. Consequently, the width of the current flowing in the direction parallel to the substrate narrows in the depth direction of the substrate.

[0006] It is known that the magnetic sensitivity of a Hall element increases proportionally to the width of the current flowing through it. In the structure of Patent Document 1, as described above, the width of the current flowing in the direction parallel to the substrate is relatively narrow, so the sensitivity is not significantly improved.

[0007] To address this problem, the inventors proposed a vertical Hall element in Patent Document 2, the structure of which is as follows: an N-type semiconductor layer with a fixed concentration distribution is disposed on a semiconductor substrate, and an N-type impurity diffusion layer with a higher concentration than the N-type semiconductor layer is disposed on the N-type semiconductor layer, and multiple electrodes composed of N-type impurity regions with a higher concentration than the N-type impurity diffusion layer are disposed along a straight line on the surface of the N-type impurity diffusion layer, and multiple P-type electrode separation diffusion layers are disposed between each of the multiple electrodes to separate the multiple electrodes.

[0008] According to the vertical Hall element in Patent Document 2, the resistance within the N-type semiconductor layer is uniform. Therefore, when current is supplied to a predetermined electrode, the current flowing in a direction parallel to the semiconductor substrate will flow throughout the entire N-type semiconductor layer, thereby improving magnetic sensitivity.

[0009] [Existing Technical Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Publication No. 2005-333103; [Patent Document 2] Japanese Patent Application Publication No. 2018-93083. Summary of the Invention

[0010] [The problem the invention aims to solve] However, further investigation by the inventors revealed that in the vertical Hall element structure proposed in Patent Document 2, the current flowing in a direction parallel to the semiconductor substrate is difficult to flow completely uniformly throughout the entire N-type semiconductor layer. This is because the current path flowing through the deeper portion of the N-type semiconductor layer, near the semiconductor substrate, includes paths perpendicular to the semiconductor substrate at its beginning and end, thus increasing the overall length of this current path. The increased resistance along this longer path hinders current flow. Therefore, while the magnetic sensitivity of the vertical Hall element in Patent Document 2 is significantly improved compared to Patent Document 1, there is room for further improvement in magnetic sensitivity.

[0011] Therefore, the object of the present invention is to provide a semiconductor device having a vertical Hall element having improved sensitivity to current flowing in a direction parallel to the substrate.

[0012] [Solutions for solving the problem] An embodiment of the present invention relates to a semiconductor device having a semiconductor substrate of a first conductivity type and a vertical Hall element disposed on the semiconductor substrate. The vertical Hall element comprises: a semiconductor layer of a second conductivity type disposed on the semiconductor substrate; an impurity diffusion layer of the second conductivity type disposed on the upper part of the semiconductor layer and having a higher concentration than the semiconductor layer; a plurality of electrodes formed by impurity regions of the second conductivity type disposed on the surface of the impurity diffusion layer and arranged in a straight line, wherein the impurity regions of the second conductivity type have a higher concentration than the impurity diffusion layer; a plurality of electrode separation diffusion layers of the first conductivity type disposed between each of the plurality of electrodes, thereby separating the plurality of electrodes; and a buried layer formed by impurity regions of the second conductivity type disposed between the semiconductor substrate and the semiconductor layer, wherein the impurity regions of the second conductivity type have a higher concentration than the semiconductor layer and a lower concentration than the impurity diffusion layer.

[0013] [Invention Effects] According to the present invention, since there is a second conductivity type buried layer between the semiconductor substrate and the second conductivity type semiconductor layer, when current is supplied between the two electrodes, the current flowing from one electrode toward the back side (downward) of the semiconductor substrate, then spreads throughout the entire second conductivity type semiconductor layer and the second conductivity type buried layer that become the magnetic sensing part, and flows in a direction parallel to the substrate, and from there flows toward the other electrode (upward).

[0014] That is, a buried layer of the second conductivity type, with a lower resistance than the semiconductor layer of the second conductivity type, exists in the lower part of the semiconductor layer of the second conductivity type. Therefore, current flows not only through the upper region of the semiconductor layer of the second conductivity type along a path parallel to the semiconductor substrate, but also through a path that continues from the impurity diffusion layer of the second conductivity type towards the buried layer of the second conductivity type and then flows through the buried layer of the second conductivity type. Thus, the current flowing in the direction parallel to the semiconductor substrate does not flow biased to a particular area, but flows uniformly throughout the entire semiconductor layer and the buried layer of the second conductivity type.

[0015] Therefore, the width of the current flowing in the depth direction parallel to the semiconductor substrate can be increased, thereby improving the magnetic sensitivity of the Hall element. Attached Figure Description

[0016]

【 Figure 1 (a) is a plan view of a semiconductor device having a vertical Hall element according to the first embodiment of the present invention, and (b) is a cross-sectional view along line L-L' of (a).

[0017]

Figure 2

[0018] 【 Figure 3 [Image 1] is a cross-sectional view of a semiconductor device having a vertical Hall element according to the second embodiment of the present invention.

[0019] 【 Figure 4 [Image 1] is a cross-sectional view of a semiconductor device having a vertical Hall element according to the third embodiment of the present invention. Detailed Implementation

[0020] Hereinafter, the methods for carrying out the present invention will be described in detail with reference to the accompanying drawings.

[0021] [First Implementation] Figure 1 This is a diagram illustrating a semiconductor device having a vertical Hall element 100 according to the first embodiment of the present invention. Figure 1 (a) is a plan view. Figure 1 (b) is along Figure 1 (a) Cross-sectional view of the L-L' line.

[0022] like Figure 1 As shown, the semiconductor device of this embodiment includes: a first conductivity type, namely a P-type semiconductor substrate 10; a vertical Hall element 100 disposed on the semiconductor substrate 10; and a P-type element separation diffusion layer 80 disposed in a manner surrounding the vertical Hall element 100.

[0023] The vertical Hall element 100 comprises the following components: an N-type semiconductor layer 20 of the second conductivity type disposed on a semiconductor substrate 10; an N-type impurity diffusion layer 30 disposed on the N-type semiconductor layer 20; electrodes 51 to 55, which are N-type impurity regions disposed in a straight line on the surface of the N-type impurity diffusion layer 30 and serve as electrodes for supplying drive current and for outputting Hall voltage; P-type electrode separation diffusion layers 61 to 64 disposed between the electrodes 51 to 55 on the surface of the N-type impurity diffusion layer 30 and separating the electrodes 51 to 55 respectively; and an N-type buried layer 40 disposed between the P-type semiconductor substrate 10 and the N-type semiconductor layer 20, which has a higher concentration than the N-type semiconductor layer 20 and a lower concentration than the N-type impurity diffusion layer 30.

[0024] Furthermore, in the vertical Hall element 100, an insulating film 70 made of SiO2 is provided, for example, to cover the area of ​​the surface of the N-type impurity diffusion layer 30 other than the area where the electrodes 51 to 55 are provided. As a result, current flowing parallel to the semiconductor substrate 10 can be suppressed on the surface of the N-type impurity diffusion layer 30.

[0025] exist Figure 1The right side of (b) shows a profile of the impurity concentration contained in the P-type semiconductor substrate 10, the N-type buried layer 40, the N-type semiconductor layer 20 and the N-type impurity diffusion layer 30.

[0026] As can be seen from the concentration distribution diagram, the N-type impurity diffusion layer 30 has a concentration distribution that is set to the highest concentration near its surface and becomes a low concentration as it enters the N-type semiconductor layer 20 from the surface. The concentration distribution of impurities in the N-type semiconductor layer 20 is fixed. The N-type buried layer 40 has a concentration distribution that is higher than that of the N-type semiconductor layer 20 and lower than that of the N-type impurity diffusion layer 30.

[0027] Such a structure is formed, for example, as follows.

[0028] First, N-type impurities are selectively implanted into the region of the semiconductor substrate 10 where an N-type buried layer 40 is desired to be formed. Then, an epitaxial layer, which becomes an N-type semiconductor layer 20, is formed on the substrate, allowing the implanted N-type impurities to diffuse, thereby forming an N-type buried layer 40 between the semiconductor substrate 10 and the N-type semiconductor layer 20. After forming the epitaxial layer, N-type impurities are selectively implanted into the region of the epitaxial layer where an N-type impurity diffusion layer 30 is desired to be formed, allowing the implanted N-type impurities to diffuse to a predetermined depth, thereby forming an N-type impurity diffusion layer 30 on top of the epitaxial layer. The epitaxial layer below the N-type impurity diffusion layer 30, where the N-type impurities have not diffused, becomes the N-type semiconductor layer 20.

[0029] In this way, the concentration of the N-type semiconductor layer 20 is fixed at a concentration lower than that of the bottommost part of the N-type impurity diffusion layer 30.

[0030] Here, to improve magnetic sensitivity, a thicker combined thickness of the N-type semiconductor layer 20 and the N-type buried layer 40, which serve as the magnetic sensing element, is preferred; for example, 6 μm or more is preferred. Furthermore, the impurity concentration of the N-type semiconductor layer 20 is preferably 1 × 10⁻⁶. 15 ~1×10 17 atoms / cm 3 The impurity concentration near the surface of the N-type impurity diffusion layer 30 is preferably 1 × 10⁻⁶. 17 ~1×10 18 atoms / cm 3 The depth of the N-type impurity diffusion layer 30 is preferably shallow, around 3–5 μm. Furthermore, the impurity concentration of the N-type buried layer 40 is preferably 1 × 10⁻⁶. 16 ~5×10 17 atoms / cm 3 about.

[0031] Alternatively, for example, P-type electrode separation diffusion layers 61 to 64 are formed by selectively diffusing P-type impurities into the N-type impurity diffusion layer 30.

[0032] Regarding electrodes 51 to 55, for example, after forming the P-type electrode separation diffusion layers 61 to 64, an insulating film (SiO2 film) 70 is formed by, for example, the LOCOS method, to cover the P-type electrode separation diffusion layers 61 to 64 while retaining the areas where electrodes 51 to 55 are formed, and N-type impurities are introduced using this film as a mask. At this time, the depth of electrodes 51 to 55 is formed to be equal to or shallower than the depth of the P-type electrode separation diffusion layers 61 to 64.

[0033] Next, refer to Figure 2 In the vertical Hall element 100 of the semiconductor device in this embodiment, the principle of detecting the magnetic field component in the direction parallel to the semiconductor substrate 10 will be explained.

[0034] Figure 2 It is magnification Figure 1 The cross-sectional view of (b) schematically illustrates the current flow when driving current is supplied to electrodes 51, 53 and 55 in such a manner as current flows from electrode 53 to electrodes 51 and 55.

[0035] As in Figure 2 As indicated by B, the magnetic field is applied from the inside to the front of the paper in a direction parallel to the semiconductor substrate 10.

[0036] like Figure 2 As shown, depletion layers D1 to D4 are formed around the P-type electrode separation diffusion layers 61 to 64, as indicated by dashed lines. The lowest position of these depletion layers D1 to D4 is approximately the same as the upper surface of the N-type semiconductor layer 20.

[0037] That is, in the vertical Hall element 100 of this embodiment, the depth and concentration of the P-type electrode separation diffusion layers 61-64 and the depth and concentration of the N-type impurity diffusion layer 30 are set such that the lowest position of the depletion layers D1-D4 is approximately the same as the upper surface of the N-type semiconductor layer 20. Furthermore, the depletion layer is also formed inside the P-type electrode separation diffusion layers 61-64, but... Figure 2 Omitted in .

[0038] In the vertical Hall element 100 with such a structure, if a current flows from electrode 53 to electrodes 51 and 55, the current first flows from electrode 53 perpendicular to the semiconductor substrate 10 and toward the back side (downward) of the semiconductor substrate 10 through the N-type impurity diffusion layer 30, the N-type semiconductor layer 20 and the N-type buried layer 40, as indicated by arrow Iv1.

[0039] Then, the current flows in the direction parallel to the semiconductor substrate 10 (left-right direction), as indicated by arrows Ih1 and Ih2. At this time, there are P-type electrode separation diffusion layers 62 and 63 and depletion layers D2 and D3 on both sides of the electrode 53. Therefore, the current flowing in the direction parallel to the semiconductor substrate 10 cannot flow in the N-type impurity diffusion layer 30, but will flow through the N-type semiconductor layer 20 and the N-type buried layer 40, as indicated by arrows Ih1 and Ih2.

[0040] In the existing vertical Hall element (Patent Document 2), the impurity concentration distribution of the N-type semiconductor layer is fixed, resulting in uniform resistance within the N-type semiconductor layer. However, since the electrodes are formed on the surface of the semiconductor substrate 10, the current path through the N-type semiconductor layer near the semiconductor substrate, i.e., the deeper portion of the N-type semiconductor layer, becomes longer. Consequently, the resistance of this current path becomes higher, making it difficult for current to flow. In contrast, in this embodiment, a higher concentration of N-type buried layer 40 is formed in the lower part of the N-type semiconductor layer 20 compared to the N-type semiconductor layer 20, thereby reducing the resistance of the deeper portion near the semiconductor substrate 10. As a result, the resistance of the longer current path through the deeper portion of the N-type semiconductor layer 20, i.e., the N-type buried layer 40, becomes lower. Therefore, the current flowing through the N-type semiconductor layer 20 and the N-type buried layer 40, indicated by arrows Ih1 and Ih2, does not flow towards the surface of the N-type semiconductor layer 20 but flows uniformly throughout the entire N-type semiconductor layer 20 and the N-type buried layer 40, as shown in the figure.

[0041] Then, the current is represented by the arrow Iv. 21 Iv 22 As indicated, the material flows perpendicular to the semiconductor substrate 10 and toward the surface of the N-type impurity diffusion layer 30 (above), through the N-type buried layer 40, the N-type semiconductor layer 20 and the N-type impurity diffusion layer 30, and into the electrodes 51 and 55.

[0042] For the various currents Iv1 and Iv flowing in this way 21 Iv 22 Under the influence of the magnetic field, Ih1 and Ih2 generate electromotive forces in directions perpendicular to both the current and the magnetic field. That is, for current Iv1, a Lorentz force is generated in the direction from electrode 53 towards electrode 52 (to the left); for current Iv... 21 This generates a Lorentz force in the direction (to the right) from electrode 51 toward electrode 52; for current Iv 22A Lorentz force is generated from electrode 55 toward the opposite side of the P-type electrode separation diffusion layer 64 (right direction); for current Ih1, a Lorentz force is generated from N-type semiconductor layer 20 and N-type buried layer 40 toward electrode 52 (upward direction); for current Ih2, a Lorentz force is generated from N-type semiconductor layer 20 and N-type buried layer 40 toward semiconductor substrate 10 (downward direction).

[0043] In particular, in this embodiment, a large Lorentz force is generated mainly by the currents Ih1 and Ih2 flowing in a direction parallel to the semiconductor substrate 10 and the magnetic field in a direction perpendicular to them. As a result, a potential difference can be generated between the electrodes 52 and 54, and the magnetic field can be detected by using this potential difference.

[0044] In this embodiment, as described above, the currents Ih1 and Ih2 flowing in a direction parallel to the semiconductor substrate 10 permeate the entire N-type semiconductor layer 20 and the N-type buried layer 40, thus increasing their width in the depth direction. The magnetic sensitivity of the Hall element is proportional to the width of the flowing current; therefore, according to this embodiment, the magnetic sensitivity can be improved. Therefore, as described above, a thicker combined thickness of the N-type semiconductor layer 20 and the N-type buried layer 40 is more desirable.

[0045] In this embodiment, current flows in the N-type semiconductor layer 20, which has a low impurity concentration and high mobility, in a direction parallel to the semiconductor substrate 10. Furthermore, the N-type buried layer 40 has a high concentration compared to the N-type semiconductor layer 20 but a low concentration compared to the N-type impurity diffusion layer 30; therefore, the mobility in the N-type buried layer 40 does not decrease significantly. The magnetic sensitivity of the Hall element also increases proportionally with the mobility; therefore, according to this embodiment, the magnetic sensitivity can be further improved.

[0046] In addition, an N-type buried layer 40 with a higher concentration than the N-type semiconductor layer 20 is formed between the N-type semiconductor layer 20 and the semiconductor substrate 10, which can suppress leakage current at high temperatures and thus also suppress the increase of bias voltage at high temperatures.

[0047] Thus, according to this embodiment, a semiconductor device with a vertical Hall element having high sensitivity and low bias voltage can be realized.

[0048] [Second Implementation] In the first embodiment described above, since a low-resistance N-type buried layer 40 is provided throughout the entire lower portion of the N-type semiconductor layer 20, i.e., the N-type buried layer 40 region is large, the current consumption may increase. Therefore, as a second embodiment of the present invention, a semiconductor device equipped with a vertical Hall element that suppresses the increase in current consumption will be described.

[0049] Figure 3This is a cross-sectional view of a semiconductor device having a vertical Hall element 200 according to the second embodiment of the present invention. Furthermore, regarding... Figure 1 The same structural elements of the semiconductor device with the vertical Hall element 100 shown are labeled with the same reference numerals, and repeated descriptions are omitted where appropriate.

[0050] The semiconductor device with a vertical Hall element 200 in this embodiment omits the N-type buried layer 40 in the vertical Hall element 100 of the first embodiment. Instead, it is configured such that an N-type buried layer 41-44 with a higher concentration than the N-type semiconductor layer 20 disposed between the semiconductor substrate 10 and the N-type semiconductor layer 20 is provided below the P-type electrode separation diffusion layers 61-64 of the electrodes 51-55, respectively.

[0051] Here, the N-type buried layers 41 to 44 are respectively disposed approximately directly below each electrode separation diffusion layer 61 to 64 and are separated from each other.

[0052] Regarding such N-type buried layers 41 to 44, for example, after selectively implanting N-type impurities in the region of the semiconductor substrate 10 where the N-type buried layers 41 to 44 are to be formed, an epitaxial layer to form an N-type semiconductor layer 20 is formed thereon, and the implanted N-type impurities diffuse, thereby forming between the semiconductor substrate 10 and the N-type semiconductor layer 20.

[0053] In this way, N-type buried layers 41-44 are formed only approximately directly below the electrode separation diffusion layers 61-64. Thus, for example, when a drive current is supplied to electrodes 51, 53, and 55 in such a way that current flows from electrode 53 to electrodes 51 and 55, the resistance of the current path flowing from electrode 53 through the N-type impurity diffusion layer 30 and the N-type semiconductor layer 20 to electrode 51, and the resistance of the current path flowing from electrode 53 through the N-type buried layers 42 and 41 to electrode 51, and to electrode 55 through the N-type buried layers 43 and 44, will not decrease excessively, thereby suppressing an increase in current consumption.

[0054] Furthermore, directly below electrodes 52 and 54, current flows through the N-type semiconductor layer 20, which has a low impurity concentration and high mobility. Since the magnetic sensitivity of the Hall element increases proportionally to its mobility, the magnetic sensitivity can be further improved according to this embodiment.

[0055] Furthermore, the N-type buried layers 41-44 are preferably not formed directly below the electrodes 51-55. With this structure, the vertical component of the current path, for example, the component pointing downwards from electrode 53 in the above example, is not completely vertical downwards, but rather points towards the N-type buried layers 42 and 43, thus pointing downwards in a slightly inclined direction. Consequently, the vertical component of this slightly inclined current path is closer to the electrodes 52 and 54, which become the Hall voltage output electrodes. Therefore, the Hall voltage obtained from the vertical component of the current path can be increased.

[0056] [Third Implementation] As a third embodiment of the present invention, a semiconductor device having a vertical Hall element that suppresses the increase of current consumption through a structure different from that of the second embodiment described above will be described.

[0057] Figure 4 This is a cross-sectional view of a semiconductor device having a vertical Hall element 300 according to the third embodiment of the present invention. Furthermore, regarding... Figure 1 The same structural elements of the semiconductor device with the vertical Hall element 100 shown are labeled with the same reference numerals, and repeated descriptions are omitted where appropriate.

[0058] The semiconductor device with a vertical Hall element 300 in this embodiment omits the N-type impurity diffusion layer 30 in the vertical Hall element 100 of the first embodiment. Instead, it is configured with N-type impurity diffusion layers 31-35 disposed separately around each electrode 51-55. The N-type impurity diffusion layers 31-35 have a depth greater than and the same as that of the electrodes 51-55, and are also formed to be larger than the electrodes 51-55. Similar to the N-type impurity diffusion layer 30 in the first embodiment, the N-type impurity diffusion layers 31-35 have the highest concentration near the surface and a concentration distribution that decreases as it penetrates from the surface into the N-type semiconductor layer 20, resulting in a high concentration compared to the N-type semiconductor layer 20.

[0059] The N-type impurity diffusion layers 31-35 of the above structure are formed, for example, by forming an N-type buried layer 40 and an N-type semiconductor layer 20 composed of an epitaxial layer on a semiconductor substrate 10, selectively implanting N-type impurities into the region of the epitaxial layer where the N-type impurity diffusion layers 31-35 are to be formed, and causing the implanted N-type impurities to diffuse to a predetermined depth.

[0060] In addition, in this embodiment, the depth of the P-type electrode separation diffusion layers 61-64 is made sufficiently shallower than the N-type impurity diffusion layers 31-35.

[0061] Based on this structure, an N-type semiconductor layer 20 with low impurity concentration exists below the P-type electrode separation diffusion layers 61-64. The region shown by the dashed line in the diagram, from the bottom of the depletion layers D1-D4 formed around the P-type electrode separation diffusion layers 61-64 to the bottom of the N-type impurity diffusion layers 31-35, also forms a current path. This current path contains the N-type semiconductor layer 20 with low impurity concentration, thus increasing its resistance. Therefore, current consumption can be suppressed. Furthermore, since the mobility of this current path is increased, magnetic sensitivity can be further improved according to this embodiment.

[0062] While the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can obviously be made without departing from the spirit of the present invention.

[0063] For example, the structure can be configured to combine the second and third embodiments, thereby further suppressing current consumption.

[0064] Furthermore, the explanation was given with the first conductivity type being P and the second conductivity type being N, but it is also acceptable to interchange the conductivity types so that the first conductivity type is N and the second conductivity type is P.

[0065] In addition, in the above embodiment, the number of electrodes is set to 5. However, if the bias voltage can be so small as to eliminate the bias (offset) without the need for the rotating current method, then as long as there are 2 electrodes for supplying the drive current and 1 electrode for outputting the Hall voltage, a total of 3 or more electrodes are sufficient.

[0066] Label Explanation 10 Semiconductor substrate; 20 N-type semiconductor layer; 30, 31, 32, 33, 34, 35 N-type impurity diffusion layers; 40, 41, 42, 43, 44 N-type buried layers; 51, 52, 53, 54, 55 Electrodes; 61, 62, 63, 64 Electrode separation diffusion layers; 70 Insulating film; 80 Element separation diffusion layer; 100, 200, 300 Vertical Hall element; D1, D2, D3, D4 Depletion layers.

Claims

1. A semiconductor device comprising: Semiconductor substrate of the first conductivity type; and The vertical Hall element disposed on the semiconductor substrate is characterized in that... The vertical Hall element comprises: A second conductivity type semiconductor layer is disposed on the semiconductor substrate; The second conductivity type of impurity diffusion layer is disposed on the upper part of the semiconductor layer and has a higher concentration compared with the semiconductor layer; Multiple electrodes, consisting of impurity regions of the second conductivity type, are disposed on the surface of the impurity diffusion layer and arranged in a straight line, wherein the multiple electrodes consisting of impurity regions of the second conductivity type have a high concentration compared to the impurity diffusion layer. Multiple electrode separation diffusion layers of the first conductivity type are respectively disposed between each of the multiple electrodes, thereby separating the multiple electrodes. as well as A buried layer composed of impurity regions of a second conductivity type is disposed between the semiconductor substrate and the semiconductor layer. The buried layer composed of impurity regions of the second conductivity type has a higher concentration than the semiconductor layer and a lower concentration than the impurity diffusion layer. The impurity diffusion layer has a concentration distribution that decreases from the surface toward the semiconductor layer. The impurity diffusion layer comprises multiple impurity diffusion layers that are separately disposed around each of the plurality of electrodes. The plurality of electrodes includes Hall voltage output electrodes.

2. The semiconductor device as claimed in claim 1, characterized in that: The embedded layer comprises multiple embedded layers located approximately directly below each of the multiple electrode separation diffusion layers and disposed separately from each other.

3. The semiconductor device as claimed in claim 1 or 2, characterized in that: The lowest part of the depletion layer formed around each of the plurality of electrode separation diffusion layers is located at approximately the same position as the upper surface of the semiconductor layer.

4. The semiconductor device as claimed in claim 1 or 2, characterized in that: The semiconductor layer and the impurity diffusion layer are epitaxial layers.

5. The semiconductor device as claimed in claim 1 or 2, characterized in that: The surfaces of the impurity diffusion layer and the plurality of electrode separation diffusion layers, except for the areas where the plurality of electrodes are disposed, are covered by an insulating film.

6. The semiconductor device as claimed in claim 1 or 2, characterized in that: The number of the plurality of electrodes is three or more.

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