Phase change random access memory element and method of forming the same

Abstract

A method for forming a phase change random access memory (PCRAM) element includes: forming a phase change element on a bottom electrode and forming a top electrode on the phase change element; forming a protective layer around the phase change element; and after forming the protective layer, forming a nitrogen-containing sidewall spacer layer around the protective layer.

Description

Technical Field

[0001] The present application relates to a phase change random access memory and a method for forming the same. Background Art

[0002] Flash memory is a widely used non-volatile memory. However, flash memory is expected to encounter difficulties in miniaturization. Therefore, alternative types of non-volatile memory are being explored. Among these alternative types of non-volatile memory is phase change memory (PCM). PCM is a non-volatile memory in which the phase of a phase change element is used to represent the state of data. PCM has the benefits of fast read and write times, non-destructive reading, and high miniaturization. Summary of the invention

[0003] In some embodiments, a method for forming a phase change random access memory element includes: forming a phase change element on a bottom electrode and forming a top electrode on the phase change element; forming a protective layer around the phase change element, wherein the protective layer is nitrogen-free and is composed of a binary carbon-hydrogen compound; and after forming the protective layer, forming a nitrogen-containing sidewall spacer layer around the protective layer.

[0004] In some embodiments, a method for forming a phase change random access memory element includes: forming a phase change material layer on a bottom electrode and forming a top electrode on the phase change material layer; etching the phase change material layer in a plasma chamber to form a phase change element; performing a deposition process in the plasma chamber to deposit a protective coating on an outer sidewall of the phase change element, wherein the protective coating is composed of a binary carbon-hydrogen compound and the deposition process does not use a nitrogen-containing precursor; and after performing the deposition process, forming a first sidewall spacer layer on the protective coating.

[0005] In some embodiments, a method for forming a phase change random access memory element includes: forming a stack structure on a bottom electrode, the stack structure including a phase change element and a top electrode; forming a carbon-hydrogen compound layer on the stack structure, wherein the carbon-hydrogen compound layer as a whole is composed of binary carbon-hydrogen compounds; forming a first sidewall spacer layer on the carbon-hydrogen compound layer; and after forming the first sidewall spacer layer, forming a conductive intermediate window on the top electrode of the stack structure.

[0006] In some embodiments, a phase change random access memory device includes a memory cell, a protective coating, and a first sidewall spacer. The memory cell is located on an intermetallic dielectric (IMD) layer, and the memory cell includes a bottom electrode, a top electrode, and a phase change element located between the top electrode and the bottom electrode. The protective coating is on an outer sidewall of the phase change element. A first sidewall spacer is on an outer sidewall of the protective coating, wherein the first sidewall spacer has a greater nitrogen atomic concentration than the protective coating. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 illustrates cross-sectional views of some embodiments of memory devices according to the present disclosure;

[0009] Figure 2 The following diagrams illustrate some embodiments of the present disclosure. Figure 1 The section line in Figure 1 A top view of a memory element;

[0010] Figure 3 The diagram shows the Figure 1 Cross-sectional views of some alternative embodiments of memory elements;

[0011] Figure 4 The diagram shows a method according to the present disclosure including Figure 1 Cross-sectional views of some embodiments of an integrated circuit (IC) of a memory device;

[0012] Figures 5 to 14 illustrates cross-sectional views of some embodiments of methods of forming memory devices according to the present disclosure;

[0013] Fig.15A and Fig. 15B illustrates a method of forming a memory device according to some embodiments;

[0014] Fig.16 Some embodiments of transformer coupled plasma (TCP) reactors that may be used to fabricate memory devices according to the present disclosure are illustrated.

[0015]

Explanation of symbols

[0016] 100a memory device

[0017] 100b memory device

[0018] 102 substrate

[0019] 104 Transistors

[0020] 106 Bottom inner connection window

[0021] 108 Bottom Conductive Wire

[0022] 110 IMD layer

[0023] 112 Dielectric layer

[0024] 114 Bottom electrode

[0025] 116 PCM units

[0026] 120 PCE

[0027] 120' PCE

[0028] 120s outer wall

[0029] 120s' side wall

[0030] 122 Top electrode

[0031] 122' Top Electrode

[0032] 122s Outer wall

[0033] 122s' side wall

[0034] 124 Hard Mask

[0035] 124' Hard Mask

[0036] 124s Outer wall

[0037] 124s' side wall

[0038] 125 Protective coating

[0039] 126 first sidewall spacer

[0040] 128 second sidewall spacer

[0041] 130 IMD layer

[0042] 132 Conductive intermediary window

[0043] 134 Upper conductive wire

[0044] 202 gate electrode

[0045] 204 Gate Dielectric

[0046] 206 Transistor Sidewall Spacer

[0047] 208 source / drain region

[0048] 300 Integrated Circuits

[0049] 304 Internal connection structure

[0050] 306 substrate

[0051] 308 Shallow Trench Isolation (STI) Region

[0052] 312 Access transistor

[0053] 320 Access gate dielectric

[0054] 322 Access Sidewall Spacer

[0055] 324 Source / Drain Region

[0056] 402 phase change material layer

[0057] 404 Top electrode layer

[0058] 406 Hard Mask Layer

[0059] 408 Organic Mask Layer

[0060] 408' Organic Mask

[0061] 410 Overlying Photoresist

[0062] 412 Protective coating

[0063] 414 sidewall spacer layer

[0064] 900 TCP Reactor

[0065] 910 Processing Chamber

[0066] 911 Gas inlet hole

[0067] 920 Plasma-containing region

[0068] 930 Wafer Suction Cup

[0069] 940 Wafer

[0070] 945 RF Power Supply

[0071] 950 Micro Actuator

[0072] 960 Power Supply

[0073] 965 Flat Helical Coil

[0074] 970 RF Power Supply

[0075] 980 Dielectric Plate

[0076] 991 x-axis

[0077] 992 y-axis

[0078] 993 z-axis

[0079] A. Heat dissipation path

[0080] C Angle

[0081] CO contact

[0082] D Angle

[0083] E angle

[0084] ESL1 Etch Stop Layer

[0085] ESL2 Etch Stop Layer

[0086] ESL3 Etch Stop Layer

[0087] IMD1 IMD layer

[0088] IMD2 IMD layer

[0089] IMD3 IMD layer

[0090] IMD4 IMD layer

[0091] IMD5 IMD layer

[0092] M-method

[0093] M1 Metallization Layer

[0094] M2 Metallization Layer

[0095] M3 Metallization Layer

[0096] S11 Block

[0097] S12 Block

[0098] S13 Block

[0099] S14 Block

[0100] S15 Block

[0101] S16 Block

[0102] S17 Block

[0103] S18 Block

[0104] S19 Block

[0105] S20 Block

[0106] S21 Block

[0107] V1 Intermediary Window

[0108] V2 Intermediary Window

[0109] V3 Intermediary Window

[0110] WT1 Width

[0111] WT2 Width

[0112] WB1 Width DETAILED DESCRIPTION

[0113] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0114] Additionally, spatially relative terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to simplify the description to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device / element in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0115] A phase change memory (PCM) cell includes a phase change element (PCE) sandwiched between a bottom electrode and a top electrode. In some embodiments, the PCE is made of chalcogenide glass. Chalcogenide glass has a crystalline state and an amorphous state, and the crystalline state and the amorphous state have completely different resistance values, so that the PCE can switch between the crystalline state and the amorphous state to correspond to different data states. More specifically, during the operation of some PCM cells, the PCE can be heated to a temperature higher than its melting point (e.g., above 600 degrees Celsius), such a temperature causes the chalcogenide glass to lose its crystallinity. The PCE can then be quickly cooled or "quenched" to "freeze" the PCE in an amorphous high resistance state, which can, for example, correspond to a "0" data state. This operation can be referred to as a "reset" operation of the PCM cell. On the other hand, by heating the PCE to a lower temperature (e.g., about 100-150 degrees Celsius), wherein the lower temperature is higher than the crystallization point of the PCE but lower than the melting point of the PCE, the PCE will be transformed into a low-resistance crystalline state, which may correspond to a "1" state, for example. This operation may be referred to as a "set" operation of the PCM cell.

[0116] During the method of manufacturing the PCM cell, a nitride-based spacer layer (e.g., a SiN layer or a SiON layer) is formed on the patterned PCM, and then the nitride-based spacer layer is patterned into a nitride-based sidewall spacer that will remain on the sidewall of the PCE cell. Various aspects of the present disclosure are inspired by using a plasma deposition process to deposit the nitride-based spacer layer. This reactive plasma will react with the outermost wall of the PCE during deposition, thereby causing damage (e.g., voids) on the PCE sidewall. Various aspects of the present disclosure are also inspired by using a plasma etching process to pattern the nitride-based spacer layer. This etchant can attack the damaged sidewall of the PCE, which in turn can aggravate the damage on the PCE sidewall (e.g., enlarge the void on the PCE sidewall).

[0117] Therefore, in some embodiments of the present disclosure, a sidewall protective coating is formed on the outer sidewalls of the PCE before forming the nitride-based spacer layer. The protective coating is deposited using a plasma that is chemically inert to the PCE. The term "chemically inert" as used herein means that no chemical reaction occurs between the plasma and the material exposed to the plasma. Therefore, the deposition process does not cause a chemical reaction with the PCE, thereby preventing the sidewalls of the PCE from being damaged (e.g., voids). In addition, the sidewall protective coating can block the sidewalls of the PCE from contacting with the reactive plasma during the deposition of the nitride-based spacer layer and / or block the sidewalls of the PCE from contacting with the etchant during the spacer patterning process. Therefore, damage to the sidewalls of the PCE can be reduced.

[0118] refer to Figure 1 , provides a cross-sectional view of a memory device 100a according to some embodiments. Figure 2 , according to some embodiments, Figure 1 The cross-sectional view shown in Figure 1 A top view of the memory device 100 a is shown in FIG.

[0119] The memory device 100a includes a phase change memory (PCM) cell 116. The PCM cell 116 includes a bottom electrode 114, a top electrode 122, and a phase change element (PCE) 120 between the bottom electrode 114 and the top electrode 122. The bottom electrode 114 is disposed within the dielectric layer 112. The PCE 120 covers the bottom electrode 114. The top electrode 122 covers the PCE 120. The memory device 100a also includes a hard mask 124, a protective coating (interchangeably referred to as a protective layer) 125, a first sidewall spacer 126, and a second sidewall spacer 128. The hard mask 124 covers the top electrode 122. The protective coating 125 directly contacts the outer sidewall 120s of the PCE 120, the outer sidewall 122s of the top electrode 122, and the outer sidewall 124s of the hard mask 124, but is separated from the bottom electrode 114. The first sidewall spacer 126 directly contacts the outer sidewall of the protective coating 125. The second sidewall spacer 128 has: a first portion that directly contacts the outer sidewall of the first sidewall spacer 126 and continuously extends from the upper surface of the hard mask 124 to the upper surface of the dielectric layer 112; and a second portion that extends from the bottom of the first portion along the top surface of the dielectric layer 112 in a direction away from the bottom electrode 114. In some embodiments, the protective coating 125 is composed of a material different from the first sidewall spacer 126 and the second sidewall spacer 128. In some embodiments, the first sidewall spacer 126 is composed of a material different from that of the second sidewall spacer 128.

[0120] PCM cell 116 is disposed on substrate 102, and inter-metal dielectric (IMD) layer 110 is disposed on substrate 102. Bottom conductive line 108 covering bottom interconnect via 106 electrically couples PCM cell 116 to transistor 104. In some embodiments, bottom conductive line 108 and bottom interconnect via 106 electrically couple PCM cell 116 to underlying metal layers and / or electrical components, such as resistors, capacitors, and / or diodes. Another IMD layer 130 is disposed on PCM cell 116. Conductive via 132 is disposed above top electrode 122 and connects top electrode 122 to an upper metal layer including upper conductive line 134. Conductive via 132 and upper conductive line 134 are within IMD layer 130 and may, for example, electrically couple top electrode 122 to a bit line (not shown).

[0121] In some embodiments, during operation of the PCM cell 116, the PCM cell 116 changes between states according to a voltage applied from the upper conductive line 134 to the bottom conductive line 108. The PCM cell 116 may, for example, be in a low resistance state in which the PCE 120 is in a crystalline phase. Changing the PCE 120 to the crystalline phase (i.e., a set operation) may be performed, for example, by heating the PCE 120 to a relatively low temperature (e.g., above the crystallization point of the PCE 120 but below the melting point of the PCE 120) using Joule heat generated by a current passing through the PCE 120. The current flowing through the PCE 120 in the set operation is referred to as a set current I set On the other hand, the PCM cell 116 may be, for example, in a high resistance state in which the PCE 120 is in an amorphous phase. Changing the PCE 120 to the amorphous phase (i.e., a reset operation) may be performed, for example, by heating the PCE 120 to a relatively high temperature (e.g., higher than the melting point of the PCE 120) using Joule heat generated by another current passing through the PCE 120. The current flowing through the PCE 120 in the reset operation is referred to as a reset current I reset .

[0122] In some embodiments, no voids exist on the outer sidewall 120s of the PCE 120. In some embodiments, the PCE 120 is a continuous layer extending from the lower surface of the top electrode 122 to the upper surface of the dielectric layer 112 and the upper surface of the bottom electrode 114. The outer sidewall 120s of the PCE 120 may be substantially aligned with the outer sidewall 122s of the top electrode 122 and the outer sidewall 124s of the hard mask 124. The protective coating 125 is configured and / or formed to prevent the PCE 120 from reacting with the plasma used to form the first sidewall spacer 126. Therefore, the formation of the first sidewall spacer 126 does not cause observable damage on the outer sidewall 120s of the PCE 120 (e.g., does not cause voids to be generated on the outer sidewall 120s of the PCE 120). In some embodiments, the protective coating 125 is also used to suppress outgassing from the PCE 120 to the surrounding environment and / or from the IMD layer 130 to the PCE 120 because the outer sidewall 120s of the PCE 120 is separated from the IMD layer 130 by three layers (e.g., layers 125, 126, and 128) instead of two layers (e.g., double spacer layers 126 and 128 without the coating 125). Therefore, toxic gases generated by outgassing of materials of the PCE 120 can be reduced, and undesirable oxidation of the PCE 120 caused by outgassing of oxide materials from the IMD layer 130 can also be reduced.

[0123] Figure 2 The top view corresponds to the Figure 1 The cross-sectional lines shown in FIG. 1 are images obtained using an imaging tool (e.g., SEM, TEM, etc.). In some embodiments, if the PCM unit 116 is circular / elliptical when viewed from above, the protective coating 125 is a single continuous annular (i.e., ring-shaped) coating when viewed from above (see, e.g., FIG. 114 ). Figure 2 ), so when depicted in cross-section, the single continuous annular coating would naturally be on opposite sidewalls of the PCE 120. Additionally, if the PCM unit 116 is circular or elliptical when viewed from above, any length and / or width associated with a cross-sectional view of a layer including the PCM unit 116 would correspond to the diameter of the circle or the length between two vertices on the major axis of the ellipse, respectively.

[0124] In some embodiments, PCE 120 includes a chalcogenide material, which is an alloy including a combination of a Group VI element and a Group IV and / or Group V element. PCM layer 118 may include, for example, Ge2Sb2Te5 (GST), ScSbTe, GeTe, InSb, Sb2Te3, Sb 70 Te 30 , GaSb, InSbTe, GaSeTe, SnSbTe4, InSbGe, AgInSbTe, Te81 Ge 15 Sb2S2, GeSbTe, SnSbTe, GeSbSe, GeSbTe, etc.

[0125] In some embodiments, the protective coating 125 is a carbon-based material or a hydrocarbon-based material. In addition, the protective coating 125 is nitrogen-free, so the protective coating 125 can be formed without using a nitrogen-containing precursor, thereby preventing chemical reactions with the PCE 120 during the formation of the protective coating 125, as described below. In addition, the protective coating 125 is a binary carbon-hydrogen compound, which provides higher adhesion to the nitride-based spacer 126 than a ternary carbon-hydrogen compound. For example, the protective coating 125 can be CH x Binary compounds, where x is between 2 and 4. In some embodiments, the thickness of the protective coating 125 may be in the range of about 10 angstroms to about 20 angstroms. If the thickness of the protective coating 125 is greater than about 20 angstroms, it may suffer from film-to-film adhesion problems (e.g., adhesion between the protective coating 125 and the nitride-based spacer 126 may be reduced) and may also have unsatisfactory surface roughness. If the thickness of the protective coating 125 is less than about 10 angstroms, sidewall protection of the PCE 120 may be unsatisfactory.

[0126] In some embodiments, the first sidewall spacer 126 is oxygen-free, thereby preventing undesired oxidation of the PCE 120 caused by outgassing (or degassing) of oxygen-containing materials. For example, the first sidewall spacer 126 can be or include silicon nitride (SiN or Si3N4), silicon carbide (SiC), or other suitable oxygen-free dielectric materials formed at low temperatures (less than about 250 degrees Celsius). In some embodiments, the second sidewall spacer 128 can be, for example, or include SiC, silicon oxycarbide (SiOC), etc., or a combination thereof.

[0127] In some embodiments, the top electrode 122 may be, for example, or include copper (Cu), aluminum copper alloy (AlCu), titanium nitride (TiN), tantalum nitride (TaN), titanium tungsten alloy (TiW), titanium tungsten nitride (TiWN), titanium tantalum nitride (TITAN), tungsten (W), etc., or a combination thereof. In some embodiments, the bottom electrode 114 may be, for example, or include Cu, TiN, TiW, TiWN, TiTaN, TaN, W, etc., or a combination thereof. In some embodiments, the hard mask 124 may be, for example, or include silicon, silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon doped carbon, carbon, etc., or a combination thereof.

[0128] In some embodiments, the conductive intermediate window 132 and the upper conductive line 134 may be, for example, respectively or include Cu, AlCu, Al, TiN, TaN, etc., or a combination thereof. In some embodiments, the dielectric layer 112 may be, for example, or include SiN, SiC, SiON, SiOC, etc. In some embodiments, the IMD layer 130 may be, for example, or include tetraethyl orthosilicate (TEOS) (e.g., plasma enhanced TEOS, low particle TEOS, etc.), an extremely low dielectric constant dielectric, etc.

[0129] In some embodiments, the PCE 120 has a trapezoidal shape, wherein the top surface of the PCE 120 is narrower than the bottom surface of the PCE 120. In more detail, the width of the PCE 120 decreases as the distance from the bottom electrode 114 increases. In this way, the width WT1 of the top surface of the PCE 120 is less than the width WB1 of the bottom surface of the PCE 120. The top and bottom surfaces of the PCE 120 may be connected by an angled outer sidewall 120s. In addition, the top electrode 122 and the hard mask 124 may present a similar trapezoidal shape.

[0130] The trapezoidal PCE 120 can reduce the heat dissipation path, thereby increasing the thermal confinement in the PCE 120. The heat dissipation path refers to the distance between the bottom electrode 114 and the outer sidewall 120s of the PCE 120. An example of one of the many heat dissipation paths is illustrated by arrow A. By reducing the heat dissipation path and increasing the thermal confinement in the PCE 120, the reset current I reset and / or set current set current I set decline.

[0131] In some embodiments, the bottom surface of the PCE 120 meets the outer sidewall 120s of the PCE 120 at an angle C. In order to achieve sufficient thermal confinement to reduce the reset current I reset and / or set current set current I set , the angle C may be an acute angle. For example, in some embodiments, in order to achieve sufficient thermal confinement to reduce the reset current I of the PCRAM element 100a, reset and / or set current set current I set , the angle C can be in the range between about 45 degrees to about 85 degrees.

[0132] Due to the nature of the trapezoidal-like shape, the width WB1 of the bottom surface of the PCE 120 is greater than the width WT1 of the top surface of the PCE 120. Similarly, the width WT1 of the top surface of the PCE 120 is greater than the width of the top surface of the top electrode 122, and the width of the top surface of the top electrode 122 is greater than the width of the top surface of the hard mask 124. In some embodiments, the width WB1 of the bottom surface of the PCE 120, the width WT1 of the top surface of the PCE 120, and the width of the top surface of the top electrode 122 are in a range from about 20 nanometers to about 300 nanometers.

[0133] The transistor 104 includes a gate electrode 202, a gate dielectric 204, a transistor sidewall spacer 206, and a source / drain region 208. The bottom inner connection interposer 106 is electrically coupled to the source / drain region 208 of the transistor 104. The source / drain region 208 is disposed in the substrate 102 on either side of the gate electrode 202. In addition, the source / drain region 208 is doped to have a first conductivity type that is opposite to a second conductivity type of a channel region in the substrate 102 and below the gate dielectric 204. The gate electrode 202 can be, for example, doped polysilicon or a metal such as TaN, TiN, tungsten, or a combination thereof. The gate dielectric 204 can be, for example, an oxide (e.g., silicon dioxide), or a high dielectric constant (high-k) dielectric material. The transistor sidewall spacer 206 can be, for example, made of silicon nitride (e.g., SiN or Si3N4).

[0134] Reference Figure 3 , provides Figure 1 Cross-sectional views of some alternative embodiments of memory elements 100b, wherein PCE 120' has a rectangular shape in the cross-sectional view. In other words, the width of PCE 120' remains substantially constant as the distance from the bottom electrode 114 increases. In this way, the width WT2 of the top surface of PCE 120' is substantially equal to the width WB2 of the bottom surface of PCE 120'. The top surface and the bottom surface of PCE 120' can be connected by a substantially vertical outer sidewall 120s'. In addition, in the cross-sectional view, the top electrode 122' and the hard mask 124' can exhibit similar rectangular shapes and have substantially vertical sidewalls 122s' and 124s', respectively.

[0135] Figure 4 A cross-sectional view of some embodiments of an integrated circuit 300 is shown, which includes a memory cell 116 disposed in an interconnect structure 304 of the integrated circuit 300. In some embodiments, a memory cell 116 is shown and described. Figure 1 The PCM unit 116 is the same as the memory unit 116 .

[0136] The integrated circuit 300 includes a substrate 306. The substrate 306 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. The illustrated embodiment depicts one or more shallow trench isolation (STI) regions 308, which may include dielectric-filled trenches within the substrate 306.

[0137] The access transistor 312 is disposed between the plurality of STI regions 308. The access transistor 312 includes an access gate electrode 316, an access gate dielectric 320, an access sidewall spacer 322, and a source / drain region 324. The source / drain region 324 is disposed in the substrate 306 between the access gate electrode 316 and the STI region 308, and is doped to have a first conductivity type that is opposite to a second conductivity type of a channel region below the gate dielectric 320. The access gate electrode 316 may be, for example, doped polysilicon or a metal such as aluminum, copper, or a combination thereof. The access gate dielectric 320 may be, for example, an oxide (e.g., silicon dioxide), or a high-k dielectric material. For example, the access sidewall spacer 322 may be made of, for example, silicon nitride (e.g., SiN or Si3N4). In some embodiments, access transistor 312 may be, for example, electrically coupled to a word line (WL) such that an appropriate WL voltage may be applied to access gate electrode 316 .

[0138] The internal connection structure 304 is arranged on the substrate 306 and couples the elements (e.g., transistors 312) to each other. The internal connection structure 304 includes a plurality of IMD layers IMD1, IMD2, IMD3, IMD4, and IMD5 and a plurality of metallization layers M1, M2, M3, M4, and M5, which are stacked on each other in an alternating manner. The IMD layers IMD1-IMD5 can be made of, for example, a low-k dielectric (such as undoped silicate glass) or an oxide (such as silicon dioxide) or an extremely low-k dielectric layer. The metallization layers M1-M5 each include metal lines or wires formed in trenches in the corresponding IMD layers IMD1-IMD5 and can be made of one or more metals (such as TiN, TaN, copper, aluminum, tungsten, etc., or a combination thereof). The contact CO extends from the bottom metallization layer M1 to the source / drain region 324 and / or the gate electrode 316; the interlayer window V1 extends between the metallization layers M1 and M2; the interlayer window V2 extends between the metallization layers M2 and M3; the interlayer window V3 extends between the metallization layers M3 and M4; and the interlayer window V4 extends between the metallization layer M5 and the top electrode 122 of the PCM cell 116. The interlayer windows V1-V3 extend through the etch stop layers ESL1, ESL2 and ESL3. The interlayer window V4 extends through the second sidewall spacer 128 and the hard mask 124. The etch stop layers ESL1-ESL3 can be made of, for example, SiC or SiN. The contact CO and the interlayer windows V1-V4 can be made of one or more metals (such as TiN, TaN, copper, aluminum, tungsten, etc., or a combination thereof).

[0139] A memory cell 116 for storing data states is arranged in the interconnect structure 304 between metal layers M4 and M5. For example, the bottom electrode 114 of the memory cell 116 extends from the top surface of the metal layer M4 to the PCE 120, and the intermediate window V4 extends from the top surface of the top electrode 122 through the hard mask 124, the second sidewall spacer 128 and the IMD layer IMD5 to the metal layer M5. The memory cell 116 is connected to the bit line (BL) via the metal layer M5, to the source line (SL) via the metal layer M2, and to the word line (WL) via the gate electrode 316, wherein the word line WL can be formed in the metal layer M3.

[0140] Figures 5 to 14 1 and 2 illustrate cross-sectional views of some embodiments of methods of forming memory devices according to the present disclosure. Figures 5 to 14 The cross-sectional view is illustrated in the reference method, but it should be understood that Figures 5 to 14 The structure shown in is not limited to this method, but can exist independently of this method. Figures 5 to 14Described as a series of actions, it should be understood that these actions are not restrictive, and the order of these actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions illustrated and / or described can be omitted in whole or in part.

[0141] like Figure 5 As shown in the cross-sectional view of , the initial structure includes: a bottom wire 108, the bottom wire 108 is in the IMD layer 110; a dielectric layer 112, the dielectric layer 112 is on the bottom wire 108 and the IMD layer 110; a bottom electrode 114, the bottom electrode 114 is in the dielectric layer 112 covering the bottom wire 108; a phase change material layer 402, the phase change material layer 402 is on the dielectric layer 112 and the bottom electrode 114; a top electrode layer 404, the top electrode layer 404 is on the phase change material layer 402; and a hard mask layer 406, the hard mask layer 406 is on the top electrode layer 404. In some embodiments, the phase change material layer 402 can be, for example, or include a phase change material such as GST.

[0142] The formation of the bottom conductive line 108 includes forming a trench in the IMD layer 110 using a suitable etching technique, depositing one or more metal layers into the trench in the IMD layer 110, and removing excess material of the one or more metal layers outside the trench in the IMD layer 110. The phase change material layer 402, the top electrode layer 404, and the hard mask layer 406 may be formed using a suitable deposition technique (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, etc.).

[0143] like Figure 6 As shown in the cross-sectional view of FIG, an organic mask layer 408 and an overlying photoresist 410 are deposited on the hard mask layer 406. In some embodiments, the photoresist 410 and the organic mask layer 408 are deposited using a spin coating process, a deposition process, or the like. The organic mask layer 408 can be a bottom anti-reflective coating (BARC), an anti-reflective coating (ARC), a bottom photoresist coating, or the like. The photoresist 410 includes a photosensitive material. Using photolithography, the photoresist 410 is patterned to cover portions of the hard mask layer 406 and the top electrode layer 404. After patterning, the photoresist 410 is located directly above the bottom electrode 114, as shown in FIG. Figure 6 In some embodiments, the photoresist 410 is patterned to be wider than the bottom electrode 114 .

[0144] like Figure 7 As shown in the cross-sectional view, according to the photoresist 410 on the organic mask layer ( Figure 6 408), hard mask layer ( Figure 6 406) and the top electrode layer ( Figure 6 An etching process including three steps is performed on the patterned organic mask 408', followed by the patterned hard mask 124, and then the patterned top electrode 122 to form a patterned organic mask 408', followed by the patterned hard mask 124, and then the patterned top electrode 122. The etching process is performed in a processing chamber and a plasma etchant can be used. In some embodiments, the plasma etchant can be formed as a transformer coupled plasma (TCP) by a TCP source. In other embodiments, the plasma etchant can be formed as a capacitively coupled plasma (CCP), an inductively coupled plasma (ICP), etc.

[0145] The first step in the etching process targets the organic mask layer ( Figure 6 408) to form a patterned organic mask 408' based on the photoresist 410. In some embodiments, the first step of the etching process is performed in the processing chamber at a pressure in a range between about 1 mTorr and about 100 mTorr. In some embodiments, the first step of the etching process can use a plasma etchant formed by a TCP source at a power in a range between about 200 Watts and about 800 Watts. In some embodiments, a bias voltage is applied to the wafer chuck, which is used to hold the wafer chuck. Figure 6 In some embodiments, the bias voltage used in the first step of the etching process is in the range of about 100 volts to about 500 volts. In some embodiments, the etching gas used in the first step of the etching process may include the following: oxygen (O2) gas, the flow rate of which is in the range of about 1 standard cubic centimeter / minute to about 20 standard cubic centimeters / minute; chlorine (Cl2) gas, the flow rate of which is in the range of about 5 standard cubic centimeters / minute to about 50 standard cubic centimeters / minute; helium (He) gas, the flow rate of which is in the range of about 100 standard cubic centimeters / minute to about 300 standard cubic centimeters / minute; and / or CH2F2 gas, the flow rate of which is in the range of about 10 standard cubic centimeters / minute to about 50 standard cubic centimeters / minute.

[0146] The second step in the etching process targets the hard mask layer ( Figure 6406) to form a patterned hard mask 124 based on the photoresist 410. In some embodiments, the second step of the etching process is performed at a pressure in a range between about 1 mTorr and about 100 mTorr. In some embodiments, the power of the TCP source is set to a power in a range between about 200 Watts and about 1000 Watts. In some embodiments, the bias voltage is set to a voltage in a range between about 100 Volts and about 700 Volts. In some embodiments, the etching gas used in the second step of the etching process may include the following: SF6, the flow rate of which is in the range between about 10 standard cubic centimeters per minute and about 80 standard cubic centimeters per minute; CF4, the flow rate of which is in the range between about 10 standard cubic centimeters per minute and about 50 standard cubic centimeters per minute; helium, the flow rate of which is in the range between about 100 standard cubic centimeters per minute and about 300 standard cubic centimeters per minute; and / or CH2F2 gas, the flow rate of which is in the range between about 10 standard cubic centimeters per minute and about 100 standard cubic centimeters per minute.

[0147] The third and final step in the etching process targets the top electrode layer ( Figure 6 404) to form a patterned top electrode 122. In some embodiments, the third step of the etching process is performed at a pressure in a range between about 1 mTorr and about 100 mTorr. In some embodiments, the TCP source power is set to a power in a power range between about 200 Watts and about 1000 Watts. In some embodiments, the bias voltage is set to a voltage in a range between about 100 Volts and about 900 Volts. In some embodiments, the etching gas used in the third step of the etching process may include the following: chlorine (Cl2) gas, the flow rate of which is in the range of about 10 standard cubic centimeters per minute to about 200 standard cubic centimeters per minute; CF4, the flow rate of which is in the range of about 10 standard cubic centimeters per minute to about 100 standard cubic centimeters per minute; argon (Ar) gas, the flow rate of which is in the range of about 50 standard cubic centimeters per minute to about 500 standard cubic centimeters per minute; and / or HBr gas, the flow rate of which is in the range of about 10 standard cubic centimeters per minute to about 100 standard cubic centimeters per minute.

[0148] like Figure 8 As shown in the cross-sectional view of Figure 7 410) and patterned organic mask ( Figure 7 408 ′), thereby leaving the patterned top electrode 122 and the patterned hard mask 124 on the patterned top electrode 122. The deposited phase change material layer 402 is wider than the patterned top electrode 122 and the patterned hard mask 124.

[0149] like Fig. 9 As shown in the cross-sectional view, in the deposited phase change material layer ( Figure 8 A plasma etching process P1 is performed on the substrate 402 to form a patterned PCE 120. The plasma etching process P1 is performed in a processing chamber and a plasma etchant may be used. In some embodiments, the plasma etchant may be formed as a transformer coupled plasma (TCP) by a TCP source. In other embodiments, the plasma etchant may be formed as a capacitively coupled plasma (CCP), an inductively coupled plasma (ICP), an electron cyclotron resonance (ECR), etc.

[0150] For example, the patterned PCE 120 may be formed using Fig.16 The exemplary TCP reactor 900 shown is formed. The TCP reactor 900 includes a processing chamber 910 having a plasma-containing region 920. The reactor 900 includes a wafer chuck 930, which is disposed below the plasma-containing region 920. The wafer chuck 930 includes an electrostatic chuck (ESC) for fixing a semiconductor wafer 940, which includes a semiconductor wafer 940 such as Figure 8 The wafer chuck 930 is coupled to a radio frequency (RF) power source 945 to provide a bias voltage to the wafer 940, which helps to direct charged plasma roots or ions toward the wafer 940 during processing. Alternatively, a matching network (not shown) can be selectively coupled between the wafer chuck 930 and the RF power source 945. A plurality of microactuators 950 are coupled below the wafer chuck 930 and are positioned around the periphery of the wafer chuck 930.

[0151] The TCP reactor 900 also includes a power supply 960 located on a top portion of the processing chamber 910. The power supply 960 includes a flat spiral coil 965 coupled to an RF power supply 970. Alternatively, a matching network (not shown) can be coupled between the coil 965 and the RF power supply 970 to match impedance and improve efficiency. The flat spiral coil 965 is separated from the plasma containing region 920 by a dielectric plate 980. The dielectric plate 980 includes a quartz material or other suitable material. The TCP reactor 900 also includes: one or more gas inlet holes 911 to allow process gases to be pumped into the processing chamber 910; and one or more gas outlet holes (not shown) to allow vacuum to be drawn to maintain an operating pressure in the processing chamber 910.

[0152] During operation, semiconductor wafer 940 is secured to electrostatic chuck 930. Wafer 940 includes phase change material layer 402 (eg, Figure 8), the phase change material layer 402 is prepared for plasma processing, such as a high density plasma etching process. Initially, the suction cup 930 is positioned in a plane (e.g., an xy plane) that is parallel to the x-axis 991 and the y-axis 992 and perpendicular to the z-axis 993. The y-axis 992 points directly to the z-axis 993. Fig.16 It should be understood that the x-axis 991, y-axis 992, and z-axis 993 are reference axes and are provided only to aid understanding of the subsequent description. The TCP reactor 900 includes a controller for controlling various process conditions, such as gas flow rate, pressure, chamber temperature, power, and radio frequency, to generate plasma in the plasma-containing region 920. These process conditions may vary depending on the type of plasma process used for a particular application.

[0153] The flat spiral coil 965 is energized by the RF power supply 970 and generates an electric field (not shown). The electric field causes the process gas in the process chamber 910 to dissociate into ions, free radicals, and electrons. The excited electrons are accelerated by the electric field and collide with gas molecules, which causes the gas molecules to be ionized (e.g., free electrons). This process continues and eventually allows the plasma to be independently self-sustaining within the process chamber 910. The wafer 940 is biased via the chuck 930, which is coupled to the RF power supply 945. Therefore, the ions in the plasma are directed toward the wafer 940 at a controlled angle, so that anisotropic etching with a controlled etching profile can be achieved.

[0154] In some embodiments, pressures in the range of about 1 mTorr and about 100 mTorr (e.g., Fig.16 The process is performed under the pressure in the processing chamber 910 Fig. 9 In some embodiments, the TCP source power (eg, Fig.16 The power of the RF power source 970 in the plasma etching process P1 is set to a power within a power range between about 100 watts and about 500 watts. In some embodiments, the bias voltage of the plasma etching process P1 (e.g., Fig.16 The maximum voltage of the RF power source 945 in the embodiment of the present invention is set to a voltage in a range between about 100 V and about 500 V. In some embodiments, the plasma etching process P1 is performed when the temperature of the electrostatic chuck 930 is in a range between about 40 degrees Celsius and about 120 degrees Celsius, when the temperature of the sidewall of the processing chamber 910 is in a range between about 40 degrees Celsius and about 70 degrees Celsius, and / or when the temperature of the top electrode 122 is in a range between about 100 degrees Celsius and about 150 degrees Celsius.

[0155] In some embodiments, the etching gas used in the plasma etching process P1 (eg, via Fig.16The gases pumped into the processing chamber 910 through one or more gas inlet holes 911 shown in FIG. 9 may include the following: chlorine (Cl2) having a flow rate in a range between about 10 SCCM / min and about 100 SCCM / min; argon (Ar) having a flow rate in a range between about 50 SCCM / min and about 500 SCCM / min; HBr having a flow rate in a range between about 10 SCCM / min and about 100 SCCM / min; CH 2F2, the flow rate of CH2F2 is in the range of about 10 standard cubic centimeters per minute and about 50 standard cubic centimeters per minute; SF6, the flow rate of SF6 is in the range of about 5 standard cubic centimeters per minute and about 20 standard cubic centimeters per minute; H2, the flow rate of H2 is in the range of about 2 standard cubic centimeters per minute and about 50 standard cubic centimeters per minute; and / or BCl3, the flow rate of BCl3 is in the range of about 10 standard cubic centimeters per minute and about 100 standard cubic centimeters per minute. It is noted that the gas used in the plasma etching process P1 does not contain ammonia gas (NH3 gas). In other words, the processing chamber (for example, as Fig.16 The chamber 910 shown does not contain ammonium plasma (NH4) generated by the protonation of ammonia during the etching process P1. + ). In this way, unwanted chemical reactions between the ammonium plasma and the chalcogenide material in layer 402 may be prevented.

[0156] like Fig. 9 As shown in the cross-sectional view of FIG. 1 , the PCE 120, the top electrode 122 and the hard mask 124 of some embodiments are shown after the plasma etching process P1 is completed. The PCE 120 has Fig. 9 The PCE 120 has a trapezoidal shape as shown, and has a top surface that is substantially flush with the bottom surface of the top electrode 122. In some embodiments, after the plasma etching process P1, the size of the top surface of the PCE 120 is substantially equal to the size of the bottom surface of the top electrode 12. In some other embodiments, after the plasma etching process P1, the top surface of the PCE 120 is wider than the bottom surface of the top electrode 122. According to the cross-sectional view, as shown in Fig. 9 In the cross-sectional view of , the trapezoidal PCE 120 may have a nonlinear outer sidewall 120s. For example, the absolute value of the slope of the upper portion of the outer sidewall 120s is greater than the absolute value of the slope of the lower portion of the outer sidewall 120s. In other words, the upper portion of the outer sidewall 120s is steeper than the lower portion of the outer sidewall 120s.

[0157] The bottom surface of the PCE 120 intersects the outer sidewall 120s of the PCE 120 at approximately an angle C. In some embodiments, the angle C may be in a range between about 45 degrees and about 85 degrees. The top electrode 122 may have an outer sidewall 122s that intersects the bottom surface of the top electrode 122 at an angle D. The outer sidewall 124s of the hard mask 124 may intersect the bottom surface of the hard mask 124 at an angle E. In some embodiments, the angles C, D, and E are substantially the same. In some other embodiments, the angles D and E may each be less than the angle C. In such embodiments, the outer sidewall 120s of the PCE 120 is steeper than the outer sidewall 122s of the top electrode 122 and the outer sidewall 124s of the hard mask 124.

[0158] like Fig.10 As shown in the cross-sectional view of FIG. 1 , immediately after the plasma etching process P1, a plasma deposition process P2 is performed in-situ to conformally blanket deposit a protective coating 412 on the hard mask 124, the top electrode 122, and the PCE 120. As used herein, the term “in-situ” is used to describe when a wafer (e.g., Fig.16 Wafer 940 in the same processing chamber (eg, Fig.16 910 in the processing chamber 910) is performed on the wafer (e.g., a plasma etching process P1 and a plasma deposition process P2), and wherein, for example, the processing chamber (e.g., Fig.16 The processing chamber 910 in the embodiment of the present invention allows the wafer to remain under vacuum conditions (i.e., without breaking the vacuum). As such, the term "in situ" may also be generally used to refer to such processes in which the wafer being processed is not exposed to the external environment (e.g., in Fig.16 In this way, although the PCE 120 is sensitive to moisture, the protective coating 412 can block the PCE 120 from contact with moisture because, without breaking the vacuum, the PCE 120 can be etched immediately after using, for example, Fig.16 The TCP reactor 900 in FIG. 1 deposits a protective coating 412 in situ on the PCE 120 .

[0159] In some embodiments, the gas used in the plasma deposition process P2 is selected so that the resulting plasma is chemically inert to the PCE 120 (i.e., the chalcogenide material of the PCE 120 is chemically inert to the plasma during the deposition process P2). Therefore, the PCE 120 does not chemically react with the plasma during the plasma deposition process P2, which in turn will reduce the risk of damage caused by unwanted chemical reactions (e.g., voids formed on the outer sidewalls 120s of the PCE 120). In this way, after performing the plasma deposition process P2, the outer sidewalls 120s of the PCE 120 have substantially the same profile as before performing the plasma deposition process P2.

[0160] In some embodiments where the PCE 120 is made of a chalcogenide material (e.g., GST), the gas used in the plasma deposition process P2 does not contain an ammonia (NH 3 ) gas, because the ammonium plasma generated from the ammonia gas reacts with the chalcogenide material, thereby damaging the outer sidewall 120s of the PCE 120 (e.g., generating voids on the outer sidewall 120s of the PCE 120). In other words, the plasma deposition process P2 is performed in an ammonia-free (i.e., ammonium-free) environment to prevent damage to the outer sidewall 120s of the PCE 120. For example, the processing chamber 910 remains ammonia-free during the execution of the plasma deposition process P2. In addition, the gas used in the plasma deposition process P2 also does not contain an oxygen-containing gas (e.g., O 2 ), thereby preventing unwanted oxidation of the outer sidewall 120s of the PCE 120. In other words, the plasma deposition process P2 is performed in an oxygen-free environment.

[0161] In some embodiments, the gas used in the plasma deposition process P2 (e.g., via Fig.16 The gas pumped into the processing chamber 910 through one or more gas inlet holes 911 shown may be a gas mixture of methane (CH4) and argon (Ar) at a flow rate in a range between about 50 standard cubic centimeters per minute and about 500 standard cubic centimeters per minute. The gas mixture does not contain nitrogen-containing gases (e.g., ammonia) and oxygen-containing gases (e.g., oxygen) to prevent unwanted chemical reactions with the PCE 120.

[0162] In some embodiments, pressures in the range of about 1 mTorr and about 100 mTorr (e.g., Fig.16 The plasma deposition process P2 is performed at a pressure in the processing chamber 910 of . In some embodiments, the TCP source power (e.g., Fig.16 The power of the RF power source 970 in the plasma deposition process P2 is set to a power within a power range between about 300 watts and about 1200 watts. In some embodiments, the bias voltage of the plasma deposition process P2 (e.g., Fig.16 The maximum voltage of the RF power source 945 in the embodiment of the present invention is set to a voltage in a range between about 30 V and about 100 V. In some embodiments, the plasma deposition process P2 is performed when the temperature of the electrostatic chuck 930 is in a range between about 40 degrees Celsius and about 120 degrees Celsius, when the temperature of the sidewall of the processing chamber 910 is in a range between about 40 degrees Celsius and about 70 degrees Celsius, and / or when the temperature of the top electrode 122 is in a range between about 100 degrees Celsius and about 150 degrees Celsius.

[0163] As a result of the selected gases and associated conditions of the plasma deposition process P2 described above, the resulting protective coating 412 is a binary hydrocarbon layer (i.e., a compound free of nitrogen and oxygen). For example, the protective coating 412 may be CH x The binary compound, wherein x is between 2 and 4. In some embodiments, the thickness of the protective coating 412 may be in the range of about 10 angstroms to about 20 angstroms. If the thickness of the protective coating 412 is greater than about 20 angstroms, it may suffer from film-to-film adhesion issues (e.g., the protective coating 412 and the subsequently formed sidewall spacer layer 414 (e.g., Fig.11 The sidewall protection of the PCE 120 may be unsatisfactory if the thickness of the protective coating 412 is less than about 10 angstroms.

[0164] like Fig.11 As shown in the cross-sectional view of , a deposition process is performed to form a first sidewall spacer layer 414 on the protective coating 412. In some embodiments, the first sidewall spacer layer 414 can be, for example, or include a material such as silicon nitride (SiN or Si3N4), silicon carbide (SiC), or other suitable dielectric materials. In some embodiments, the first sidewall spacer layer 414 can be a nitrogen-containing layer, such as a silicon nitride layer, deposited using, for example, CVD, ALD, PVD, or other suitable deposition processes. Because the first sidewall spacer layer 414 is a nitrogen-containing layer and the protective coating 412 does not contain nitrogen, the first sidewall spacer layer 414 has a greater nitrogen atomic concentration than the protective coating 412. For example, the protective coating 412 has a nitrogen atomic concentration of zero, and the first sidewall spacer layer 414 has a nitrogen atomic concentration of a non-zero value (i.e., a positive value). It should be noted that the protective coating 412 ideally has a nitrogen atomic concentration of zero, but the final IC product (such as Figure 4 The resulting protective coating 125 in FIG. 1 may have a non-zero nitrogen atomic concentration due to unintentional thermal diffusion in subsequent process steps in the back-end of the line (BEOL). However, in the final IC product, the resulting protective coating 125 may still have a lower nitrogen atomic concentration than the resulting first sidewall spacer 126.

[0165] can be carried out in an oxygen-free environment (e.g., in an environment such as Fig.16 The nitrogen-containing layer 414 is deposited in an oxygen-free chamber such as 910 of the embodiment of the present invention, thereby producing a nitrogen-containing but oxygen-free layer 414. Because the first sidewall spacer layer 414 contains nitride but does not contain oxygen, it can prevent the PCE 120 from undesired oxidation caused by outgassing of oxide materials and / or provide the PCE 120 with a subsequent etching process using a halogen etchant (e.g., fluorine, chlorine, and bromine) (e.g., as Fig.12 More protection in the anisotropic etch shown in .

[0166] In some embodiments where the first sidewall spacer layer 414 is an oxygen-free silicon nitride layer, the first sidewall spacer layer 414 may be formed by a plasma deposition process using a silicon-containing precursor (e.g., silane, disilane, or trisilane or line) and a nitrogen-containing precursor (e.g., ammonia) in the absence of an oxygen-containing precursor (e.g., oxygen). If the silicon nitride layer is formed directly on (i.e., in contact with) the PCE 120 without an intervening protective coating 412, the chalcogenide material of the PCE 120 will be exposed to and react with the ammonium plasma generated by the ammonia gas. Such a chemical reaction may generate voids on the outer sidewalls 120s of the PCE 120. However, because the PCE 120 is completely covered or coated by the protective coating 412 in some embodiments of the present disclosure, the protective coating 142 can block the PCE 120 from contacting the ammonium plasma, which in turn will prevent the formation of voids on the sidewalls 120s of the PCE 120 during the formation of the first sidewall spacer layer 414.

[0167] Furthermore, the CHx binary compound of the protective coating 125 is chemically inert to the plasma generated by the silicon-containing precursor (e.g., silane, disilane, or trisilane or the like) and the nitrogen-containing precursor (e.g., ammonia), so the deposition of the first sidewall spacer layer 414 does not cause a chemical reaction with the protective coating 125, which in turn will prevent damage to the protective coating 125. x Binary compounds can provide higher adhesion to silicon nitride than ternary carbon-hydrogen compounds, so due to the CH x The binary compound may achieve improved adhesion between the first sidewall spacer layer 414 and the protective coating 125. In some embodiments, the deposition of the first sidewall spacer layer 414 reaches a maximum temperature of less than about 250 degrees Celsius, which in turn will reduce the risk of melting, boiling and / or sublimation of the PCE 120.

[0168] like Fig.12 As shown in the cross-sectional view of FIG. 1 , one or more anisotropic etching processes are performed to remove the first sidewall spacer layer ( Fig.11 414) and protective coating ( Fig.11 The first sidewall spacer layer 414 is formed by etching the horizontal portion of the first sidewall spacer layer 412, while leaving the inclined portion (or vertical portion) of the first sidewall spacer layer 414 as the first sidewall spacer 126, and leaving the portion of the protective coating 412 surrounded by the first sidewall spacer 126 as the protective coating 125. In some embodiments, the anisotropic etching process is a plasma etching process. In more detail, the anisotropic etching process is performed by exposing the first sidewall spacer layer 414 to a plasma etchant (e.g., fluorine, chlorine, and / or bromine plasma).

[0169] If the outer sidewall 120s of the PCE 120 already has damage caused by a previous process step (e.g., voids created by plasma deposition of the sidewall spacer layer 414), the plasma etchant (e.g., fluorine, chlorine, and / or bromine plasma) may exacerbate the damage on the outer sidewall 120s of the PCE 120 (e.g., enlarge the voids on the outer sidewall 120s of the PCE 120). However, because the protective coating 412 can prevent the outer sidewall 120s of the PCE 120 from being damaged (e.g., preventing the formation of voids), the outer sidewall 120s of the PCE 120 can still remain substantially intact during the plasma etching process. In addition, because the first sidewall spacer layer 414 does not contain oxygen, it can provide enhanced etch resistance against plasma etchants, and thus improve protection of the protective coating 125 and / or the PCE 120 during the anisotropic etching process.

[0170] like Fig.13 As shown in the cross-sectional view of , a deposition process is performed to form a second sidewall spacer 128 blanket over the hard mask 124, the dielectric layer 112, and the first sidewall spacer 126. In some embodiments, the second sidewall spacer 128 can be, for example, or include a material that does not contain oxygen, such as SiC. Because the second sidewall spacer 128 does not contain oxygen, it can prevent the PCE 120 from undesired oxidation caused by outgassing of the oxide material. The deposition process can be performed, for example, by CVD, PVD, some other suitable deposition process, or any combination of the foregoing. In some embodiments, the deposition process reaches a maximum temperature of less than about 350 degrees Celsius.

[0171] like Fig.14 As shown in the cross-sectional view of , a deposition process is performed to form an IMD layer 130 above the second sidewall spacer 128. In some embodiments, the IMD layer 130 can be, for example, or include an oxide (such as silicon dioxide), an extremely low dielectric constant dielectric, etc. The deposition process to form the IMD layer 130 can be, for example, performed by CVD, PVD, a spin coating process, some other suitable deposition process, or any combination of the foregoing. In some embodiments, the deposition process reaches a maximum temperature of less than about 400 degrees Celsius.

[0172] The IMD layer 130 is an oxygen-containing layer (e.g., an oxide layer or a porous oxide layer) for reducing the dielectric constant of the IMD layer 130 and, in turn, reducing the resistance-capacitance (RC) delay. Because the IMD layer 130 is an oxygen-containing layer and the protective coating 125, the first sidewall spacer 126, and the second sidewall spacer 128 are oxygen-free, the IMD layer 130 has a greater oxygen atomic concentration than the protective coating 125, the first sidewall spacer 126, and the second sidewall spacer 128. For example, the protective coating 125, the first sidewall spacer 126, and the second sidewall spacer 128 may have an oxygen atomic concentration of zero, and the IMD layer 130 has an oxygen atomic concentration of a non-zero value (i.e., a positive value). It should be noted that the protective coating 125, the first sidewall spacer 126, and the second sidewall spacer 128 ideally have an oxygen atomic concentration of zero, but in the final IC product (e.g., Figure 4 The protective coating 125, the first sidewall spacer 126, and the second sidewall spacer 128 in the IMD layer 130 may have a non-zero oxygen atomic concentration due to unintentional thermal diffusion in subsequent process steps in the BEOL. However, in the final IC product, the protective coating 125, the first sidewall spacer 126, and the second sidewall spacer 128 may still have a lower oxygen atomic concentration than the IMD layer 130.

[0173] In some embodiments, oxygen may be outgassed during the formation of the IMD layer 130 and / or in one or more subsequent process steps in the BEOL. If the outgassed oxygen reaches the outer sidewall 120s of the PCE 120, undesired oxidation of the PCE 120 may occur. However, because the outer sidewall 120s of the PCE 120 is separated from the IMD layer 130 by three layers (e.g., layers 125, 126, and 128) that are free of oxygen, rather than by a double layer (e.g., double spacer layers 126 and 128, without coating 125) or a single layer (single spacer layer 126, without coating 125 and spacer layer 128) that is free of oxygen, outgassing from the IMD layer 130 to the outer sidewall 120s of the PCE 120 may be suppressed, which in turn will prevent undesired oxidation of the PCE 120.

[0174] Furthermore, if the chalcogenide material of the PCE 120 outgasses into the ambient environment during the formation of the IMD layer 130 and / or in one or more subsequent process steps in the BEOL, the gas of the chalcogenide material may react with moisture in the ambient environment to generate toxic gases. However, because the outer sidewall 120s of the PCE 120 is separated from the IMD layer 130 by three layers (e.g., layers 125, 126, and 128) rather than by a double layer (e.g., double spacer layers 126 and 128 without the coating layer 125) or a single layer (a single spacer layer 126 without the coating layer 125 and the spacer layer 128), outgassing from the outer sidewall 120s of the PCE 120 to the ambient environment can be suppressed, which in turn will prevent the generation of toxic gases during the formation of the IMD layer 130 and / or in one or more subsequent process steps in the BEOL.

[0175] After forming the IMD layer 130, a conductive interposer 132 is formed in the IMD layer 130 and on the top electrode 122, and an upper conductive line 134 is formed in the IMD layer 130 and on the conductive interposer 132. The conductive interposer 132 and the upper conductive line 134 may be formed, for example, by patterning the IMD layer 130 using a dual damascene process to form vias and trenches having patterns of the conductive interposer 132 and the upper conductive line 134; depositing one or more conductive layers (e.g., metal layers) to fill the vias and trenches and cover the IMD layer 130; and performing planarization (e.g., chemical mechanical planarization) on the one or more conductive layers until reaching the IMD layer 130. The patterning may be performed, for example, by a photolithography / etching process and / or some other suitable patterning process. In some embodiments, if the conductive interposer 132 and the upper conductive line 134 are deposited using the same deposition process as described above, there may be no distinguishable interface between them.

[0176] Fig.15A and Fig. 15B A method M of forming a memory element according to some embodiments is illustrated. Although the method M is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the illustrated order or actions. Therefore, in some embodiments, the actions may be performed in a different order than shown, and / or may be performed simultaneously. In addition, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other unillustrated actions or events may be included.

[0177] At block S11 , a phase change material layer is deposited on the bottom electrode in the dielectric layer.

[0178] At block S12, a top electrode layer is deposited on the phase change material layer.

[0179] At block S13, a hard mask layer is deposited on the top electrode layer. Figure 5 Cross-sectional views of some embodiments corresponding to the actions in blocks S11-S13 are illustrated.

[0180] At block S14 , the top electrode layer and the hard mask layer are patterned to expose a portion of the phase change material layer. Figure 7 A cross-sectional view of some embodiments corresponding to the actions in block S14 is illustrated.

[0181] At block S15 , a plasma etching process is performed on the exposed portion of the phase change material layer to form a PCE that covers the bottom electrode and exposes a portion of the dielectric layer. Fig. 9 A cross-sectional view of some embodiments corresponding to the actions in block S15 is illustrated.

[0182] At block S16 , a protective coating is deposited to cover the stack of the PCE, top electrode, and hard mask using a plasma deposition process performed in-situ with the plasma etching process of block S15 . Fig.10 A cross-sectional view of some embodiments corresponding to the actions in block S16 is illustrated.

[0183] At block S17 , a first sidewall spacer layer is formed on the protective coating layer. Fig.11 A cross-sectional view of some embodiments corresponding to the actions in block S17 is illustrated.

[0184] At block S18 , an anisotropic etching process is performed on the first sidewall spacer layer and the protective coating layer to define the first sidewall spacers and the protective coating layer. Fig.12 A cross-sectional view of some embodiments corresponding to the actions in block S18 is illustrated.

[0185] At block S19 , a second sidewall spacer is formed on the first sidewall spacer. Fig.13 A cross-sectional view of some embodiments corresponding to the actions in block S19 is illustrated.

[0186] At block S20 , an IMD layer is formed on the second sidewall spacer.

[0187] At block S21 , a conductive interposer and a conductive line are formed in the IMD layer and on the top electrode. Fig.14 Cross-sectional views of some embodiments corresponding to the actions in blocks S20 and S21 are illustrated.

[0188] Based on the above discussion, it can be seen that the present disclosure provides the following advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed here, and not all embodiments require particular advantages.

[0189] One advantage is that the protective coating is deposited on the PCE without using a nitrogen-containing precursor. Voids on the outer sidewalls of the PCE are caused by chemical reactions between the nitrogen-containing precursor and the chalcogenide material in the PCE. Therefore, the present disclosure can reduce voids on the outer sidewalls of the PCE.

[0190] Another advantage is that a protective coating is formed on the PCE using a plasma that is chemically inert to the PCE, thereby preventing damage to the outer sidewall of the PCE (eg, forming voids on the outer sidewall of the PCE). Thus, voids on the outer sidewall of the PCE can be reduced.

[0191] Another advantage is that the protective coating can block the outer sidewalls of the PCE from being affected by reactive plasma (e.g., ammonium plasma) during the formation of the nitride-based spacer layer and / or block the outer sidewalls of the PCE from being affected by etchants (e.g., fluorine, chlorine, and / or bromine) during the patterning of the nitride-based spacer layer. Therefore, voids on the outer sidewalls of the PCE can be reduced.

[0192] Another advantage is that the protective coating improves outgassing suppression from the PCE to the surrounding environment, thereby reducing toxic gases caused by chemical reactions between the gases of the chalcogenide material and moisture in the surrounding environment.

[0193] Another advantage is that the protective coating improves outgassing suppression from the IMD layer to the PCE, thereby reducing undesired oxidation of the PCE caused by outgassing of oxide materials in the IMD layer.

[0194] In some embodiments, the present disclosure relates to a method comprising: forming a phase change element on a bottom electrode and forming a top electrode on the phase change element; forming a protective layer around the phase change element; and after forming the protective layer, forming a nitrogen-containing sidewall spacer layer around the protective layer.

[0195] In some embodiments, forming the phase change element includes forming a phase change material layer on the bottom electrode; and patterning the phase change material layer into the phase change element, wherein forming the protection layer is performed in-situ by patterning the phase change material layer.

[0196] In some embodiments, the protective layer is formed using a plasma deposition process.

[0197] In some embodiments, the phase change element does not undergo a chemical reaction with the plasma used in the plasma deposition process.

[0198] In some embodiments, forming the protective layer includes exposing the phase change element to plasma generated from methane and argon.

[0199] In some embodiments, forming the nitrogen-containing sidewall spacer layer includes exposing the protective layer to an ammonium plasma, wherein the protective layer does not undergo a chemical reaction with the ammonium plasma.

[0200] In some embodiments, the nitrogen-containing sidewall spacer layer is formed by a deposition process without using an oxygen-containing gas.

[0201] In some embodiments, the protection layer is formed by a deposition process without using an oxygen-containing gas.

[0202] In some embodiments, the method further includes removing a first portion of the protective layer from above the top electrode, wherein after removing the first portion of the protective layer from above the top electrode, an outer sidewall of the phase change element is covered by a second portion of the protective layer.

[0203] In some embodiments, the step further includes forming a conductive interposer on the top electrode after removing the first portion of the protection layer from above the top electrode.

[0204] In some embodiments, the present disclosure relates to a method comprising: forming a phase change element on a bottom electrode and forming a top electrode on the phase change element; performing a deposition process in a processing chamber to deposit a protective coating on an outer side wall of the phase change element, wherein the processing chamber does not contain ammonium plasma during the deposition process; and forming a first sidewall spacer layer on the protective coating after performing the deposition process.

[0205] In some embodiments, forming the phase change element includes forming a phase change material layer on the bottom electrode; and performing an etching process on the phase change material layer, wherein the etching process is performed in the processing chamber performing the deposition process.

[0206] In some embodiments, the etching process is performed without using monoammonium plasma.

[0207] In some embodiments, the step further includes removing a first portion of the protective coating to expose a dielectric layer surrounding the bottom electrode and exposing a hard mask on the top electrode, wherein a second portion of the protective coating remains on the outer side wall of the phase change element during removal of the first portion of the protective coating.

[0208] In some embodiments, after removing the first portion of the protective coating, a second sidewall spacer is formed on the exposed dielectric layer; and a conductive interposer is formed through the second sidewall spacer and on the top electrode.

[0209] In some embodiments, the present disclosure relates to a PCRAM element, comprising: a memory cell, which is located on an intermetal dielectric (IMD) layer and includes a bottom electrode, a top electrode, and a phase change element located between the top electrode and the bottom electrode; a protective coating, which is on the outer side wall of the phase change element; and a first sidewall spacer, which is on the outer side wall of the protective coating, wherein the first sidewall spacer has a greater nitrogen atomic concentration than the protective coating.

[0210] In some embodiments, the protective layer is nitrogen-free.

[0211] In some embodiments, the protective layer is a carbon-containing film.

[0212] In some embodiments, the protection layer is further located on an outer sidewall of the top electrode.

[0213] In some embodiments, a second sidewall spacer is also included, the second sidewall spacer having a first portion and a second portion, the first portion extending along an outer side wall of the first sidewall spacer, and the second portion extending from a bottom of the first portion along a top surface of the IMD layer in a direction away from the bottom electrode.

[0214] The features of several embodiments have been previously summarized so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a phase change random access memory device, characterized in that: include: forming a phase change element on a bottom electrode and forming a top electrode on the phase change element; forming a protective layer around the phase change element, wherein the protective layer is nitrogen-free and is composed of a binary carbon-hydrogen compound; and After the protection layer is formed around the phase change element, a nitrogen-containing sidewall spacer layer is formed around the protection layer.

2. The method according to claim 1, characterized in that Forming the phase change element includes: forming a phase change material layer on the bottom electrode; and The phase change material layer is patterned into the phase change element, wherein forming the protection layer is performed in-situ by patterning the phase change material layer.

3. The method according to claim 1, characterized in that The protection layer is formed using a plasma deposition process.

4. The method according to claim 3, characterized in that The phase change element does not undergo a chemical reaction with the plasma used in the plasma deposition process.

5. The method according to claim 1, characterized in that Forming the protective layer includes exposing the phase change element to plasma generated from methane and argon.

6. The method according to claim 1, characterized in that Forming the nitrogen-containing sidewall spacer layer includes exposing the protective layer to an ammonium plasma, wherein the protective layer does not chemically react with the ammonium plasma.

7. The method according to claim 1, characterized in that The nitrogen-containing sidewall spacer layer is formed by a deposition process without using an oxygen-containing gas.

8. The method according to claim 1, characterized in that The protective layer is formed by a deposition process without using an oxygen-containing gas.

9. The method according to claim 1, characterized in that Also includes: A first portion of the protective layer is removed from above the top electrode, wherein an outer sidewall of the phase change element is covered by a second portion of the protective layer after the first portion of the protective layer is removed from above the top electrode.

10. The method according to claim 9, characterized in that Also includes: After removing the first portion of the protection layer from above the top electrode, a conductive interposer is formed on the top electrode.

11. The method according to claim 1, characterized in that The interface between the protection layer and the phase change element has a lower portion and an upper portion, and the upper portion is steeper than the lower portion.

12. The method according to claim 1, characterized in that The binary carbon-hydrogen compound has higher adhesion to the nitrogen-containing sidewall spacer layer than the ternary carbon-hydrogen compound.

13. A method for forming a phase change random access memory device, characterized in that: include: forming a phase change material layer on a bottom electrode and forming a top electrode on the phase change material layer; etching the phase change material layer in a plasma chamber to form a phase change element; Performing a deposition process in the plasma chamber to deposit a protective coating on an outer sidewall of the phase change element, wherein the protective coating is composed of a binary carbon-hydrogen compound and the deposition process does not use a nitrogen-containing precursor; as well as After the deposition process is performed, a first sidewall spacer layer is formed on the protective coating layer.

14. The method according to claim 13, characterized in that The etching process is performed without using monoammonium plasma.

15. The method according to claim 13, characterized in that Also includes: A first portion of the protective coating is removed to expose a dielectric layer surrounding the bottom electrode and to expose a hard shield on the top electrode, wherein a second portion of the protective coating remains on the outer sidewall of the phase change element during removal of the first portion of the protective coating.

16. The method according to claim 15, characterized in that Also includes: After removing the first portion of the protective coating, forming a second sidewall spacer on the exposed dielectric layer: and A conductive interposer is formed through the second sidewall spacer and on the top electrode.

17. The method according to claim 13, characterized in that The protective coating is nitrogen-free and is composed of a binary carbon-hydrogen compound CH x Binary compounds where x is between 2 and 4.

18. The method according to claim 13, characterized in that The protective coating and the phase change element form a non-straight interface, and the non-straight interface has more than one slope change.

19. A method for forming a phase change random access memory device, characterized in that: include: forming a stack structure on a bottom electrode, the stack structure comprising a phase change element and a top electrode; forming a carbon-hydrogen compound layer on the stack structure, wherein the carbon-hydrogen compound layer is entirely composed of binary carbon-hydrogen compounds; forming a first sidewall spacer layer on the hydrocarbon layer; and After forming the first sidewall spacer layer, a conductive intermediate window is formed on the top electrode of the stack structure.

20. The method of claim 19, wherein: The carbon-hydrogen compound layer forms a curved interface with the phase change element.

21. A phase change random access memory device, characterized in that: include: A memory cell located on an intermetal dielectric (IMD) layer, the memory cell comprising a bottom electrode, a top electrode and a phase change element located between the top electrode and the bottom electrode; a protective coating on an outer sidewall of the phase change element, the protective coating being composed of a binary carbon-hydrogen compound; and A first sidewall spacer is on an outer sidewall of the protective coating, wherein the first sidewall spacer has a nitrogen atomic concentration greater than that of the protective coating.

22. The phase change random access memory device as claimed in claim 21, characterized in that: The protective coating is also located on an outer sidewall of the top electrode.

23. The phase change random access memory device as claimed in claim 21, characterized in that: Also includes: A second sidewall spacer has a first portion and a second portion, wherein the first portion extends along an outer sidewall of the first sidewall spacer, and the second portion extends from a bottom of the first portion along a top surface of the intermetallic dielectric layer in a direction away from the bottom electrode.

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