Delay phase-locked loop circuit, synchronous clock signal method and semiconductor memory

Abstract

The present invention provides a delay phase-locked loop circuit, a synchronous clock signal method and a semiconductor memory. The delay phase-locked loop circuit includes a delay chain, a first register, a second register, a logic processing unit, a control unit, a copy delay unit and a phase detector; the delay chain is used to delay the input signal; the logic processing unit is used to read the setting code of the first register and the second register to obtain an estimated clock cycle; the control unit is connected to the logic processing unit and the delay chain to set the initial length of the delay chain; the copy delay unit is connected to the delay chain to generate a copy delay signal; the phase detector is connected to the copy delay unit to output a comparison result signal; the control unit is connected to the phase detector to continue to adjust the length of the access delay chain along the initial length. The present invention obtains the estimated clock cycle by reading the setting code of the register, thereby quickly adjusting the length of the delay chain to ensure the reliability and accuracy of the circuit.

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