Esd protection device with deep trench isolation island

Abstract

This application relates to ESD protection devices with deep trench isolation islands and discloses an electronic device (100) comprising a substrate (105) having a second conductivity type, the substrate including a semiconductor surface layer (115) having a buried layer (BL) having a first conductivity type. A first doped region (e.g., collector) (117) and a second doped region (e.g., emitter) (119) both having the first conductivity type are in the semiconductor surface layer, wherein a third doped region (e.g., base) (118) having the second conductivity type is in the second doped region, wherein the first doped region is below the third doped region and extends laterally to the third doped region. At least one row of deep trench (DT) isolation islands (1251-125) are present. 15 Located within the first doped region, each isolation island includes a dielectric pad extending along the trench sidewall from the semiconductor surface layer to the BL, and an associated deeply doped region (125a) extending from the semiconductor surface layer to the BL. The deeply doped regions can be merged to form a merged deeply doped region spanning the DT island.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically, but not exclusively, to ESD protection devices based on vertical bipolar transistors. Background Technology

[0002] For certain devices, such as bipolar complementary metal-oxide-semiconductor (BiCMOS) based integrated circuits (ICs), vertical bipolar electrostatic discharge (ESD) protection devices can be used for ESD protection, especially for some low-voltage MOS devices. For example, to implement an NPN-based ESD protection device, a single deep trench (DT) isolation ring can be placed around the n-collector of the NPN transistor.

[0003] In ESD protection for vertical bipolar-based ESD protection devices, the preferred current path typically passes through a deep, heavily doped region between the collector contact and the buried layer (BL) at the device surface, where the BL extends laterally, including below the base, and where the series resistance of the deeply doped region sets the clamping voltage of the ESD protection device. For example, a deeply heavily doped region is arranged prior to trench filling using angled ion implantation through DT isolation ring holes to form a highly doped and narrow (resistive) region at the edge of the DT isolation ring connected to the BL. Summary of the Invention

[0004] This summary provides a simplified overview of the disclosed concepts, which are further described in specific embodiments, including the provided drawings. This summary is not intended to limit the scope of the claimed subject matter.

[0005] This disclosure includes an electronic device comprising a substrate having a second conductivity type, the substrate including a semiconductor surface layer having a BL having a first conductivity type. A first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type are located in the semiconductor surface layer, wherein a third doped region (e.g., base) has the second conductivity type, and the second doped region is located within the third doped region. The first doped region includes a portion located below and laterally spaced from the second and third doped regions. At least one row of DT isolation islands is located within the first doped region, each DT isolation island including a dielectric pad extending along a trench sidewall from the semiconductor surface layer to the BL, and an associated deeply doped region extending from the semiconductor surface layer to the BL. The corresponding deeply doped regions are merged to form a merged deeply doped region spanning multiple DT isolation islands. While the disclosed examples are expected to provide improvements in various device operating parameters, specific results are not required unless explicitly stated in the specific claims. Attached Figure Description

[0006] Now refer to the accompanying drawings, which are not necessarily drawn to scale, in which:

[0007] Figure 1A The image is a top perspective view of a disclosed ESD protection device according to a disclosed example, the ESD protection device including a vertical NPN transistor having a single row of multiple DT isolation islands between the collector contacts and the base, and having merged deep n-doped in the collector of the NPN transistor, wherein an optional external DT isolation ring is shown.

[0008] Figure 1B The image is a top perspective view of a disclosed ESD protection device based on a published example, which includes a vertical NPN transistor with DT isolation islands between the collector contact and the base, wherein the merged deep n-doped structure shows two rows of DT isolation islands that are staggered and placed in the collector of the NPN transistor, and again shows an optional external DT isolation ring.

[0009] Figure 1C The above is a top perspective view of a disclosed ESD protection device based on a disclosed example, the ESD protection device including a vertical NPN transistor having multiple DT isolation islands between the collector contact and the base and emitter, wherein the DT isolation islands are shown in a single row, and also having merged deep n-doped regions, wherein an optional external DT isolation ring is shown again, wherein the collector contact is in the deep n-doped region.

[0010] Figure 1D The above is a top perspective view of a disclosed ESD protection device according to a disclosed example, the ESD protection device including a vertical NPN transistor having a single row of multiple DT isolation islands between the collector contact and the base, and having merged deep n-doped in the collector of the NPN transistor, wherein an optional external DT isolation ring is shown, wherein the DT isolation islands do not extend from one side of the external DT ring across the width of the device to its opposite side.

[0011] Figure 2A It is the disclosed ESD protection device from Figure 1C The cross-sectional view obtained by the marked cut line shown in the figure shows a single DT isolation island, which has a collector contact with the deep n region only on the side of the DT isolation island opposite to the base and emitter of the NPN transistor.

[0012] Figure 2B From Figure 1C The cross-sectional view obtained by the marked cutting line between the two DT isolation islands is shown in the figure.

[0013] Figure 2C yes Figure 1C Details of the top view.

[0014] Figures 3A-3G The cross-sectional view of the disclosed example illustrates the process of forming an IC with an example method having a disclosed ESD protection device, which includes an NPN transistor having a DT isolation island in the collector and having merged deep n-doped.

[0015] Figure 4 A high-level schematic diagram of an IC with ESD protection according to the disclosed example is shown, incorporating multiple disclosed ESD cells to protect one or more terminals of the IC. These ESD cells include NPN transistors having DT isolation islands and having merged deep n-doped structures.

[0016] Figure 5A The technical computer-aided design (TCAD) simulation of normalized IV characteristics of an ESD protection device including an NPN transistor with a single external DT isolation ring and a publicly disclosed ESD protection device with a single row of DT isolation islands and merged deep n-doped elements within the DT ring is shown.

[0017] Figure 5B The normalized IV data for a 100 ns transmission line pulse (TLP) test is shown, comparing an ESD protection device including an NPN transistor with a single external DT isolation ring with a publicly disclosed ESD protection device having two rows of staggered DT isolation islands and merged deep n-doped transistors. Detailed Implementation

[0018] This disclosure is described with reference to the accompanying drawings, wherein the same reference numerals are used to denote similar or equivalent elements. The illustrated order of actions or events should not be considered limiting, as some actions or events may occur in a different order and / or simultaneously with other actions or events. Furthermore, some of the shown actions or events may not be necessary to implement the method according to this disclosure.

[0019] Similarly, unless further specified, the terms “coupled to” or “coupled with” (etc.) used herein are intended to describe indirect or direct electrical connections. Thus, if a first device is “coupled” to a second device, the connection can be a direct electrical connection where only the parasite exists in the path, or an indirect electrical connection via an intervening element that includes other devices and the connection. For indirect coupling, the intervening element typically does not modify the information of the signal, but may adjust its current level, voltage level, and / or power level.

[0020] This disclosure recognizes that for certain electronic devices, such as ESD protection bipolar transistors, which utilize a vertical current path through a highly doped deep region (e.g., the deep n-region of an NPN device or the deep p-region of a PNP device) at the edge of the DT isolation ring, the resistance of the deep doped region may be too large to provide satisfactory voltage clamping to adequately protect the MOS device due to the high collector series resistance. This disclosure provides various arrangements that increase the total cross-sectional area of ​​the deep n-region or deep p-region for lateral current, which reduces the resistance of the deep doped region and thus its series resistance. This reduction in resistance is expected to enable the disclosed bipolar ESD protection device to provide a satisfactory clamping voltage (typically a low clamping voltage) over a wide range of operating conditions.

[0021] Exposed ESD protection devices with DT isolation islands and merged deeply doped regions can be implemented as standalone devices or can be part of an IC, such as a BiCMOS IC chip, which typically has multiple ESD protection devices to protect multiple nodes on the IC, as described below. Figure 4 As shown. Although NPN-based ESD protection devices are generally described herein, it will be apparent to those skilled in the art that the principles described can be applied to form PNP-based ESD protection devices, for example, by replacing n-doped regions with p-doped regions and vice versa.

[0022] Figure 1A This is a top perspective view of a disclosed ESD protection device 100, which has DT isolation islands 1251 to 125 in a collector (C) 117 having a first doping type (more generally referred to as a first doped region). 15 The collector 117 has an associated collector contact 117a. The base (B) 118 has a second dopant type (more generally referred to as a third doped region), and the emitter (E) 119 has a first dopant type (more generally referred to as a second doped region). The collector 117 extends from the collector contact 117a to the bottom of the base 118 from the n-type buried layer (NBL) 110 (see description below). Figure 2A Extending horizontally above. DT quarantine island 1251 to 125 15 This can be collectively referred to as DT Island 125. DT Island 125 can also be referred to as a dielectric structure, which may have an optional conductive core (e.g., a doped polysilicon core with the same doping type as the substrate) to enable electrical connection to the substrate 105.

[0023] DT isolation islands 1251 to 125 are shown. 15Between the collector contact 117a and the base 118 in which the emitter 119 is formed, DT islands 125 are arranged in a single row extending from the left to the right of the optional outer DT isolation ring 120 shown. The DT islands 125 are located within a merged deep n-region 125a. An n-type region, such as a shallow n-well (SNW) 240 (see description below), is also considered. Figure 2A It can be located on the surface of the merged deep n-region 125a and can extend between the DT island 125 and the outer DT ring 120, including on the surface of the collector contact 117a on the side opposite to the base 118 and the emitter 119. Figure 1A (Top of the device). NBL110, deep n-region 125a, and SNW 240 can operate together as the collector 117 of ESD protection device 100. NBL110 can be formed by one or more n-type implantations, possibly involving the formation of multiple epitaxial (epi) layers to provide a desired dopant distribution, as understood by those skilled in the art.

[0024] Collector contact 117a forms an electrical contact with BL 110. (The following description...) Figure 1A and Figure 1B The arrangement shown places the collector contact 117a outside the merged deep n-region 125a. This arrangement is made possible by n-type doping, such as SNW 240 extending between the merged deep n-region 125a and the collector contact 117a, where all these regions have the same doping type, described herein as n-type (the same type as the collector 117). Alternatively, to provide a lower collector series resistance, the collector contact 117a can be placed within the merged deep n-region 125a between the DT islands, as described below. Figure 1C , Figure 2A , Figure 2B and Figure 2C As shown.

[0025] Following deep n-implantation (for NPN transistors) and diffusion processes, the merged deep n-region 125a shown is formed. Multiple DT isolation islands 1251 to 125... 15 The DT islands have a sufficiently small spacing to allow adjacent deep n-diffusion regions to form a single merged deep n-region 125a, as shown, to provide merged / continuous walls for the n-type material (for NPN transistors). Although the row of DT islands 125 is shown as extending the width of the ESD protection device 100, there is no such limitation for the disclosed ESD protection device (see description below). Figure 1D Furthermore, although the DT quarantine island is in Figure 1A They are shown as ellipses, but they can also be squares or circles, which can minimize the stress on the semiconductor surface layer shown as p-epitaxial layer 115.

[0026] In some examples, at least one semiconductor surface layer exists on substrate 105, shown as a p-epitaxial layer 115 on substrate 105. However, in some examples, the p-epitaxial layer 115 may be omitted, such that the semiconductor surface layer is a surface region of substrate 105. Substrate 105 and / or p-epitaxial layer 115 may comprise silicon, silicon germanium, or other semiconductor materials. Substrate 105 may comprise p-doped silicon with a doping level from about 1 × 10⁻⁶. 16 Up to approximately 1×10 19 cm -3 Within the range.

[0027] External DT isolation ring 120 and DT isolation islands 1251 to 125 15 This includes dielectric sidewalls (e.g., silicon oxide) and can be completely filled with the dielectric, or a dielectric pad can be made and filled with another material, such as doped polysilicon, which can provide electrical contact with the substrate 105 or the p-epitaxial layer 115 below the BL 110. In the case of the p-epitaxial layer 115, the doped polysilicon will typically also be p-type.

[0028] Figure 1B The disclosed ESD protection device 150, based on a published example, has DT isolation islands in the collector 117a between the collector 117a and the base 118. The merged deep n-region 125a has two rows of DT isolation islands, shown as R1 and R2, staggered relative to each other, and also includes an optional external DT isolation ring 120. The staggered DT configuration is believed to increase the cross-sectional area of ​​the deeply doped regions and also provides some ballast effect (e.g., additional resistance between the collector contact 117a and the emitter 119), which can improve current conduction of the bipolar device under fast recovery (snapback) conditions.

[0029] Figure 1C This is a top perspective view of the disclosed ESD protection device 180, which includes a vertical NPN transistor having multiple DT isolation islands 1251 to 125 located within DT island 125. 15 In the example shown, DT island 125 is located between collector contact 117a and base 118. In this arrangement, the current flowing between collector contact 117a and emitter 119 is directed to flow directly through the merged deep n-region 125a between DT islands 125 to BL. In some examples, this current direction can provide beneficial performance.

[0030] Figure 1DThis is a top perspective view of the disclosed ESD protection device 190, which includes a vertical NPN transistor having a plurality of DT isolation islands 1251 to 1259 arranged in a single row between a collector contact 117a and a base 118. The collector 117 of the NPN transistor has merged deep n-doped regions, again showing an optional external DT isolation ring 120. The DT isolation islands 1251 to 1259 are shown as optionally not extending completely between opposite sides of the external DT ring 120, such that a portion of the collector 117 lies between the DT islands 125a and the external DT ring 120. In such an example, the merged deep n-region 125a can still increase the resistance between the collector contact 117a and the emitter 119, but does not necessarily have to completely span the distance between the opposing external DT rings 120 as is required instead of using dielectric isolation.

[0031] Figure 2A yes Figure 1C A cross-sectional view of the ESD protection device 180 shown, taken from the marked cut lines 2A-2A, which includes Figures 1A-1D SNW 240 is not explicitly shown. An ESD protection device 180 is shown, with a single DT isolation island, shown as 1258, located between contacts 232 of the collector contact 117a via a pre-metal dielectric (PMD) layer 242, such as a PMD containing silicon oxide. Other contacts shown include the emitter contact 235 of the n+ contact 119a in the n-well 119b at the surface of the emitter 119 via the PMD layer 242, and the base contact 234 of the p+ base contact 118a in the p-well 118b at the surface of the base 118 via the PMD layer 242.

[0032] Although SNW 240 is shown within the merged deep n-region 125a, SNW 240 may optionally extend beyond the periphery of the merged deep n-region 125a, for example, toward the outer DT ring 120, such as

[0033] Figure 1A In this example, collector contact 117a is located between DT island 125 and outer DT ring 120. SNW 240 provides a conductive n-doped path for current from collector contact 117a to the merged deep n-region 125a. SNW 240 can be formed using mask levels used in MOSFET or BiCMOS processes, thus no additional mask levels are required. The lateral extent of collector 117 away from base 118 can be considered to be primarily determined by the lateral extent of the merged deep n-region 125a and the lateral extent of SNW 240 (if it extends beyond the merged deep n-region 125a).

[0034] Collector contact 117a is shown optionally situated above the SNW 240 within the merged deep n-region 125a. In some other examples, if the correct type of doping is used (for NPN, it is n-type, for example, the region between DT island 125 and collector contact 117a is also N-type), instances of collector contact 117a may be situated above a portion of the semiconductor surface, such as having SNW 240, and thus not situated above the merged deep n-region 125a. As discussed further below, instances of collector contact 117a are not included in the portion of collector 117 situated between DT island 125 and base 118 and emitter 119. NBL 110 is shown situated within p-epitaxial layer 115, which can be formed conventionally. NBL 110 provides a path for the lateral flow of current between collector contact 117a and emitter 119, and although not within... Figure 2A As shown in (and described below) Figure 2B and 3G (not shown in the image), but the NBL 110 also includes a portion that extends upward to the bottom of the base 118.

[0035] There are also contacts 233 extending through the PMD layer 242 to the DT isolation island 1258, where the DT isolation island 1258 has a pad oxide 261. Metal 1 (M1) is shown in contact with the corresponding contacts. Optionally, one or more additional first interlayer dielectric (ILD) layers and interconnect layers may be formed on M1 as needed to support interconnections with other devices on the substrate 105. Shallow trench isolation (STI) 138 is shown on the surface of the p-epitaxial layer 115, which may also be a localized oxidation (LOCOS) field oxide of silicon.

[0036] exist Figure 2A The reference line 250 is shown, which coincides with the surface of the DT island 125 on the side closest to the emitter 119. The portion of the merged deep n-region 125a located between the reference line 250 and the emitter 119 is referred to herein as the “front” portion of the merged deep n-region 125a, while the portion of the merged deep n-region 125a located on the opposite side of the device 180 is referred to herein as the “rear” portion of the merged deep n-region 125a. Figure 2A As shown, in this example, all collector contacts 117a are located at the rear of the merged deep n-region 125a.

[0037] Figure 2B It is between two DT isolation islands Figure 1CAnother cross-sectional view of device 180 taken at the corresponding cut line shown. At this location, the merged deep n-region 125a is continuous in the plane of substrate 105 between the vertical boundaries of the merged deep n-region 125a. Therefore, during device operation, current from collector contact 117a to the collector of emitter 119 can flow primarily through the rear portion of the merged deep n-region 125a through the merged deep n-region 125a, and to a lesser extent through the front portion of the merged deep n-region 125a between reference line 250 and emitter 119. It will be understood that the presence of DT island 125 reduces the cross-sectional area of ​​the merged deep n-region 125a available for lateral / horizontal conduction to the front portion of the merged deep n-region 125a, effectively increasing the resistance of this conduction path.

[0038] Therefore, compared to the deep n-regions 125a that are contacted and merged on both sides of the baseline 250, the deep n-regions 125a that are contacted and merged only on the rear of the collector 117 result in a path with slightly greater resistance. The increased resistance can help improve the current-carrying capacity of the ESD protection device in at least two ways. One approach is to create negative feedback (by increasing the resistance) that can counteract feedback (fast recovery) and improve the stability of the ESD device performance by avoiding filamentation, thus increasing reliability. The additional resistance can also improve device performance by directing a larger portion of the current vertically, thereby increasing the cross-section of the conductive path as the current is pushed vertically towards NBL 110.

[0039] Figure 2C This corresponds to the disclosed ESD protection device 180. Figure 1C A detailed top view of the cross-section. Several collector contacts 117a are shown connecting the collector terminal 232 to the merged deep n-region 125a. The collector contacts 117a are shown directly over the merged deep n-region 125a. However, as mentioned above, in some other arrangements, one or more collector contacts 117a may be located on the side of the DT island opposite to the base 118 and emitter 119, above the n-type region connected to the NBL, such as by extending the SNW 240 at the surface beyond the merged deep n-region 125a between the DT island 125 and the DT isolation ring 120. The reference line 250 is again shown coinciding with the surface of the DT island 125 closest to the emitter 119. In various examples and as... Figure 2C As shown, the area between the baseline 250 and the emitter 119 (the front part of the merged deep n-region 125a) does not include the collector contact with the merged deep n-region 125a. Figure 2CThe diagram is shown as "Collector contacts not included," while "Collector contacts allowed" is shown for the rear portion of the merged deep n-region 125a. Optional contacts 233 for the p-doped polysilicon core 260 with the DT isolation island 1258 are also shown (via PMD). In some examples, these optional contacts can be used to connect the substrate 105 to a known potential during operation, such as ground.

[0040] Figures 3A-3G This is a cross-sectional view of a process for forming an example IC with a disclosed ESD protection device, based on a disclosed example, illustrating certain processing steps of the process. The ESD protection device has DT isolation islands in the collector with merged deep n-region (for NPN) or deep p-region (for PNP) doping. Without implying limitation, according to Figure 2A The method is described using the structural features of the device 180 shown, but with an example of two rows of staggered DT islands 125. First, refer to... Figure 3A Before forming DT vias 311 and 312, a first epitaxial layer can be grown on the substrate 105. For example, the first epitaxial layer can be about 17 μm thick and have a surface area of ​​about 1 × 10⁻⁶. 15 cm -3 A p-type doped p-epitaxial layer is formed. Then, n-type implantation can be performed to form NBL 110. A second epitaxial layer, such as approximately 7 μm thick, with approximately 1 × 10⁻⁶ ppm, can then be formed. 15 cm -3 The p-type doping concentration is then adjusted. Another p-epitaxial layer, such as approximately 6.5 μm thick, can then be grown with a doping concentration of approximately 1 x 10⁻⁶. 15 cm -3 The p-type doping concentration. The combined epitaxial layer in Figure 3A This is collectively referred to as epitaxial layer 115.

[0041] Then, DT islands 125 can be formed in a first doped region (e.g., an n-collector) doped with the first doping type, or in a region that will later be doped into the first doped region (e.g., an n-collector). Holes 311, 312 for the DT islands 125 can be formed using mask DT etching, such as reactive ion etching (RIE), which are typically at least 5 μm deep, such as 10 μm to 15 μm deep, reaching at least NBL 110. Figure 3AThe diagram shows a device after a DT etching process, with DT vias 311 and 312 spaced apart by the distance d shown. The spacing d should be small enough that dopants from subsequent deep n-implantations merge from adjacent DT islands 125 to form merged deep n-regions. This spacing d depends on the width of the DT islands and the extent to which dopants diffuse outward from angled deep n-implants or other deep implantations. In some examples, spacing values ​​between approximately 0.8 μm and approximately 2.5 μm are generally acceptable. As used throughout this document, “approximately” means ±20%. Angled deep n- or deep p-implantations through vias 311 and 312, while still containing the DT mask (not shown), can have a thickness of approximately 13 μm.

[0042] Figure 3B An angled deep n-implantation 315 is shown, which can be performed at the same mask level as for deep trench masks. This implantation places dopant into the semiconductor sidewalls of DT vias 311, 312. The implantation angle depends on the width and depth of the DT. However, an angle range such as 10 to 16 degrees (relative to the normal to the semiconductor surface) is generally considered suitable for angled implantation. The deep n-implantation dose can include approximately 5 × 10⁻⁶. 13 cm -2 Approximately 5×10 14 cm -2 The phosphorus implantation dose is within the range of approximately 150 keV to approximately 250 keV. A second mask DT etching can then be performed to extend the holes 311, 312 deeper into the substrate 105. Figure 3C The structure in the process after the second DT etching is shown, which also shows the merging of deep n regions to form merged deep n regions 125a, which can be merged during implantation under first activation, or by subsequent activation / diffusion annealing steps in the process flow.

[0043] Figure 3DThe device is shown after an oxide pad 261 is formed on the sidewalls of vias 311, 312 and a polysilicon core 260 is formed. The oxide pad 261 can be formed by thermal oxidation of the sidewalls of vias 311, 312, and the oxide pad 261 can have a thickness in the range of about 0.2 μm and about 0.3 μm. In some examples, the bottom of the pad oxide 261 is removed, for example, to allow the polysilicon core 260 to contact the substrate 105 through the bottom of vias 311, 312. When the substrate is p-type, in-situ p+ polysilicon deposition can provide doped polysilicon without an implantation step to allow the deposited polysilicon filler material to electrically connect the core of the DT island 125 to the substrate 105. In other examples, such as when the DT structure elsewhere on the device can be used to form an isolation capacitor, the bottom of the pad oxide 261 is not removed. In any case, polysilicon patterning is then performed, such as by removing the polysilicon overburden using chemical mechanical polishing (CMP).

[0044] In some examples, conventional BiCMOS devices can be formed at other locations above substrate 105. Some of these processes are well known and are briefly described here. P-type and n-type well regions (e.g., SNW) can be implanted, followed by the formation of an STI structure and possibly additional well regions. A gate oxide layer can be formed (for low-voltage and high-voltage MOS devices), and a polysilicon gate and gate sidewalls can be formed on top of the gate oxide layer. Lightly doped drain (LDD) regions can be formed near the gate using spacers, and n+ source and p+ drain implants can be formed to provide ohmic contacts to the various doped regions.

[0045] Figure 3E The diagram shows a process structure that can be used to form a BiCMOS device after a p-well formation step, for example, a p-base shown as base (B) 118 is formed by boron ion implantation, and an SNW 204 is typically formed at the surface of a merged deep n-region 125a by n-type implantation. Figure 3FThis diagram illustrates a process structure following the n-well formation step in forming a BiCMOS device, specifically source and drain n-type ion implantation, which is a mask implantation forming an n-emitter (E 119) within the base 118. A collector contact 117a, as shown in SNW 240, is formed on the surface of the merged deep n-region 125a, on the rear portion of the merged deep n-region 125a. As previously mentioned, the front portion of the merged deep n-region 125a does not include the collector contact 117a. As a result, during device operation, a portion of the current flowing between the collector contact 117a and the emitter 119 is directed vertically DC through the merged deep n-region 125a between the DT islands, downwards to BL 110, and then laterally in NBL 110 to below the base 118. SNW 240 can be formed during n-well implantation in a BiCMOS device process.

[0046] The process can continue with either conventional or unconventional interconnect layer formation. Such processing may include, for example, forming a PMD layer and contacts within the PMD layer (e.g., see...). Figure 2A The contacts 232, 233, 234, and 235 extend through the PMD layer 242. For example, the contacts are formed by forming tungsten plugs, and a metal stack comprising, for example, two or more metal layers can subsequently be formed. Adjacent metal layers may be separated by an ILD having through-holes between the metal layers (e.g., tungsten or copper).

[0047] Figure 3G The device is shown in the process following the formation of PMD 242. The illustration includes contacts 232 with collector contact 117a, contacts 233 with polysilicon core 260, contacts 234 with base 118, and contacts 235 with emitter 119 in the merged deep n-region 125a. Corresponding MET1 lines for 232a, 233a, 234a, and 235a are shown connected to each of these respective contacts.

[0048] Figure 4 A high-level description of an ESD-protected IC 400 according to the disclosed example is shown, wherein multiple disclosed ESD units are incorporated to protect one or more terminals of the IC, the ESD unit being an ESD protection device 100 having a DT island and a merged deep n-region. Figure 4 The “T” indicated on the top of the corresponding ESD protection device 100 indicates an input in response to an ESD event provided by a suitable trigger circuit.

[0049] IC 400 includes functional circuitry 424, which is an integrated circuit that implements and performs the desired functions of IC 400, such as a digital IC (e.g., a digital signal processor) or an analog IC (e.g., an amplifier or power converter). The capabilities of the functional circuitry provided by IC 400 can vary, for example, ranging from simple devices to complex devices. The specific functions included in functional circuitry 424 do not imply any limitation on the disclosed examples.

[0050] IC 400 also includes multiple external terminals through which functional circuitry 424 performs its functions. Figure 4 Some of these external terminals are shown in the diagram. It should be understood that the number of terminals and their functions can vary considerably. Figure 4 In the example of IC 400 shown, the two terminals are used as common input and output terminals (I / O), through which functional circuit 424 can receive input signals and generate outputs, as is known in the art. Figure 4 The diagram also shows a dedicated input terminal IN for the IC, and a dedicated output terminal OUT. Each of terminals IN and OUT is also connected to functional circuitry 424. In this example, the power supply terminal V... DD It receives a positive power supply voltage, while the ground terminal V SS It is provided to receive a reference voltage, such as system ground. Although not shown, the ground shown as being connected to ESD protection device 100 is coupled to V. SS Such as resistive coupling or shorting together.

[0051] IC 400 includes instances of exposed ESD protection devices 100 connected to each of its terminals. Each ESD protection device 100 is connected in parallel with functional circuitry 424 to its corresponding terminal. The ESD protection device 100 is also connected in parallel with functional circuitry 424 to power supply terminal V. DD and reference voltage terminal V SS However, in some applications, some of the protected pins of IC 400 can be self-protected, such as diode-protected power supply pins. Pins can also be protected against different levels of ESD shocks (Human Body Model (HBM), Charged Device Model (CDM), IEC standards (e.g., IEC 61000-4-2), etc.). The functional circuit 424 in IC 400 can be a BiCMOS circuit with bipolar transistors and MOSFETs.

[0052] Example

[0053] The disclosed embodiments are further illustrated by the following specific examples, which should not be construed as limiting the scope or content of this disclosure in any way.

[0054] Figure 5A Normalized TCAD analog IV characteristics (shown as reference) of an ESD protection device with a single external DT ring are shown, and normalized TCAD analog IV characteristics (shown as 'DT islands') of a disclosed ESD protection device having a single row of deeply n-doped DT islands with merged arrangement inside the DT ring, consistent with some of the described examples. Compared to ESD protection devices lacking this row of DT islands, the disclosed ESD protection device exhibits a clamping voltage approximately 5V lower, thus providing fast recovery protection at a lower voltage than the reference device.

[0055] Figure 5B Normalized measurement IV data from a 100ns TLP test are shown, comparing an ESD protection device with an external DT ring but lacking a row of DT islands in the collector to a disclosed ESD protection device with two rows of staggered DT islands in the collector and merged deep n-doped material. The horizontal shift from DT ring-only characteristics (triangles and x-symbols) to DT island characteristics (squares and circles) indicates a reduction in clamping voltage due to the presence of DT islands. It can be seen that the clamping voltage of the disclosed ESD protection device is reduced by 7V to 10V.

[0056] Arranging DT islands in a staggered configuration across multiple rows improves manufacturability and eliminates the need for external DT rings. Furthermore, outward diffusion of DT dopants is significantly less compared to a deep n-arrangement alone. Staggered DT islands improve manufacturability better than straight parallel rows because of reduced stress on the semiconductor surface. If the DT islands are placed close enough that the deep n-regions merge together, isolation is still maintained, providing isolation and a low-resistance collector path, thus eliminating the need for conventional external DT rings. Eliminating external DT rings can facilitate lower DT density, which improves manufacturability by further reducing stress on the semiconductor surface and thus reducing the likelihood of cracking and defects.

[0057] The disclosed examples can be used to form semiconductor dies, which can be integrated into various assembly processes to form a wide variety of devices and related products. Semiconductor dies can include various components and / or layers thereon, including barrier layers, dielectric layers, device structures, active components, and passive components (including source regions, drain regions, bit lines, bases, emitters, collectors, wires, conductive vias, etc.). Furthermore, semiconductor dies can be formed using various processes including bipolar insulated gate bipolar transistors (IGBTs), CMOS, BiCMOS, and MEMS.

[0058] Those skilled in the art will understand that many other examples are possible within the scope of the claimed invention, and that the described examples may be further added to, deleted from, replaced and modified without departing from the scope of this disclosure.

Claims

1. A method for manufacturing an electronic device, comprising: A first doped region and a second doped region, both having a first conductivity type, are formed in the semiconductor surface layer of the substrate, and a buried layer, BL, having the first conductivity type is formed, wherein the substrate has a second conductivity type; A third doped region having the second conductivity type is formed between the first doped region and the second doped region in the semiconductor surface layer; and A plurality of dielectric structures are formed in the first doped region, each dielectric structure extending from the semiconductor surface layer to at least the BL, wherein the current path from the second doped region to the contact with the first doped region is between the plurality of dielectric structures.

2. The method of claim 1, further comprising forming a merged deep-doped region of the first conductivity type, the merged deep-doped region extending from the semiconductor surface layer to the BL and spanning the plurality of dielectric structures.

3. The method of claim 1, wherein each of the plurality of dielectric structures includes a conductive core electrically connected to the substrate.

4. The method of claim 1, wherein the plurality of dielectric structures are arranged along a line perpendicular to the direction from the second doped region to the contact with the first doped region.

5. The method of claim 1, wherein the first doped region and the second doped region are configured to operate as the collector and emitter of a bipolar transistor, respectively, and the third doped region is configured to operate as the base of the bipolar transistor.

6. The method of claim 1, wherein the second doped region and the third doped region extend into the substrate at corresponding second and third depths, and wherein the first doped region extends into the substrate at a first depth greater than the second and third depths.

7. The method of claim 1, further comprising forming a contact with the first doped region, and not including any contact with the first doped region between the plurality of dielectric structures and the third doped region.

8. A method for manufacturing an electronic device, comprising: A first doped region and a second doped region, both having a first conductivity type, are formed in the semiconductor surface layer of a substrate having a second conductivity type, and a buried layer, namely BL, having the first conductivity type is formed. Forming a contact with the first doped region; A third doped region having the second conductivity type is formed between the first doped region and the second doped region; A row of deep trench openings, namely DT openings, is formed in the semiconductor surface layer within the first doped region, wherein the DT openings reach the BL; Dopant of the first conductivity type is implanted through the DT opening, thereby forming a deeply doped region extending from the semiconductor surface layer to the BL for each of the DT openings, and The DT opening is filled to form a plurality of DT isolation islands, each DT isolation island including at least a dielectric pad; The deeply doped regions are merged into a merged deeply doped region spanning the plurality of DT isolation islands, and the current path from the contact to the second doped region is between the DT isolation islands.

9. The method of claim 8, further comprising forming an external DT isolation ring, wherein the plurality of DT isolation islands extend from one side of the DT isolation ring to the opposite side of the DT isolation ring.

10. The method of claim 8, further comprising forming a shallow well having the first conductivity type within the merged deeply doped region.

11. The method of claim 8, wherein the row of DT openings is a first row of DT openings, and further comprising forming a second row of DT openings, wherein the first row and the second row are staggered relative to each other.

12. The method of claim 8, wherein the first doped region and the second doped region and the BL are configured to operate as a protection device including a vertical bipolar transistor, further comprising forming a contact including at least one contact with the first doped region, the at least one contact contacting the merged deep doped region or the side of the merged deep doped region opposite to the third doped region and the second doped region.

13. An electronic device, comprising: A semiconductor surface layer of a substrate, the substrate having a second conductivity type, and the semiconductor surface layer including a buried layer, namely BL, having a first conductivity type; A second doped region having the first conductivity type, which is within a region surrounded by a third doped region having the second conductivity type, and a first doped region having the first conductivity type, which is spaced apart from the third doped region and extends from the surface of the substrate to the BL; A contact region that is located within the first doped region and has the first conductivity type; At least one row of deep trench isolation islands, or DT islands, within the first doped region, each DT island includes a dielectric pad extending along the trench sidewall from the semiconductor surface layer to the BL, and The merged deeply doped regions, for each of the DT islands, include a deeply doped region extending from the semiconductor surface layer to the BL. The current path from the second doped region to the contact region is between the DT islands.

14. The electronic device of claim 13, wherein the at least one row comprises a first row of DT islands and a second row of DT islands, the DT islands of the first row being offset relative to the DT islands of the second row.

15. The electronic device of claim 13, wherein each of the DT islands comprises a polysilicon filler providing an electrical connection to the substrate below the BL, and wherein the dielectric pad is located between the polysilicon filler and the substrate.

16. The electronic device of claim 13, wherein the first doped region is configured to operate as the collector of a vertical bipolar transistor, the second doped region is configured to operate as the emitter of a vertical bipolar transistor, and the third doped region is configured to operate as the base of a vertical bipolar transistor; and further comprising a contact, the contact including at least one contact with the collector, the at least one contact contacting the merged deeply doped region on the side of the merged deeply doped region opposite to the base and the emitter.

17. The electronic device of claim 16, wherein the contact of the collector contacts the merged deep-doped region such that current between the collector and the emitter is directed through the merged deep-doped region between the DT islands to the BL.

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