A display panel and a display panel manufacturing method

Abstract

The embodiment of the present application provides a display panel and a display panel manufacturing method, wherein the display panel has a pixel area and a binding area arranged adjacent to each other. The display panel includes: a pixel electrode layer, the pixel electrode layer is at least partially arranged in the binding area, and the pixel electrode layer includes: a first transparent conductive film layer, a metal layer, a second transparent conductive film layer and a third transparent conductive film layer. The first transparent conductive film layer includes a first surface and a second surface arranged opposite to each other; the metal layer is arranged on the first surface; the second transparent conductive film layer is arranged on a side of the metal layer away from the first surface; the third transparent conductive film layer covers a side of the second transparent conductive film layer away from the metal layer and wraps the edges of the first transparent conductive film layer, the metal layer and the second transparent conductive film layer. The display panel provided in the embodiment of the present application is wrapped by adding a third transparent conductive film layer to protect the metal layer from oxidation.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display panel manufacturing method. Background Art

[0002] In top-emitting organic light-emitting diode (OLED) panels, the anode is usually made of metal, which is easily oxidized after long-term exposure. Usually, the metal layer needs to be removed from the PAD in the peripheral bonding area, or the metal layer cannot be exposed to the outside. Summary of the invention

[0003] The embodiments of the present application provide a display panel and a display panel manufacturing method, which can solve the problem that the metal layer in the binding area is exposed and easily oxidized.

[0004] The present application provides a display panel, comprising:

[0005] The display panel has a pixel area and a binding area, and the pixel area and the binding area are arranged adjacent to each other; the display panel includes:

[0006] A pixel electrode layer, wherein the pixel electrode layer is at least partially disposed in the binding area, and the pixel electrode layer comprises:

[0007] A first transparent conductive film layer, wherein the first transparent conductive film layer comprises a first surface and a second surface which are arranged opposite to each other;

[0008] a metal layer, the metal layer being disposed on the first surface;

[0009] a second transparent conductive film layer, wherein the second transparent conductive film layer is disposed on a side of the metal layer away from the first surface;

[0010] A third transparent conductive film layer covers a side of the second transparent conductive film layer away from the metal layer and wraps the first transparent conductive film layer, the metal layer and edges of the second transparent conductive film layer.

[0011] In some embodiments, the display panel further includes an interlayer insulating layer, a source-drain electrode layer, a passivation layer, a planarization layer, and a pixel definition layer; the planarization layer is arranged on a side of the pixel electrode layer close to the first transparent conductive film layer; the passivation layer is arranged on a side of the planarization layer away from the pixel electrode layer; the source-drain electrode layer is arranged on a side of the passivation layer away from the planarization layer; the interlayer insulating layer is arranged on a side of the source-drain electrode layer away from the passivation layer and the source-drain electrode layer partially covers the interlayer insulating layer, and the passivation layer covers the source-drain electrode layer and the interlayer insulating layer; the pixel definition layer is arranged on a side of the pixel electrode layer away from the planarization layer and covers the planarization layer;

[0012] The passivation layer and the planarization layer in the binding area are provided with a first contact hole; the first contact hole extends from a surface of the planarization layer away from the passivation layer to a surface of the source and drain layer away from the interlayer insulating layer; the pixel electrode layer is connected to the source and drain layer through the first contact hole.

[0013] In some embodiments, the passivation layer and the planarization layer of the pixel area are provided with a second contact hole, and the second contact hole extends from the side surface of the planarization layer away from the passivation layer to the side surface of the source and drain layer away from the interlayer insulating layer; the pixel electrode layer is connected to the source and drain layer through the second contact hole.

[0014] In some embodiments, the pixel definition layer in the binding area is provided with a first groove; the first groove extends from a side surface of the pixel definition layer away from the pixel electrode layer to a side surface of the third transparent conductive film layer in the pixel area away from the first surface.

[0015] In some embodiments, the pixel definition layer in the pixel area is provided with a second groove; the second groove extends from a side surface of the pixel definition layer away from the pixel electrode layer to a side surface of the third transparent conductive film layer in the pixel area away from the first surface.

[0016] In some embodiments, the material of the first transparent conductive film layer, the second transparent conductive film layer and the third transparent conductive film layer is indium tin oxide; and the material of the metal layer is silver.

[0017] In some embodiments, the thickness of the first transparent conductive film layer is to The thickness of the metal layer is to The thickness of the second transparent conductive film layer is to The thickness of the third transparent conductive film layer is to

[0018] In some embodiments, the interlayer insulating layer and the passivation layer are made of silicon oxide derivatives, silicon nitride derivatives, or a combination of the above materials. The thickness of the interlayer insulating layer is to The thickness of the passivation layer is to

[0019] In some embodiments, the material of the planarization layer is a photoresist material, and the thickness of the planarization layer is 0.5 μm to 3 μm.

[0020] The present application provides a method for manufacturing a display panel, comprising:

[0021] Providing a first transparent conductive film layer, wherein the first transparent conductive film layer comprises a first surface and a second surface arranged opposite to each other;

[0022] Disposing a metal layer on the first surface;

[0023] Disposing a second transparent conductive film layer on the metal layer;

[0024] Disposing a third transparent conductive film layer on the second transparent conductive film layer, wherein the third transparent conductive film layer covers a side of the second transparent conductive film layer away from the metal layer and wraps the first transparent conductive film layer, the metal layer and the edges of the second transparent conductive film layer to form a pixel electrode layer;

[0025] The pixel electrode layer is at least partially disposed in a binding area of ​​the display panel, wherein the binding area is disposed adjacent to the pixel.

[0026] The display panel provided in the embodiment of the present application has a pixel area and a binding area that are adjacently arranged. The display panel includes: a pixel electrode layer, and the pixel electrode layer is at least partially arranged in the binding area. The pixel electrode layer includes: a first transparent conductive film layer, a metal layer, a second transparent conductive film layer and a third transparent conductive film layer. The first transparent conductive film layer includes a first surface and a second surface that are relatively arranged, the metal layer is arranged on the first surface, the second transparent conductive film layer is arranged on the side of the metal layer away from the first surface, and the third transparent conductive film layer covers the side of the second transparent conductive film layer away from the metal layer and wraps the edges of the first transparent conductive film layer, the metal layer and the second transparent conductive film layer. The display panel provided in the embodiment of the present application is wrapped by adding a third transparent conductive film layer to protect the metal layer from oxidation. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application.

[0029] Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0030] Figure 3 A schematic diagram of the structure of a pixel electrode layer provided in an embodiment of the present application.

[0031] Figure 4 This is a first flow chart of a display panel manufacturing method provided in an embodiment of the present application.

[0032] Figure 5 A second flow chart of the display panel manufacturing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0034] It should be noted that, in the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0035] An embodiment of the present application provides a display panel, which is described in detail below.

[0036] See also Figure 1 , Figure 1 1 is a schematic diagram of a display panel 10 in an embodiment of the present application. The display panel 10 comprises a pixel region 10a and a binding region 10b, and the pixel region 10a and the binding region 10b are arranged adjacent to each other.

[0037] See also Figure 2 , Figure 21 is a schematic diagram of the structure of the display panel 10 in the embodiment of the present application. The display panel 10 includes a glass substrate 101, a light shielding layer 102, a buffer layer 103, a semiconductor layer 104, a conductor layer 105, a gate insulating layer 106, a gate metal layer 107, an interlayer insulating layer 108, a source-drain electrode layer 109, a passivation layer 110, a planarization layer 111, a pixel electrode layer 112, and a pixel definition layer 113. The light shielding layer 102, the buffer layer 103, the semiconductor layer 104, the conductor layer 105, the gate insulating layer 106, the gate metal layer 107, the interlayer insulating layer 108, the source-drain electrode layer 109, the passivation layer 110, the planarization layer 111, the pixel electrode layer 112, and the pixel definition layer 113 are sequentially deposited on the glass substrate 101.

[0038] The light shielding layer 102 is located in the pixel region 10a. The material used for the light shielding layer 102 is metal or alloy. Specifically, the material used for the light shielding layer 102 can be molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti) or alloys of the above metals. The thickness of the light shielding layer 102 is to Specifically, the thickness of the light shielding layer 102 can be or

[0039] The material of the buffer layer 103 is a silicon oxide derivative, a silicon nitride derivative or a combination of the above materials. The thickness of the buffer layer 103 is to Specifically, the thickness of the buffer layer 103 can be or

[0040] The semiconductor layer 104 is located in the conductor layer 105, and a gate insulating layer 106 and a gate metal layer 107 are sequentially disposed on the semiconductor layer 104. The semiconductor layer 104 and the conductor layer 105 are located in the pixel region 10a.

[0041] The material used for the semiconductor layer 104 is a metal oxide. Specifically, the material used for the semiconductor layer 104 is any one of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium zinc tin oxide (IGZTO), indium tin oxide (ITO), indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO), indium gallium tin oxide (IGTO) or antimony tin oxide (ATO). The thickness of the semiconductor layer 104 and the conductor layer 105 is to Specifically, the thickness of the semiconductor layer 104 and the conductor layer 105 can be or

[0042] The gate insulating layer 106 is made of a silicon oxide derivative, a silicon nitride derivative or a combination of the above materials. The thickness of the gate insulating layer 106 is to Specifically, the thickness of the gate insulating layer 106 can be or

[0043] The gate metal layer 107 may be made of molybdenum (Mo), aluminum Copper (Cu), titanium (Ti) or alloys thereof. The thickness of the gate metal layer 107 is to Specifically, the thickness of the gate metal layer 107 can be or

[0044] The interlayer insulating layer 108 is made of a silicon oxide derivative, a silicon nitride derivative, or a combination of the above materials. The thickness of the interlayer insulating layer 108 is to Specifically, the thickness of the interlayer insulating layer 108 is or The interlayer insulating layer 108 of the pixel region 10a is disposed on the conductive layer 105 , and is provided with a third contact hole and a fourth contact hole. The interlayer insulating layer 109 covers the conductive layer 105 , the gate insulating layer 106 and the gate metal layer 107 .

[0045] The source and drain electrode layer 109 is made of metal. Specifically, the source and drain electrode layer 109 may be made of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or alloys of the above metals. The thickness of the source and drain electrode layer 109 is to Specifically, the thickness of the source-drain layer 109 is or

[0046] The source-drain electrode layer 109 of the binding region 10b is disposed on the interlayer insulating layer 108 and partially covers the interlayer insulating layer 108, and the source-drain electrode layer 109 of the pixel region 10a is patterned and connected to the conductor layer 105 through the third contact hole and the fourth contact hole.

[0047] The material used for the passivation layer 110 is a silicon oxide derivative, a silicon nitride derivative, or a combination of the above materials. The thickness of the passivation layer 110 is to Specifically, the thickness of the passivation layer 110 may be or The passivation layer 110 covers the source and drain electrode layer 109 and the interlayer insulating layer 108 .

[0048] The material used for the planarization layer 111 is a photoresist material. The thickness of the planarization layer 111 is 0.5 μm to 3 μm. Specifically, the thickness of the planarization layer 111 can be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm.

[0049] Among them, see Figure 3 , Figure 3 1 is a schematic diagram of the structure of the pixel electrode layer 112 in the display panel 10 in the embodiment of the present application. The display panel 10 includes a pixel electrode layer 112, which is at least partially arranged in the binding area 10b, and the pixel electrode layer 112 includes: a first transparent conductive film layer 1121, a metal layer 1122, a second transparent conductive film layer 1123 and a third transparent conductive film layer 1124. The first transparent conductive film layer 1121 includes a first surface 1121a and a second surface 1121b arranged opposite to each other. The metal layer 1122 is arranged on the first surface 1121a. The second transparent conductive film layer 1123 is arranged on a side of the metal layer 1122 away from the first surface 1121a. The third transparent conductive film layer 1124 covers a side of the second transparent conductive film layer 1123 away from the metal layer 1122 and wraps the edges of the first transparent conductive film layer 1121, the metal layer 1122 and the second transparent conductive film layer 1123.

[0050] The first transparent conductive film layer 1121 , the second transparent conductive film layer 1123 and the third transparent conductive film layer 1124 are made of indium tin oxide (ITO), and the metal layer 1122 is made of silver (Ag).

[0051] The thickness of the first transparent conductive film layer 1121 is to The thickness of the metal layer 1122 is to The thickness of the second transparent conductive film layer 1123 is to The thickness of the third transparent conductive film layer 1124 is to Specifically, the thickness of the first transparent conductive film layer 1121 can be or The thickness of the metal layer 1122 can be or The thickness of the second transparent conductive film layer 1123 can be or The thickness of the third transparent conductive film layer 1124 can be or

[0052] It should be noted that the first surface 1121a may be the upper surface of the first transparent conductive film layer 1121, and the second surface 1121b may be the lower surface of the first transparent conductive film layer 1121. Of course, the first surface 1121a may also be the lower surface of the first transparent conductive film layer 1121, and the second surface 1121b may be the upper surface of the first transparent conductive film layer 1121. In the embodiment of the present application, unless otherwise specified, it is assumed that the first surface 1121a is the upper surface of the first transparent conductive film layer 1121, and the second surface 1121b is the lower surface of the first transparent conductive film layer 1121.

[0053] The passivation layer 110 and the planarization layer 111 of the binding region 10b are provided with a first contact hole, and the first contact hole extends from the side surface of the planarization layer 111 away from the passivation layer 110 to the side surface of the source-drain electrode layer 109 away from the interlayer insulating layer 108. The pixel electrode layer 112 is connected to the source-drain electrode layer 109 through the first contact hole. The passivation layer 110 and the planarization layer 111 of the pixel region 10a are provided with a second contact hole, and the second contact hole extends from the side surface of the planarization layer 111 away from the passivation layer 110 to the side surface of the source-drain electrode layer 109 away from the interlayer insulating layer 108. The pixel electrode layer 112 is connected to the source-drain electrode layer 109 through the second contact hole.

[0054] The pixel definition layer 113 of the binding area 10b is provided with a first groove 114. The first groove 114 extends from a side surface of the pixel definition layer 113 away from the pixel electrode layer 112 to a side surface of the third transparent conductive film layer 1124 of the binding area 10b away from the first surface 1121a. The pixel definition layer 113 of the pixel area 10a is provided with a second groove 115. The second groove 115 extends from a side surface of the pixel definition layer 113 away from the pixel electrode layer 112 to a side surface of the third transparent conductive film layer 1124 of the pixel area 10a away from the first surface 1121a.

[0055] The display panel 10 provided in the embodiment of the present application includes a glass substrate 101, a light shielding layer 102, a buffer layer 103, a semiconductor layer 104, a conductor layer 105, a gate insulating layer 106, a gate metal layer 107, an interlayer insulating layer 108, a source and drain electrode layer 109, a passivation layer 110, a planarization layer 111, a pixel electrode layer 112, and a pixel definition layer 113. Among them, the pixel electrode layer 112 wraps the first transparent conductive film layer 1121, the metal layer 1122 and the second transparent conductive film layer 1123 through the third transparent conductive film layer 1124, which can protect the metal layer from being oxidized. Since the third transparent conductive film layer 1124 is covered, the thickness of the second transparent conductive film layer 1123 can be reduced, making the etching process easier to operate and reducing the taper angle (taper angle). In addition, the thickness of the third transparent conductive film layer 1124 is relatively thick, which is more conducive to the development and selection of OLED devices.

[0056] The present application embodiment provides a display panel manufacturing method, which is described in detail below. Figure 4 , Figure 4 It is a first flow chart of the display panel manufacturing method in the embodiment of the present application.

[0057] 201 provides a first transparent conductive film layer, wherein the first transparent conductive film layer comprises a first surface and a second surface which are oppositely disposed.

[0058] 202 A metal layer is provided on the first surface.

[0059] 203: Dispose a second transparent conductive film layer on the metal layer.

[0060] 204 : Disposing a third transparent conductive film layer on the second transparent conductive film layer, wherein the third transparent conductive film layer covers a side of the second transparent conductive film layer away from the metal layer and wraps the first transparent conductive film layer, the metal layer and the edge of the second transparent conductive film layer to form a pixel electrode layer.

[0061] The display panel manufacturing method provided in the embodiment of the present application can protect the metal layer from being oxidized by providing a third transparent conductive film layer to wrap the first transparent conductive film layer, the metal layer and the second transparent conductive film layer.

[0062] See also Figure 5 , Figure 5 It is a second flow chart of the display panel manufacturing method in the embodiment of the present application.

[0063] 301 provides a glass substrate and cleans the glass substrate.

[0064] 302: Depositing a light shielding layer on the glass substrate.

[0065] Wherein, the light shielding layer is located in the pixel area.

[0066] 303 A buffer layer is deposited on the glass substrate and the light shielding layer.

[0067] The buffer layer covers the glass substrate and the light shielding layer.

[0068] 304: Depositing a semiconductor layer on the buffer layer.

[0069] Among them, yellow light or etching methods are used to make patterns on the semiconductor layer.

[0070] Yellow light is a process of photolithography of silicon wafers and other chips by coating, soft baking, exposure, development, and hard baking. Etching is a technique of removing materials by chemical reaction or physical impact. In the embodiment of the present application, the semiconductor layer material can be applied to the buffer layer, and then the semiconductor layer pattern can be photolithography by yellow light process; or the semiconductor layer material can be deposited on the buffer layer and patterned by etching.

[0071] Wherein, the semiconductor layer is arranged in the pixel area.

[0072] 305: depositing a gate insulating layer on the semiconductor layer.

[0073] 306 : Depositing a gate metal layer on the gate insulating layer.

[0074] Among them, the gate metal layer pattern is produced by yellow light or etching, and then the gate metal layer pattern is used for self-alignment, and the gate insulating layer is produced by yellow light or etching, and all the gate insulating layer not covered by the gate metal layer is etched away.

[0075] 307 The semiconductor layer, the gate insulating layer, and the gate metal layer are all subjected to plasma treatment, and part of the semiconductor layer is formed into a conductor layer.

[0076] Among them, plasma is an ionized gaseous substance composed of negatively charged particles (negative ions, electrons), positively charged particles (positive ions) and uncharged particles. It is usually listed alongside the solid, liquid and gaseous states of matter and is called the fourth state of matter. By applying plasma technology, a new surface structure can be obtained on the semiconductor layer. Specifically, for the semiconductor layer without the protection of the gate insulating layer and the gate metal layer above, the resistance is reduced after plasma treatment to form a conductor layer; the semiconductor layer below the gate insulating layer is not processed, and the semiconductor characteristics are maintained as a thin film transistor (TFT) channel. In a display panel, a thin film transistor can be used as a switching device or a driving device, and therefore, the channel formed by the thin film transistor can be used as a path channel for moving charge carriers.

[0077] 308 : Deposit an interlayer insulating layer on the buffer layer, the conductor layer, and the gate metal layer.

[0078] Wherein, a third contact hole and a fourth contact hole are etched in the interlayer insulating layer.

[0079] 309: depositing a source and drain layer on the interlayer insulating layer.

[0080] The source and drain electrode layers of the pixel area are patterned and connected to the conductor layer through the third contact hole and the fourth contact hole arranged in the interlayer insulating layer. The source and drain electrode layers of the binding area are arranged on the interlayer insulating layer and partially cover the interlayer insulating layer.

[0081] 310 A passivation layer is deposited on the interlayer insulating layer and the source and drain electrode layers.

[0082] The passivation layer covers the source and drain electrode layers and the interlayer insulating layer.

[0083] 311 A planarization layer is deposited on the passivation layer.

[0084] Among them, the first contact hole and the second contact hole are made in the passivation layer and the planarization layer by using the yellow light process. The passivation layer and the planarization layer in the binding area are provided with a first contact hole, and the first contact hole extends from the surface of the planarization layer away from the passivation layer to the surface of the source and drain layer away from the interlayer insulating layer. The passivation layer and the planarization layer in the pixel area are provided with a second contact hole, and the second contact hole extends from the surface of the planarization layer away from the passivation layer to the surface of the source and drain layer away from the interlayer insulating layer.

[0085] 312: a pixel electrode layer is disposed on the planarization layer.

[0086] The pixel electrode layer is connected to the source and drain electrode layer through the first contact hole and the second contact hole.

[0087] 313 A pixel definition layer is provided on the planarization layer and the pixel electrode layer.

[0088] After the pixel definition layer is provided, a first groove is provided on the pixel definition layer in the binding area, and a second groove is provided on the pixel definition layer in the pixel area, wherein the first groove extends from a side surface of the pixel definition layer away from the pixel electrode layer to a side surface of the third transparent conductive film layer in the binding area away from the first surface. The second groove extends from a side surface of the pixel definition layer away from the pixel electrode layer to a side surface of the third transparent conductive film layer in the pixel area away from the first surface. Then, a cathode layer is deposited and encapsulated.

[0089] The display panel manufacturing method provided in the embodiment of the present application can protect the metal layer from being oxidized by wrapping the first transparent conductive film layer, the metal layer and the second transparent conductive film layer with the third transparent conductive film layer. Since the third transparent conductive film layer is covered, the thickness of the second transparent conductive film layer can be reduced, making the etching process easier to operate and reducing the taper angle. In addition, the thickness of the third transparent conductive film layer is relatively thick, which is more conducive to the development and selection of OLED devices.

[0090] The above is a detailed introduction to the display panel and display panel manufacturing method provided by the embodiment of the present application. The principle and implementation method of the present application are described in detail using specific examples herein. The description of the above embodiments is only used to help understand the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A display panel, characterized in that: The display panel has a pixel area and a binding area, and the pixel area and the binding area are arranged adjacent to each other; the display panel includes: A substrate and a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a source-drain electrode layer, a passivation layer, a planarization layer, a pixel electrode layer and a pixel definition layer sequentially deposited on the substrate; the semiconductor layer is located in the pixel area; The display panel further comprises: a conductor layer located in the pixel area, and the semiconductor layer is located in the conductor layer; The pixel electrode layer is at least partially disposed in the binding area, the passivation layer and the planarization layer in the binding area are provided with a first contact hole, the first contact hole extends from a side surface of the planarization layer away from the passivation layer to a side surface of the source and drain electrode layer away from the interlayer insulating layer, the pixel electrode layer is connected to the source and drain electrode layer through the first contact hole, and the pixel electrode layer includes: a first transparent conductive film layer, the first transparent conductive film layer being arranged on a side of the planarization layer away from the substrate, the first transparent conductive film layer comprising a first surface and a second surface arranged opposite to each other, the second surface corresponding to the concave portion of the first transparent conductive film layer being in contact with the side wall of the first contact hole and extending to a surface of a side of the source-drain electrode layer away from the interlayer insulating layer; a metal layer, wherein the metal layer is disposed on the first surface, and a concave portion of the metal layer is attached to the first surface corresponding to a concave portion of the first transparent conductive film layer; a second transparent conductive film layer, the second transparent conductive film layer being arranged on a side of the metal layer away from the first surface, the concave portion of the second transparent conductive film layer being in contact with a side of the concave portion of the metal layer away from the first surface; a third transparent conductive film layer, the third transparent conductive film layer covering a side of the second transparent conductive film layer away from the metal layer and wrapping edges of the first transparent conductive film layer, the metal layer and the second transparent conductive film layer; The material of the first transparent conductive film layer is the same as that of the second transparent conductive film layer, and the thickness of the first transparent conductive film layer is to The thickness of the second transparent conductive film layer is to 2. The display panel according to claim 1, characterized in that: The passivation layer and the planarization layer of the pixel region are provided with a second contact hole, and the second contact hole extends from a surface of the planarization layer on a side away from the passivation layer to a surface of the source and drain electrode layer on a side away from the interlayer insulating layer; The pixel electrode layer is connected to the source and drain electrode layer through the second contact hole.

3. The display panel according to claim 2, characterized in that: The pixel definition layer in the binding area is provided with a first groove; the first groove extends from a side surface of the pixel definition layer away from the pixel electrode layer to a side surface of the third transparent conductive film layer in the binding area away from the first surface.

4. The display panel according to claim 3, characterized in that: The pixel definition layer in the pixel area is provided with a second groove; the second groove extends from a side surface of the pixel definition layer away from the pixel electrode layer to a side surface of the third transparent conductive film layer in the pixel area away from the first surface.

5. The display panel according to any one of claims 1 to 4, characterized in that: The materials of the first transparent conductive film layer, the second transparent conductive film layer and the third transparent conductive film layer are indium tin oxide; the material of the metal layer is silver.

6. The display panel according to claim 5, characterized in that The thickness of the metal layer is to The thickness of the third transparent conductive film layer is to 7. The display panel according to any one of claims 1 to 4, characterized in that: The interlayer insulating layer and the passivation layer are made of silicon oxide derivatives, silicon nitride derivatives or a combination of the above materials. The thickness of the interlayer insulating layer is to The thickness of the passivation layer is to 8. The display panel according to any one of claims 1 to 4, characterized in that: The material of the planarization layer is a photoresist material, and the thickness of the planarization layer is 0.5 μm to 3 μm.

9. A display panel manufacturing method, characterized in that: include: Providing a substrate, the substrate comprising a pixel area and a binding area arranged adjacent to each other; Disposing a semiconductor layer in the pixel region on the substrate; Disposing a gate insulating layer on the semiconductor layer; Disposing a gate metal layer on the gate insulating layer; Performing plasma treatment on the entire surface of the semiconductor layer, the gate insulating layer, and the gate metal layer, so that part of the semiconductor layer forms a conductor layer; Disposing an interlayer insulating layer on the conductor layer and the gate metal layer; Disposing a source-drain electrode layer on the interlayer insulating layer, wherein the source-drain electrode layer partially covers the interlayer insulating layer; Disposing a passivation layer on the source-drain electrode layer, wherein the passivation layer covers the source-drain electrode layer and the interlayer insulating layer; A planarization layer is provided on the passivation layer, and a first contact hole is made on the planarization layer located in the binding region, wherein the first contact hole extends from a surface of the planarization layer away from the passivation layer to a surface of the source-drain electrode layer away from the interlayer insulating layer; Manufacturing a pixel electrode layer on the planarization layer, wherein the pixel electrode layer is at least partially disposed in the binding area; Disposing a pixel definition layer on a side of the pixel electrode layer away from the planarization layer; Wherein, the step of manufacturing a pixel electrode layer on the planarization layer comprises: A first transparent conductive film layer is disposed on a side of the planarization layer away from the substrate, and the thickness of the first transparent conductive film layer is to The first transparent conductive film layer comprises a first surface and a second surface which are arranged opposite to each other, and the second surface corresponding to the concave portion of the first transparent conductive film layer is in contact with the side wall of the first contact hole and extends to a surface of the source and drain electrode layer which is away from the interlayer insulating layer; A metal layer is disposed on the first surface, wherein the concave portion of the metal layer is attached to the first surface corresponding to the concave portion of the first transparent conductive film layer; A second transparent conductive film layer is disposed on a side of the metal layer away from the first surface, and the thickness of the second transparent conductive film layer is to The material of the second transparent conductive film layer is the same as that of the first transparent conductive film layer, and the concave portion of the second transparent conductive film layer is attached to a side of the concave portion of the metal layer away from the first surface; A third transparent conductive film layer is disposed on a side of the second transparent conductive film layer away from the metal layer, and the third transparent conductive film layer covers a side of the second transparent conductive film layer away from the metal layer and wraps the edges of the first transparent conductive film layer, the metal layer and the second transparent conductive film layer.

Images