High performance standard cell

Abstract

A high performance standard transistor cell is provided that includes a contiguous oxide defined (OD) region defined in a substrate; a gate (450) of a transistor between a first dummy gate (425) and a second dummy gate (430), wherein a source of the transistor is defined in a first portion of the OD region between the gate and the first dummy gate, and wherein a drain of the transistor is defined in a second portion of the OD region between the gate and a first side of the second dummy gate; a first gate oriented local interconnect (470) and a first diffusion oriented local interconnect (440) couple a third portion of the OD region adjacent to a second opposite side of the second dummy gate and the second dummy gate to a source voltage.

Description

[0001] This divisional application is a divisional application of the PCT national phase patent application with the international filing date of February 19, 2015, national application number 201580011681.4, entitled "High-performance standard unit". Technical Field

[0002] This application relates to processors, and more particularly to power optimization of processors. background

[0003] As semiconductor technology advances to deep submicron process nodes, short-channel effects can severely degrade performance. Carrier velocities saturate in such short channels, slowing switching speeds and reducing transistor strength. To achieve high density while maintaining sufficient transistor strength, strain engineering techniques have been developed to strain the lattice in the source and drain diffusion regions (often referred to as oxide-bound (OD) in transistor layout terminology). The OD is not only appropriately n-type or p-type doped to achieve the desired transistor type (NMOS or PMOS), but also strained to improve carrier velocity and transistor strength. In this respect, the OD is only localized strain, contrasting with straining the entire substrate.

[0004] Such localized strain has proven superior to global strain across the entire substrate. The type of strain depends on the transistor type. The OD (overhead strain) for PMOS transistors is compressive strain, while the OD for NMOS transistors is tensile strain. For example, a SiGe film can be applied to a p-type OD to introduce compressive strain, while a SiN or SiC film can be applied to an n-type OD to introduce tensile strain. The resulting silicon strain engineering has proven quite successful in achieving satisfactory transistor strength at deep submicron process nodes.

[0005] The use of strain engineering introduces several constraints into the layout process. Figure 1 illustrates the layout of an example transistor pair. The source (S) and drain (D) of the first transistor 100 are defined by a first OD region 105. A polysilicon gate 110 separates the source and drain regions. A similar arrangement of another OD region 115 and a polysilicon gate 120 defines another transistor 101. At advanced process nodes, the layout of Figure 1 would be inefficient because both ODs 115 and 110, which form the drain and source regions, are relatively short. This short length to the ODs allows their lattice to be overly relaxed, despite the use of local strain engineering. Transistors 100 and 101 would therefore be too weak. Conversely, if ODs 105 and 115 could be extended to form a continuous OD as shown by dashed line 125, ODs 105 and 115 would have increased strain, resulting in better performance. However, this extension of the ODs would short the drain of transistor 100 to the source of transistor 101.

[0006] To achieve satisfactory transistor performance at deep submicron process nodes, a “continuous OD” layout has been developed. Figure 2 illustrates an example layout of continuous OD 200. Transistors 100 and 101 are still defined with respect to polysilicon gates 110 and 120, respectively. However, OD 200 is continuous for both transistors so that OD 200 can form a lattice strain sufficient to achieve satisfactory transistor strength. A dummy polysilicon gate 205 electrically insulates transistors 100 and 101 by being configured to be charged to the source voltage. For example, if OD 200 is p-type doped, the dummy gate 205 will be bonded to the supply voltage VDD. Alternatively, if OD 200 is n-type doped, the dummy gate 205 will be bonded to ground. Similarly, a dummy gate 210 isolates transistor 100 from the transistor (not shown) to the left of the dummy gate 210 in continuous OD 200.

[0007] While the use of continuous OD 200 enables sufficient lattice strain, several design complexities exist. For example, each transistor can be considered to reside within a separate "standard cell." The standard cell 201 forming transistor 100 extends from boundary A along dummy gate 210 to boundary B along dummy gate 205. Each dummy gate is always bonded to a source voltage—VDD in the PMOS embodiment and ground in the NMOS embodiment. Interconnect 215 provides a source voltage coupled between dummy gate 205 and the source of transistor 101. Similarly, interconnect 220 provides a source voltage coupled between dummy gate 210 and the source of transistor 100. Considering this standard cell topology, note the issues that arise regarding the characterization of leakage in standard cell 201. Regarding leakage from the drain of transistor 100, leakage from the source of transistor 100 across gate 110 can only be defined at the cell level. However, the leakage current from the source of transistor 100 depends on the state of the diffusion region 225 to the left of the dummy gate 210. A priori, it is impossible to know whether the diffusion region 225 is the source or drain of another transistor in the additional standard cell until standard cell 201 is instantiated immediately following another standard cell. This uncertainty greatly complicates the leakage calculation of transistor 100. For example, assuming the diffusion region 225 forms the source of another transistor—that source would be at the same voltage as the source of transistor 100, making leakage across the dummy gate 210 impossible. Conversely, if the diffusion region 225 forms the drain of another transistor, the leakage current will flow from the source of transistor 101 to the diffusion region 225. We know that the leakage current will always exist across gate 110 between the drain and source of transistor 100. This leakage current can be represented as a "always present" leakage current to distinguish it from the "optional" leakage current that depends on whether the diffusion region 225 forms a drain or a source. Therefore, for standard cells such as cell 201, there are two possibilities: either only a persistent leakage current, or a persistent leakage current plus an optional leakage current. Leakage current characterization is a crucial performance imprint for a design. However, the conventional standard cell architecture for continuous OD 200 shown in Figure 2 significantly complicates the determination of leakage current for a given design.

[0008] Therefore, there is a need in this field for improved standard cell continuous OD architecture.

[0009] Overview

[0010] A cell architecture is disclosed that provides a consistent leakage current characterization for continuous oxide-defined (OD) region processes. In this context, a "cell" refers to the layout of circuit building blocks (such as logic gates or inverters). Such circuit building blocks typically include several transistors; however, the embodiments disclosed herein may also include only a single transistor. A conventional cell can be considered to extend from a first dummy gate to a second dummy gate. Depending on the number of transistors, one or more gates may exist within the dummy gate boundaries. Similarly, one or more continuous OD regions may extend across the cell. These continuous OD regions can also be represented as continuous active regions. For example, if the cell is to include both NMOS and PMOS transistors, the cell will require at least two continuous OD regions—at least one p-type doped active region for PMOS transistors and at least one n-type doped active region for NMOS transistors. In a conventional cell, the cell structure stops at the dummy gate boundary. However, the advantageous cell disclosed herein needs to extend beyond the dummy gate adjacent to the drain of the transistor. In this respect, the transistor has a drain and a source, each defined within the OD region so as to be separated by the transistor's gate. The drain is therefore defined within a portion of the OD region that extends from the gate to a first side of an adjacent dummy gate. This dummy gate adjacent to the drain may also be referred to herein as a drain-side dummy gate. The remaining dummy gates may therefore be referred to as source-side dummy gates.

[0011] The drain-side dummy gate includes an opposing second side. In a conventional cell, there is no structure extending to a portion of the OD region adjacent to this opposing second side of the drain-side dummy gate. However, as will be explained further below, the cell discussed herein includes a local interconnect structure that couples the portion of the OD region adjacent to the opposing second side of the drain-side dummy gate to the source voltage. This is quite advantageous because the drain of the cell is guaranteed to always be separated from the portion of the OD region charged to the source voltage by the drain-side dummy gate. Note that the OD region including this cell will typically include numerous other cells. These cells can be considered to extend from the first cell to the last cell. However, even if the cell is the last cell (or the first cell) and thus there are no further cells defined in that portion of the OD region adjacent to the second side of the drain-side dummy gate, that portion of the OD region will behave no differently from the transistor source in terms of the leakage current flowing from that portion of the region across the drain-side dummy gate to the drain. In other words, there may be cells defined in that portion of the OD region, or there may not be. Regardless of the presence of another cell adjacent to the dummy gate on the drain side, the portion of the OD region adjacent to the second side of the dummy gate on the drain side is charged to the source voltage.

[0012] Given this cell architecture, the uncertainties discussed above regarding leakage in conventional continuous OD cells have been mitigated. The resulting cells always provide consistent, predictable leakage. In this regard, note that the cell does not require the local interconnect to extend beyond the source-side dummy gate to the continuous OD region outside that source-side dummy gate. Additional cells with drains can be defined within this portion of the continuous OD region. Leakage current will indeed flow from the source of this cell to the drain of the additional cell. However, such additional leakage current does not disrupt the leakage current characterization at the cell level because the additional cell has the same structure and therefore the leakage current is measured as its own leakage current. Conversely, if this adjacent cell is against its source, there is no leakage current between adjacent cells due to source-to-source contact. Brief description of the attached diagram

[0013] Figure 1 illustrates a conventional transistor pair with a discontinuous diffusion region.

[0014] Figure 2 illustrates a conventional transistor pair in a continuous diffusion region.

[0015] Figure 3 is a cross-sectional view of the multi-level local interconnection and associated structure.

[0016] Figure 4A The layout of a cell in a continuous diffusion region is explained, wherein the transistor includes a drain adjacent to a first side of the dummy gate, and wherein the cell includes a local interconnect structure configured to charge a portion of the diffusion region and the dummy gate to the source voltage.

[0017] Figure 4B Explained and Figure 4B The elements are elements that have a mirror relationship.

[0018] Figure 5A Commentary Figure 4A A variant of the cell structure, in which an additional dummy gate is floating.

[0019] Figure 5B Commentary Figure 5A The cell is against the drain of the transistor in the adjacent cell.

[0020] Figure 6 This is a flowchart of an example leakage current analysis for a cell based on this disclosure.

[0021] Figure 7 It is aimed at Figures 4A to 5B A flowchart of an example manufacturing method for a unit. Detailed description

[0022] To meet the need for continuous-outlet (OD) standard cells with predictable leakage current, various continuous-outlet (OD) standard cell architectures are disclosed that provide known leakage current amounts. In other words, the uncertainties discussed above regarding the conventional layout shown in Figure 2 are eliminated. This is highly advantageous because the leakage current can then be confidently predicted solely from the number of standard cells incorporated into the design. Conversely, the leakage current from a circuit constructed using the conventional standard cell 201 of Figure 2 must be determined through simulation, as this leakage current will depend on various drain-source or source-to-source cell proximity. In stark contrast, the leakage circuit calculation remains unchanged for the disclosed cells, regardless of whether the cell has source-to-source or source-to-drain proximity with adjacent cells. These advantageous features are better understood by discussing modern local interconnects.

[0023] Referring again to Figure 2, note that local interconnects 220 and 215 are shown in a simplified form. In reality, various local interconnect layouts or structures are known for coupling between the gate and non-gate regions. These structures are disclosed herein with respect to a two-layer local interconnect topology (where the third layer is dedicated to vias). Although wires in metal layers adjacent to the substrate are sometimes referred to as “local interconnects,” such wires are excluded from the definition of “local interconnect” as used herein. In older process nodes, interconnects in the first metal layer (and higher metal layers) would be coupled to the transistor gate and drain / source terminals via vias. However, as semiconductor process technology has advanced to the deep submicron region, vias from the first metal layer (or higher layers) are coupled to these transistor structures via two-layer local interconnect structures. These vias are therefore located between the two lower layers (level 1 and level 2) of the local interconnect in the upper third layer (level 3).

[0024] Figure 3 illustrates some examples of two-level local interconnects. As can be seen in the figure, there are three levels of local interconnects, ranging from level 1 to level 3. Level 1 defines a local interconnect layer adjacent to the continuous diffusion region (OD) 305. Level 3 defines a local interconnect layer adjacent to the first metal layer M1. Finally, level 2 defines a local interconnect layer coupled between the level 1 and level 3 local interconnects.

[0025] Stage 1 local interconnects 310 include local interconnect (LI) types denoted as LIc. Two types of local interconnects exist in Stage 2: LIa 315 and LIb 320. Therefore, there is one type (LIc 310) in Stage 1 and two types (LIa 315 and LIb 320) in Stage 2. Stage 1 interconnects (such as LIc 310) are directly coupled to the continuous diffusion region 305. This type of Stage 1 interconnect will therefore be applied to the continuous diffusion region (OD) 305 through a suitable semiconductor process mask before any Stage 2 interconnects are formed. Stage 1 is also the stage for the gate layer 300 (such as a polysilicon layer or a high-k metal layer). The gate layer 300 is not a form of local interconnect because it forms the gate of a transistor with a source, drain, and channel in the continuous diffusion region 305. Level 2 interconnects (such as Lia 315 and Lib 320) are coupled to the first metal layer M1 (or a higher metal layer) via vias (such as via V0 325). These vias are arranged in Level 3, which is located between Level 2 and the first metal layer M1.

[0026] Referring back to Figure 2, the layouts of gate layers 110, 120, and 205 form relatively narrow polygons, the vertical axes of which are orthogonal to the vertical axis of the polygonal layout of the continuous diffusion region 200. Local interconnects follow an organization whereby a given type of local interconnect is generally arranged to have a polygonal shape, the vertical axis of which is either parallel to the gate layer or parallel to the continuous diffusion region (i.e., the vertical axis of the polygonal layout is parallel to the vertical axis of either the gate layer or the continuous diffusion region). Because it would be cumbersome to repeatedly refer to the vertical axis of the polygonal shape used for layout purposes, a local interconnect is defined herein as a "gate-oriented local interconnect" if the vertical axis of the polygonal layout of the local interconnect is parallel to the vertical axis of the polygonal layout of the gate layer. Conversely, a local interconnect is defined herein as a "diffusion-oriented local interconnect" if the vertical axis of the polygonal layout of the local interconnect is parallel to the vertical axis of the polygonal layout of the diffusion region.

[0027] Stage 1 local interconnects (such as Lic 310) are formed on diffusion region 305. Lic 310 thus acts as a direct electrical coupling to diffusion region 305 for higher layer interconnects. It is thus immediately apparent that stage 1 local interconnects must be gate-oriented local interconnects, as otherwise they would interfere with the layout of gate layer 300: Lic 310 cannot be a diffusion-oriented local interconnect, otherwise it might be shorted and intersected with gate layer 300. Conversely, stage 2 local interconnects can be either gate-oriented or diffusion-oriented local interconnects. A stage 2 type local interconnect is necessary for coupling to Lic 310 (such as Lia 315). Thus, Lia 315 is a gate-oriented local interconnect and is coupled between the corresponding via (not explained) in stage 3 and M1 (or a higher metal layer). Stage 2 Lib 320 is coupled to gate layer 300 and is arranged to have either a square layout (considered diffusion-oriented herein) or a diffusion-oriented polygonal layout. LIb 320 may also be referred to herein as "MP" 320. The via V0 coupled between LIb 320 and metal layer M1 represents the stage 3 interconnect between M1 and the stage 1 and stage 2 local interconnects. The first metal layer M1 is located above stage 3. LIa 315, LIb 320, and LIc 310 typically comprise tungsten, while via V0 and M1 typically comprise copper. Other materials may be used as known in the field of local interconnects.

[0028] Keep these local interconnection concepts in mind, in Figure 4A An example standard cell 400 is shown. Note that this figure (and this is true for all other layouts) is a plan view. In other words, Figure 3 is a cross-sectional view of the substrate including OD 305, while Figure 4AA plan view of the effective surface of the supporting standard cell 400 of the substrate is shown. In this arrangement, the standard cell 400 includes a transistor 405 having a source 410 and a drain 415 formed in a continuous OD 420. Because the OD 420 is continuous, the standard cell 400 extends from a first dummy polysilicon gate 425 across the polysilicon gate 450 of the transistor 405 to a second dummy gate 430. Note that the cell 400 may include additional polysilicon gates, such as the gate 450 of other transistors. For clarity, the cell 400 is therefore shown as including only one polysilicon gate 450; however, it will be appreciated that additional such polysilicon gates may be included in alternative embodiments. Similarly, the cell 400 may include additional continuous OD regions in addition to the continuous OD 420. A stage 2MP interconnect 435 is coupled from the first dummy gate 425 to the source 410 via a stage 1LIc interconnect 455. Via 460 is coupled between a metal layer (such as metal layer M1 (unexplained)) and a stage 1 Lic interconnect 455 via a stage 2 interconnect Lia layer (not explained), thereby charging the source region 410 and the dummy gate 425 to the appropriate source voltage (depending on whether transistor 405 is a PMOS or NMOS transistor, VDD or ground, respectively).

[0029] Similar to interconnect 435, stage 2MP interconnect 440 is coupled from the second dummy gate 430 through stage 1Lic interconnect 465 to the diffusion region 445 to the right of the dummy gate 430 in OD 420. Because the dummy gate 430 should be bonded to the source voltage so that it functions as a dummy gate, via 470 is coupled between the source interconnect (not explained) in the metal layer and the stage 1Lic interconnect 465 through stage 2Lia interconnect (not explained). The diffusion region 445 is thus also charged to the source voltage. As previously discussed, both Lic 465 and Lia interconnects are gate-oriented interconnects. In these stage 1 / stage 2 stacks of gate-oriented interconnects, the combination of Lia and Lic interconnects can be referred to as the MO-OD layer. For example, the MO-OD layer 480 is coupled to the drain 415.

[0030] Note that cell 400 includes MP interconnect 440, L1 interconnect 465, and via 470, although these structures exist outside the conventional cell boundaries, which conventional cell boundaries conventionally extend from dashed line A on dummy gate 425 to dashed line B on dummy gate 430. These additional structures are quite advantageous because they force diffusion region 445 to always be charged to the source voltage. The leakage current from this additional "source" (diffusion region 445) across dummy gate 430 to drain 415 can then be calculated. This leakage current will thus be the same for each replica of cell 400. These variability in whether the source or drain exists in diffusion region 485 to the left of dummy gate 425 in OD 420 is therefore irrelevant, because at the cell level, the leakage current from the additional "source" (diffusion region 445) to drain 415 is always calculated. If diffusion region 485 includes the source of another cell (not shown), there cannot be an additional leakage current across the dummy gate 425 between the source / diffusion region 485 and the source 410, because these nodes are charged to the same potential. Conversely, if diffusion region 485 includes the drain of another cell (not shown), a cell-level leakage current from the source 410 to diffusion region 485 will be captured at the drain of that additional cell. This is quite advantageous because the leakage current can now be characterized at the cell level, which, as discussed above, is problematic for conventional cell 201. Note how advantageous this is: depending on the fabrication process and cell size, a range can always be set for this defined leakage current for various anticipated process corners, supply voltages, and temperatures. Whatever that range is, it only needs to be multiplied by the number of cells 400 to characterize the leakage current. In contrast, there is no such ready-made solution for the leakage current of cell 201 in Figure 2. Specifically, interconnect 215 (which is shown in a simplified form as discussed above, excluding the two-layer local interconnect structure discussed above) is not part of cell 201. Therefore, cell 201 does not provide the certainty provided by cell 400 in relation to providing a known amount of leakage current.

[0031] Note that there are specific physical differences between cell 400 and conventional cell 201. For example, suppose cell 201 is at the edge of the transistor array. In other words, the gates (such as gates 110 and 101 (and dummy gates 210 and 205)) are arranged according to a gate pitch. This pitch defines the regular spacing between adjacent gate structures. The OD diffusion region (such as OD 200) thus extends across the numerous gates of each cell. These gates are therefore arranged across the range of a continuous OD diffusion region from one end of the OD diffusion region to the remaining end of the OD diffusion region. Each gate, in terms of its arrangement, can be considered to be arranged from the initial gate to the final gate ground according to the gate pitch across the OD diffusion region. Similarly, the transistors corresponding to each gate can also be considered to be arranged from the first transistor to the final transistor ground for any given continuous OD diffusion region. In this regard, suppose transistor 100 of FIG. 2 is the final transistor on the continuous OD diffusion region 200. Then there will be no transistor 101 to the right of transistor 100. Because interconnect 215 is part of a cell of transistor 101, transistor 100 would not exist if it were the final transistor on the continuous OD diffusion region 200. The dummy gate 205 would therefore float in this conventional case. However, cell 400 is quite different—it doesn't matter whether cell 400 is the final cell on the continuous OD diffusion region 420, because interconnect 440, interconnect 465, and via 470 are included within cell 400. Gate 430 and diffusion region 445 are therefore always charged to the source voltage, regardless of whether cell 400 is the final cell or an earlier cell.

[0032] In one embodiment, the local interconnect structure of the diffusion-oriented local interconnect 440 and the gate-oriented local interconnect 465 may be considered to include means for coupling the dummy gate 430 and the diffusion region 445 to the source voltage.

[0033] As defined herein, the longitudinal axis of an OD-aligned structure can be considered to extend in the "diffusion-oriented" direction, while a gate-aligned structure can be considered to extend in the "gate-aligned" direction orthogonal to the diffusion-oriented direction. Referring again to cell 400, MP local interconnects 435 and 440 can be considered to extend in the diffusion-oriented direction. For example, interconnect 440 extends in the diffusion-oriented direction from the dummy gate 430 to the stage 1Lic interconnect 465. Conversely, stage 1Lic interconnect 465 extends clearly in the gate-oriented direction because stage 1Lic interconnect 465 is parallel to a portion of the dummy gate 430.

[0034] Figure 4A The cell architecture shown can be easily "flipped" 180 degrees, such as... Figure 4BThe diagram shows cell 401, which includes transistor 495. In other words, the source 410 of cell 400 is to the left of gate 450 and its drain is to the right of gate 450, while the source 410 of cell 401 is to the right of gate 450. Similarly, in cell 401, the drain 415 is to the left of gate 450. Cells 400 and 401 are therefore mirror images of each other. The remaining structure in cell 401 follows this mirror relationship, except as discussed with respect to cell 400. For example, in cell 400, interconnect 470 is to the right of gate 450, while in cell 401, interconnect 470 is to the left of gate 450. It can be understood that cell 401 may abut against another cell 401 or cell 400 at boundary A or B. Similarly, cell 400 may abut against other cells 400 or cell 401 at boundaries A and B. Regardless of the resistance, the leakage current of cells 400 and 401 can always be effectively characterized at the cell level. As discussed with respect to cell 400, cell 401 includes only a single polysilicon gate 450 and a continuous OD 445; however, it will be appreciated that alternative cell architectures may include multiple gates and continuous OD regions.

[0035] Figure 5A The diagram shows an alternative cell architecture for cell 500. The difference between cell 500 and cell 400 is the absence of the MP interconnect 435. Otherwise, the structure in cell 500 is as discussed regarding cell 400. As a result, the dummy gate 425 is floating. However, this does not cause any problems because the dummy gate 425 is appropriately charged upon contact with another cell. For example, if the drain 515 of another transistor (not shown) in a cell having the same structure as cell 500 (although this cell may have a varying number of polysilicon gates and continuous OD regions) is adjacent to the dummy gate 425, as... Figure 5BAs shown, the additional transistor requires the addition of a stage 2 diffusion-oriented interconnect 510 to couple the dummy gate 425 to a stage 1 gate-oriented interconnect 455, just as cell 500 requires a stage 2 diffusion-oriented interconnect 440 to couple to a stage 1 gate-oriented interconnect 465. Note that the purpose of interconnect 440 is to ensure that the OD portion adjacent to the second dummy gate 430 is bound to the source voltage, since the second dummy gate 430 is adjacent to the drain of transistor 505. In this way, the leakage current of cell 500 can be characterized regardless of whether drain 515 becomes a source. The leakage from source 410 to drain 515 will then be captured in the cell (not shown) for the transistor including drain 515. If the additional cell instead has a source where drain 515 is shown, there will be no leakage between source 410 and the other source. Therefore, it can be understood that the cell-level leakage for cell 500 (and also for cells 400 and 401) is the same, regardless of the proximity (source or drain) of adjacent cells. Example fabrication methods will now be discussed for these advantageous cell structures.

[0036] Example methods for leakage current analysis and manufacturing

[0037] As discussed above, the innovative cell designs disclosed herein greatly simplify circuit design and analysis. Similar to conventional cell architectures, these cell designs use dummy gates to isolate their transistors. Specifically, the cell includes a drain adjacent to a first side of a first dummy gate. Similarly, the cell includes a source adjacent to a second dummy gate. The gate of the cell is located between the drain and the source. Such a structure is conventional. However, what is unconventional is that the cell includes a local interconnect structure extending from the first dummy gate, such that both the first dummy gate and a portion of the second opposing side of the OD region adjacent to the first dummy gate are charged to the source voltage. This guarantees a predictable leakage current for each cell: with respect to a single OD region, it is the leakage current across the OD region from the source-charged portion of the OD region to the drain of the cell. Depending on the number of OD regions extending across the cell, the leakage current can therefore be predicted accordingly. Given this guarantee, it is not necessary to concern oneself with whether the source or drain is against the drain of the cell. If the source of an additional cell is against the source of this cell, no additional leakage current occurs. If the drain of an additional cell abuts against the source of the current cell, the adjacent additional cell will "capture" the leakage current flowing from the current cell to the drain of the additional cell. In this way, the circuit designer only needs to calculate what the leakage current is for a specific instantiation of the cell. As is known in the art, this calculation is routine and will depend on the transistor size and the expected semiconductor angle. There will certainly be some tolerance in such a calculation, since the exact process angle will not be known until after manufacturing. However, this tolerance is the same for all cells. The leakage calculation thus becomes relatively effortless: simply count the cells extending across a given OD region and multiply the result by the expected cell leakage.

[0038] Figure 6 The flowchart outlines this advantageous leakage current analysis method. This analysis can be performed using a processor (not described). The method begins at step 600 of designing a circuit comprising a plurality of cells extending across a continuous OD region, each cell including a drain adjacent to a first side of a first dummy gate and a local interconnect structure configured to couple both the first dummy gate and a first portion of the OD region adjacent to the first dummy gate to a source voltage. The method includes an action 605 in the processor to calculate the cell leakage current between the first portion of the OD region and the drain. Finally, the analysis includes an action 610 in the processor to count the number of cells in the plurality of cells and multiply that number by the cell leakage current to obtain the total leakage current of the plurality of cells.

[0039] In an additional step (not explained), the multiple cells and corresponding OD regions can be formed in a semiconductor substrate to complete the fabrication. However, note that leakage current analysis is greatly simplified, as it only requires counting the cells and multiplying that count by the cell leakage current. This is not the case for conventional cells, as it is unknown whether the drain of a conventional cell is adjacent to the drain or source of another conventional cell. Therefore, the disclosed cell architecture greatly simplifies circuit design and analysis.

[0040] Figure 7 An example manufacturing method for a cell according to this disclosure is provided. In an initial step 700, a continuous oxide-defined (OD) region is defined in a substrate. Step 705 includes forming a gate of a transistor between a first dummy gate and a second dummy gate, wherein the source of the transistor is defined in the portion of the OD region between the gate and the first dummy gate, and wherein the drain of the transistor is defined in the portion of the OD region between the gate and a first side of the second dummy gate. Step 710 includes forming a first gate-oriented local interconnect coupled to a portion of the OD region adjacent to a second opposing side of the second dummy gate. Finally, step 715 includes forming a first diffused-oriented local interconnect coupled between the first gate-oriented interconnect and the second dummy gate. It will be appreciated that similar formation steps may be performed to create the remaining structures of cells 400, 401, and 500.

[0041] As will be appreciated by those skilled in the art by this time, and depending on the specific application at hand, many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the devices disclosed herein without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments explained and described herein (as they are merely examples), but should be fully equivalent to the appended claims and their functional equivalents.

Claims

1. A unit comprising only a single transistor and including additional structures, said unit comprising: The continuous oxide layer defined in the substrate defines the OD region; The transistor has a gate located between a first dummy gate and a second dummy gate, wherein the source of the transistor is defined in a first portion of the oxide-defined OD region, the first portion being located between the gate and the first dummy gate, and wherein the drain of the transistor is defined in a second portion of the oxide-defined OD region, the second portion being located between the gate and a first side of the second dummy gate. The additional structure includes: a first gate-oriented local interconnect coupled to a third portion of the oxide-defined OD region, the third portion being adjacent to a second side of the second dummy gate, the second side being opposite to the first side, wherein the third portion of the oxide-defined OD region can always be charged to a source voltage; a first diffusion-oriented local interconnect configured to couple the first gate-oriented local interconnect to the second dummy gate; and a via configured to couple the first diffusion-oriented local interconnect to a source voltage interconnect in a metal layer adjacent to the substrate.

2. The unit as described in claim 1, characterized in that, Further includes: Configured to couple to a second gate-oriented local interconnect that defines the portion of the source in the oxide-defined OD region; And a second diffused directional local interconnect configured to couple the first dummy gate to the second gate directional local interconnect.

3. The unit as described in claim 2, characterized in that, It further includes a via configured to couple the second gate oriented local interconnect to a source voltage interconnect in a metal layer adjacent to the substrate.

4. The unit as described in claim 1, characterized in that, The unit is the last unit in an array of units extending across the oxide-defined OD region, wherein the oxide-defined OD region extends from a first end to a second end, the second end being adjacent to the third portion and facing the first end.

5. The unit as described in claim 1, characterized in that, The unit is a first unit in a unit array extending across the oxide-defined OD region, wherein the oxide-defined OD region extends from a first end to a second end, the first end being adjacent to the third portion, and the second end being opposite to the first end.

6. The unit as described in claim 3, characterized in that, The first gate-oriented local interconnect and the first diffusion-oriented local interconnect are each local interconnects of stage 2, the unit further includes a first stage 1 gate-oriented local interconnect arranged between the first stage 2 gate-oriented local interconnect and the third portion to couple the first stage 2 gate-oriented local interconnect to the third portion, and wherein the via is a stage 3 local interconnect.

7. The unit as described in claim 6, characterized in that, The gate-oriented local interconnect of the first stage 1, the gate-oriented local interconnect of the first stage 2, and the diffusion-oriented local interconnect of the first stage 2 all include tungsten.

8. The unit as described in claim 6, characterized in that, The first dummy gate, the gate, and the second dummy gate are separated from each other according to the gate pitch.

9. The unit as claimed in claim 1, characterized in that, The oxide-defined OD region includes the PMOS OD region.

10. The unit as claimed in claim 1, characterized in that, The oxide-defined OD region includes the NMOS OD region.

11. A circuit comprising a plurality of units as described in claim 9, characterized in that, The plurality of units include a plurality of gates.

12. A circuit comprising a plurality of units as described in claim 1, characterized in that, It further includes additional oxides defining the OD region.

13. A circuit comprising a plurality of units as described in claim 1, characterized in that, The plurality of units include a plurality of transistors.

14. A method for forming a cell comprising only a single transistor and including additional structures, comprising: A continuous oxide-defined OD region is formed in the substrate; The transistor is formed by a gate arranged between a first dummy gate and a second dummy gate according to a gate pitch, wherein the source of the transistor is defined in a portion of the oxide-defined OD region between the gate and the first dummy gate, and wherein the drain of the transistor is defined in a portion of the oxide-defined OD region between a first side of the gate and the second dummy gate. And forming the additional structure includes: forming a first gate orientation local interconnect coupled to the oxide-defined OD region and adjacent to a portion of the second opposing side of the second dummy gate, wherein the portion of the oxide-defined OD region adjacent to the second opposing side of the second dummy gate can always be charged to the source voltage; A first diffused oriented local interconnect configured to couple the first gate oriented local interconnect to the second dummy gate is formed; and a via configured to couple the first gate oriented local interconnect to a source voltage supply is formed.

15. A unit comprising only a single transistor and including additional structures, said unit comprising: The continuous oxide layer defined in the substrate defines the OD region; A first dummy gate, wherein the oxide-defined OD region includes the drain of the transistor, the drain being adjacent to a first side of the first dummy gate and including a first portion adjacent to a second side of the dummy gate, the second side being opposite to the first side; and the additional structure including means for interconnecting the first dummy gate and the first portion to a source voltage supply, the means for interconnecting including diffusion-oriented local interconnects and gate-oriented local interconnects.

16. The unit as claimed in claim 15, characterized in that, The device includes a two-stage local interconnect structure extending between the first dummy gate and the first portion.

17. The unit as claimed in claim 15, characterized in that, It further includes: a gate; and a second dummy gate, wherein the oxide-defined OD region includes a source located between the second dummy gate and the gate.

18. The unit as claimed in claim 16, characterized in that, The two-level local interconnect structure includes tungsten.

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