semiconductor devices

Abstract

A semiconductor device includes: a first trench in a device region; a first device isolation layer with an active pattern defining the device region in the first trench; a second trench in an interface region; and a second device isolation layer in the second trench. The second device isolation layer includes a buried dielectric pattern, a dielectric pad pattern on the buried dielectric pattern, and a first gap-filling dielectric pattern on the dielectric pad pattern. The buried dielectric pattern includes a bottom section on the bottom surface of the second trench and sidewall sections on the sidewalls of the second trench. The thickness of the sidewall sections is different from the thickness of the bottom section.

Description

[0001] Cross-references to related applications

[0002] This non-provisional application claims priority to Korean Patent Application No. 10-2018-0168299, filed on December 24, 2018, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to semiconductor devices, and more specifically, to semiconductor devices including data storage elements. Background Technology

[0004] Semiconductor devices hold a vital position in the electronics industry due to their small size, versatility, and / or low manufacturing cost. Data storage devices within semiconductor devices store logical data. As the electronics industry evolves, data storage devices are becoming increasingly integrated. Consequently, the size (e.g., linewidth) of components that at least partially include data storage devices continues to decrease.

[0005] Furthermore, as the integration level of data storage devices increases, the demand for high reliability also grows. However, increased integration can lead to decreased reliability. Therefore, various studies have been conducted to improve the reliability of data storage devices. Summary of the Invention

[0006] Some exemplary embodiments of the present invention provide semiconductor devices with improved threshold voltage uniformity.

[0007] According to some exemplary embodiments of the present invention, a semiconductor device may include: a substrate including a device region and an interface region adjacent to the device region; a first trench in the device region; a first device isolation layer in the first trench, the first device isolation layer defining an active pattern of the device region; a second trench in the interface region; and a second device isolation layer in the second trench. The second isolation layer may include a buried dielectric pattern, a dielectric pad pattern on the buried dielectric pattern, and a first gap-filling dielectric pattern on the dielectric pad pattern. The buried dielectric pattern may include a bottom surface segment on the bottom surface of the second trench and a sidewall segment on the sidewall of the second trench. The thickness of the sidewall segment may be different from the thickness of the bottom surface segment.

[0008] According to some exemplary embodiments conceived in this invention, a semiconductor device may include: a first trench on a substrate extending in a first direction; a buried dielectric pattern on the sidewalls and bottom surface of the first trench; a dielectric pad pattern on the buried dielectric pattern; a first gap-filling dielectric pattern on the dielectric pad pattern and filling the first trench; and a plurality of second trenches extending in a second direction intersecting the first direction, the second trenches being shallower than the first trench. The buried dielectric pattern may include a bottom surface segment on the bottom surface of the first trench and a sidewall segment on the sidewall of the first trench, the thickness of the sidewall segment being different from the thickness of the bottom surface segment.

[0009] According to some exemplary embodiments of the present invention, a semiconductor device may include: a substrate including a first device region and a second device region and an interface region between the first device region and the second device region; a first trench and a second trench defining separate corresponding active patterns in the first and second active patterns on the first and second device regions; a third trench on the interface region; a first device isolation layer, a second device isolation layer, and a third device isolation layer in the separate corresponding trenches in the first, second, and third trenches; and a plurality of fourth trenches extending across the first and second active patterns. The third device isolation layer may include a buried dielectric pattern, a dielectric pad pattern on the buried dielectric pattern, and a first gap-filling dielectric pattern on the dielectric pad pattern and filling the third trench. The buried dielectric pattern may include a bottom section on the bottom surface of the third trench and a sidewall section on the sidewall of the third trench, the thickness of the sidewall section being greater than the thickness of the bottom section. Attached Figure Description

[0010] Figure 1 A plan view illustrating an example of a semiconductor device showing some exemplary embodiments of the concept according to the present invention is shown.

[0011] Figure 2A , Figure 2B and Figure 2C Examples of exemplary embodiments of the present invention are illustrated along the respective criterion. Figure 1 A sectional view taken from lines A-A', B-B', and C-C'.

[0012] Figure 3 , Figure 5 , Figure 7 , Figure 9 and Figure 11 Examples illustrating some exemplary embodiments of the invention are given. Figure 1 A plan view of the manufacturing method of the semiconductor device shown.

[0013] Figure 4A , Figure 6A , Figure 8A , Figure 10A and Figure 12A Examples of exemplary embodiments of the present invention are illustrated along the respective criterion. Figure 3 , Figure 5 , Figure 7 , Figure 9 and Figure 11 A sectional view taken by line A-A'.

[0014] Figure 4B , Figure 6B , Figure 8B , Figure 10B and Figure 12B Examples of exemplary embodiments of the present invention are illustrated along the respective criterion. Figure 3 , Figure 5 , Figure 7 , Figure 9 and Figure 11 The sectional view taken by line B-B'.

[0015] Figure 4C , Figure 6C , Figure 8C , Figure 10C and Figure 12C Examples of exemplary embodiments of the present invention are illustrated along the respective criterion. Figure 3 , Figure 5 , Figure 7 , Figure 9 and Figure 11 A sectional view taken by line C-C'.

[0016] Figure 13 and Figure 14 Examples illustrating the formation of some exemplary embodiments according to the concept of the present invention are given. Figure 5 The flowchart shows an example of a buried dielectric layer. Detailed Implementation

[0017] Figure 1 A plan view illustrating an example of a semiconductor device showing some exemplary embodiments of the concept according to the present invention is shown. Figure 2A and Figure 2B Examples of exemplary embodiments of the present invention are illustrated along the respective criterion. Figure 1 A cross-sectional view of a semiconductor device taken along lines A-A' and B-B'. Figure 2C Examples of some exemplary embodiments of the present invention are illustrated along the lines of the present invention. Figure 1 A cross-sectional view of the semiconductor device taken along line C-C' and a graph showing how the normalized thickness varies with the depth of the buried dielectric pattern.

[0018] Reference Figure 1 as well as Figures 2A to 2CThe semiconductor device may include a substrate W, which includes a first device region MCR, a second device region CPR, and an interface region IFR between the first device region MCR and the second device region CPR. In some example embodiments, the first device region MCR may be a memory cell region. The first device region MCR may include a data storage element DS. The data storage element DS may store data in response to signals from word lines WL and bit lines BL. The second device region CPR may be a core / peripheral circuitry region. The second device region CPR may include core / peripheral circuitry such as word line drivers, bit line drivers, and sense amplifiers, which write data to and read data from the data storage element DS via word lines WL and bit lines BL. The interface region IFR may be a field region separating the first device region MCR and the second device region CPR from each other. The interface region IFR may be adjacent to the respective device regions in the first device region MCR and the second device region CPR. Word lines WL and bit lines BL will be discussed further below.

[0019] The first device region MCR may include a first trench TR1, such that the first trench TR1 can be understood as being on the first device region MCR. A first device isolation layer ST1 may be disposed in the first trench TR1 of the first device region MCR. For example, at least... Figure 2A As shown, the first device isolation layer ST1 may partially or completely fill the first trench TR1. In some example embodiments, the first device isolation layer ST1 may include silicon oxide. The first device isolation layer ST1 may define an active pattern (including a first active pattern ACT1) of the first device region MCR. When viewed in a plan view, the first active pattern ACT1 may be discontinuously arranged in a diagonal direction in the first direction X and the second direction Y. The first active pattern ACT1 may have a channel region CH and a first source / drain region SD1 and a second source / drain region SD2. As at least Figure 2B As shown, the channel region CH may overlap with the word line WL in the Z direction, where Z can be understood as extending perpendicularly to the directions in which the first trench TR1, second trench TR2, third trench TR3, and fourth trench TR4 extend. The first source / drain region SD1 and the second source / drain region SD2 may be located on opposite sides of the word line WL. To reiterate, the first source / drain region SD1 may be on one side of the word line WL, and the second source / drain region SD2 may be on the other side. The distance between the first active patterns ACT1 may fall within the range of approximately 10 nm to approximately 300 nm. The first device isolation layer ST1 may be free of defects such as voids or gaps in the first trench TR1 between a pair of first active patterns ACT1. The defect-free first device isolation layer ST1 may provide improved threshold voltage uniformity for the first active patterns ACT1.

[0020] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, the associated numerical values ​​are intended to include a tolerance of ±10% to the left or right of the value. When a range is specified, the range includes all values ​​in increments such as 0.1%.

[0021] The second device region CPR may include a second trench TR2, such that the second trench TR2 can be understood as being on the second device region CPR. A second device isolation layer ST2 may be disposed within the second trench TR2 of the second device region CPR. For example, at least... Figure 2A As shown, the second device isolation layer ST2 may partially or completely fill the second trench TR2. The second device isolation layer ST2 may include silicon oxide. The second device isolation layer ST2 may define a second active pattern ACT2 for the second device region CPR. It will be understood that, as Figures 2A to 2C As shown, in some example embodiments, the first trench TR1 and the second trench TR2 may define separate corresponding active patterns of the first active pattern ACT1 and the second active pattern ACT2 on the first device region MCR and the second device region CPR. The second active pattern ACT2 may include core / peripheral circuitry.

[0022] The interface region IFR may include a third trench TR3, such that the third trench TR3 can be understood as being on the interface region IFR. A third device isolation layer ST3 may be disposed within the third trench TR3 of the interface region IFR. For example, at least... Figure 2A As shown, the third device isolation layer ST3 may partially or completely fill the third trench TR3. The third device isolation layer ST3 may be disposed between field patterns FR. The width of the third device isolation layer ST3 between field patterns FR may be greater than the width of the first device region MCR between a pair of first active patterns ACT1. In some example embodiments, the third device isolation layer ST3 may include a buried dielectric pattern BI, a dielectric pad pattern SN, and a first gap-filling dielectric pattern GP1.

[0023] A buried dielectric pattern BI may be disposed on the sidewalls and bottom surface of the third trench TR3. The buried dielectric pattern BI may be formed from the same layer as the first device isolation layer ST1 and the second device isolation layer ST2. In some example embodiments, the buried dielectric pattern BI may include silicon oxide. In some embodiments, the buried dielectric pattern BI may have a non-uniform thickness. In some example embodiments, the buried dielectric pattern BI may have a larger thickness on the sidewalls of the third trench TR3 and a smaller thickness on the bottom surface of the third trench TR3.

[0024] When the buried dielectric pattern BI has a uniform thickness, the first device isolation layer ST1 and the second device isolation layer ST2 may have defects such as voids or gaps. The occurrence of defects in the first device isolation layer ST1 and / or the second device isolation layer ST2 may depend on variations in the thickness of the buried dielectric pattern BI. For example, at least... Figure 2A As shown, the buried dielectric pattern BI may include a bottom section BP and a sidewall section SW. As shown, the bottom section BP may be disposed on the bottom surface TR3_F of the third trench TR3. As further shown, the sidewall section SW may be disposed on the sidewall TR3_SW of the third trench TR3. The thickness SW_T of the sidewall section SW may be different from the thickness BP_T of the bottom section BP. The thickness SW_T of the sidewall section SW may be less than the thickness BP_T of the bottom section BP. The thickness SW_T of the sidewall section SW may be greater than the thickness BP_T of the bottom section BP. In some example embodiments, the thickness SW_T of the sidewall section SW may gradually increase in the downstream direction or in the depth direction of the third trench TR3. When the thickness SW_T of the sidewall section SW increases in the depth direction of the third trench TR3, the first device isolation layer ST1 and the second device isolation layer ST2 may not have defects such as voids or gaps. Conversely, when the thickness SW_T of the sidewall segment SW decreases or remains constant in the depth direction of the third trench TR3, the first device isolation layer ST1 and the second device isolation layer ST2 may have defects such as voids or gaps.

[0025] Such as at least Figure 2A As shown, a dielectric pad pattern SN may be disposed on a buried dielectric pattern BI. The dielectric pad pattern SN may have a uniform thickness. The dielectric pad pattern SN may include silicon nitride.

[0026] Such as at least Figure 2A As shown, a first gap-filling dielectric pattern GP1 may be disposed on a dielectric pad pattern SN. The first gap-filling dielectric pattern GP1 may partially or completely fill the third trench TR3. In some example embodiments, the first gap-filling dielectric pattern GP1 may include silicon oxide. The density of the first gap-filling dielectric pattern GP1 may be less than the density of the buried dielectric pattern BI.

[0027] exist Figure 2A and Figure 2B In the diagram, the second trench TR2 is shown to have a width similar to that of the first trench TR1. When the width of the second trench TR2 is greater than the width of the first trench TR1, the second device isolation layer ST2 may include a buried dielectric pattern, a dielectric pad pattern, and a first gap-filling dielectric pattern. The buried dielectric pattern of the second device isolation layer ST2 may have a thicker sidewall section and a thinner bottom section.

[0028] Further reference Figure 1 as well as Figures 2A to 2C At least one pair of fourth trenches TR4 (e.g., multiple fourth trenches TR4) may be disposed on the first active pattern ACT1. Each fourth trench TR4 may be defined between a first source / drain region SD1 and a second source / drain region SD2 of the first active pattern ACT1. Each fourth trench TR4 may be configured to extend (“extend”) across the first active pattern ACT1, the second active pattern ACT2, the field pattern FR, and the first device isolation layer ST1, the second device isolation layer ST2, and the third device isolation layer ST3. The depth of each fourth trench TR4 may be less than the depth of the first trench TR1, the second trench TR2, and the third trench TR3. Each fourth trench TR4 may extend in a first direction X. The fourth trench TR4 may intersect with the third trench TR3. When each fourth trench TR4 extends in the first direction X, the third trench TR3 intersecting with the fourth trench TR4 may extend in the second direction Y.

[0029] A first-line structure LST1 may be disposed in each of the fourth trenches TR4. In some example embodiments, the first-line structure LST1 may include a gate dielectric pattern GI, word lines WL, and a second gap-filling dielectric pattern GP2. Therefore, it will be understood that multiple word lines WL may be disposed in separate, respective fourth trenches TR4. The gate dielectric pattern GI may be disposed on the lower inner wall of the fourth trench TR4. The gate dielectric pattern GI may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric material. In some example embodiments, the high-k dielectric material may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. The word lines WL may be disposed on the gate dielectric pattern GI. The word lines WL may fill the lower portion of the fourth trench TR4. The word line WL may include one or more of conductive metal nitrides (e.g., titanium nitride or tantalum nitride) and metals (e.g., titanium, tantalum, tungsten, copper, or aluminum). A second gap-filling dielectric pattern GP2 may be disposed on the word line WL. Therefore, it will be understood that a plurality of second gap-filling dielectric patterns GP2 may be disposed on separate corresponding word lines WL. The second gap-filling dielectric pattern GP2 may fill the upper portion of the fourth trench TR4. The top surface of the second gap-filling dielectric pattern GP2 may be coplanar with the top surfaces of the first device isolation layer ST1, the second device isolation layer ST2, and the third device isolation layer ST3. The second gap-filling dielectric pattern GP2 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0030] Reference Figures 2A to 2C The sidewall section SW of the buried dielectric pattern BI may include a lower LP, a middle MP, and an upper UP.

[0031] The lower LP can be disposed between the bottom surface SN_BS of the dielectric pad pattern SN and the bottom surface TR4_F of the fourth trench TR4. The lower LP can also be on the sidewall TR3_SW of the third trench TR3. In some example embodiments, the lower LP can be disposed between the lower corner SN_LC of the dielectric pad pattern SN and the bottom surface TR4_F of the fourth trench TR4. The thickness LP_T of the lower LP can be greater than the thickness BP_T of the bottom surface segment BP. In some example embodiments, the thickness LP_T of the lower LP can be approximately 1.2 times the thickness BP_T of the bottom surface segment BP. When the thickness BP_T of the bottom surface segment BP is approximately 30 nm, the thickness LP_T of the lower LP can be approximately 36 nm.

[0032] The middle MP can be disposed on the lower LP. The middle MP can be disposed between a pair of word lines WL. In some example embodiments, the middle MP can be disposed between a pair of gate dielectric patterns GI. The thickness MP_T of the middle MP can be less than the thickness LP_T of the lower LP and greater than the thickness BP_T of the bottom segment BP. The thickness MP_T of the middle MP can be greater than the thickness UP_T of the upper UP.

[0033] The upper UP can be disposed on the middle MP. The upper UP can be disposed between a pair of second gap-filled dielectric patterns GP2. Therefore, it will be understood that the upper UP can be between adjacent second gap-filled dielectric patterns GP2 among a plurality of second gap-filled dielectric patterns GP2. The thickness UP_T of the upper UP can be less than each of the thickness MP_T of the middle MP and the thickness LP_T of the lower LP. The thickness UP_T of the upper UP can be greater than the thickness BP_T of the bottom segment BP. The thickness UP_T of the upper UP can be approximately 1.1 times the thickness BP_T of the bottom segment BP. When the thickness BP_T of the bottom segment BP is approximately 30 nm, the thickness UP_T of the upper UP can be approximately 36 nm.

[0034] Return to reference Figure 1 as well as Figures 2A to 2C The first interlayer dielectric layer IL1 can be disposed on the substrate W. The first interlayer dielectric layer IL1 can selectively expose the first source / drain region SD1 of the first active pattern ACT1.

[0035] A second line structure LST2 extending in the second direction Y may be disposed on the first interlayer dielectric layer IL1. The second line structures LST2 may be spaced apart from each other in the first direction X. When viewed in a plan view, the second line structures LST2 may intersect with the word line WL. A pair of spacers SP may be disposed on opposite sidewalls of the second line structures LST2. The spacers SP may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0036] The second-line structure LST2 may include sequentially stacked conductive patterns CP, barrier patterns BA, bit lines BL, and dielectric capping patterns IC. For example, at least... Figure 2A As shown, the bit line BL may be on the first source / drain region SD1. A conductive pattern CP may selectively contact the first source / drain region SD1. A blocking pattern BA may suppress the diffusion of metallic material in the bit line BL toward the conductive pattern CP. The bit line BL may be electrically connected to the first source / drain region SD1 through the blocking pattern BA and the conductive pattern CP.

[0037] The conductive pattern CP may include one of a doped semiconductor material (e.g., doped silicon or doped germanium), a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). The blocking pattern BA may include a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The bit line BL may include a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0038] The second interlayer dielectric layer IL2 can be disposed on the first interlayer dielectric layer IL1. The second interlayer dielectric layer IL2 can cover the spacer SP. The contact hole CNH can be configured to penetrate the second interlayer dielectric layer IL2 and the first interlayer dielectric layer IL1 and expose the second source / drain region SD2.

[0039] The contact CNT may be disposed in the contact hole CNH. The contact CNT may contact the second source / drain region SD2. The spacer SP may separate the contact CNT from the bit line BL. The contact CNT may include one or more of conductive metal nitrides (e.g., titanium nitride or tantalum nitride) and metals (e.g., titanium, tantalum, tungsten, copper or aluminum).

[0040] The data storage element DS can be mounted on the contact CNT. For example, at least... Figure 2A As shown, the data storage element DS may be located on the second source / drain region SD2. The data storage element DS may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and a variable resistance layer including a phase change material. In some example embodiments, the data storage element DS may be a capacitor.

[0041] The manufacturing method of the semiconductor device configured as described above will be described below.

[0042] Figure 3 , Figure 5 , Figure 7 , Figure 9 and Figure 11 Examples illustrating some exemplary embodiments of the invention are given. Figure 1 A plan view of the manufacturing method of the semiconductor device shown. Figure 4A , Figure 6A , Figure 8A , Figure 10A and Figure 12A Examples of exemplary embodiments of the present invention are illustrated along the respective criterion. Figure 3 , Figure 5 , Figure 7 , Figure 9 and Figure 11 A sectional view taken by line A-A'. Figure 4B , Figure 6B , Figure 8B , Figure 10B and Figure 12B Examples of exemplary embodiments of the present invention are illustrated along the respective criterion. Figure 3 , Figure 5 , Figure 7 , Figure 9 and Figure 11 The sectional view taken by line B-B'. Figure 4C , Figure 6C , Figure 8C , Figure 10C and Figure 12C Examples of exemplary embodiments of the present invention are illustrated along the respective criterion. Figure 3 , Figure 5 , Figure 7 , Figure 9 and Figure 11 A sectional view taken by line C-C'.

[0043] Reference Figure 3 as well as Figures 4A to 4C The upper portion of the substrate W can be patterned to form a first active pattern ACT1, a second active pattern ACT2, and a field pattern FR. The first active pattern ACT1 and the second active pattern ACT2 may have a first conductive region implanted with a first dopant. The first active pattern ACT1 and the second active pattern ACT2 may be divided by a first trench TR1 and a second trench TR2, respectively, and a pair of field patterns FR may be divided by a third trench TR3. The first trench TR1 may be defined between a pair of first active patterns ACT1. The second trench TR2 may be defined between adjacent second active patterns ACT2. The third trench TR3 may be defined by a pair of field patterns FR. The width of the first trench TR1 may be smaller than the width of the third trench TR3.

[0044] Reference Figure 5 as well as Figures 6A to 6C A buried dielectric layer (PBI) can be formed on the substrate W.

[0045] Figure 13 Examples illustrating the formation of some exemplary embodiments according to the concept of the present invention are given. Figure 5 The flowchart shown is an example of a buried dielectric layer (PBI).

[0046] Reference Figure 13The formation of the buried dielectric layer (PBI) may include performing advanced atomic layer deposition (ALD) or practical atomic layer deposition (ALD). In some example embodiments, the formation of the buried dielectric layer (PBI) may include performing advanced chemical vapor deposition (CVD) or practical chemical vapor deposition (CVD). In some example embodiments, the formation of the buried dielectric layer (PBI) may include providing a first reactant (S10), providing a first plasma (S20), providing a first purge gas (S30), providing a second reactant (S40), and providing a second purge gas (S60).

[0047] Reference Figure 5 , Figures 6A to 6C as well as Figure 13 The first reactant can be provided onto the substrate W (S10). The first reactant can be deposited or adsorbed onto the entire surface of the substrate W. In some example embodiments, the first reactant may include a silicon-containing reactant. The first reactant may be a silane, a halosilane, or an aminosilane. Silanes may include silane (SiH4), silane (Si2H6), or organosilanes such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane, isopentylsilane, tert-butyldisilane, di-tert-butylsilane, and tetraethyl orthosilicate (TEOS, also known as tetraethoxysilane). Halosilanes may include iodosilane, bromosilane, chlorosilane, or fluorosilane. Aminosilanes may include monoaminosilanes, diaminosilanes, triaminosilanes, tetraaminosilanes, tert-butylaminosilanes, methylaminosilanes, tert-butylsilaneamines, or bis(tert-butylamino)silanes.

[0048] A first plasma can be provided onto the substrate W (S20). The first plasma can be primarily provided on the top surface of the first active pattern ACT1, the top surface of the second active pattern ACT2, the top surface of the field pattern FR, and the bottom surface of the third trench TR3. The first plasma can partially remove first reactants from the top surfaces of the first active pattern ACT1, the second active pattern ACT2, the field pattern FR, and the bottom surface of the third trench TR3. The first reactants can be retained in the first trench TR1 and the second trench TR2. The first reactants can also be retained on the sidewalls of the third trench TR3.

[0049] A first purge gas may be provided to the substrate W (S30). The first purge gas may include nitrogen (N2).

[0050] A second reactant may be provided onto the substrate W (S40). The second reactant may include an oxidizing reactant. The oxidizing reactant may be oxygen, ozone, nitrous oxide, or carbon monoxide. The second reactant and the first reactant may react to form a buried dielectric layer PBI.

[0051] A second purge gas may be provided to the substrate W (S60). The second purge gas may include nitrogen (N2). The second purge gas can remove gases after the first reactant and the second reactant have reacted.

[0052] Steps S10 to S60 can be repeated until the buried dielectric layer PBI fills the first trench TR1 and the second trench TR2. The buried dielectric layer PBI may have an irregular thickness in the third trench TR3. The buried dielectric layer PBI may include a bottom layer BPL and a sidewall layer SWL. The bottom layer BPL may be formed to be thinner than the sidewall layer SWL.

[0053] Figure 14 Examples illustrating the formation of some exemplary embodiments according to the concept of the present invention are given. Figure 5 The flowchart illustrates an example of a buried dielectric layer (PBI). In some example embodiments, it is consistent with the above reference. Figure 13 Detailed descriptions of the repetitive technical features of the formation of the buried dielectric layer (PBI) will be omitted, and the differences will be described in detail.

[0054] Reference Figure 14 The formation of the buried dielectric layer PBI may further include providing a second plasma (S50). Providing the second plasma (S50) may be performed between providing a second reactant (S40) and providing a second purge gas (S60). The second plasma may partially remove the buried dielectric layer PBI from the top surface of the first active pattern ACT1, the top surface of the second active pattern ACT2, the top surface of the field pattern FR, and the bottom surface of the third trench TR3. The buried dielectric layer PBI may remain in the first trench TR1 and the second trench TR2. The buried dielectric layer PBI may also remain on the sidewalls of the third trench TR3. In the third trench TR3, the sidewall layer SWL of the buried dielectric layer PBI may be formed to be thicker than the bottom layer BPL of the buried dielectric layer PBI.

[0055] Return to reference Figure 5 as well as Figures 6A to 6C The buried dielectric layer PBI can fill the first trench TR1 without creating defects such as voids or gaps. When the first trench TR1 fills the buried dielectric layer PBI without defects such as voids or gaps, the first active pattern ACT1 can improve the uniformity of the threshold voltage. When the buried dielectric layer PBI has defects such as voids or gaps, the first active pattern ACT1 can reduce the uniformity of the threshold voltage.

[0056] A dielectric liner layer and a first gap-filling dielectric layer can be formed on the buried dielectric layer PBI. The dielectric liner layer can be conformally formed. The dielectric liner layer may include silicon nitride formed by atomic layer deposition (ALD). The first gap-filling dielectric layer may include silicon oxide, such as TOSZ (tonen silazane), USG (undoped silicate glass), BPSG (borophosphosilicate glass), PSG (phosphosilicate glass), FOX (flowable oxide), PE-TEOS (plasma-enhanced tetraethyl orthosilicate), or FSG (fluorosilicate glass). The first gap-filling dielectric layer may fill a third trench TR3. The first gap-filling dielectric layer may partially fill a second trench TR2.

[0057] Reference Figure 7 as well as Figures 8A to 8C The dielectric pad layer and the first gap-filling dielectric layer can be partially polished to form the dielectric pad pattern SN and the first gap-filling dielectric pattern GP1. The dielectric pad layer can be used as a polishing barrier.

[0058] A wet etching process can be performed to wet-etch a buried dielectric layer PBI on a first active pattern ACT1 and a second active pattern ACT2 to form a buried dielectric pattern BI. The buried dielectric pattern BI may include a bottom segment BP and a sidewall segment SW. The sidewall segment SW may be thicker than the bottom segment BP. The dielectric pad pattern SN and the first gap-filling dielectric pattern GP1 can be partially removed by the wet etching process performed on the buried dielectric layer PBI. The wet etching process may use an etchant comprising a strong acid (e.g., LAL solution or phosphoric acid). The substrate W may be planarized by etching.

[0059] Reference Figure 9 as well as Figures 10A to 10C The upper portion of the substrate W can be patterned to form a fourth trench TR4. When viewed in a plan view, the fourth trench TR4 can have a linear shape extending in the first direction X.

[0060] The formation of the fourth trench TR4 may include forming a hard mask pattern with openings and performing an etching process, wherein the hard mask pattern serves as an etching mask to partially etch the first active pattern ACT1 and the second active pattern ACT2, the field pattern FR, and the first device isolation layer ST1, the second device isolation layer ST2, and the third device isolation layer ST3. Figures 2A to 2C As shown, the fourth trench TR4 may be shallower than the first trench TR1, the second trench TR2, and the third trench TR3.

[0061] During the etching process, the first device isolation layer ST1, the second device isolation layer ST2, and the third device isolation layer ST3 may be etched in greater depth than the first active pattern ACT1, the second active pattern ACT2, and the field pattern FR. The first active pattern ACT1 and the second active pattern ACT2 in the fourth trench TR4 may protrude in the third direction Z relative to the first device isolation layer ST1 and the second device isolation layer ST2. In some example embodiments, the first active pattern ACT1 and the second active pattern ACT2 in the fourth trench TR4 may have a fin shape.

[0062] A gate dielectric pattern GI, a word line WL, and a second gap-filling dielectric pattern GP2 may be formed in each of the fourth trenches TR4. In some example embodiments, a gate dielectric layer may be conformally formed in the fourth trenches TR4. The gate dielectric layer may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric material. A conductive layer may be formed on the gate dielectric layer to fill the fourth trenches TR4. The conductive layer may include one or more of a metal and a conductive metal nitride. The conductive layer and the gate dielectric layer may be recessed to form the gate dielectric pattern GI and the word line WL. A second gap-filling dielectric pattern GP2 may be formed in the upper portion of the fourth trenches TR4 where the gate dielectric pattern GI and the word line WL are formed. The top surface of the second gap-filling dielectric pattern GP2 may be coplanar with the top surfaces of the first active pattern ACT1, the second active pattern ACT2, the field pattern FP, and the first device isolation layer ST1, the second device isolation layer ST2, and the third device isolation layer ST3. The sidewall segment SW of the buried dielectric pattern BI may include a lower LP, a middle MP, and an upper UP. The lower LP may be defined between the bottom surface of the dielectric pad pattern SN and the bottom surface of the fourth trench TR4. The middle MP may be disposed between a pair of word lines WL. The upper UP may be defined between a pair of second gap-filling dielectric patterns GP2.

[0063] Reference Figure 11 as well as Figures 12A to 12C An implantation process can be performed to implant a second dopant into a first active pattern ACT1 and a second active pattern ACT2. The second dopant may have a conductivity type different from that of the first dopant.

[0064] A first source / drain region SD1 and a pair of second source / drain regions SD2 may be defined on the upper portion of the first active pattern ACT1. The pair of second source / drain regions SD2 may span across the first source / drain region SD1 and be spaced apart from each other.

[0065] The channel region CH can be defined as the first active pattern ACT1 below the word line WL. When viewed in a plan view, the channel region CH can be inserted between the first source / drain region SD1 and the second source / drain region SD2. The word line WL can be disposed on the top surface and opposite sidewalls of the channel region CH.

[0066] A first interlayer dielectric layer IL1, a second line structure LST2, and a spacer SP can be formed on the substrate W.

[0067] A first interlayer dielectric layer IL1 may be formed on the entire surface of the substrate W. In some example embodiments, the first interlayer dielectric layer IL1 may include a silicon oxide layer. The first interlayer dielectric layer IL1 may be patterned to selectively expose a first source / drain region SD1.

[0068] A first conductive layer, a barrier layer, and a second conductive layer may be sequentially formed on the exposed first source / drain region SD1 and the first interlayer dielectric layer IL1. The first conductive layer may be in contact with and / or connected to the first source / drain region SD1. The first interlayer dielectric layer IL1 may perpendicularly separate the first conductive layer from the second source / drain region SD2 of the first active pattern ACT1. The first conductive layer may include one of a doped semiconductor material, a metallic material, and a metal-semiconductor compound.

[0069] A barrier layer may be formed between a first conductive layer and a second conductive layer. The barrier layer may include a conductive metal nitride. The second conductive layer may include a metallic material. The barrier layer may inhibit the diffusion of the metallic material in the second conductive layer toward the first conductive layer.

[0070] A dielectric capping pattern IC can be formed on the second conductive layer. The dielectric capping pattern IC can be formed with a linear shape extending in the second direction Y. In some example embodiments, the dielectric capping pattern IC may include a silicon nitride layer or a silicon oxynitride layer.

[0071] The dielectric capping pattern IC can be used as an etching mask to sequentially etch a second conductive layer, a barrier layer, and a first conductive layer to form a bit line BL, a barrier pattern BA, and a conductive pattern CP, respectively. The dielectric capping pattern IC, bit line BL, barrier pattern BA, and conductive pattern CP can overlap perpendicularly to each other. The dielectric capping pattern IC, bit line BL, barrier pattern BA, and conductive pattern CP can constitute a second line structure LST2.

[0072] The conductive pattern CP and the blocking pattern BA can be connected to the first source / drain region SD1. The bit line BL can be electrically connected to the first source / drain region SD1 through the conductive pattern CP and the blocking pattern BA. When viewed in a planar diagram, the bit line BL may intersect with the word line WL.

[0073] A pair of spacers SP can be formed on opposite sidewalls of each second line structure LST2. The formation of spacers SP may include conformally forming a spacer layer on the entire surface of the substrate 100 and anisotropically etching the spacer layer.

[0074] Return to reference Figure 1 as well as Figures 2A to 2C A second interlayer dielectric layer IL2 can be formed on the substrate W. In some example embodiments, the second interlayer dielectric layer IL2 may include a silicon oxide layer. A planarization process can be performed on the second interlayer dielectric layer IL2 until the top surface of the dielectric capping pattern IC is exposed.

[0075] A patterning process can be performed such that the second interlayer dielectric layer IL2 and the first interlayer dielectric layer IL1 are patterned to form a contact hole CNH that exposes the second source / drain region SD2 of the first active pattern ACT1. Because the dielectric capping pattern IC and the spacer SP are used as etching masks during the patterning process, the contact hole CNH can be formed in a self-aligned manner.

[0076] The contact hole CNH may be filled with a conductive material to form a contact CNT. The contact CNT may be connected to a second source / drain region SD2. Data storage elements DS may be formed on each contact CNT. In some example embodiments, the data storage element DS may be a capacitor.

[0077] According to the present invention, semiconductor devices can use defect-free device isolation layers to improve the uniformity of threshold voltage of active patterns.

[0078] Some exemplary embodiments have been described in the specification and accompanying drawings. Although specific terms are used herein, they are for descriptive purposes only and not to limit the technical meaning or scope of the inventive concept disclosed in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments can be derived from the inventive concept. In summary, the true technical scope of the inventive concept to be protected should be determined by the technical concept of the appended claims.

Claims

1. A semiconductor device, comprising: A substrate, comprising a device region and an interface region adjacent to the device region; A first trench is located in the device region; A first device isolation layer is located in the first trench, and the first device isolation layer defines an active pattern of the device region; A second trench is present in the interface region; as well as A second device isolation layer is located in the second trench. The second device isolation layer includes: Buried dielectric pattern, Dielectric pad pattern, which is on the buried dielectric pattern, and The first gap is filled with a dielectric pattern, which is located on the dielectric pad pattern. The buried dielectric pattern includes: The bottom section, which is on the bottom surface of the second trench, and A sidewall section, located on the sidewall of the second trench, has a thickness different from that of the bottom section. Wherein, the thickness of the sidewall section is greater than the thickness of the bottom section, and The semiconductor device further includes a plurality of third trenches, each of the plurality of third trenches extending across the first trench and the second trench. The sidewall section includes a lower portion between the bottom surface of the dielectric pad pattern and the bottom surface of the third trench, and the thickness of the lower portion is greater than the thickness of the bottom surface section.

2. The semiconductor device according to claim 1, wherein, The thickness of the lower part is 1.2 times the thickness of the bottom section.

3. The semiconductor device according to claim 1, wherein, The sidewall section also includes an upper portion on the lower portion between the third grooves, the thickness of the lower portion being greater than the thickness of the upper portion.

4. The semiconductor device according to claim 3, wherein, The thickness of the upper part is greater than the thickness of the bottom section.

5. The semiconductor device according to claim 4, wherein, The thickness of the upper part is 1.1 times the thickness of the bottom section.

6. The semiconductor device according to claim 4, wherein The sidewall section also includes a middle section between the lower part and the upper part, and The thickness of the middle part is greater than the thickness of the upper part and less than the thickness of the lower part.

7. The semiconductor device according to claim 4, further comprising: Multiple word lines, which are separated in corresponding third grooves in the plurality of third grooves; as well as Multiple second gaps are filled with dielectric patterns on corresponding word lines separated from the multiple word lines. The upper part is located between adjacent second gap-filling dielectric patterns in the plurality of second gap-filling dielectric patterns.

8. The semiconductor device according to claim 1, wherein The buried dielectric pattern and the first gap-filling dielectric pattern each comprise silicon oxide, and The density of the buried dielectric pattern is greater than the density of the first gap-filling dielectric pattern.

9. A semiconductor device, comprising: A first trench, which is on the substrate, extends in a first direction; A dielectric pattern is buried on the sidewalls and bottom surface of the first trench; Dielectric pad pattern, which is on the buried dielectric pattern; The first gap is filled with a dielectric pattern, which is on the dielectric pad pattern and fills the first groove; as well as Multiple second grooves extend in a second direction intersecting the first direction, and the second grooves are shallower than the first grooves. The buried dielectric pattern includes: The bottom section, which lies on the bottom surface of the first trench, and A sidewall section, located on the sidewall of the first trench, has a thickness different from that of the bottom surface section. The sidewall section includes a lower portion on the sidewall of the first trench between the bottom surface of the dielectric pad pattern and the bottom surface of one of the plurality of second trenches, the thickness of the lower portion being greater than the thickness of the bottom section.

10. The semiconductor device according to claim 9, wherein, The sidewall section also includes an upper portion on the lower portion, the thickness of the lower portion being greater than the thickness of the upper portion.

11. The semiconductor device according to claim 10, wherein, The thickness of the upper part is greater than the thickness of the bottom section.

12. The semiconductor device of claim 10, wherein... The thickness of the upper part is 1.1 times the thickness of the bottom section, and The thickness of the lower part is 1.1 times the thickness of the bottom section.

13. A semiconductor device, comprising: A substrate comprising a first device region and a second device region and an interface region between the first device region and the second device region; The first trench and the second trench define separate corresponding active patterns in the first active pattern and the second active pattern on the first device region and the second device region, respectively. A third trench is located on the interface region; A first device isolation layer, a second device isolation layer, and a third device isolation layer are located in separate corresponding trenches of the first trench, the second trench, and the third trench; as well as Multiple fourth trenches extend across the first active pattern and the second active pattern. The third device isolation layer includes: Buried dielectric pattern, Dielectric pad pattern, which is on the buried dielectric pattern, and The first gap is filled with a dielectric pattern, which is located on the dielectric pad pattern and fills the third trench. The buried dielectric pattern includes: The bottom section, on the bottom surface of the third trench, and A sidewall section, located on the sidewall of the third trench, wherein the thickness of the sidewall section is greater than the thickness of the bottom section.

14. The semiconductor device according to claim 13, further comprising: The first line structure, in each of the plurality of fourth trenches The first line structure includes: Gate dielectric pattern, Word lines, which extend on the gate dielectric pattern and in a first direction, and The second gap is filled with a dielectric pattern on the word line.

15. The semiconductor device according to claim 14, wherein, The first active pattern includes: The channel region overlaps with the letter lines in a direction perpendicular to the extending directions of the first, second, third, and fourth grooves. The first source / drain region, on one side of the word line, and The second source / drain region is located on the other side of the word line.

16. The semiconductor device of claim 15, further comprising: Bit lines are located in the first source / drain region and extend in a second direction that intersects the first direction. as well as Data storage element located in the second source / drain region.

17. The semiconductor device of claim 14, wherein The first device region is a memory cell region. The second device region is the core / peripheral circuit region, and The interface region is the field region.

Images