Fusion memory device and method of manufacturing the same

Abstract

Fused memory devices and methods of manufacturing the same are disclosed. A fused memory device includes a first memory device including a first substrate having an active surface and an inactive surface opposite each other and first memory cell circuitry on the active surface of the first substrate, a non-memory device including a second substrate having an active surface and an inactive surface opposite each other and non-memory circuitry on the active surface of the second substrate, the non-memory device disposed on the first memory device, and a second memory device on the inactive surface of the second substrate and including second memory cell circuitry different from the first memory cell circuitry. The non-memory device is disposed between the first memory cell circuitry and the second memory cell circuitry and controls electrical operation of each of the first memory cell circuitry and the second memory cell circuitry.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0167111, filed on December 21, 2018, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more specifically, to a fused memory device in which heterogeneous memory devices are merged together and a method for manufacturing the same. Background Technology

[0004] Attempts have been made to combine heterogeneous memory devices to take advantage of their different electrical characteristics. Here are examples of fused memory devices: combinations of non-volatile memory devices (such as NAND flash or NOR flash) and volatile memory devices (such as SRAM or DRAM), or combinations of volatile memory devices (such as flash, PRAM, MRAM, or RRAM).

[0005] One method of combining heterogeneous memory devices includes stacking the heterogeneous memory devices and electrically connecting them to each other using bonding wires or through electrodes. This method is advantageous for compatibility when manufacturing heterogeneous memory devices, but disadvantageous for reducing the manufacturing cost of individual memory devices and ensuring sufficient area for bonding wires.

[0006] Another method for combining heterogeneous memory devices involves forming peripheral circuitry for driving each memory device and performing sequential processing to sequentially form heterogeneous memory devices stacked on the peripheral circuitry. In this method, the pre-formed peripheral circuitry or memory devices are affected by subsequent processing required to form other memory devices. For example, when performing subsequent processing at high temperatures, heat may degrade the electrical characteristics of the pre-formed peripheral circuitry or memory devices. Therefore, limitations may exist in forming memory devices with desired electrical performance.

[0007] As mentioned above, the sequential fabrication of heterogeneous memory devices may lack processing compatibility. Therefore, there may be a need for fused memory devices and their manufacturing methods that possess the desired electrical performance unaffected by subsequent processing. Summary of the Invention

[0008] Some exemplary embodiments of the present invention provide a fused memory device and a method for manufacturing the same, which are unaffected by subsequent processing.

[0009] Some exemplary embodiments of the present invention provide a fusion memory device with desired electrical performance and a method for manufacturing the same.

[0010] Some exemplary embodiments of the present invention provide a fusion memory device and a method for manufacturing the same that ensures compatibility.

[0011] According to an example embodiment, this disclosure relates to a fused memory device, comprising: a first memory device including a first substrate having active and passive surfaces opposite each other and a first memory cell circuit located on the active surface of the first substrate; a non-memory device including a second substrate having active and passive surfaces opposite each other and a non-memory circuit located on the active surface of the second substrate, the non-memory device being disposed on the first memory device; and a second memory device located on the passive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit, wherein the non-memory device is disposed between the first memory cell circuit and the second memory cell circuit and is configured to control the electrical operation of each of the first memory cell circuit and the second memory cell circuit.

[0012] According to an example embodiment, this disclosure relates to a fused memory device, comprising: a lower memory device including a lower substrate having active and passive surfaces opposite each other and a plurality of lower memory cells stacked on the active surfaces of the lower substrate; a non-memory device including an upper substrate having active and passive surfaces opposite each other and a plurality of wires located on the active surfaces of the upper substrate, the non-memory device being stacked on the lower memory device; and an upper memory device including a plurality of upper memory cells different from the lower memory cells and stacked on the passive surfaces of the upper substrate, the upper memory device being stacked on the non-memory device, wherein the upper memory cells and the lower memory cells are electrically connected to the wires.

[0013] According to an example embodiment, this disclosure relates to a method of manufacturing a fused memory device, the method comprising: forming a first memory cell circuit including a plurality of first memory cells on an active surface of a first substrate; forming a non-memory circuit including a plurality of wires on an active surface of a second substrate; combining the first memory cell circuit with the non-memory circuit; and forming a second memory cell circuit including a plurality of second memory cells on a passive surface of the second substrate, wherein forming the first memory cell circuit and forming the non-memory circuit are performed independently of each other, and wherein the temperature at which the first memory cell circuit is formed is higher than the temperature at which the second memory cell circuit is formed. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view illustrating the process of forming a first semiconductor device in a method of manufacturing a fused memory device according to some exemplary embodiments of the present invention.

[0015] Figure 2This is a cross-sectional view illustrating the process of forming a second semiconductor device in a method of manufacturing a fused memory device according to some example embodiments of the present invention.

[0016] Figure 3 This is a cross-sectional view illustrating the process of combining a first semiconductor device and a second semiconductor device in a method of manufacturing a fused memory device according to some exemplary embodiments of the present invention.

[0017] Figure 4 This is a cross-sectional view illustrating a substrate thinning process in a method for manufacturing a fused memory device according to some exemplary embodiments of the present invention.

[0018] Figure 5 This is a cross-sectional view illustrating the process of forming a third semiconductor device in a method of manufacturing a fused memory device according to some example embodiments of the present invention.

[0019] Figure 6 This is a cross-sectional view showing some example embodiments of a converged memory device according to the present invention.

[0020] Figure 7 This is a cross-sectional view showing some example embodiments of a converged memory device according to the present invention.

[0021] Figure 8 This is a cross-sectional view showing some example embodiments of a converged memory device according to the present invention.

[0022] Figure 9 This is a cross-sectional view showing some example embodiments of a converged memory device according to the present invention. Detailed Implementation

[0023] The fused memory device and its manufacturing method will now be described in detail below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals denote the same elements.

[0024] For ease of description, this document may use spatially relative terms such as “below,” “below,” “down,” “above,” and “up” to describe the relationship between one element or feature and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations shown in the drawings, the spatially relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “below” the other element or feature will be oriented as “above” the other element or feature. Thus, the term “below” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein shall be interpreted accordingly.

[0025] Figure 1 This is a cross-sectional view illustrating the process of forming a first semiconductor device in a method of manufacturing a fused memory device according to some exemplary embodiments of the present invention.

[0026] Reference Figure 1 A first semiconductor device D1, comprising a first substrate 111 and a first circuit 110, may be provided. The first semiconductor device D1, and other devices described herein, may be implemented as a semiconductor chip (e.g., an integrated circuit device portion of a wafer or an integrated circuit device diced from a wafer). The first substrate 111 may have an active surface 111a and an opposite passive surface 111b. The first substrate 111 may be a semiconductor substrate, such as crystalline silicon (e.g., a portion of a silicon substrate wafer). The first substrate 111 may have the first circuit 110 encapsulated in a dielectric layer 119 in and / or on its active surface 111a. The dielectric layer 119 may have a multilayer structure in which multiple layers of one or both of silicon oxide and silicon nitride are stacked. The active surface of the substrate or semiconductor device as described herein corresponds to the surface of the substrate on which various patterned layers of the semiconductor device are sequentially formed during device fabrication (i.e., patterned layers integrally formed as part of a semiconductor chip during device fabrication, or semiconductor devices integrally formed in a wafer to form an integrated circuit). The active surface of a semiconductor device (chip) can be the upper surface of the semiconductor chip above the active surface of the substrate (or, the upper surface of the wafer on which the semiconductor device is formed before the wafer is divided into multiple semiconductor chips through a singulation process). The passive surface used herein refers to the surface of the substrate or device opposite the active surface (sometimes called the back side). The passive surface of the device can be the same as the passive surface of the substrate.

[0027] The first circuit 110 may include a plurality of gate electrodes 112 stacked in a stepped manner on the active surface 111a of the first substrate 111, a plurality of cylindrical vertical channels 113 having perpendicular penetrations through the gate electrodes 112, and a memory layer 114 surrounding the vertical channels 113. The memory layer 114 may include a tunnel dielectric layer adjacent to the vertical channels 113, a barrier dielectric layer adjacent to the gate electrodes 112, and a charge storage layer between the tunnel dielectric layer and the barrier dielectric layer.

[0028] The first circuit 110 may further include a plurality of common source plugs 115 electrically connected to the first substrate 111, a plurality of metal contacts 117 coupled to the end of the gate electrode 112, and a plurality of wires 116 disposed on the gate electrode 112. The wires 116 may be electrically connected to the vertical channel 113, the common source plugs 115, and the metal contacts 117.

[0029] The gate electrode 112 can form a ground select line closest to the first substrate 111, a string select line furthest from the first substrate 111, and a plurality of word lines between the ground select line and the string select line. In the wires 116, wires electrically connected to the vertical channel 113 can form bit lines. Word lines and bit lines can extend to intersect each other. For example, word lines and bit lines can extend longitudinally in directions perpendicular to each other and can intersect each other when viewed from above.

[0030] The first circuit 110 constructed as described above can be a memory cell circuit having memory cells vertically stacked and three-dimensionally arranged on the active surface 111a of the first substrate 111, and the first semiconductor device D1 including the first circuit 110 can be a vertical NAND flash memory. Alternatively, the first circuit 110 can include a plurality of capacitors, and the first semiconductor device D1 including the first circuit 110 can be a dynamic random access memory (DRAM).

[0031] Multiple first external terminals 118 may be further configured to connect to wires 116. The first external terminals 118 may be exposed by a dielectric layer 119. For example, the top surface of the first external terminal 118 may be coplanar with the top surface of the dielectric layer 119. Alternatively, the first external terminals 118 may protrude above the dielectric layer 119. The shape of the first external terminals 118 may be like a cylinder, solder ball, solder bump, or pad.

[0032] Figure 2 This is a cross-sectional view illustrating the process of forming a second semiconductor device in a method of manufacturing a fused memory device according to some example embodiments of the present invention.

[0033] Reference Figure 2 A second semiconductor device D2 may be provided, including a second substrate 121 and a second circuit 120. The second substrate 121 may have an active surface 121a and an opposite passive surface 121b. The second substrate 121 may be a semiconductor substrate, such as a silicon wafer (or a portion thereof). The second circuit 120, encapsulated with a dielectric layer 129, may be disposed on the active surface 121a of the second substrate 121. The dielectric layer 129 may have a multilayer structure in which multiple layers of one or both of silicon oxide and silicon nitride layers are stacked.

[0034] The second circuit 120 may include a plurality of transistors 122 disposed on the active surface 121a of the second substrate 121, a plurality of connection lines 123 electrically connected to the transistors 122, and a plurality of metal lines 124 electrically connected to the transistors 122 via the connection lines 123.

[0035] The second circuit 120 may include peripheral circuitry for controlling the operation of the first semiconductor device D1. For example, the second circuit 120 may include high-voltage transistors suitable for operating the first semiconductor device D1 at relatively high voltages, and may also include low-voltage transistors suitable for operating at relatively low voltages.

[0036] Furthermore, the second circuit 120 may also include peripheral circuitry for controlling the operation of the third semiconductor device D3, which will be referred to below. Figure 5 This will be discussed. Therefore, the second circuit 120 can have a design suitable for... Figure 1 The operation of the first semiconductor device D1 shown and Figure 5 The diagram illustrates the peripheral circuit structure for the operation of the third semiconductor device D3. The second semiconductor device D2 may be a non-memory device. In some embodiments, the second semiconductor device D2 may include an application processor AP and / or logic device circuitry.

[0037] Multiple second external terminals 128 may be further configured to connect to the metal line 124. The second external terminals 128 may be exposed by the dielectric layer 129. For example, the top surface of the second external terminal 128 may be coplanar with the top surface of the dielectric layer 129. Alternatively, the second external terminals 128 may protrude above the dielectric layer 129. The shape of the second external terminals 128 may be like a cylinder, solder ball, solder bump, or pad.

[0038] Refer to together Figure 1 and Figure 2 The formation of the first semiconductor device D1 can be performed independently of the formation of the second semiconductor device D2. Therefore, one of the two formations can be unaffected by the other. For example, critical dimensions and / or processing temperatures can be established independently to form the first semiconductor device D1 and the second semiconductor device D2 separately from each other.

[0039] Conversely, when the first circuit 110 is formed on top of the previously formed second circuit 120, or when the second circuit 120 and the first circuit 110 are formed simultaneously, the relatively high processing temperature required to form the first circuit 110 may degrade the electrical characteristics of the second circuit 120. For example, high processing temperatures may cause short-channel effects, such as punch-through of transistor 122.

[0040] In some embodiments, because the formation of the first semiconductor device D1 and the second semiconductor device D2 are performed independently of each other, the formation of the first circuit 110 and the second circuit 120 can be completely independent of each other. Thus, the first circuit 110 and the second circuit 120 can have processing independence, and therefore, when the second circuit 120 is formed, the transistor 122 can be reduced to the smallest possible size. Therefore, the second semiconductor device D2 can be formed to include the second circuit 120, which has excellent electrical characteristics such as operating voltage and operating speed.

[0041] Figure 3 This is a cross-sectional view illustrating the process of combining a first semiconductor device and a second semiconductor device in a method of manufacturing a fused memory device according to some exemplary embodiments of the present invention.

[0042] Reference Figure 3 The first semiconductor device D1 and the second semiconductor device D2 can be combined with each other. Although not shown in the figures, as described herein (for this embodiment and other embodiments), when a semiconductor device is part of a wafer (e.g., a wafer containing the same semiconductor devices integrally formed as part of the wafer), semiconductor devices that are combined with each other can be combined with each other. For example, the first semiconductor device D1 may be part of a first wafer having a plurality of devices identical to the first semiconductor device D1, and the second semiconductor device D2 may be part of a second wafer having a plurality of devices identical to the second semiconductor device D2. Therefore, in the case of... Figure 3 When the first semiconductor device D1 and the second semiconductor device D2 are combined as shown, each of the plurality of first semiconductor devices can be simultaneously combined with a corresponding one of the plurality of second semiconductor devices. Similarly, other processes described herein can occur at the wafer level, such that processing is performed simultaneously for all devices within the wafer. For example, after combining the semiconductor devices into a combination of semiconductor wafers, the combined semiconductor wafers can be diced to monolithize the chip combination with each other. The first semiconductor device D1 may have an inverted second semiconductor device D2 disposed thereon, and a first external terminal 118 may be positioned to correspond to a second external terminal 128. For example, the first external terminal 118 and the second external terminal 128 may be aligned with each other in the vertical direction. The corresponding external terminals 118 and 128 may be bonded to each other to form a connection terminal 90. For example, a pair of corresponding external terminals 118 and 128 may be provided by heating or by solder and heating, and then bonded to each other to form a connection terminal 90.

[0043] The first circuit 110 of the first semiconductor device D1 can be physically electrically connected to the second circuit 120 of the second semiconductor device D2 via the connection terminal 90. The second circuit 120 of the second semiconductor device D2 can be used as a peripheral circuit for operating the first circuit 110 of the first semiconductor device D1.

[0044] As described above, an inverted second semiconductor device D2 is disposed on the first semiconductor device D1, so the first semiconductor device D1 can stand upright and the second semiconductor device D2 can be inverted. The active surface 111a of the first substrate 111 can face the active surface 121a of the second substrate 121, and the passive surface 111b of the first substrate 111 and the passive surface 121b of the second substrate 121 can face opposite directions and be exposed to the outside.

[0045] Figure 4 This is a cross-sectional view illustrating a substrate thinning process in a method for manufacturing a fused memory device according to some exemplary embodiments of the present invention.

[0046] Reference Figure 4 The second substrate 121 can be thinned physically or chemically. For example, the passive surface 121b of the second substrate 121 can undergo chemical mechanical polishing or etching to form a passive surface 121c that is closer to the active surface 121a than the passive surface 121b. The thinned second substrate 121 can have a thickness T2 that is less than the thickness T1 of the first substrate 111.

[0047] The reduced thickness T2 of the second substrate 121 can reduce the overall height of the fused memory device 1 (this will be referred to below). Figure 5 (To be discussed), and to enable the second semiconductor device D2 to be easily electrically connected to the third semiconductor device D3 (which will be referred to below). Figure 5 (To be discussed). In some embodiments, thinning of the second substrate 121 may not be performed.

[0048] Figure 5 This is a cross-sectional view illustrating the process of forming a third semiconductor device in a method of manufacturing a fused memory device according to some example embodiments of the present invention. Figure 6 These illustrate some example embodiments based on the concept of the present invention. Figure 5 A cross-sectional view of another example of a fused memory device shown.

[0049] Reference Figure 5The second substrate 121 may have a third semiconductor device D3 disposed on its recessed passive surface 121c. The third semiconductor device D3 includes a third circuit 130 packaged with a dielectric layer 139. The dielectric layer 139 may have a multilayer structure in which multiple layers of one or both of silicon oxide and silicon nitride are stacked. The formation of the third semiconductor device D3 can be used to manufacture a fused memory device 1 in which a first semiconductor device D1, a second semiconductor device D2, and a third semiconductor device D3 are sequentially stacked.

[0050] The third circuit 130 may include: a plurality of word lines 131 extending horizontally in parallel on the passive surface 121c of the second substrate 121; a plurality of bit lines 132 located on and intersecting the word lines 131; and a plurality of memory layers 133 disposed at corresponding intersections between the word lines 131 and the bit lines 132. For example, the plurality of memory layers 133 may be stacked on top of each other between the word lines 131 and the bit lines 132 at the locations where the word lines 131 and the bit lines 132 intersect each other. A select element 138a and a lower electrode 138b may be formed between the word lines 131 and the memory layers 133. An upper electrode 138c may be formed between the bit lines 132 and the memory layers 133.

[0051] Memory layer 133 may be a variable resistance layer. For example, memory layer 133 may include: a phase change material such as a chalcogenide, a magnetic tunnel junction consisting of two magnetic layers and a dielectric layer therebetween, or a variable resistance material such as a perovskite compound or a transition metal oxide. Third circuit 130 may write or read data by using phase changes, magnetization direction changes, or resistance changes in memory layer 133.

[0052] The third circuit 130 may be a memory cell circuit having memory cells arranged in three dimensions and intersecting each other on the passive surface 121c of the second substrate 121. The type of the third semiconductor device D3 may depend on the material included in the memory layer 133. For example, when the memory layer 133 includes a phase change material, the third semiconductor device D3 may be a phase change random access memory (PRAM). As another example, when the memory layer 133 includes a magnetic tunnel junction or a variable resistance material, the third semiconductor device D3 may be a magnetic random access memory (MRAM) or a resistive random access memory (RRAM).

[0053] like Figure 5 As shown, the third circuit 130 can have a two-layer structure. Alternatively, the third circuit 130 can have a single-layer structure or a multi-layer structure with three or more layers. Multiple metal lines 135 can be formed on the third circuit 130. One or all of the metal lines 135 can be formed in the second semiconductor device D2.

[0054] Multiple through electrodes 134, 134a, and 136 can realize electrical connections between the third semiconductor device D3 and the second semiconductor device D2. For example, the through electrode 134, coupled to the bit line 132 of the third circuit 130, can be coupled to the connection line 123 of the second circuit 120 while extending toward the second semiconductor device D2 and penetrating the second substrate 121. Similarly, the through electrode 136, coupled to the metal line 135 of the third semiconductor device D3, can be coupled to another connection line 123 of the second circuit 120 while extending toward the second semiconductor device D2 and penetrating the second substrate 121. The through electrodes 134 and 136 can be electrically insulated from the second substrate 121.

[0055] In some embodiments, vertically spaced bit lines 132 may be electrically connected to each other via through electrodes 134a formed between them. For example, in an embodiment where the third circuit 130 has a multilayer structure, through electrodes 134a may electrically connect vertically adjacent bit lines 132. In some embodiments, such as Figure 6 As shown, the through electrode 134 coupled to the corresponding bit line 132 can penetrate the second substrate 121 and be directly connected to the connection line 123 of the second circuit 120. For example, in an embodiment where the third circuit 130 has a multilayer structure, all through electrodes 134 can extend from the bit line 132 to the connection line of the second circuit 120.

[0056] In some embodiments, a third semiconductor device D3 may be formed on the second semiconductor device D2. For example, one or more etching processes may be performed to form through electrodes 134 and 136, such that they penetrate the second substrate 121 and are directly connected to the connection line 123 of the second circuit 120.

[0057] Similar to or analogous to bit line 132, word line 131 may have an electrical connection to the second circuit 120. This will be referred to below. Figures 7 to 9 Further discussion.

[0058] Figures 7 to 9 This is a cross-sectional view showing some example embodiments of a fused memory device 1 according to the present invention.

[0059] exist Figures 7 to 9 In this diagram, to facilitate understanding of the electrical connection between the third semiconductor device D3 and the second semiconductor device D2, the third semiconductor device D3 is shown by a cross-section along the word line direction and a cross-section along the bit line direction. In the following embodiments, details differing from the fused memory device 1 will be discussed primarily.

[0060] Reference Figure 7The through electrode 137, coupled to the corresponding word line 131 of the third circuit 130, can extend toward the second semiconductor device D2 and penetrate the second substrate 121 while being directly coupled to the connection line 123 of the second circuit 120. The through electrode 137 can be electrically insulated from the second substrate 121 and can be electrically connected to the word line 131 and the connection line 123.

[0061] In one example embodiment, such as Figure 8 As shown, vertically spaced word lines 131 can be electrically connected to each other via through electrodes 137a formed between them. For example, in an embodiment where the third circuit 130 has a multilayer structure, the through electrodes 137a can electrically connect vertically adjacent word lines 131. In another example embodiment, as... Figure 9 As shown, the through electrode 134 coupled to the corresponding bit line 132 can penetrate the second substrate 121 and is directly connected to the connection line 123 of the second circuit 120. Similarly, the through electrode 137 coupled to the corresponding word line 131 can penetrate the second substrate 121 and is directly connected to the connection line 123 of the second circuit 120.

[0062] In some embodiments, the third semiconductor device D3 may be formed on the second semiconductor device D2. For example, one or more etching processes may be performed to form through electrodes 134, 136 and 137, such that they penetrate the second substrate 121 and are directly connected to the connection line 123 of the second circuit 120.

[0063] In some embodiments, diffusion processes may be performed at relatively high temperatures when forming the first circuit 110 constituting the first semiconductor device D1 (such as a vertical NAND flash memory). Similarly, diffusion processes may be required when forming the second circuit 120, which consists of a plurality of transistors 122. For example, each of the first semiconductor device D1 and the second semiconductor device D2 may be formed at a temperature between about 800°C and about 850°C or higher.

[0064] Conversely, a third semiconductor device D3, such as a variable resistance memory, can be formed at a temperature lower than the formation temperature of the first semiconductor device D1 and / or the second semiconductor device D2. In some embodiments, because the formation of the third semiconductor device D3 follows the formation of the first semiconductor device D1 and the second semiconductor device D2, the formation of the third semiconductor device D3 may not impose any thermal burden on the first semiconductor device D1 and the second semiconductor device D2 at all. Therefore, thermal degradation of the first semiconductor device D1 and the second semiconductor device D2 can be prevented.

[0065] According to the present invention, the formation of the memory device and the non-memory device can be performed separately from each other, thus ensuring processing independence. Therefore, the memory device and the non-memory device can be formed with desired electrical performance without any design limitations.

[0066] Furthermore, the formation of a cryogenic memory device can be performed after the formation of a high-temperature memory device. Therefore, neither the high-temperature memory device nor the non-memory device is affected by the subsequent processing required to form the cryogenic memory device.

[0067] As a result, it is possible to realize a fused memory device in which each of the memory device and the non-memory device has excellent electrical characteristics.

[0068] This detailed description of the inventive concept should not be construed as limiting it to the embodiments set forth herein, and the inventive concept is intended to cover various combinations, modifications, and variations of the invention without departing from the spirit and scope of the inventive concept. The appended claims should be interpreted to include other embodiments.

Claims

1. A fused memory device, comprising: A first memory device includes a first substrate and a first memory cell circuit, the first substrate having an active surface and a passive surface opposite to each other, the first memory cell circuit being located on the active surface of the first substrate. A non-memory device includes a second substrate and a non-memory circuit, the second substrate having an active surface and a passive surface opposite each other, the non-memory circuit being located on the active surface of the second substrate, and the non-memory device being disposed on a first memory device. and A second memory device is located on a passive surface of the second substrate and includes a second memory cell circuit that is different from the first memory cell circuit. The non-memory device is disposed between the first memory cell circuit and the second memory cell circuit, and is configured to control the electrical operation of each of the first memory cell circuit and the second memory cell circuit. The active surface of the second substrate faces the active surface of the first substrate. The passive surface of the second substrate faces the second memory cell circuit. The second memory device does not include a semiconductor substrate. The non-memory circuit includes a transistor disposed on the active surface of the second substrate, a connection line electrically connected to the transistor, and a metal line electrically connected to the transistor through the connection line. The second memory device includes: a plurality of word lines horizontally arranged on a passive surface of the second substrate; a plurality of bit lines located on and intersecting the word lines; and through electrodes electrically connecting the bit lines of the second memory device to the connection lines of the non-memory circuit, and penetrating the second substrate. The fused memory device further includes a connection terminal for the metal wire connecting the first memory cell circuit and the non-memory circuit.

2. The apparatus of claim 1, wherein, The non-memory circuit includes: A first peripheral circuit, electrically connected to the first memory cell circuit, and configured to control the electrical operation of the first memory cell circuit; and A second peripheral circuit is electrically connected to the second memory cell circuit and is configured to control the electrical operation of the second memory cell circuit.

3. The apparatus of claim 1, wherein, The processing temperature of the first memory cell circuit is greater than that of the second memory cell circuit.

4. The apparatus of claim 1, wherein, The thickness of the second substrate is less than the thickness of the first substrate.

5. A fused memory device, comprising: A lower memory device includes a lower substrate and a plurality of lower memory cells, the lower substrate having active and passive surfaces opposite each other, the plurality of lower memory cells being stacked on the active surfaces of the lower substrate; A non-memory device includes: an upper substrate having an active surface and a passive surface opposite to each other; a transistor disposed on the active surface of the upper substrate; a connection line electrically connected to the transistor; and a metal wire electrically connected to the transistor via the connection line, the non-memory device being stacked on a lower memory device; An upper memory device comprising a plurality of upper memory cells, distinct from the lower memory cells and stacked on a passive surface of the upper substrate, the upper memory device being stacked on the non-memory device; and Connection terminals, which are metal wires connecting the lower memory unit and the non-memory device. The upper memory unit and the lower memory unit are electrically connected to the connecting line and the metal wire. The active surface of the upper substrate faces the active surface of the lower substrate. The passive surface of the upper substrate faces the upper memory cell. The upper memory device does not include a semiconductor substrate. The upper memory device includes: a plurality of word lines arranged horizontally on a passive surface of the upper substrate; a plurality of bit lines located on and intersecting the word lines; and a first through electrode that electrically connects the bit lines of the upper memory device to the connection lines of the non-memory device and penetrates the upper substrate.

6. The apparatus of claim 5, wherein, The non-memory device also includes peripheral circuitry configured to control the electrical operation of the lower memory cell and the electrical operation of the upper memory cell.

7. The apparatus of claim 5, further comprising: The second through electrode electrically connects the word line to the connection line of the non-memory device and penetrates the upper substrate. The connection terminal is located between the lower memory cell and the metal wire.

8. The apparatus of claim 5, wherein, The thickness of the upper substrate is less than the thickness of the lower substrate.

9. The apparatus of claim 5, wherein, The lower memory unit includes: Multiple word lines are stacked vertically on the active surface of the lower substrate; Multiple vertical channels that penetrate the word lines vertically and are surrounded by multiple corresponding memory layers; and Multiple bit lines are electrically connected to the vertical channel and intersect the word lines.

10. The apparatus of claim 5, wherein, The upper memory unit includes: Multiple variable resistor layers are located at corresponding intersections between the word lines and the bit lines.

11. The apparatus of claim 5, wherein, The upper memory device further includes: Multiple metal lines are located on the upper memory cell; and The third through electrode electrically connects the metal wire of the upper memory cell to the connection line of the non-memory device. The third through electrode penetrates the upper substrate.

12. A method of manufacturing a fusion memory device, the method comprising: A first memory cell circuit comprising a plurality of first memory cells is formed on the active surface of a first substrate to form a first memory device; A non-memory circuit comprising multiple wires is formed on the active surface of the second substrate to form a non-memory device; Combine the first memory device with the non-memory device; and After combining the first memory device with the non-memory device, the second substrate is physically or chemically thinned, and a second memory device is formed on the passive surface of the thinned second substrate at a temperature below the formation temperature of the first memory device and the non-memory device. The second memory device includes a second memory cell circuit that is different from the first memory cell circuit, and the second memory cell circuit includes a plurality of second memory cells. The formation of the first memory cell circuit and the formation of the non-memory circuit are performed independently of each other. The combination of the first memory device and the non-memory device includes: combining the first substrate and the second substrate with each other such that the active surface of the second substrate faces the active surface of the first substrate, and The second memory device does not include a semiconductor substrate.

13. The method of claim 12, wherein, The circuit forming the first memory cell includes: Multiple word lines are vertically stacked on the active surface of the first substrate; Multiple vertical channels are formed that penetrate the plurality of word lines, each of which is surrounded by a memory layer; and A plurality of bit lines are formed that are electrically connected to the vertical channel and intersect the word lines.

14. The method of claim 12, wherein, The circuit forming the second memory cell includes: Multiple word lines are formed on the passive surface of the second substrate in a horizontal arrangement; Multiple bit lines are formed on the word lines, and the bit lines intersect with the word lines; and Multiple variable resistance layers are formed at the corresponding intersections between the word lines and the bit lines.

15. The method of claim 14, wherein, The formation of the second memory cell circuit further includes forming a plurality of through electrodes for wires electrically connecting the word lines and the bit lines to the non-memory circuit, the plurality of through electrodes penetrating the second substrate perpendicularly.

Images