Semiconductor devices

Abstract

A semiconductor device includes: a semiconductor layer having a main surface with a trench; a first conductivity type body region formed along the sidewall of the trench on the surface portion of the main surface of the semiconductor layer; a second conductivity type impurity region formed along the sidewall of the trench on the surface portion of the body region; a gate insulating layer formed on the inner wall of the trench; a gate electrode embedded in the trench and facing the body region and the impurity region through the gate insulating layer; a contact electrode extending through the sidewall of the trench and led out to the surface portion of the main surface of the semiconductor layer, and electrically connected to the body region and the impurity region; and an embedded insulating layer located within the trench between the gate electrode and the contact electrode, insulating the gate electrode and the contact electrode.

Description

Technical Field

[0001] This invention relates to the semiconductor device of the present invention. Background Technology

[0002] Patent Document 1 discloses a semiconductor device incorporating an IGBT (Insulated Gate Bipolar Transistor). This semiconductor device includes a semiconductor substrate (semiconductor layer) having a main surface. A trench is formed on the main surface of the semiconductor substrate. A p-type body region is formed along the sidewalls of the trench on the surface portion of the main surface of the semiconductor substrate. An n-type emitter region (impurity region) is formed along the sidewalls of the trench on the surface portion of the body region.

[0003] A gate insulating layer is formed on the inner wall of the trench. A gate electrode layer is embedded in the trench through the gate insulating layer. A contact groove is formed on the main surface of the semiconductor substrate, spaced apart from the trench to expose the emitter region. An emitter electrode (contact electrode) is embedded in the contact groove.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2016-225566 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] In a structure where a gate electrode and a contact electrode are embedded in the surface layer of a semiconductor layer, the contact electrode is formed with a gap between it and the gate electrode, without contacting the gate electrode. The distance between the gate electrode and the contact electrode is set considering the dimensional tolerance of the contact electrode. Therefore, the distance between the gate electrode and the contact electrode cannot be narrower than a predetermined value set according to the dimensional tolerance of the contact electrode. This problem hinders the miniaturization of semiconductor devices.

[0009] One embodiment of the present invention provides a semiconductor device that mitigates the limitations of dimensional tolerances caused by contact electrodes and can contribute to miniaturization.

[0010] Solution for solving the problem

[0011] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor layer having a main surface with a trench formed therein; a first conductivity type body region formed along the sidewall of the trench on a surface portion of the main surface of the semiconductor layer; a second conductivity type impurity region formed along the sidewall of the trench on a surface portion of the body region; a gate insulating layer formed on the inner wall of the trench; a gate electrode embedded in the trench and facing the body region and the impurity region through the gate insulating layer; a contact electrode extending through the sidewall of the trench and led out to the surface portion of the main surface of the semiconductor layer, and electrically connected to the body region and the impurity region; and an embedded insulating layer located within the trench between the gate electrode and the contact electrode, insulating the gate electrode and the contact electrode.

[0012] According to this semiconductor device, the contact electrode can be formed without leaving a gap with the gate electrode, thus mitigating the limitations caused by the dimensional tolerances of the contact electrode. Therefore, it is possible to improve semiconductor devices that contribute to miniaturization.

[0013] The above-mentioned or other objects, features, and effects of the present invention will become clearer from the description of the embodiments below with reference to the accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a cross-sectional perspective view showing a portion of a semiconductor device according to the first embodiment of the present invention.

[0015] Figure 2 From Figure 1 A cross-sectional perspective view of the structure after removing the semiconductor layer from the main surface.

[0016] Figure 3 From Figure 2 A three-dimensional cross-sectional view after the emitter contact electrode layer has been removed.

[0017] Figure 4 Viewed from the main surface of the semiconductor layer Figure 3 Top view.

[0018] Figure 5 It is along Figure 4 The cross-sectional view of the VV line shown.

[0019] Figure 6 It is along Figure 4 The sectional view along line VI-VI is shown.

[0020] Figure 7 This is a cross-sectional perspective view showing a portion of a semiconductor device of the reference example, and is a view after the structure above the main surface of the semiconductor layer has been removed.

[0021] Figure 8 The current-voltage characteristic curve is obtained through simulation.

[0022] Figure 9 The peak collector current curve is obtained through simulation.

[0023] Figure 10A It is used for explanation Figure 1 A cross-sectional perspective view of an example of a method for manufacturing a semiconductor device.

[0024] Figure 10B It means Figure 10A A three-dimensional cross-sectional view of the subsequent processes.

[0025] Figure 10C It means Figure 10B A three-dimensional cross-sectional view of the subsequent processes.

[0026] Figure 10D It means Figure 10C A three-dimensional cross-sectional view of the subsequent processes.

[0027] Figure 10E It means Figure 10D A three-dimensional cross-sectional view of the subsequent processes.

[0028] Figure 10F It means Figure 10E A three-dimensional cross-sectional view of the subsequent processes.

[0029] Figure 10G It means Figure 10F A three-dimensional cross-sectional view of the subsequent processes.

[0030] Figure 10H It means Figure 10G A three-dimensional cross-sectional view of the subsequent processes.

[0031] Figure 10I It means Figure 10H A three-dimensional cross-sectional view of the subsequent processes.

[0032] Figure 10J It means Figure 10I A three-dimensional cross-sectional view of the subsequent processes.

[0033] Figure 10K It means Figure 10J A three-dimensional cross-sectional view of the subsequent processes.

[0034] Figure 10L It means Figure 10K A three-dimensional cross-sectional view of the subsequent processes.

[0035] Figure 10M It means Figure 10L A three-dimensional cross-sectional view of the subsequent processes.

[0036] Figure 10N It means Figure 10M A three-dimensional cross-sectional view of the subsequent processes.

[0037] Figure 11 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the second embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0038] Figure 12 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the third embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0039] Figure 13 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the fourth embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0040] Figure 14 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the fifth embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0041] Figure 15 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the sixth embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0042] Figure 16 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the seventh embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0043] Figure 17 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the eighth embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0044] Figure 18 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the ninth embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0045] Figure 19 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the tenth embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0046] Figure 20 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the eleventh embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0047] Figure 21This is a cross-sectional perspective view showing a portion of the semiconductor device according to the twelfth embodiment of the present invention, and is a view after removing the structure above the main surface of the semiconductor layer.

[0048] Figure 22 This is a cross-sectional perspective view showing a portion of the semiconductor device according to the thirteenth embodiment of the present invention.

[0049] Figure 23 It means Figure 22 The cross-sectional perspective view of a portion of the semiconductor device shown is a diagram of the structure after removing the main surface of the semiconductor layer.

[0050] Figure 24 yes Figure 23 Top view.

[0051] Figure 25 It is along Figure 24 The cross-sectional view of the XXV-XXV line shown.

[0052] Figure 26 Is with Figure 22 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view showing a portion of the semiconductor device according to the fourteenth embodiment of the present invention.

[0053] Figure 27 Is with Figure 25 The sectional view of the corresponding area is Figure 26 A cross-sectional view of a portion of the semiconductor device shown.

[0054] Figure 28 Is with Figure 24 The top view of the corresponding area is a top view showing a portion of the semiconductor device according to the fifteenth embodiment of the present invention.

[0055] Figure 29 It is along Figure 28 The cross-sectional view of the XXIX-XXIX line shown.

[0056] Figure 30 Is with Figure 29 The cross-sectional view of the corresponding region is a cross-sectional view showing a portion of the semiconductor device according to the sixteenth embodiment of the present invention.

[0057] Figure 31 Is with Figure 29 The cross-sectional view of the corresponding region is a cross-sectional view showing a portion of the semiconductor device according to the seventeenth embodiment of the present invention.

[0058] Figure 32 Is with Figure 29 The cross-sectional view of the corresponding region is a cross-sectional view showing a portion of the semiconductor device according to the eighteenth embodiment of the present invention.

[0059] Figure 33 Is with Figure 2 The top view of the corresponding part is a diagram showing a modified example of the semiconductor layer.

[0060] Figure 34 Is with Figure 4 The top view of the corresponding part is a diagram showing a modified example of the gate being embedded in an insulating layer.

[0061] Figure 35 Is with Figure 4 The top view of the corresponding part is a diagram showing a modified example of the emitter contact electrode layer. Detailed Implementation

[0062] Figure 1 This is a cross-sectional perspective view showing a portion of the semiconductor device 1 according to the first embodiment of the present invention. Figure 2 From Figure 1 A cross-sectional perspective view after removing the structure above the first main surface 3 of semiconductor layer 2. Figure 3 From Figure 2 A cross-sectional perspective view after removing the emitter contact electrode layer 51.

[0063] Figure 4 Observed from the first main surface 3 of semiconductor layer 2 Figure 3 Top view. Figure 5 It is along Figure 4 The cross-sectional view of the VV line shown. Figure 6 It is along Figure 4 The sectional view shown along line VI-VI. Figure 5 as well as Figure 6 The diagram also illustrates the structure on the first main surface 3 of the semiconductor layer 2.

[0064] In this approach, the semiconductor device 1 has a basic configuration of an IGBT (Insulated Gate Bipolar Transistor) with a trench gate type. (Refer to...) Figures 1-6 The semiconductor device 1 includes an n-type semiconductor layer 2. In this configuration, the semiconductor layer 2 is made of an n-type silicon single-crystal substrate. The silicon single-crystal substrate is formed using an n-type silicon single-crystal semiconductor wafer manufactured via the FZ (Floating Zone) method.

[0065] The semiconductor layer 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The thickness of the semiconductor layer 2 can also be 50 μm or more and 300 μm or less. Alternatively, the thickness of the semiconductor layer 2 can be 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, or 250 μm or more and 300 μm or less.

[0066] A p-type collector region 5 is formed on the surface of the second main surface 4. An n-type charge accumulation region 6 is formed on the surface of the first main surface 3. The charge accumulation region 6 is formed on the side of the first main surface 3 with a gap relative to the collector region 5.

[0067] In semiconductor layer 2, an n-type drift region 7 is formed in the region between collector region 5 and charge accumulation region 6. Drift region 7 is formed in semiconductor layer 2 by the region located between collector region 5 and charge accumulation region 6. A p-type body region 8 is formed on the surface of charge accumulation region 6. On the surface of the first main surface 3, a plurality of trench gate electrode structures 10 and a plurality of trench emitter electrode structures 11 are formed with spacing.

[0068] exist Figures 1-6 Only one trench gate electrode structure 10 and one trench emitter electrode structure 11 adjacent to each other are shown in the diagram. The structure of the semiconductor device 1 will be described below with emphasis on the structure of the trench gate electrode structure 10 and the trench emitter electrode structure 11.

[0069] The trench gate electrode structure 10 and the trench emitter electrode structure 11 are formed with gaps along an arbitrary first direction X. In top view, the trench gate electrode structure 10 and the trench emitter electrode structure 11 extend in a strip shape along a second direction Y that intersects the first direction X.

[0070] More specifically, a top view refers to a view taken from the normal direction Z of the first principal plane 3 (hereinafter referred to as "normal direction Z"). More specifically, the second direction Y is a direction orthogonal to the first direction X. Both the first direction X and the second direction Y are also tangent directions to the first principal plane 3.

[0071] The trench spacing P0 between the trench gate electrode structure 10 and the trench emitter electrode structure 11 can also be 0.1 μm or more and less than 0.6 μm. The trench spacing P0 can also be 0.1 μm or more and less than 0.2 μm, 0.2 μm or more and less than 0.3 μm, 0.3 μm or more and less than 0.4 μm, 0.4 μm or more and less than 0.5 μm, or 0.5 μm or more and less than 0.6 μm. The trench spacing P0 is preferably 0.2 μm or more and less than 0.4 μm (e.g., around 0.25 μm).

[0072] The trench gate electrode structure 10 includes a gate trench 12 (trench), a gate insulating layer 13, a gate electrode layer 14 (gate electrode), a plurality of gate buried vias 15, and a plurality of gate buried insulating layers 16 (buried insulating layers). The gate trench 12 extends from the first main surface 3 through the main body region 8 and the charge accumulation region 6 to the drift region 7.

[0073] The depth of the gate trench 12 can also be 2.0 μm or more and 4.0 μm or less. The depth of the gate trench 12 can also be 2.0 μm or more and 2.5 μm or less, 2.5 μm or more and 3.0 μm or less, 3.0 μm or more and 3.5 μm or less, or 3.5 μm or more and 4.0 μm or less. Preferably, the depth of the gate trench 12 is 2.5 μm or more and 3.5 μm or less (e.g., around 3.0 μm).

[0074] The width of the gate trench 12 in the first direction can also be 0.5 μm or more and 1.5 μm or less. The width of the gate trench 12 in the first direction can also be 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1.0 μm or less, 1.0 μm or more and 1.25 μm or less, or 1.25 μm or more and 1.5 μm or less. Preferably, the width of the gate trench 12 in the first direction is 0.5 μm or more and 1.0 μm or less (e.g., around 0.75 μm).

[0075] The gate insulating layer 13 may also comprise silicon oxide. The gate insulating layer 13 is formed as a film along the inner wall surface of the gate trench 12. The gate insulating layer 13 divides concave spaces within the gate trench 12.

[0076] The gate electrode layer 14 may comprise conductive polysilicon. The gate electrode layer 14 is controlled by a gate voltage. The gate electrode layer 14 is buried in the gate trench 12 through the gate insulating layer 13. More specifically, the gate electrode layer 14 is buried within the gate trench 12 in a concave space defined by the gate insulating layer 13. The upper end of the gate electrode layer 14 is located on the first main surface 3 relative to the bottom of the body region 8.

[0077] In this configuration, a plurality of gate buried vias 15 are formed spaced apart along the second direction Y on the main surface of the gate electrode layer 14. Thus, the upper end of the gate electrode layer 14 has a concave-convex structure including a plurality of gate buried vias 15.

[0078] The spacing between adjacent gate buried vias 15 can also be greater than 0 μm and less than 10 μm. The spacing between adjacent gate buried vias 15 is also the width of the portion of the gate electrode layer 14 sandwiched between two adjacent gate buried vias 15 in the second direction Y. The spacing between adjacent gate buried vias 15 can also be greater than 0 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm.

[0079] In this configuration, the sidewalls of each gate buried via 15 are defined by a gate insulating layer 13 and a gate electrode layer 14. The bottom wall of each gate buried via 15 is defined by the gate electrode layer 14. The bottom wall of each gate buried via 15 is located in the region between the first main surface 3 and the bottom of the main body region 8 in the normal direction Z.

[0080] Reference Figure 6 Each gate hole 15 is formed into a conical shape with a base area smaller than the opening area. The angle θ formed by the main surface of the gate electrode layer 14 and the sidewall of the gate hole 15 within the gate electrode layer 14 can also be greater than 90° and less than 105° (e.g., around 102°).

[0081] Multiple gate buried insulating layers 16 are respectively buried in the surface portion of the gate electrode layer 14 within the gate trench 12. More specifically, the multiple gate buried insulating layers 16 are respectively buried in multiple gate buried vias 15. Each gate buried insulating layer 16 is exposed from the opening of the gate trench 12.

[0082] The trench emitter electrode structure 11 includes an emitter trench 17 (second trench), an emitter insulating layer 18 (inner wall insulating layer), an emitter electrode layer 19 (embedded electrode), an emitter embedding hole 20, and an emitter embedded insulating layer 21 (second embedded insulating layer). The emitter trench 17 extends from the first main surface 3 through the main body region 8 and the charge accumulation region 6 to the drift region 7.

[0083] The depth of the emitter trench 17 can also be 2.0 μm or more and 4.0 μm or less. The depth of the emitter trench 17 can also be 2.0 μm or more and 2.5 μm or less, 2.5 μm or more and 3.0 μm or less, 3.0 μm or more and 3.5 μm or less, or 3.5 μm or more and 4.0 μm or less. The depth of the emitter trench 17 is preferably 2.5 μm or more and 3.5 μm or less (e.g., around 3.0 μm). The depth of the emitter trench 17 is preferably approximately equal to the depth of the gate trench 12.

[0084] The width of the emitter trench 17 in the first direction can also be 0.5 μm or more and 1.5 μm or less. The width of the emitter trench 17 in the first direction can also be 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1.0 μm or less, 1.0 μm or more and 1.25 μm or less, or 1.25 μm or more and 1.5 μm or less. The width of the emitter trench 17 in the first direction is preferably 0.5 μm or more and 1.0 μm or less (e.g., about 0.75 μm). The width of the emitter trench 17 in the first direction is preferably approximately equal to the width of the gate trench 12 in the first direction.

[0085] The emitter insulating layer 18 may also contain silicon oxide. The emitter insulating layer 18 is formed as a film along the inner wall surface of the emitter trench 17. The emitter insulating layer 18 divides concave spaces within the emitter trench 17.

[0086] The emitter electrode layer 19 may also comprise conductive polysilicon. The emitter electrode layer 19 is controlled by an emitter voltage. The emitter voltage has a voltage value that is less than the gate voltage. The emitter voltage may also be a reference voltage (e.g., ground voltage).

[0087] The emitter electrode layer 19 is embedded in the emitter trench 17 through the emitter insulating layer 18. More specifically, the emitter electrode layer 19 is embedded in the emitter trench 17 in a concave space defined by the emitter insulating layer 18.

[0088] In this method, the emitter embedment hole 20 is formed by excavating approximately the entire surface of the main surface of the emitter electrode layer 19. In other words, the emitter electrode layer 19 is embedded to the middle of the depth direction of the concave space defined by the emitter insulating layer 18.

[0089] In this configuration, the sidewalls of the emitter hole 20 are defined by the emitter insulating layer 18. The bottom wall of the emitter hole 20 is defined by the emitter electrode layer 19. The bottom wall of the emitter hole 20 is located in the region between the first main surface 3 and the bottom of the main body region 8 in the normal direction Z. That is, the upper end of the emitter electrode layer 19 is located on the side of the first main surface 3 relative to the bottom of the main body region 8. The depth of the emitter hole 20 in the normal direction Z can also be approximately equal to the depth of the gate hole 15.

[0090] The emitter embedding insulating layer 21 is embedded in the surface portion of the emitter electrode layer 19 within the emitter trench 17. More specifically, the emitter embedding insulating layer 21 is embedded in the emitter embedding hole 20. Thus, the emitter embedding insulating layer 21 seals the emitter electrode layer 19. The emitter embedding insulating layer 21 is exposed from the opening of the emitter trench 17.

[0091] In the surface portion of the main body region 8, along the sidewall of the gate trench 12, an n+ type emitter region 25 (dump region) is formed. More specifically, multiple emitter regions 25 are formed along one sidewall and the other sidewall of the gate trench 12 in the first direction X. The multiple emitter regions 25 are each formed in a band shape extending along the second direction Y. The emitter regions 25 are in contact with the sidewall of the gate trench 12. The emitter regions 25 are also in contact with the sidewall of the emitter trench 17.

[0092] In the region along the sidewall of the gate trench 12 on the surface of the first main surface 3, an emitter region 25, a main body region 8, a charge accumulation region 6, and a drift region 7 are formed sequentially from the first main surface 3 toward the second main surface 4. In the main body region 8, an IGBT channel CH is formed in the region opposite the gate electrode layer 14, separated by the gate insulating layer 13.

[0093] Reference Figure 3 as well as Figure 4 A plurality of first contact holes 31 are formed on the surface portion of the first main surface 3. The plurality of first contact holes 31 are formed at intervals along the second direction Y. The plurality of first contact holes 31 are each formed in a band shape extending along the first direction X. The second direction width of each first contact hole 31 is smaller than the second direction width of the gate trench 12. The first direction width of each first contact hole 31 is larger than the first direction width of the gate trench 12.

[0094] More specifically, each first contact hole 31 extends from the inner region of the corresponding gate buried insulating layer 16 through the sidewall of the gate trench 12 and is led out to the surface portion of the first main surface 3. In this configuration, each first contact hole 31 extends from the inner region of the gate buried insulating layer 16 through one sidewall and the other sidewall of the gate trench 12 in the first direction X. The second direction width of each first contact hole 31 is smaller than the second direction width of the corresponding gate buried insulating layer 16.

[0095] Each first contact hole 31 also has a lead-out portion 32 extending from one sidewall of the gate trench 12 toward the emitter trench 17. Each lead-out portion 32 extends from the surface portion of the first main surface 3 through the sidewall of the emitter trench 17 and into the emitter trench 17. In this manner, each lead-out portion 32 extends through one sidewall and the other sidewall of the emitter trench 17 in the first direction X.

[0096] Each first contact hole 31 has a first intersection region 33 that intersects with the gate electrode layer 14 when viewed from above. In the first intersection region 33, the sidewalls and bottom wall of each first contact hole 31 are defined by the gate embedded insulating layer 16.

[0097] Each first contact hole 31 has a second intersection region 34 that intersects with the emitter electrode layer 19 when viewed from above. In the second intersection region 34, the sidewalls and bottom walls of each first contact hole 31 are defined by the emitter embedded insulating layer 21.

[0098] Each first contact hole 31 has a connection region 35, which, when viewed from above, connects a first cross region 33 and a second cross region 34 in the region between the gate trench 12 and the emitter trench 17. In the connection region 35, the sidewalls and bottom walls of each first contact hole 31 are defined by a semiconductor layer 2.

[0099] The sidewalls of each first contact hole 31 are formed on the same surface in the first intersection region 33, the second intersection region 34, and the connecting region 35. The bottom wall of each first contact hole 31 is formed on the same surface in the first intersection region 33, the second intersection region 34, and the connecting region 35.

[0100] The bottom wall of each first contact hole 31 is formed in the region between the bottom of the first main surface 3 and the bottom of the main body region 8. More specifically, the bottom wall of each first contact hole 31 is formed in the region between the bottom of the main body region 8 and the bottom of the emitter region 25.

[0101] The arrangement of the plurality of first contact holes 31 is arbitrary. The plurality of first contact holes 31 may also be formed at equal intervals along the second direction Y. The plurality of first contact holes 31 may also be formed at non-equal intervals along the second direction Y.

[0102] In the main body region 8, a p+ type contact region 36 is formed along the bottom wall of each first contact hole 31. The contact region 36 may also be formed in the main body region 8 along the bottom wall and side wall of each first contact hole 31. The contact region 36 is formed in the main body region 8 in a region that is deeper than the emitter region 2 in the normal direction Z.

[0103] The contact area 36 has an exposed surface that protrudes from the bottom wall of the first contact hole 31. The exposed surface of the contact area 36 is formed in the region between the first main surface 3 and the bottom of the main body region 8. More specifically, the exposed surface of the contact area 36 is formed in the region between the bottom of the main body region 8 and the bottom of the emitter region 25. More specifically, the exposed surface of the contact area 36 is formed in the region between the upper surface of the emitter electrode layer 19 and the bottom of the emitter region 25.

[0104] exist Figures 1-3 The diagram shows an example of a contact region 36 being formed relatively shallowly on the bottom surface of the first contact hole 31 through a single ion implantation. However, the contact region 36 can also be formed deeper by adjusting the number of ion implantations and the energy of the ion implantation.

[0105] Refer again Figure 1An interlayer insulating layer 41 (insulating layer) is formed on the first main surface 3. The interlayer insulating layer 41 covers the trench gate electrode structure 10 and the trench emitter electrode structure 11. The interlayer insulating layer 41 covers the gate buried insulating layer 16 exposed from the gate trench 12 and the emitter buried insulating layer 21 exposed from the emitter trench 17.

[0106] The interlayer insulating layer 41 may also comprise an oxide film (SiO2 film) or a nitride film (SiN film). The interlayer insulating layer 41 may also have a laminated structure comprising an oxide film (SiO2 film) and a nitride film (SiN film). The oxide film (SiO2 film) may also comprise a BPSG (Boron Phosphorus Silicon Glass) film containing boron and phosphorus, and / or a PSG (Phosphorus Silicon Glass) film containing phosphorus.

[0107] The interlayer insulating layer 41 may also have a laminated structure comprising a BPSG film and a PSG film sequentially stacked from the first main surface 3. The thickness of the BPSG film may also be... The above and The following (e.g.) (Approximately). The thickness of the PSG film can also be... The above and The following (e.g.) about).

[0108] A plurality of second contact holes 42 are formed in the interlayer insulating layer 41. The plurality of second contact holes 42 are respectively connected to the corresponding first contact holes 31. That is, the plurality of second contact holes 42 are formed with gaps along the second direction Y, and are respectively formed in a band shape extending along the first direction X.

[0109] Multiple second contact holes 42 penetrate the interlayer insulating layer 41 and are connected to corresponding first contact holes 31. Thus, the multiple second contact holes 42 form an emitter contact hole 31, 42 between themselves and the corresponding first contact hole 31.

[0110] The second-direction width of each second contact hole 42 can also be greater than or equal to the second-direction width of each first contact hole 31. That is, the second-direction width of each second contact hole 42 can be equal to or greater than the second-direction width of each first contact hole 31. When the second-direction width of each second contact hole 42 is greater than the second-direction width of each first contact hole 31, the inner wall surface of each second contact hole 42 can also surround the inner wall surface of the corresponding first contact hole 31.

[0111] The configuration of the plurality of second contact holes 42 is arbitrary and adjusted according to the configuration of the first contact holes 31. The plurality of second contact holes 42 can also be formed at equal intervals along the second direction Y. Alternatively, the plurality of second contact holes 42 can be arranged at non-equal intervals along the second direction Y.

[0112] An emitter main electrode layer 43, serving as a first main electrode layer, is formed on the interlayer insulating layer 41. The emitter main electrode layer 43 extends from the interlayer insulating layer 41 into the second contact hole 42 and the first contact hole 31 (that is, emitter contact holes 31 and 42).

[0113] The emitter main electrode layer 43 may also have a stacked structure comprising a first electrode layer 44 and a second electrode layer 45 sequentially stacked from the interlayer insulating layer 41 side. The first electrode layer 44 forms the base layer of the second electrode layer 45. The first electrode layer 44 is formed as a barrier electrode layer to suppress the diffusion of the second electrode layer 45.

[0114] The first electrode layer 44 is formed as a film along the main surface of the interlayer insulating layer 41. The first electrode layer 44 enters the emitter contact holes 31 and 42. The first electrode layer 44 is formed as a film within the emitter contact holes 31 and 42. The first electrode layer 44 divides concave spaces within the emitter contact holes 31 and 42. The first electrode layer 44 is connected to the main body region 8, the emitter region 25, and the contact region 36 within the emitter contact holes 31 and 42.

[0115] The first electrode layer 44 may also have a stacked structure comprising titanium layers and titanium nitride layers sequentially stacked from the first main surface 3. The first electrode layer 44 may also have a single-layer structure comprising either a titanium layer or a titanium nitride layer.

[0116] The second electrode layer 45 is formed as a film on the first electrode layer 44. The second electrode layer 45 enters the concave space defined by the first electrode layer 44 within the emitter contact holes 31 and 42. The second electrode layer 45 is electrically connected to the main body region 8, the emitter region 25, and the contact region 36 via the first electrode layer 44. The second electrode layer 45 may also contain a tungsten layer.

[0117] The portion of the main surface of the emitter main electrode layer 43 covering the interlayer insulating layer 41 may also be formed by a third electrode layer containing a conductive material different from that of the second electrode layer 45. In this case, the third electrode layer is formed on the interlayer insulating layer 41 in such a way that it covers the second electrode layer 45.

[0118] The third electrode layer may also include at least one of nickel, palladium, aluminum, copper, aluminum alloys, and copper alloys. The third electrode layer may also include at least one of Al-Si-Cu (aluminum-silicon-copper) alloy, Al-Si (aluminum-silicon) alloy, and Al-Cu (aluminum-copper) alloy, which are examples of aluminum alloys. The third electrode layer is preferably composed of a conductive material with aluminum as its main component.

[0119] In this method, multiple emitter contact electrode layers 51 (contact electrodes) are formed in the emitter main electrode layer 43 by portions located within multiple first contact holes 31. Thus, referring to... Figures 1-6 Multiple emitter contact electrode layers 51 are formed with a structure that is embedded in the surface portion of the semiconductor layer 2.

[0120] The multiple emitter contact electrode layers 51 are arranged and shaped in a manner corresponding to the arrangement and shape of the multiple first contact holes 31. That is, the multiple emitter contact electrode layers 51 are formed with gaps along the second direction Y, and are respectively formed as a band extending along the first direction X.

[0121] The second-direction width of each emitter contact electrode layer 51 is smaller than the second-direction width of the gate trench 12. The first-direction width of each emitter contact electrode layer 51 is larger than the first-direction width of the gate trench 12.

[0122] Each emitter contact electrode layer 51 extends from the inner region of the corresponding gate buried insulating layer 16 through the sidewall of the gate trench 12 and is led out to the surface portion of the first main surface 3. In this configuration, each emitter contact electrode layer 51 extends from the inner region of the gate buried insulating layer 16 through one sidewall and the other sidewall of the gate trench 12 in the first direction X. The width of each emitter contact electrode layer 51 in the second direction is smaller than the width of the corresponding gate buried insulating layer 16 in the second direction.

[0123] Each emitter contact electrode layer 51 also has a lead-out portion 52 extending from one sidewall of the gate trench 12 toward the emitter trench 17. Each lead-out portion 52 extends from the surface portion of the first main surface 3 through the sidewall of the emitter trench 17 and into the emitter trench 17. In this configuration, each lead-out portion 52 extends through one sidewall and the other sidewall of the emitter trench 17 in the first direction X.

[0124] Each emitter contact electrode layer 51 has a first intersection region 53 that intersects with the gate electrode layer 14 when viewed from above. In the first intersection region 53, each emitter contact electrode layer 51 is opposed to the gate electrode layer 14 in the normal direction Z and the second direction Y, separated by the gate buried insulating layer 16. Each emitter contact electrode layer 51 is insulated from the gate electrode layer 14 through the gate buried insulating layer 16.

[0125] Each emitter contact electrode layer 51 has a second intersection region 54 that intersects with the emitter electrode layer 19 when viewed from above. In the second intersection region 54, each emitter contact electrode layer 51 is opposite to the emitter electrode layer 19 in the normal direction Z, separated by an emitter-embedded insulating layer 21. Each emitter contact electrode layer 51 is insulated from the emitter electrode layer 19 through the emitter-embedded insulating layer 21.

[0126] Each emitter contact electrode layer 51 has a connection region 55, which, when viewed from above, connects a first cross region 53 and a second cross region 54 in the region between the gate trench 12 and the emitter trench 17. In the connection region 55, each emitter contact electrode layer 51 is connected to the body region 8, the emitter region 25, and the contact region 36.

[0127] Reference Figure 5 The thickness of the gate buried insulating layer 16 between each emitter contact electrode layer 51 and the gate electrode layer 14 can also be approximately equal to the thickness of the emitter buried insulating layer 21 between each emitter contact electrode layer 51 and the emitter electrode layer 19.

[0128] A collector electrode layer 61, serving as a second main surface electrode layer, is formed on the second main surface electrode layer 4 of the semiconductor layer 2. The collector electrode layer 61 is connected to the collector region 5. Although not shown, a gate main surface electrode layer having the same structure as the emitter main surface electrode layer 43 may also be formed on the interlayer insulating layer 41. The gate main surface electrode layer may also be electrically connected to the gate electrode layer 14 via a gate contact hole formed in the interlayer insulating layer 41.

[0129] Figure 7 This is a cross-sectional perspective view showing a portion of the semiconductor device 62 of the reference example, after removing the structure above the first main surface 3. In the semiconductor device 62 of the reference example, the same reference symbols are used for the structures corresponding to those of the semiconductor device 1, and the descriptions are omitted.

[0130] The semiconductor device 62 of the reference example includes a contact hole 63 and an emitter contact electrode layer 64, which replace the first contact hole 31 and the emitter contact electrode layer 51. The contact hole 63 is formed in the region between the gate trench 12 and the emitter trench 17 on the surface portion of the first main surface 3.

[0131] Contact holes 63 are formed spaced apart from the gate trench 12 and the emitter trench 17. Viewed from above, the contact holes 63 are formed in a band shape extending along the second direction Y. An emitter contact electrode layer 64 is embedded in the contact holes 63.

[0132] The width PA of the contact hole 63 in the first direction is greater than 0.2 μm. The spacing PB between the contact hole 63 and the gate trench 12 is greater than 0.2 μm. The spacing PC between the contact hole 63 and the emitter trench 17 is greater than 0.2 μm. That is, the trench spacing PX between the gate trench 12 and the emitter trench 17 is greater than 0.6 μm.

[0133] The trench spacing PB and PC are generally set considering the dimensional tolerances of the emitter contact electrode layer 64. In the semiconductor device 62 of the reference example, the trench spacing PX is set to a predetermined value greater than 0.6 μm based on the dimensional tolerances of the emitter contact electrode layer 64. Therefore, in the semiconductor device 62 of the reference example, the trench spacing PX cannot be less than 0.6 μm.

[0134] In other words, narrowing the trench pitch PX is hindered by the aforementioned dimensional tolerances. Therefore, the hole accumulation effect between the gate trench 12 and the emitter trench 17 cannot be improved. Consequently, electrical characteristics such as switching speed and withstand voltage are limited.

[0135] To address this, in semiconductor device 1, the emitter contact electrode layer 51 has a structure on the surface portion of the first main surface 3 that intersects with the gate electrode layer 14 through the gate-buried insulating layer 16. Therefore, the emitter contact electrode layer 51 can be formed without leaving a gap with the gate electrode layer 14, thus mitigating the limitations caused by the dimensional tolerances of the emitter contact electrode layer 51. As a result, the trench spacing P0 between the gate trench 12 and the emitter trench 17 can be reduced.

[0136] According to the semiconductor device 1, a trench pitch P0 of 0.2 μm or more and 0.4 μm or less (e.g., about 0.25 μm) can be achieved. As a result, the gate trench 12 and the emitter trench 17 can be narrowed, thus providing a semiconductor device 1 that can help with miniaturization.

[0137] Furthermore, since a narrower pitch can be achieved between the gate trench 12 and the emitter trench 17, the hole accumulation effect between the gate trench 12 and the emitter trench 17 can be improved. Therefore, it is possible to obtain... Figure 8 as well as Figure 9 The electrical properties are shown.

[0138] Figure 8 The current-voltage characteristic curve is obtained through simulation. Figure 8 In the diagram, the vertical axis represents the collector current IC[A], and the horizontal axis represents the collector-emitter voltage VCE[V].

[0139] Figure 8A first characteristic L1 and a second characteristic L2 are shown. The first characteristic L1 represents the characteristic of the semiconductor device 62 of the reference example. The second characteristic L2 represents the characteristic of the semiconductor device 1. Both the first characteristic L1 and the second characteristic L2 represent the current-voltage characteristics when the collector-emitter voltage VCE changes from 0V to 2V.

[0140] Referring to the first characteristic L1, in the semiconductor device 62 of the reference example, the collector-emitter voltage VCE when the collector current IC is 200A, 400A, 600A and 800A are 0.96V, 1.22V, 1.42V and 1.61V respectively.

[0141] Referring to the second characteristic L2, in the semiconductor device 1, the collector-emitter voltage VCE is 0.86V, 1.06V, 1.22V and 1.37V when the collector current IC is 200A, 400A, 600A and 800A, respectively.

[0142] As can be seen from the above, according to semiconductor device 1, compared with semiconductor device 62 of the reference example, the collector-emitter voltage VCE required for the rise can be reduced, and thus the switching speed can be improved.

[0143] Figure 9 The peak collector current (ICP) curve is obtained through simulation. Figure 9 In the diagram, the vertical axis represents the collector current IC[A], and the horizontal axis represents the collector-emitter voltage VCE[V].

[0144] Figure 9 The first characteristic L11 and the second characteristic L12 are shown. The first characteristic L11 represents the current-voltage characteristic of the semiconductor device 62 of the reference example. The second characteristic L12 represents the current-voltage characteristic of the semiconductor device 1. Both the first characteristic L11 and the second characteristic L12 represent the characteristics when the collector-emitter voltage VCE is varied from 0V to 15V.

[0145] Referring to the first characteristic L11, in the semiconductor device 62 of the reference example, the collector peak current ICP is greater than 5000A when the collector-emitter voltage VCE is 10V or more and 15V or less.

[0146] Referring to the second characteristic L12, in the semiconductor device 1, when the collector-emitter voltage VCE is 10V or more and 15V or less, the collector peak current ICP is less than 5000A (4500A or more and less than 5000A).

[0147] As can be seen from the above, according to semiconductor device 1, compared with semiconductor device 62 of the reference example, the collector peak current ICP can be reduced, and thus the short-circuit withstand capability can be improved.

[0148] Figures 10A to 10N This is a cross-sectional perspective view illustrating an example of a method for manufacturing semiconductor device 1. Figures 10A to 10N Is with Figure 1 A three-dimensional cross-sectional view of the corresponding part.

[0149] Reference Figure 10A First, an n-type semiconductor layer 2 is prepared. Next, a p-type collector region 5 and an n-type charge accumulation region 6 are formed within the semiconductor layer 2. The collector region 5 is formed by introducing p-type impurities relative to the second main surface 4 of the semiconductor layer 2. Alternatively, the collector region 5 can be formed on the surface portion of the second main surface 4 of the semiconductor layer 2 by ion implantation via an ion implantation mask (not shown).

[0150] The charge accumulation region 6 is formed by introducing n-type impurities relative to the first main surface 3. The charge accumulation region 6 can also be formed on the surface of the first main surface 3 by ion implantation via an ion implantation mask (not shown).

[0151] Next, refer to Figure 10B A mask 71 with a predetermined pattern is formed on the first main surface 3. The mask 71 has a plurality of openings 72 that expose the areas where the gate trench 12 and the emitter trench 17 should be formed.

[0152] Next, refer to Figure 10C Unwanted portions of the semiconductor layer 2 are removed from the first main surface 3. These unwanted portions can also be removed by etching via the mask 71 (e.g., wet etching). This forms the gate trench 12 and the emitter trench 17. Afterward, the mask 71 is removed.

[0153] Next, refer to Figure 10D A substrate insulating layer 73 is formed to cover the first main surface 3, serving as the substrate for the gate insulating layer 13 and the emitter insulating layer 18. The substrate insulating layer 73 may also be formed by an oxidation process performed relative to the first main surface 3.

[0154] The oxidation process can be either thermal oxidation or wet oxidation. The substrate insulating layer 73 can also contain silicon oxide. The substrate insulating layer 73 can also be formed by CVD (chemical vapor deposition) instead of oxidation.

[0155] Next, refer to Figure 10EA first substrate conductive layer 74 is formed on the first main surface 3 to serve as the substrate for the gate electrode layer 14 and the emitter electrode layer 19. The first substrate conductive layer 74 may also be a conductive polysilicon layer. The first substrate conductive layer 74 may also be formed by a CVD method. The CVD method may also be LP-CVD (Low Pressure CVD).

[0156] Next, the unwanted portions of the first substrate conductive layer 74 are removed. The unwanted portions of the first substrate conductive layer 74 are removed at least until the substrate insulating layer 73 is exposed. The unwanted portions of the first substrate conductive layer 74 can also be removed by etching (e.g., wet etching).

[0157] Unwanted portions of the first substrate conductive layer 74 can also be removed by etching (e.g., wet etching) after the main surface of the first substrate conductive layer 74 has been planarized by CMP (Chemical Mechanical Polishing).

[0158] Next, refer to Figure 10F A mask 75 with a predetermined pattern is formed on the first main surface 3. The mask 75 has a plurality of openings 76 that expose the areas where the gate buried via 15 and the emitter buried via 20 should be formed.

[0159] Next, unwanted portions of the gate electrode layer 14 and the emitter electrode layer 19 are removed. These unwanted portions can also be removed by etching via a mask 75 (e.g., wet etching). This forms the gate buried via 15 and the emitter buried via 20.

[0160] Then, refer to Figure 10G The mask 75 is removed. The gate buried via 15 and the emitter buried via 20 are formed through different masks (not shown). That is, the gate buried via 15 and the emitter buried via 20 can also be formed with different depths.

[0161] Next, refer to Figure 10H A substrate insulating layer 77 is formed on the first main surface 3 to serve as the substrate for the gate buried insulating layer 16 and the emitter buried insulating layer 21. The substrate insulating layer 77 may also contain silicon oxide. The substrate insulating layer 77 may also be formed by a CVD method. The CVD method may also be an LP-CVD method.

[0162] Next, refer to Figure 10IUnwanted portions of the substrate insulating layer 77 are removed. Unwanted portions of the substrate insulating layer 73 can also be removed by etching (e.g., wet etching). Thus, the gate buried insulating layer 16 and the emitter buried insulating layer 21 are formed.

[0163] In this process, the portion covering the first main surface 3 is also removed from the substrate insulating layer 73. This forms the gate insulating layer 13 and the emitter insulating layer 18. Furthermore, this forms the trench gate electrode structure 10 and the trench emitter electrode structure 11.

[0164] Next, refer to Figure 10J A p-type host region 8 and an n+ type emitter region 25 are formed within the semiconductor layer 2. The host region 8 is formed by introducing p-type impurities relative to the first host surface 3. The host region 8 can also be formed on the surface portion of the first host surface 3 by ion implantation via an ion implantation mask (not shown).

[0165] The emitter region 25 is formed by introducing an n-type impurity relative to the first main surface 3. The emitter region 25 can also be formed on the surface of the first main surface 3 by ion implantation via an ion implantation mask (not shown).

[0166] Next, refer to Figure 10K An interlayer insulating layer 41 is formed on the first main surface 3. The interlayer insulating layer 41 is formed on the first main surface 3 in such a way that it covers the trench gate electrode structure 10 and the trench emitter electrode structure 11. This process may also include sequentially forming a BPSG film (e.g., CVD) on the first main surface 3. ) and PSG membranes (e.g. (The process of)

[0167] Next, refer to Figure 10L A mask 78 with a predetermined pattern is formed on the interlayer insulating layer 41. The mask 78 has a plurality of openings 79 that allow the areas where the first contact hole 31 and the second contact hole 42 should be formed.

[0168] Next, refer to Figure 10M Unnecessary portions of the interlayer insulating layer 41, the gate buried insulating layer 16, and the emitter buried insulating layer 21 are removed. Unnecessary portions of the interlayer insulating layer 41, etc., can also be removed by etching via the mask 78 (e.g., dry etching).

[0169] Furthermore, in this process, after removing the unwanted portions of the interlayer insulating layer 41, the unwanted portions of the semiconductor layer 2 are removed. The unwanted portions of the semiconductor layer 2 can also be removed by an etching method (e.g., dry etching) via a mask 78.

[0170] Thus, a first contact hole 31 is formed on the first main surface 3, and a second contact hole 42 communicating with the first contact hole 31 is formed on the interlayer insulating layer 41. After that, the mask 78 is removed.

[0171] Next, a contact area 36 is formed on the surface of the first main surface 3. More specifically, the contact area 36 is formed on the surface of the main body region 8 in the region along the bottom wall of the first contact hole 31. The contact area 36 may also be formed in the region along the side wall and bottom wall of the first contact hole 31.

[0172] The contact region 36 is formed by introducing p-type impurities relative to the first contact hole 31. Alternatively, the contact region 36 can be introduced into the first contact hole 31 via ion implantation through an ion implantation mask (not shown). This forms a contact region 36 along the bottom wall of the first contact hole 31.

[0173] Contact area 36 can also be achieved through Figure 10J In this process, p-type impurities are introduced relative to the first main surface 3 to form the contact region 36. In this case, the contact region 36 can also be formed on the surface of the first main surface 3 by ion implantation via an ion implantation mask (not shown). In this process, the contact region 36 is also formed along the bottom wall of the first contact hole 31.

[0174] Next, refer to Figure 10N An emitter main electrode layer 43 is formed on the interlayer insulating layer 41. This process includes the process of sequentially forming a first electrode layer 44 and a second electrode layer 45 on the interlayer insulating layer 41.

[0175] The process of forming the first electrode layer 44 includes the process of sequentially forming a titanium layer and a titanium nitride layer on the interlayer insulating layer 41. The titanium layer and the titanium nitride layer can also be formed by sputtering and CVD, respectively. The process of forming the second electrode layer 45 includes the process of forming a tungsten layer on the first electrode layer 44. The tungsten layer can also be formed by CVD.

[0176] Thus, an emitter main electrode layer 43 is formed on the interlayer insulating layer 41. Furthermore, an emitter contact electrode layer 51 is formed in the portion of the emitter main electrode layer 43 that extends into the first contact hole 31. Additionally, a collector electrode layer 61 is formed on the second main surface 4 of the semiconductor layer 2. Through the processes described above, the semiconductor device 1 is formed.

[0177] Figure 11 This is a cross-sectional perspective view showing a portion of the semiconductor device 81 according to the second embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described in the semiconductor device 1, and descriptions will be omitted.

[0178] Reference Figure 11 In this configuration, each first contact hole 31 intersects only with the gate trench 12 when viewed from above. The lead-out portion 32 of each first contact hole 31 is formed with a gap between it and the emitter trench 17. That is, the lead-out portion 32 does not reach the emitter trench 17.

[0179] In this configuration, each emitter contact electrode layer 51 intersects only with the gate trench 12 when viewed from above. The lead-out portion 52 of each emitter contact electrode layer 51 is formed with a gap between it and the emitter trench 17. That is, the lead-out portion 52 does not reach the emitter trench 17.

[0180] As described above, the semiconductor device 81 can achieve the same effect as the semiconductor device 1. The semiconductor device 81 can be manufactured simply by changing the layout of each mask in the manufacturing method of the semiconductor device 1.

[0181] Figure 12 This is a cross-sectional perspective view showing a portion of the semiconductor device 91 according to the third embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described in the semiconductor device 1, and descriptions will be omitted.

[0182] Reference Figure 12 In this configuration, the plurality of first contact holes 31 include a first contact hole 92A and a first contact hole 92B. The first contact hole 92A intersects only with the gate trench 12 when viewed from above. The first contact hole 92B intersects only with the emitter trench 17 when viewed from above.

[0183] In this configuration, the plurality of emitter contact electrode layers 51 include emitter contact electrode layer 93A and emitter contact electrode layer 93B. Emitter contact electrode layer 93A is embedded in the first contact hole 92A. Emitter contact electrode layer 93A intersects only with the gate trench 12 when viewed from above. Emitter contact electrode layer 93B is embedded in the first contact hole 92B. Emitter contact electrode layer 93B intersects only with the emitter trench 17 when viewed from above.

[0184] As described above, the semiconductor device 91 can achieve the same effect as the semiconductor device 1. The semiconductor device 91 can be manufactured simply by changing the layout of each mask in the manufacturing method of the semiconductor device 1.

[0185] Figure 13 This is a cross-sectional perspective view showing a portion of the semiconductor device 101 according to the fourth embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described in the semiconductor device 1, and descriptions will be omitted.

[0186] Reference Figure 13In this configuration, the semiconductor device 101 includes a trench emitter electrode configuration 102 in place of the trench emitter electrode configuration 11. The trench emitter electrode configuration 102 has the same configuration as the trench gate electrode configuration 10.

[0187] More specifically, the trench emitter electrode structure 102 includes an emitter trench 103, an emitter insulating layer 104, an emitter electrode layer 105, a plurality of emitter embedding holes 106, and a plurality of emitter embedding insulating layers 107.

[0188] Emitter trench 103, emitter insulating layer 104, emitter electrode layer 105, emitter buried via 106, and emitter buried insulating layer 107 have the same structure as gate trench 12, gate insulating layer 13, gate electrode layer 14, gate buried via 15, and gate buried insulating layer 16. Detailed description of the trench emitter electrode structure 102 is omitted.

[0189] In this configuration, each first contact hole 31 has a first intersection region 108 that intersects with the gate electrode layer 14 when viewed from above. In the first intersection region 108, the sidewalls and bottom wall of each first contact hole 31 are defined by the gate embedded insulating layer 16.

[0190] Each first contact hole 31 has a second intersection region 109 that intersects with the emitter electrode layer 105 when viewed from above. In the second intersection region 109, the sidewalls and bottom walls of each first contact hole 31 are defined by the emitter embedded insulating layer 107.

[0191] Each first contact hole 31 has a connection region 110, which, when viewed from above, connects a first cross region 108 and a second cross region 109 in the region between the gate trench 12 and the emitter trench 17. In the connection region 110, the sidewalls and bottom walls of each first contact hole 31 are divided by a semiconductor layer 2.

[0192] The sidewalls of each first contact hole 31 are formed on the same surface in the first intersection region 108, the second intersection region 109, and the connecting region 110. The bottom wall of each first contact hole 31 is formed on the same surface in the first intersection region 108, the second intersection region 109, and the connecting region 110.

[0193] In this configuration, each emitter contact electrode layer 51 has a first intersection region 111 that intersects with the gate electrode layer 14 when viewed from above. In the first intersection region 111, each emitter contact electrode layer 51 is positioned opposite the gate electrode layer 14 in the normal direction Z and the second direction Y, separated by a gate-buried insulating layer 16. Each emitter contact electrode layer 51 is insulated from the gate electrode layer 14 through the gate-buried insulating layer 16.

[0194] Each emitter contact electrode layer 51 has a second intersection region 112 that intersects with the emitter electrode layer 105 when viewed from above. In the second intersection region 112, each emitter contact electrode layer 51 is opposite to the emitter electrode layer 105 in the normal direction Z and the second direction Y, separated by an emitter-embedded insulating layer 107. Each emitter contact electrode layer 51 is insulated from the emitter electrode layer 105 through the emitter-embedded insulating layer 107.

[0195] Each emitter contact electrode layer 51 has a connection region 113, which, when viewed from above, connects a first cross region 111 and a second cross region 112 in the region between the gate trench 12 and the emitter trench 17. In the connection region 113, each emitter contact electrode layer 51 is connected to the body region 8, the emitter region 25, and the contact region 36.

[0196] As described above, the semiconductor device 101 can achieve the same effect as the semiconductor device 1 described above. The semiconductor device 101 can be manufactured simply by changing the layout of each mask in the manufacturing method of the semiconductor device 1.

[0197] Figure 14 This is a cross-sectional perspective view showing a portion of the semiconductor device 121 according to the fifth embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described for the semiconductor device 101, and descriptions will be omitted.

[0198] Reference Figure 14 In this configuration, each first contact hole 31 intersects only with the gate trench 12 when viewed from above. The lead-out portion 32 of each first contact hole 31 is formed with a gap between it and the emitter trench 17. That is, the lead-out portion 32 does not reach the emitter trench 17.

[0199] In this configuration, each emitter contact electrode layer 51 intersects only with the gate trench 12 when viewed from above. The lead-out portion 52 of each emitter contact electrode layer 51 is formed with a gap between it and the emitter trench 17. That is, the lead-out portion 52 does not reach the emitter trench 17.

[0200] In this case, such as Figure 14 As shown, the trench emitter electrode structure 102 does not necessarily include the emitter embedment hole 106 and the emitter embedment insulating layer 107.

[0201] As described above, the semiconductor device 121 can achieve the same effect as that described for the semiconductor device 1. The semiconductor device 121 can be manufactured simply by changing the layout of each mask in the manufacturing method of the semiconductor device 1.

[0202] Figure 15This is a cross-sectional perspective view showing a portion of the semiconductor device 131 according to the sixth embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described for the semiconductor device 101, and descriptions will be omitted.

[0203] Reference Figure 15 In this configuration, the plurality of first contact holes 31 include a first contact hole 132A and a first contact hole 132B. The first contact hole 132A intersects only with the gate trench 12 when viewed from above. The first contact hole 132B intersects only with the emitter trench 17 when viewed from above.

[0204] In this configuration, the plurality of emitter contact electrode layers 51 include emitter contact electrode layer 133A and emitter contact electrode layer 133B. Emitter contact electrode layer 133A is embedded in the first contact hole 132A. Emitter contact electrode layer 133A intersects only with the gate trench 12 when viewed from above. Emitter contact electrode layer 133B is embedded in the first contact hole 132B. Emitter contact electrode layer 133B intersects only with the emitter trench 17 when viewed from above.

[0205] As described above, the semiconductor device 131 can achieve the same effect as that described for semiconductor device 1. Semiconductor device 131 can be manufactured simply by changing the layout of each mask in the manufacturing method of semiconductor device 1.

[0206] Figure 16 This is a cross-sectional perspective view showing a portion of the semiconductor device 141 according to the seventh embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described in the semiconductor device 1, and descriptions will be omitted.

[0207] Reference Figure 16 In this configuration, the semiconductor device 141 includes a second trench gate electrode configuration 142 in place of the trench emitter electrode configuration 11. The second trench gate electrode configuration 142 has the same configuration as the trench gate electrode configuration 10.

[0208] More specifically, the second trench gate electrode structure 142 includes a second gate trench 143, a second gate insulating layer 144, a second gate electrode layer 145, a plurality of second gate buried vias 146, and a plurality of second gate buried insulating layers 147. The second gate electrode layer 145 is formed at the same potential as the gate electrode layer 14.

[0209] The second gate trench 143, the second gate insulating layer 144, the second gate electrode layer 145, the second gate buried via 146, and the second gate buried insulating layer 147 have the same structure as the gate trench 12, the gate insulating layer 13, the gate electrode layer 14, the gate buried via 15, and the gate buried insulating layer 16. A detailed description of the second trench gate electrode structure 142 is omitted.

[0210] In the surface portion of the main body region 8, along the sidewall of the second gate trench 143, an n+ type emitter region 25 is formed. Multiple emitter regions 25 are formed along one sidewall and the other sidewall of the second gate trench 143 in the first direction X. The multiple emitter regions 25 are each formed in a band shape extending along the second direction Y.

[0211] In this configuration, the emitter region 25 formed along the sidewall of the gate trench 12 is integrally formed with the emitter region 25 formed along the sidewall of the second gate trench 143. That is, in the region between the gate trench 12 and the second gate trench 143, the emitter region 25 is shared by both the gate trench 12 and the second gate trench 143.

[0212] Each first contact hole 31 has a first intersection region 148 that intersects with the gate electrode layer 14 when viewed from above. In the first intersection region 148, the sidewalls and bottom wall of each first contact hole 31 are defined by the gate embedded insulating layer 16.

[0213] Each first contact hole 31 has a second intersection region 149 that intersects with the second gate electrode layer 145 when viewed from above. In the second intersection region 149, the sidewalls and bottom walls of each first contact hole 31 are defined by the second gate embedded insulating layer 147.

[0214] Each first contact hole 31 has a connection region 150, which, when viewed from above, connects a first cross region 148 and a second cross region 149 in the area between the gate trench 12 and the second gate trench 143. In the connection region 150, the sidewalls and bottom walls of each first contact hole 31 are defined by a semiconductor layer 2.

[0215] The sidewalls of each first contact hole 31 are formed on the same surface in the first intersection region 148, the second intersection region 149, and the connecting region 150. The bottom wall of each first contact hole 31 is formed on the same surface in the first intersection region 148, the second intersection region 149, and the connecting region 150.

[0216] In this configuration, each emitter contact electrode layer 51 has a first intersection region 151 that intersects with the gate electrode layer 14 when viewed from above. In the first intersection region 151, each emitter contact electrode layer 51 is positioned opposite the gate electrode layer 14 in the normal direction Z and the second direction Y, separated by a gate-buried insulating layer 16. Each emitter contact electrode layer 51 is insulated from the gate electrode layer 14 through the gate-buried insulating layer 16.

[0217] Each emitter contact electrode layer 51 has a second intersection region 152 that intersects with the second gate electrode layer 145 when viewed from above. In the second intersection region 152, each emitter contact electrode layer 51 is opposed to the second gate electrode layer 145 in the normal direction Z and the second direction Y through the second gate buried insulating layer 147. Each emitter contact electrode layer 51 is insulated from the second gate electrode layer 145 through the second gate buried insulating layer 147.

[0218] Each emitter contact electrode layer 51 has a connection region 153, which, when viewed from above, connects the first cross region 151 and the second cross region 152 in the area between the gate trench 12 and the second gate trench 143. In the connection region 153, each emitter contact electrode layer 51 is connected to the body region 8, the emitter region 25, and the contact region 36.

[0219] As described above, the semiconductor device 141 can achieve the same effect as that described for semiconductor device 1. Semiconductor device 141 can be manufactured simply by changing the layout of each mask in the manufacturing method of semiconductor device 1.

[0220] Figure 17 This is a cross-sectional perspective view showing a portion of the semiconductor device 161 according to the eighth embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described for the semiconductor device 141, and descriptions will be omitted.

[0221] Reference Figure 17 In this configuration, the plurality of first contact holes 31 include a first contact hole 162A and a first contact hole 162B. The first contact hole 162A intersects only with the gate trench 12 when viewed from above. The first contact hole 162B intersects only with the second gate trench 143 when viewed from above.

[0222] In this configuration, the plurality of emitter contact electrode layers 51 include emitter contact electrode layer 163A and emitter contact electrode layer 163B. Emitter contact electrode layer 163A is embedded in the first contact hole 162A. Emitter contact electrode layer 163A intersects only with the gate trench 12 when viewed from above. Emitter contact electrode layer 163B is embedded in the first contact hole 162B. Emitter contact electrode layer 163B intersects only with the second gate trench 143 when viewed from above.

[0223] As described above, the semiconductor device 161 can achieve the same effect as that described for semiconductor device 1. Semiconductor device 161 can be manufactured simply by changing the layout of each mask in the manufacturing method of semiconductor device 1.

[0224] Figure 18 This is a cross-sectional perspective view showing a portion of the semiconductor device 171 according to the ninth embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described in the semiconductor device 1, and descriptions will be omitted.

[0225] Reference Figure 18 In this configuration, a plurality of trench gate electrode structures 10 are formed on the surface portion of the first main surface 3. In this configuration, the plurality of trench gate electrode structures 10 include a first trench gate electrode structure 172 and a second trench gate electrode structure 173 formed with gaps between them.

[0226] The first trench gate electrode structure 172 and the second trench gate electrode structure 173 are formed with a gap along the first direction X. The first trench gate electrode structure 172 and the second trench gate electrode structure 173 extend in a band shape along the second direction Y when viewed from above.

[0227] The trench spacing PT between the first trench gate electrode structure 172 and the second trench gate electrode structure 173 can also be 1.6 μm or more and 4.8 μm or less. The trench spacing PT can also be 1.6 μm or more and 2.4 μm or less, 2.4 μm or more and 3.2 μm or less, 3.2 μm or more and 4.0 μm or less, or 4.0 μm or more and 4.8 μm or less. Preferably, the trench spacing PT is 1.5 μm or more and 3.0 μm or less (e.g., around 2.25 μm).

[0228] The first trench gate electrode structure 172 includes a first gate trench 174, a first gate insulating layer 175, a first gate electrode layer 176, a plurality of first gate buried vias 177, and a plurality of first gate buried insulating layers 178.

[0229] The first gate trench 174, the first gate insulating layer 175, the first gate electrode layer 176, the first gate buried via 177, and the first gate buried insulating layer 178 each have the same structure as the gate trench 12, the gate insulating layer 13, the gate electrode layer 14, the gate buried via 15, and the gate buried insulating layer 16 in the first embodiment. A detailed description of the first trench gate electrode structure 172 is omitted.

[0230] The second trench gate electrode structure 173 includes a second gate trench 184, a second gate insulating layer 185, a second gate electrode layer 186, a plurality of second gate buried vias 187, and a plurality of second gate buried insulating layers 188.

[0231] The second gate trench 184, the second gate insulating layer 185, the second gate electrode layer 186, the second gate buried via 187, and the second gate buried insulating layer 188 each have the same structure as the gate trench 12, the gate insulating layer 13, the gate electrode layer 14, the gate buried via 15, and the gate buried insulating layer 16 in the first embodiment. A detailed description of the second trench gate electrode structure 173 is omitted.

[0232] On the surface portion of the first main surface 3, in the region between the first trench gate electrode structure 172 and the second trench gate electrode structure 173, a plurality of (two or more) trench emitter electrode structures 11 are formed. In this configuration, the plurality of trench emitter electrode structures 11 include a first trench emitter electrode structure 191 and a second trench emitter electrode structure 192 formed with a gap between them.

[0233] In the region between the first trench gate electrode structure 172 and the second trench gate electrode structure 173, only one trench emitter electrode structure may be formed. Alternatively, in the region between the first trench gate electrode structure 172 and the second trench gate electrode structure 173, four or more trench emitter electrode structures 11 may be formed.

[0234] The first trench emitter electrode structure 191 and the second trench emitter electrode structure 192 are formed with a gap along the first direction X. The first trench emitter electrode structure 191 and the second trench emitter electrode structure 192 extend in a band shape along the second direction Y when viewed from above.

[0235] The first trench emitter electrode structure 191 includes a first emitter trench 193, a first emitter insulating layer 194, a first emitter electrode layer 195, a first emitter buried hole 196, and a first emitter buried insulating layer 197.

[0236] The first emitter trench 193, the first emitter insulating layer 194, the first emitter electrode layer 195, the first emitter embedment hole 196, and the first emitter embedment insulating layer 197 each have the same structure as the emitter trench 17, the emitter insulating layer 18, the emitter electrode layer 19, the emitter embedment hole 20, and the emitter embedment insulating layer 21 in the first embodiment. A detailed description of the first trench emitter electrode structure 191 is omitted.

[0237] The second trench emitter electrode structure 192 includes a second emitter trench 203, a second emitter insulating layer 204, a second emitter electrode layer 205, a second emitter embedded hole 206, and a second emitter embedded insulating layer 207.

[0238] The second emitter trench 203, second emitter insulating layer 204, second emitter electrode layer 205, second emitter embedment hole 206, and second emitter embedment insulating layer 207 each have the same structure as the emitter trench 17, emitter insulating layer 18, emitter electrode layer 19, emitter embedment hole 20, and emitter embedment insulating layer 21 in the first embodiment. A detailed description of the second trench emitter electrode structure 192 is omitted.

[0239] The first trench spacing P1 between the first trench gate electrode structure 172 and the first trench emitter electrode structure 191 can also be 0.1 μm or more and less than 0.6 μm. The first trench spacing P1 can also be 0.1 μm or more and less than 0.2 μm, 0.2 μm or more and less than 0.3 μm, 0.3 μm or more and less than 0.4 μm, 0.4 μm or more and less than 0.5 μm, or 0.5 μm or more and less than 0.6 μm. The first trench spacing P1 is preferably 0.2 μm or more and less than 0.4 μm (for example, around 0.25 μm).

[0240] The second trench spacing P2 between the first trench emitter electrode structure 191 and the second trench emitter electrode structure 192 can also be 0.1 μm or more and less than 0.6 μm. The second trench spacing P2 can also be 0.1 μm or more and less than 0.2 μm, 0.2 μm or more and less than 0.3 μm, 0.3 μm or more and less than 0.4 μm, 0.4 μm or more and less than 0.5 μm, or 0.5 μm or more and less than 0.6 μm. The second trench spacing P2 is preferably 0.2 μm or more and less than 0.4 μm (for example, around 0.25 μm).

[0241] The third trench spacing P3 between the second trench gate electrode structure 173 and the second trench emitter electrode structure 192 can also be 0.1 μm or more and less than 0.6 μm. The third trench spacing P3 can also be 0.1 μm or more and less than 0.2 μm, 0.2 μm or more and less than 0.3 μm, 0.3 μm or more and less than 0.4 μm, 0.4 μm or more and less than 0.5 μm, or 0.5 μm or more and less than 0.6 μm. The third trench spacing P3 is preferably 0.2 μm or more and less than 0.4 μm (e.g., around 0.25 μm).

[0242] In the surface layer of the first main surface 3, in the region between the first trench emitter electrode structure 191 and the second trench emitter electrode structure 192, no emitter region 25 is formed. In the surface layer of the first main surface 3, in the region between the first trench emitter electrode structure 191 and the second trench emitter electrode structure 192, a p-type impurity region 208 is formed.

[0243] Impurity region 208 is exposed from the sidewalls of the first emitter trench 193 and the second emitter trench 203. Impurity region 208 is formed on the surface of charge accumulation region 6. Impurity region 208 is exposed from the first main surface 3. Impurity region 208 is formed to the same depth as the main region 8. Impurity region 208 has a p-type impurity concentration equal to that of the main region 8. Impurity region 208 is not electrically connected to emitter region 25 and thus has different electrical properties from the main region 8.

[0244] In this configuration, a plurality of first contact holes 31 are formed with spacing along the second direction Y when viewed from above, and extend into a band shape along the first direction X. In this configuration, each first contact hole 31 intersects with the first trench gate electrode structure 172, the first trench emitter electrode structure 191, the second trench emitter electrode structure 192, and the second trench gate electrode structure 173.

[0245] In this configuration, multiple emitter contact electrode layers 51 are formed with gaps along the second direction Y when viewed from above, and extend in a band shape along the first direction X. In this configuration, each emitter contact electrode layer 51 intersects with the first trench gate electrode structure 172, the first trench emitter electrode structure 191, the second trench emitter electrode structure 192, and the second trench gate electrode structure 173. At the portion of each emitter contact electrode layer 51 that contacts the semiconductor layer 2, it connects with the main body region 8, the emitter region 25, the contact region 36, and the impurity region 208.

[0246] As described above, the semiconductor device 171 can achieve the same effect as that described for semiconductor device 1. Semiconductor device 171 can be manufactured simply by changing the layout of each mask in the manufacturing method of semiconductor device 1.

[0247] Figure 19 This is a cross-sectional perspective view showing a portion of the semiconductor device 211 according to the tenth embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described for the semiconductor device 171, and descriptions will be omitted.

[0248] Reference Figure 19In this configuration, the plurality of first contact holes 31 include a plurality of first contact holes 212A and a plurality of first contact holes 212B. The plurality of first contact holes 212A are formed spaced apart along the first gate trench 174 (second direction Y) in a top view. The plurality of first contact holes 212A intersect only with the first gate trench 174 in a top view.

[0249] Multiple first contact holes 212B are formed spaced apart along the second gate trench 184 (second direction Y) when viewed from above. In this configuration, the multiple first contact holes 212B are opposite to corresponding first contact holes 212A along the first direction X. The multiple first contact holes 212A intersect the second gate trench 184 only when viewed from above.

[0250] In this configuration, the plurality of emitter contact electrode layers 51 include a plurality of emitter contact electrode layers 213A and a plurality of emitter contact electrode layers 213B. The plurality of emitter contact electrode layers 213A are respectively embedded in corresponding first contact holes 212A. The plurality of emitter contact electrode layers 213A are formed with spacing along the first gate trench 174 (second direction Y) in a top view. The plurality of emitter contact electrode layers 213A intersect only with the first gate trench 174 in a top view.

[0251] Multiple emitter contact electrode layers 213B are embedded in corresponding first contact holes 212B. The multiple emitter contact electrode layers 213B are formed with gaps along the second gate trench 184 (second direction Y) when viewed from above. The multiple emitter contact electrode layers 213B intersect only with the second gate trench 184 when viewed from above. That is, in this configuration, each emitter contact electrode layer 51 is not electrically connected to the impurity region 208. The impurity region 208 is formed in an electrically floating state.

[0252] As described above, semiconductor device 211 can achieve the same effect as semiconductor device 1. Semiconductor device 211 can be manufactured simply by changing the layout of each mask in the manufacturing method of semiconductor device 1.

[0253] Figure 20 This is a cross-sectional perspective view showing a portion of the semiconductor device 221 according to the eleventh embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, for structures corresponding to the structure described in the semiconductor device 171 of the ninth embodiment, the same reference numerals will be used and descriptions will be omitted.

[0254] In the semiconductor device 171 described above, an example in which a p-type collector region 5 is formed on the surface layer of the second main surface 4 has been described. In contrast, in the semiconductor device 221, an n-type drain region 222 is formed on the surface layer of the second main surface 4 instead of the p-type collector region 5.

[0255] Thus, semiconductor device 221 has a basic configuration of a trench-gate type MISFET (Metal Insulator Semiconductor Field Effect Transistor). The description of semiconductor device 171 above replaces "emitter" with "source" and "collector" with "drain," and is adapted to the description of semiconductor device 221.

[0256] As described above, semiconductor device 221 can achieve the same effect as semiconductor device 1. In the manufacturing method of semiconductor device 1, semiconductor device 221 can be manufactured by simply replacing the p-type collector region 5 with an n-type drain region 222 and changing the layout of each mask.

[0257] Of course, the structure forming the drain region 222 can also be applied to embodiments other than the ninth embodiment (semiconductor device 171). In this case, in the embodiment where the drain region 222 is applied, the "emitter" is replaced by the "source" and the "collector" is replaced by the "drain".

[0258] Figure 21 This is a cross-sectional perspective view showing a portion of the semiconductor device 241 according to the twelfth embodiment of the present invention, with the structure above the first main surface 3 removed. Hereinafter, the same reference numerals will be used to denote structures corresponding to those described for the semiconductor device 171, and descriptions will be omitted.

[0259] Semiconductor device 241 includes semiconductor device 171 in the ninth embodiment (see reference). Figure 18 The semiconductor device 141 of the seventh embodiment is combined with (see) Figure 16 The semiconductor device 241 has a structure consisting of multiple trench gate electrodes 10. Specifically, the semiconductor device 241 does not have a trench emitter electrode structure 11.

[0260] Multiple trench gate electrode structures 10 are formed with gaps along a first direction X. The multiple trench gate electrode structures 10 extend in a band shape along a second direction Y when viewed from above.

[0261] The trench spacing PG between the multiple trench gate electrode structures 10 can be 0.1 μm or more and less than 0.6 μm. The individual trench spacing PG can also be 0.1 μm or more and less than 0.2 μm, 0.2 μm or more and less than 0.3 μm, 0.3 μm or more and less than 0.4 μm, 0.4 μm or more and less than 0.5 μm, or 0.5 μm or more and less than 0.6 μm. The individual trench spacing PG is preferably 0.2 μm or more and less than 0.4 μm (e.g., around 0.25 μm). The multiple trench spacings PG can be equal or different.

[0262] The multiple trench gate electrode structures 10 include a gate trench 12, a gate insulating layer 13, a gate electrode layer 14, multiple gate buried vias 15, and multiple gate buried insulating layers 16. Descriptions of the gate trench 12, gate insulating layer 13, gate electrode layer 14, multiple gate buried vias 15, and multiple gate buried insulating layers 16 are omitted.

[0263] In this configuration, a plurality of first contact holes 31 are formed spaced apart along the second direction Y when viewed from above, and extend in a band shape along the first direction X. In this configuration, the plurality of first contact holes 31 intersect with a plurality of trench gate electrode structures 10 when viewed from above.

[0264] In this configuration, multiple emitter contact electrode layers 51 are formed with spacing along the second direction Y when viewed from above, and extend in a band shape along the first direction X. In this configuration, the multiple emitter contact electrode layers 51 intersect with multiple trench gate electrode structures 10 when viewed from above. Each emitter contact electrode layer 51 is connected to the main body region 8, the emitter region 25, and the contact region 36 at the portion that contacts the semiconductor layer 2.

[0265] As described above, semiconductor device 241 can achieve the same effect as semiconductor device 1. Semiconductor device 241 can be manufactured simply by changing the layout of each mask in the manufacturing method of semiconductor device 1.

[0266] Figure 22 This is a cross-sectional perspective view showing a portion of the semiconductor device 251 according to the thirteenth embodiment of the present invention. Figure 23 It means Figure 22 The cross-sectional perspective view of a portion of the semiconductor device 251 shown is a view after removing the structure above the first main surface 3. Figure 24 yes Figure 23 Top view. Figure 25 It is along Figure 24 The cross-sectional view of the XXV-XXV line is shown. Hereinafter, for semiconductor device 211 (refer to...) Figure 19 The structures described correspond to the structures described, and are marked with the same reference symbol and the explanation is omitted.

[0267] Reference Figures 22-25 Similar to semiconductor device 211, the plurality of first contact holes 31 include a plurality of first contact holes 212A and a plurality of first contact holes 212B. (See reference...) Figure 25 In this configuration, the bottom wall of each first contact hole 212A is formed as an uneven shape, protruding towards the first main surface 3 and sinking towards the second main surface 4. More specifically, each first contact hole 212A includes a first region 252 formed in the first gate trench 174 and a second region 253 formed in the semiconductor layer 2.

[0268] The sidewalls and bottom wall of the first region 252 are defined by the first gate insulating layer 175 and the first gate embedded insulating layer 178. The bottom wall of the first region 252 is located on the side of the second main surface 4 relative to the first main surface 3 in the thickness direction of the semiconductor layer 2. More specifically, the bottom wall of the first region 252 is located in the region between the first main surface 3 and the bottom of the main body region 8 in the thickness direction of the semiconductor layer 2. Of course, the bottom wall of the first region 252 can also be located on the same plane as the first main surface 3. That is, a first contact hole 212A without the first region 252 can also be formed.

[0269] The sidewalls and bottom wall of the second region 253 are defined by the semiconductor layer 2 and the trench gate electrode structure 10 (first trench gate electrode structure 172). The sidewalls of the second region 253 may also be defined by the first gate insulating layer 175 and / or the first gate buried insulating layer 178. The bottom wall of the second region 253 is located in the region between the bottom wall of the first region 252 and the bottom of the main body region 8 in the thickness direction of the semiconductor layer 2. More specifically, the bottom wall of the second region 253 is located in the region between the bottom of the emitter region 25 and the bottom of the main body region 8 in the thickness direction of the semiconductor layer 2.

[0270] Reference Figure 25 In this configuration, the bottom wall of the first contact hole 212B is formed as an uneven shape, protruding towards the first main surface 3 and sinking towards the second main surface 4. More specifically, each first contact hole 212B includes a first region 254 formed in the second gate trench 184 and a second region 255 formed in the semiconductor layer 2.

[0271] The sidewalls and bottom wall of the first region 254 are defined by the second gate insulating layer 185 and the second gate embedded insulating layer 188. The bottom wall of the first region 254 is located on the side of the second main surface 4 relative to the first main surface 3 in the thickness direction of the semiconductor layer 2. More specifically, the bottom wall of the first region 254 is located in the region between the first main surface 3 and the bottom of the main body region 8 in the thickness direction of the semiconductor layer 2. Of course, the bottom wall of the first region 254 can also be located on the same plane as the first main surface 3. That is, a first contact hole 212B without the first region 254 can also be formed.

[0272] The sidewalls and bottom wall of the second region 255 are defined by the semiconductor layer 2 and the trench gate electrode configuration 10. The sidewalls of the second region 255 may also be defined by the second gate insulating layer 185 and / or the second gate buried insulating layer 188. The bottom wall of the second region 255 is located in the region between the bottom wall of the first region 254 and the bottom of the main body region 8 in the thickness direction of the semiconductor layer 2. More specifically, the bottom wall of the second region 255 is located in the region between the bottom of the emitter region 25 and the bottom of the main body region 8 in the thickness direction of the semiconductor layer 2.

[0273] Multiple first contact holes 31 in this manner can be manufactured simply by changing the layout of each mask and the etching conditions in the manufacturing method of semiconductor device 1. That is, during the removal process of semiconductor layer 2 (refer to...) Figure 10M By removing unwanted portions of the semiconductor layer 2 in a manner where the bottom wall of the first contact hole 31 is located on the side of the second main surface 4 relative to the upper surface of the first gate buried insulating layer 178 (second gate buried insulating layer 188), a plurality of first contact holes 31 are formed. At this time, part or all of the first gate insulating layer 175 that should divide the second region 253 can also be removed by etching. Similarly, part or all of the second gate insulating layer 185 that should divide the second region 255 can also be removed by etching.

[0274] The emitter main surface electrode layer 43 includes multiple emitter contact electrode layers 51 and a main surface electrode layer 256. The multiple emitter contact electrode layers 51 include multiple emitter contact electrode layers 213A and multiple emitter contact electrode layers 213B.

[0275] Multiple emitter contact electrode layers 213A are embedded in corresponding first contact holes 212A. Each emitter contact electrode layer 213A has an uneven portion in the corresponding first contact hole 212A that engages with the first region 252 and the second region 253.

[0276] Each emitter contact electrode layer 213A includes a first electrode layer 44 and a second electrode layer 45. The first electrode layer 44 divides a concave first space SP1 within a first region 252. The first electrode layer 44 also divides a concave second space SP2 within a second region 253. When the bottom wall of the first region 252 is located on the same plane as the first main surface 3, the first space SP1 is not formed, but only the second space SP2 is formed.

[0277] The second electrode layer 45 fills the first space SP1 and the second space SP2 within the first contact hole 212A. In this way, each emitter contact electrode layer 213A having a concave-convex portion that engages with the first region 252 and the second region 253 is formed.

[0278] Multiple emitter contact electrode layers 213B are embedded in corresponding first contact holes 212B. Each emitter contact electrode layer 213B has an uneven portion within its corresponding first contact hole 212B that engages with the first region 254 and the second region 255.

[0279] Each emitter contact electrode layer 213B includes a first electrode layer 44 and a second electrode layer 45. The first electrode layer 44 divides a concave first space SP3 within a first region 254. The first electrode layer 44 also divides a concave second space SP4 within a second region 255. When the bottom wall of the first region 254 is located on the same plane as the first main surface 3, the first space SP3 is not formed, but only the second space SP4 is formed.

[0280] The second electrode layer 45 fills the first space SP3 and the second space SP4 within the first contact hole 212B. In this way, each emitter contact electrode layer 213B having a concave-convex portion that engages with the first region 254 and the second region 255 is formed.

[0281] The main surface electrode layer 256 covers a plurality of emitter contact electrode layers 51 on the interlayer insulating layer 41. The main surface electrode layer 256 has a stacked structure including a first main surface electrode layer 257 and a second main surface electrode layer 258 stacked sequentially from the side of the interlayer insulating layer 41.

[0282] The first main surface electrode layer 257 forms the base layer of the second main surface electrode layer 258. The first main surface electrode layer 257 is formed as a barrier electrode layer to suppress the diffusion of the second main surface electrode layer 258. The first main surface electrode layer 257 is formed as a film along the main surface of the interlayer insulating layer 41, and together covers the plurality of emitter contact electrode layers 51. The first main surface electrode layer 257 is connected to the plurality of emitter contact electrode layers 51.

[0283] The first main electrode layer 257 may also have a stacked structure comprising a titanium layer and a titanium nitride layer sequentially stacked from the side of the interlayer insulating layer 41. The first main electrode layer 257 may also have a single-layer structure comprising a titanium layer or a titanium nitride layer.

[0284] The second main surface electrode layer 258 is formed as a film on the first main surface electrode layer 257. The second main surface electrode layer 258 is electrically connected to the plurality of emitter contact electrode layers 51 via the first electrode layer 44.

[0285] The second main electrode layer 258 may also contain at least one of aluminum, copper, aluminum alloy, and copper alloy. The second main electrode layer 258 is preferably composed of a conductive material with aluminum as the main component. The second main electrode layer 258 may also contain at least one of Al-Si-Cu (aluminum-silicon-copper) alloy, Al-Si (aluminum-silicon) alloy, and Al-Cu (aluminum-copper) alloy, which are examples of aluminum alloys.

[0286] After embedding multiple emitter contact electrode layers 51 into corresponding contact holes 31, a main surface electrode layer 256 is formed on the interlayer insulating layer 41. The formation process of the main surface electrode layer 256 includes the sequential formation of a first main surface electrode layer 257 and a second main surface electrode layer 258 from the side of the interlayer insulating layer 41. The first main surface electrode layer 257 can also be formed by sputtering. The second main surface electrode layer 258 can also be formed by sputtering, vapor deposition, CVD, or electroplating.

[0287] As described above, the semiconductor device 251 can achieve the same effect as that described for semiconductor device 1. Of course, the structure of semiconductor device 251 can also be applied to embodiments other than the thirteenth embodiment.

[0288] Figure 26 Is with Figure 22 The cross-sectional perspective view of the corresponding region is a cross-sectional perspective view showing a portion of the semiconductor device 261 of the fourteenth embodiment of the present invention. Figure 27 Is with Figure 25 The sectional view of the corresponding area is Figure 26 A cross-sectional view of a portion of the semiconductor device 261 shown. Hereinafter, for semiconductor device 251 (refer to...) Figure 22 The structures described correspond to the structures described, and are marked with the same reference symbol and the explanation is omitted.

[0289] Reference Figure 26 as well as Figure 27The plurality of emitter contact electrode layers 51 include a plurality of emitter contact electrode layers 213A and a plurality of emitter contact electrode layers 213B. In this configuration, each emitter contact electrode layer 213A includes a first contact electrode layer 262 and a second contact electrode 263 contained in a structure primarily composed of mutually different conductive materials.

[0290] The first contact electrode layer 262 is contained in a tungsten-based structure and embedded in the first contact hole 212A. The second contact electrode 263 is contained in an aluminum-based structure and embedded in the second contact hole 42, which communicates with the first contact hole 212A.

[0291] More specifically, the first contact electrode layer 262 is embedded in the second region 253 of the first contact hole 212A. In the second region 253, the first contact electrode layer 262 is connected to the main body region 8, the emitter region 25, and the contact region 36.

[0292] The upper end of the first contact electrode layer 262 can be located on the same plane as the bottom wall of the first region 252, or it can be located on the bottom side of the main body region 8 relative to the bottom wall of the first region 252.

[0293] The first contact electrode layer 262 includes a first electrode layer 44 and a second electrode layer 45. The first electrode layer 44 is formed in a film shape along the inner wall of the second region 253. The first electrode layer 44 divides concave spaces within the second region 253. The first electrode layer 44 is connected to the main body region 8, the emitter region 25, and the contact region 36.

[0294] The second electrode layer 45 is embedded in the concave space defined by the first electrode layer 44 in the second region 253. The second electrode layer 45 is electrically connected to the main body region 8, the emitter region 25 and the contact region 36 via the first electrode layer 44.

[0295] The second contact electrode 263 is formed using a portion of the main surface electrode layer 256. In this configuration, the main surface electrode layer 256 extends into the second contact hole 42 from above the interlayer insulating layer 41. In this configuration, the main surface electrode layer 256 also extends into the first contact hole 31 (first region 252) from the second contact hole 42. If the first region 252 is not formed in the first contact hole 212A, the main surface electrode layer 256 is configured to be embedded only in the second contact hole 42.

[0296] More specifically, the first main surface electrode layer 257 of the main surface electrode layer 256 is formed in a film shape along the main surface of the interlayer insulating layer 41 and the inner wall of the second contact hole 42. The first main surface electrode layer 257 divides a concave space within the second contact hole 42. The first main surface electrode layer 257 is connected to the first contact electrode layer 262 within the second contact hole 42. The first main surface electrode layer 257 may also be connected to the emitter region 25 depending on the position of the upper end of the first contact electrode layer 262.

[0297] A second main surface electrode layer 258 is formed on top of the first main surface electrode layer 257. The second main surface electrode layer 258 extends into the second contact hole 42 from above the interlayer insulating layer 41. The second main surface electrode layer 258 fills the concave space defined by the first main surface electrode layer 257 within the second contact hole 42. The second main surface electrode layer 258 is electrically connected to the first contact electrode layer 262 via the first main surface electrode layer 257.

[0298] Thus, the second contact electrode 263 is formed using a portion of the main surface electrode layer 256. Of course, the second contact electrode 263 can also be formed separately from the main surface electrode layer 256.

[0299] In this configuration, each emitter contact electrode layer 213B includes a first contact electrode layer 264 and a second contact electrode layer 265 contained in a structure primarily composed of different conductive materials. The first contact electrode layer 264 and the second contact electrode layer 265 each have a structure corresponding to the first contact electrode layer 262 and the second contact electrode 263, respectively. Specific descriptions of the first contact electrode layer 264 and the second contact electrode layer 265 are omitted.

[0300] As described above, the semiconductor device 261 can achieve the same effect as that described for the semiconductor device 1. Of course, the structure of the semiconductor device 261 can also be applied to embodiments other than the fourteenth embodiment.

[0301] Figure 28 Is with Figure 24 The top view of the corresponding area is a top view showing a portion of the semiconductor device 271 according to the fifteenth embodiment of the present invention. Figure 29 It is along Figure 28 The cross-sectional view along the XXIX-XXIX line is shown. Hereinafter, for the semiconductor device 251 (refer to...) Figure 22 The structures described correspond to the structures described, and are marked with the same reference symbol and the explanation is omitted.

[0302] Reference Figure 28 as well as Figure 29In this configuration, the plurality of first contact holes 212A each include a first sidewall contact hole 272 and a second sidewall contact hole 273. The first sidewall contact hole 272 is formed on one sidewall of the first gate trench 174. The second sidewall contact hole 273 is formed on the other sidewall of the first gate trench 174.

[0303] Multiple first sidewall contact holes 272 are formed at intervals along the second direction Y. Each first sidewall contact hole 272 extends from the inside of the first gate trench 174 through one sidewall and is led out to the surface portion of the first main surface 3 of the semiconductor layer 2.

[0304] Although specific illustrations are omitted, in this configuration, each first sidewall contact hole 272 penetrates one sidewall of the emitter trench 17 (second emitter trench 203) adjacent to one sidewall of the first gate trench 174 and is led out into the emitter trench 17. Each first sidewall contact hole 272 does not necessarily need to be led out into the emitter trench 17; it can also be formed with a gap between it and the emitter trench 17.

[0305] Each first sidewall contact hole 272 has one end located within the first gate trench 174 and another end located within the emitter trench 17 in the first direction X. One end of each first sidewall contact hole 272 is formed with a gap between it and the other sidewall of the first gate trench 174. The other end of each first sidewall contact hole 272 is formed with a gap between it and the other sidewall of the emitter trench 17.

[0306] Each first sidewall contact hole 272 is formed into a quadrilateral shape when viewed from above. In this configuration, each first sidewall contact hole 272 is formed into a band-like (rectangular) shape extending along a first direction X when viewed from above. The width WX of each first sidewall contact hole 272 in the first direction X is greater than 0 μm and less than 1 μm. The width WY of each first sidewall contact hole 272 in the second direction Y is greater than 0 μm and less than 1 μm.

[0307] Multiple second sidewall contact holes 273 are formed at intervals along the second direction Y. In this configuration, each second sidewall contact hole 273 is opposite to a corresponding first sidewall contact hole 272 along the first direction X.

[0308] Each second sidewall contact hole 273 extends from the inside of the first gate trench 174 through another sidewall and is led out to the surface portion of the first main surface 3 of the semiconductor layer 2. In this configuration, each second sidewall contact hole 273 extends through one sidewall of the first emitter trench 193 and is led out into the first emitter trench 193. Each second sidewall contact hole 273 does not necessarily need to be led out into the first emitter trench 193; it can also be formed with a gap between it and the first emitter trench 193.

[0309] Each second sidewall contact hole 273 has one end located within the first gate trench 174 and another end located within the first emitter trench 193 in the first direction X. One end of each second sidewall contact hole 273 may also be formed with a gap between it and one sidewall of the first gate trench 174. More specifically, one end of each second sidewall contact hole 273 may also be formed with a gap between it and the first sidewall contact hole 272. The other end of each second sidewall contact hole 273 is formed with a gap between it and the other sidewall of the first emitter trench 193.

[0310] Each second sidewall contact hole 273 is formed into a quadrilateral shape when viewed from above. In this configuration, each second sidewall contact hole 273 is formed into a band-like (rectangular) shape extending along a first direction X when viewed from above. The width WX of each second sidewall contact hole 273 in the first direction X is greater than 0 μm and less than 1 μm. The width WY of each second sidewall contact hole 273 in the second direction Y is greater than 0 μm and less than 1 μm.

[0311] One end of each first sidewall contact hole 272 and one end of each second sidewall contact hole 273 are divided within the first gate trench 174 by a common first gate buried insulating layer 178. A portion of the first gate buried insulating layer 178 is located in the region between one end of each first sidewall contact hole 272 and one end of each second sidewall contact hole 273.

[0312] In this configuration, the plurality of first contact holes 212B each include a first sidewall contact hole 274 and a second sidewall contact hole 275. The first sidewall contact hole 274 is formed on one sidewall of the second gate trench 184. The second sidewall contact hole 275 is formed on the other sidewall of the second gate trench 184.

[0313] Multiple first sidewall contact holes 274 are formed spaced apart along the second direction Y. Each first sidewall contact hole 274 extends from the inside of the second gate trench 184 through one sidewall and is led out to the surface portion of the first main surface 3 of the semiconductor layer 2. In this configuration, each first sidewall contact hole 274 extends through one sidewall of the second emitter trench 203 and is led out into the second emitter trench 203. Each first sidewall contact hole 274 does not necessarily need to be led out into the second emitter trench 203; it can also be formed spaced apart from the second emitter trench 203.

[0314] Each first sidewall contact hole 274 has one end located within the second gate trench 184 and another end located within the second emitter trench 203 in the first direction X. One end of each first sidewall contact hole 274 is formed with a gap between it and the other sidewall of the second gate trench 184. The other end of each first sidewall contact hole 274 is formed with a gap between it and the other sidewall of the second emitter trench 203.

[0315] Each first sidewall contact hole 274 is formed into a quadrilateral shape when viewed from above. In this configuration, each first sidewall contact hole 274 is formed into a band-like (rectangular) shape extending along a first direction X when viewed from above. The width WX of each first sidewall contact hole 274 in the first direction X is greater than 0 μm and less than 1 μm. The width WY of each first sidewall contact hole 274 in the second direction Y is greater than 0 μm and less than 1 μm.

[0316] Multiple second sidewall contact holes 275 are formed at intervals along the second direction Y. In this configuration, each second sidewall contact hole 275 is opposite to a corresponding first sidewall contact hole 274 along the first direction X. The multiple second sidewall contact holes 275 extend from the inside of the second gate trench 184 through another sidewall and are respectively led out to the surface portion of the first main surface 3 of the semiconductor layer 2.

[0317] Although specific illustrations are omitted, in this configuration, each second sidewall contact hole 275 penetrates one sidewall of the emitter trench 17 (first emitter trench 193) adjacent to the other sidewall of the second gate trench 184 and is led out into the emitter trench 17. Each second sidewall contact hole 275 does not necessarily need to be led out into the emitter trench 17; it can also be formed with a gap between it and the emitter trench 17.

[0318] Each second sidewall contact hole 275 has one end located within the second gate trench 184 and another end located within the emitter trench 17 in the first direction X. One end of each second sidewall contact hole 275 is formed with a gap between it and one sidewall of the second gate trench 184. More specifically, one end of each second sidewall contact hole 275 is formed with a gap between it and the first sidewall contact hole 274. The other end of each second sidewall contact hole 275 is formed with a gap between it and the other sidewall of the emitter trench 17.

[0319] Each second sidewall contact hole 275 is formed into a quadrilateral shape when viewed from above. In this configuration, each second sidewall contact hole 275 is formed into a band-like (rectangular) shape extending along a first direction X when viewed from above. The width WX of each second sidewall contact hole 275 in the first direction X is greater than 0 μm and less than 1 μm. The width WY of each second sidewall contact hole 275 in the second direction Y is greater than 0 μm and less than 1 μm.

[0320] One end of each first sidewall contact hole 274 and one end of each second sidewall contact hole 275 are separated within the second gate trench 184 by a common second gate buried insulating layer 188. A portion of the second gate buried insulating layer 188 is located in the region between one end of each first sidewall contact hole 274 and one end of each second sidewall contact hole 275.

[0321] Multiple second contact holes 42 are connected to corresponding first sidewall contact holes 272, second sidewall contact holes 273, first sidewall contact holes 274, and second sidewall contact holes 275 in a one-to-one correspondence. A portion of the interlayer insulating layer 41 is located on the first gate buried insulating layer 178 in the region between two adjacent second contact holes 42. A portion of the interlayer insulating layer 41 is located on the second gate buried insulating layer 188 in the region between two adjacent second contact holes 42.

[0322] Similar to semiconductor device 251, the plurality of emitter contact electrode layers 51 include a plurality of emitter contact electrode layers 213A and a plurality of emitter contact electrode layers 213B. The plurality of emitter contact electrode layers 213A are respectively embedded in a plurality of first sidewall contact holes 272 and a plurality of second sidewall contact holes 273 in the same manner as semiconductor device 251. The plurality of emitter contact electrode layers 213B are respectively embedded in a plurality of first sidewall contact holes 274 and a plurality of second sidewall contact holes 275 in the same manner as semiconductor device 251.

[0323] As described above, the semiconductor device 271 can achieve the same effects as those described for the semiconductor device 1. Furthermore, the semiconductor device 271 has a first sidewall contact hole 272, a second sidewall contact hole 273, a first sidewall contact hole 274, and a second sidewall contact hole 275, each having a width WX of 1 μm or less and a width WY of 1 μm or less. Therefore, an emitter contact electrode layer 51 (particularly a second electrode layer 45 containing tungsten) can be appropriately embedded in the first sidewall contact hole 272, the second sidewall contact hole 273, the first sidewall contact hole 274, and the second sidewall contact hole 275. Of course, the structure of the semiconductor device 271 can also be applied to embodiments other than the fifteenth embodiment.

[0324] Figure 30 Is with Figure 29 The cross-sectional view of the corresponding region is a cross-sectional view showing a portion of the semiconductor device 281 according to the sixteenth embodiment of the present invention. Hereinafter, for the semiconductor device 271 (see reference 271)... Figure 29 The structures described correspond to the structures described, and are marked with the same reference symbol and the explanation is omitted.

[0325] Reference Figure 30 In this configuration, the first sidewall contact hole 272 is formed on the surface portion of the first main surface 3 of the semiconductor layer 2 in the region between adjacent trench gate electrode structures 10 and trench emitter electrode structures 11. The first sidewall contact hole 272 is divided by the semiconductor layer 2, the trench gate electrode structure 10, and the trench emitter electrode structure 11.

[0326] One end of the first sidewall contact hole 272 may also be defined by the first gate insulating layer 175 and / or the first gate buried insulating layer 178. One end of the first sidewall contact hole 272 may also be formed with a gap from the trench gate electrode structure 10. That is, one end of the first sidewall contact hole 272 may also be opposed to the trench gate electrode structure 10 through a portion of the semiconductor layer 2.

[0327] Although specific illustrations are omitted, the other end of the first sidewall contact hole 272 can also be defined by the emitter insulating layer 18 and / or the emitter embedded insulating layer 21 (the second emitter insulating layer 204 and / or the second emitter embedded insulating layer 207). The other end of the first sidewall contact hole 272 can also be formed with a gap from the trench emitter electrode structure 11. That is, the other end of the first sidewall contact hole 272 can also be opposed to the trench emitter electrode structure 11 through a portion of the semiconductor layer 2.

[0328] In this configuration, the second sidewall contact hole 273 is formed on the surface portion of the first main surface 3 of the semiconductor layer 2 in the region between adjacent trench gate electrode structures 10 and trench emitter electrode structures 11. The second sidewall contact hole 273 is defined by the semiconductor layer 2, the trench gate electrode structure 10, and the trench emitter electrode structure 11.

[0329] One end of the second sidewall contact hole 273 may also be defined by the first gate insulating layer 175 and / or the first gate buried insulating layer 178. One end of the second sidewall contact hole 273 may also be formed with a gap from the trench gate electrode structure 10. That is, one end of the first sidewall contact hole 272 may also be opposite to the trench gate electrode structure 10 through a portion of the semiconductor layer 2.

[0330] The other end of the second sidewall contact hole 273 may also be divided by the first emitter insulating layer 194 and / or the first emitter embedded insulating layer 197. The other end of the second sidewall contact hole 273 may also be formed with a gap from the trench emitter electrode structure 11. That is, the other end of the first sidewall contact hole 272 may also be opposite to the trench emitter electrode structure 11 through a portion of the semiconductor layer 2.

[0331] The first sidewall contact hole 274 and the second sidewall contact hole 275 are formed in the same manner as the first sidewall contact hole 272 and the second sidewall contact hole 273. Detailed descriptions of the first sidewall contact hole 274 and the second sidewall contact hole 275 are omitted.

[0332] Multiple second contact holes 42 are connected to corresponding first sidewall contact holes 272, second sidewall contact holes 273, first sidewall contact holes 274, and second sidewall contact holes 275 in a one-to-one correspondence. The opening width of each second contact hole 42 is greater than the opening width of the corresponding first sidewall contact hole 272, second sidewall contact hole 273, first sidewall contact hole 274, and first sidewall contact hole 275.

[0333] Each second contact hole 42 exposes a portion of the corresponding trench gate electrode structure 10 and a portion of the corresponding trench emitter electrode structure 11. The sidewalls of each second contact hole 42 are located above the corresponding trench gate electrode structure 10 and the corresponding trench emitter electrode structure 11.

[0334] As described above, the semiconductor device 281 can achieve the same effect as that described for semiconductor device 1. Semiconductor device 281 can be manufactured simply by changing the layout of each mask and the etching conditions in the manufacturing method of semiconductor device 271. Of course, the structure of semiconductor device 281 can also be applied to embodiments other than the sixteenth embodiment.

[0335] Figure 31 Is with Figure 29 The cross-sectional view of the corresponding region is a cross-sectional view showing a portion of the semiconductor device 291 according to the seventeenth embodiment of the present invention. (Refer to...) Figure 31 Semiconductor device 291 has semiconductor device 271 (refer to) Figure 29 On-board semiconductor device 261 (refer to) Figure 26 The structure is formed by the construction of ).

[0336] That is, each emitter contact electrode layer 213A includes a first contact electrode layer 262 and a second contact electrode 263, both of which are primarily composed of different conductive materials. The first contact electrode layer 262 is contained within a tungsten-based structure and is embedded in a first contact hole 212A. The second contact electrode 263 is contained within an aluminum-based structure and is embedded in a second contact hole 42 that communicates with the first contact hole 212A.

[0337] Furthermore, in this configuration, each emitter contact electrode layer 213B includes a first contact electrode layer 264 and a second contact electrode layer 265, each composed primarily of different conductive materials. The first contact electrode layer 264 and the second contact electrode layer 265 each have a structure corresponding to the first contact electrode layer 262 and the second contact electrode 263, respectively.

[0338] Furthermore, regarding the semiconductor device 261 (see reference) Figure 26 ) and semiconductor device 271 (see reference) Figure 29The structures described correspond to the structures described, and are marked with the same reference symbol and the explanation is omitted.

[0339] As described above, the semiconductor device 291 can achieve the same effect as that described for semiconductor device 1. Of course, the structure of semiconductor device 291 can also be applied to embodiments other than the seventeenth embodiment.

[0340] Figure 32 Is with Figure 29 The cross-sectional view of the corresponding region is a cross-sectional view showing a portion of the semiconductor device 301 according to the eighteenth embodiment of the present invention. (Refer to...) Figure 32 Semiconductor device 301 has semiconductor device 281 (refer to) Figure 30 On-board semiconductor device 261 (refer to) Figure 26 The structure is formed by the construction of ).

[0341] That is, each emitter contact electrode layer 213A includes a first contact electrode layer 262 and a second contact electrode 263, which are mainly composed of different conductive materials. The first contact electrode layer 262 is contained in a tungsten-based structure and is embedded in a first contact hole 212A. The second contact electrode 263 is contained in an aluminum-based structure and is embedded in a second contact hole 42 that communicates with the first contact hole 212A.

[0342] Furthermore, in this configuration, each emitter contact electrode layer 213B includes a first contact electrode layer 264 and a second contact electrode layer 265, each composed primarily of different conductive materials. The first contact electrode layer 264 and the second contact electrode layer 265 each have a structure corresponding to the first contact electrode layer 262 and the second contact electrode 263, respectively.

[0343] Furthermore, regarding the semiconductor device 261 (see reference) Figure 26 ) and semiconductor device 281 (see reference) Figure 30 The structures described correspond to the structures described, and are marked with the same reference symbol and the explanation is omitted.

[0344] As described above, the semiconductor device 301 can achieve the same effect as that described for the semiconductor device 1. Of course, the structure of the semiconductor device 301 can also be applied to embodiments other than the eighteenth embodiment.

[0345] The embodiments of the present invention have been described above, but the present invention can also be implemented in other ways.

[0346] In the above embodiments, the following methods may also be adopted: Figure 33 The structure shown. Figure 33 Is with Figure 2The top view of the corresponding part is a diagram showing a modified example of semiconductor layer 2. Hereinafter, for structures corresponding to the structure described for semiconductor device 1, the same reference numerals will be used and descriptions will be omitted. The structures described below can also be applied to the second to eighteenth embodiments.

[0347] Reference Figure 33 The semiconductor layer 2 may also have a stacked structure comprising a silicon p-type semiconductor substrate 2A and a silicon n-type epitaxial layer 2B formed on the semiconductor substrate 2A, in place of the silicon single crystal substrate.

[0348] The second main surface 4 of the semiconductor layer 2 is formed from a p-type semiconductor substrate 2A. The first main surface 3 is formed from an n-type epitaxial layer 2B. In this case, the p-type semiconductor substrate 2A corresponds to the collector region 5. The n-type epitaxial layer 2B corresponds to the drift region 7.

[0349] Of course, the semiconductor layer 2 can also have a stacked structure including a silicon n-type semiconductor substrate 2A and a silicon n-type epitaxial layer 2B formed on the semiconductor substrate 2A, in order to replace the silicon single crystal substrate.

[0350] The second main surface 4 of the semiconductor layer 2 is formed from an n-type semiconductor substrate 2A. The first main surface 3 is formed from an n-type epitaxial layer 2B. In this case, the n-type semiconductor substrate 2A corresponds to the drain region. Furthermore, the n-type epitaxial layer 2B corresponds to the drift region 7.

[0351] In the above embodiments, the following methods may also be adopted: Figure 34 The structure shown. Figure 34 Is with Figure 4 The top view of the corresponding part is a diagram showing a modified example of the gate-embedded insulating layer 16. Hereinafter, for configurations corresponding to the configuration described for semiconductor device 1, the same reference numerals will be used and descriptions will be omitted. The configurations described below can also be applied to the second to eighteenth embodiments.

[0352] In this example, the gate buried via 15 has a first-direction width that is larger than the first-direction width of the gate trench 12. In the first direction X, the semiconductor layer 2 is exposed in the region outside the gate trench 12, with one side of the gate buried via 15 and the other side of the gate buried via 15 located on the outside of the gate trench 12.

[0353] The gate buried insulating layer 16 is buried in the gate buried hole 15 having such a structure. Therefore, the gate buried insulating layer 16 has a first direction width that is larger than the first direction width of the gate trench 12.

[0354] In the first direction X, one side of the gate buried insulating layer 16 and the other side are located outside the gate trench 12 and are in contact with the semiconductor layer 2. The first contact hole 31 and the emitter contact electrode layer 51 intersect with the gate buried insulating layer 16 when viewed from above.

[0355] When a gate buried insulating layer 16 with the above-described structure is formed, the same effect as described in the semiconductor device 1 can be achieved. Such a structure can be manufactured simply by changing the layout of each mask in the manufacturing method of the semiconductor device 1.

[0356] In the above embodiments, a method with... Figure 35 The emitter contact electrode layer 51 of the structure shown. Figure 35 Is with Figure 4 The top view of the corresponding part is a diagram showing a modified example of the emitter contact electrode layer 51. Hereinafter, for structures corresponding to the structure described for semiconductor device 1, the same reference numerals will be used and descriptions will be omitted. The structures described below can also be applied to the second to eighteenth embodiments.

[0357] Reference Figure 35 In this example, the plurality of gate buried vias 15 include gate buried vias 231A and 231B. Gate buried vias 231A and 231B are formed with a gap along the gate trench 12 (second direction Y).

[0358] The gate buried via 231A is formed with a gap between it and the sidewall of the gate trench 12 in the first direction X, and is formed close to one sidewall of the gate trench 12. A portion of the gate electrode layer 14 is located between the gate buried via 231A and the sidewall of the gate trench 12. In this example, the sidewall of the gate buried via 231A is defined by the gate insulating layer 13 and the gate electrode layer 1.

[0359] The gate buried via 231B is formed with a gap between it and one sidewall of the gate trench 12 in the first direction X, and is formed close to the sidewall of the other sidewall of the gate trench 12. A portion of the gate electrode layer 14 is located between the gate buried via 231B and the sidewall of one sidewall of the gate trench 12. In this example, the sidewall of the gate buried via 231B is defined by the gate insulating layer 13 and the gate electrode layer 14.

[0360] In this example, the gate buried insulating layer 16 includes a gate buried insulating layer 232A and a gate buried insulating layer 232B. The gate buried insulating layer 232A is buried in the gate buried via 231A. The gate buried insulating layer 232B is buried in the gate buried via 231B.

[0361] In this example, the plurality of first contact holes 31 include first contact holes 233A and first contact holes 233B. The first contact holes 233A and first contact holes 233B are formed with a gap along the gate trench 12 (second direction Y).

[0362] In the first direction X, the first contact hole 233A penetrates only one sidewall of the gate trench 12 from the inner region of the gate buried insulating layer 232A. The first contact hole 233A is formed with a gap between it and the sidewall of the other side of the gate trench 12.

[0363] In the first direction X, the first contact hole 233B extends from the gate into the inner region of the insulating layer 232B, penetrating only the sidewall of the other side of the gate trench 12. The first contact hole 233B is formed with a gap between it and the sidewall of one side of the gate trench 12.

[0364] In this example, the plurality of emitter contact electrode layers 51 include emitter contact electrode layer 234A and emitter contact electrode layer 234B. Emitter contact electrode layer 234A is embedded in the first contact hole 233A. Therefore, emitter contact electrode layer 234A penetrates only one sidewall of the gate trench 12 in the first direction X, within the inner region of the insulating layer 232A buried from the gate. Emitter contact electrode layer 234A is formed with a gap from the sidewall of the other side of the gate trench 12.

[0365] The emitter contact electrode layer 234B is embedded in the first contact hole 233B. Therefore, the emitter contact electrode layer 234B extends from the gate into the inner region of the insulating layer 232B in the first direction X, penetrating only one sidewall of the gate trench 12. The emitter contact electrode layer 234B is formed with a gap between it and one sidewall of the gate trench 12.

[0366] exist Figure 35 In such a configuration, the same effect as described for semiconductor device 1 can be achieved. It is possible to manufacture the semiconductor device 1 simply by changing the arrangement of the masks in the manufacturing method. Figure 35 That kind of structure.

[0367] In the embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed can also be used. That is, the p-type portion can be n-type and the n-type portion can be p-type.

[0368] In the embodiments described above, an example of semiconductor layer 2 being made of silicon single crystal has been given. However, semiconductor layer 2 may also contain SiC. Alternatively, semiconductor layer 2 may also be made of SiC single crystal.

[0369] This specification does not limit how the features shown in the first to eighteenth embodiments can be combined. The first to eighteenth embodiments can be combined in any form and in any manner. That is, the features shown in the first to eighteenth embodiments can also be combined in any form and in any manner.

[0370] This application corresponds to Japanese Patent Application No. 2017-226109 filed with the Japanese Patent Office on November 24, 2017, the entire disclosure of which is incorporated herein by reference.

[0371] Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention. The present invention should not be interpreted as limited to these specific examples, and the scope of the present invention is defined only by the appended claims.

[0372] Explanation of symbols

[0373] 1—Semiconductor device, 2—Semiconductor layer, 3—First main surface, 8—Main region, 12—Gate trench, 13—Gate insulating layer, 14—Gate electrode layer, 16—Gate buried insulating layer, 17—Emitter trench, 19—Emitter electrode layer, 21—Emitter buried insulating layer, 25—Emitter region, 41—Interlayer insulating layer, 51—Emitter contact electrode layer, 81—Semiconductor device, 91—Semiconductor device, 93A—Emitter contact electrode layer, 93B—Emitter contact electrode layer, 101—Semiconductor device, 103—Emitter trench 105—Emitter electrode layer, 107—Emitter buried insulating layer, 121—Semiconductor device, 131—Semiconductor device, 133A—Emitter contact electrode layer, 133B—Emitter contact electrode layer, 141—Semiconductor device, 143—Second gate trench, 144—Second gate insulating layer, 145—Second gate electrode layer, 147—Second gate buried insulating layer, 161—Semiconductor device, 163A—Emitter contact electrode layer, 163B—Emitter contact electrode layer, 171—Semiconductor device, 174—First gate trench 175—First gate insulating layer, 176—First gate electrode layer, 178—First gate buried insulating layer, 184—Second gate trench, 185—Second gate insulating layer, 186—Second gate electrode layer, 188—Second gate buried insulating layer, 193—First emitter trench, 195—First emitter electrode layer, 197—First emitter buried insulating layer, 203—Second emitter trench, 205—Second emitter electrode layer, 207—Second emitter buried insulating layer, 211—Semiconductor device, 213A—Emitter contact electrode layer 213B—Emitter contact electrode layer, 221—Semiconductor device, 232A—Gate buried insulating layer, 232B—Gate buried insulating layer, 234A—Emitter contact electrode layer, 234B—Emitter contact electrode layer, 251—Semiconductor device, 261—Semiconductor device, 271—Semiconductor device, 281—Semiconductor device, 291—Semiconductor device, 301—Semiconductor device, P0—Trench pitch, P1—First trench pitch, P2—Second trench pitch, P3—Third trench pitch, X—First direction, Y—Second direction.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor layer having a main surface with trenches formed thereon; The main region of the first conductivity type is formed along the sidewall of the trench on the surface portion of the main surface of the semiconductor layer. The second type of impurity region is formed along the sidewall of the trench on the surface of the main region. A gate insulating layer is formed on the inner wall of the aforementioned trench; The gate electrode is buried in the trench and is positioned opposite the main body region and the impurity region through the gate insulating layer. A contact electrode extends from the trench through the sidewall of the trench and is led out to the surface portion of the main surface of the semiconductor layer, and is electrically connected to the main body region and the impurity region. An insulating layer is embedded in the surface portion of the gate electrode, which is embedded in the trench between the gate electrode and the contact electrode to insulate the gate electrode and the contact electrode; and An insulating layer that covers the aforementioned main surface. The contact electrode is located in the trench and faces the gate electrode across the buried insulating layer in the normal direction and the tangential direction of the main surface of the semiconductor layer.

2. The semiconductor device according to claim 1, characterized in that, The aforementioned trenches extend in one direction. The aforementioned contact electrode is led out along a cross direction that intersects with one of the aforementioned directions.

3. The semiconductor device according to claim 2, characterized in that, In one of the aforementioned directions, the width of the contact electrode is smaller than the width of the trench.

4. The semiconductor device according to claim 1, characterized in that, The contact electrode extends from the trench through one sidewall and the other sidewall of the trench and is led out to the surface portion of the semiconductor layer.

5. The semiconductor device according to claim 1, characterized in that, The aforementioned contact electrode penetrates the aforementioned insulating layer in such a way that it reaches the aforementioned trench and the surface portion of the aforementioned semiconductor layer.

6. The semiconductor device according to claim 1, characterized in that, The gate electrode is exposed from the opening of the trench. The aforementioned embedded insulation layer is exposed from the opening of the aforementioned trench. The aforementioned insulating layer covers the aforementioned gate electrode and the aforementioned buried insulating layer.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, On the main surface of the semiconductor layer, a second trench is formed at a distance from the trench.

8. The semiconductor device according to claim 7, characterized in that, The contact electrode is led out from the surface portion of the semiconductor layer, through the sidewall of the second trench, and into the second trench.

9. The semiconductor device according to claim 8, characterized in that, Also includes: An inner wall insulating layer is formed on the inner wall of the second trench described above; An electrode layer is embedded, which is buried in the middle of the depth direction of the second trench through the aforementioned inner wall insulating layer; as well as The second embedded insulating layer is located within the second trench between the embedded electrode layer and the contact electrode, and insulates the embedded electrode layer and the contact electrode.

10. The semiconductor device according to claim 9, characterized in that, A voltage less than the gate voltage applied to the gate electrode is applied to the buried electrode layer.

11. The semiconductor device according to claim 8, characterized in that, Also includes: A second gate insulating layer is formed on the inner wall of the second trench; The second gate electrode is embedded in the second trench through the second gate insulating layer. as well as The second embedded insulating layer is located within the second trench between the second gate electrode and the contact electrode, and insulates the second gate electrode and the contact electrode.

12. The semiconductor device according to claim 11, characterized in that, The second gate electrode is formed at the same potential as the gate electrode.

13. The semiconductor device according to claim 7, characterized in that, The distance between the aforementioned groove and the aforementioned second groove is greater than 0.1 μm and less than 0.6 μm.

14. The semiconductor device according to claim 7, characterized in that, The distance between the aforementioned groove and the aforementioned second groove is 0.2 μm or more and 0.4 μm or less.

15. The semiconductor device according to claim 1, characterized in that, The aforementioned impurity region is the emitter region. The aforementioned contact electrode is the emitter contact electrode.

16. The semiconductor device according to claim 1, characterized in that, The aforementioned impurity region is the source region. The aforementioned contact electrode is the source contact electrode.

17. The semiconductor device according to claim 1, characterized in that, The aforementioned embedded insulating layer is formed into a cone shape with a base area smaller than the opening area.

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