Display device

Abstract

The present disclosure provides a display device, including: a first signal wiring and a second signal wiring, each extending in a first direction on a substrate and arranged in a second direction intersecting the first direction; a plurality of first metal patterns separated from each other, at least a portion of which overlaps with the first signal wiring and is electrically connected to the first signal wiring; and a plurality of second metal patterns separated from each other, at least a portion of which overlaps with the second signal wiring and is electrically connected to the second signal wiring, each of the plurality of first metal patterns and each of the plurality of second metal patterns being arranged in a zigzag manner along the first direction.

Description

Technical Field

[0001] An embodiment of the present disclosure relates to a display device. Background Art

[0002] A display device is a device that displays data visually. Such a display device includes a substrate divided into a display area and a peripheral area. Scan wiring and data wiring are formed in the display area in an insulated manner and include a plurality of pixels.

[0003] The display region may include a display element including a thin film transistor corresponding to each pixel, and the peripheral region may include a drive unit, a control unit, and the like for transmitting electrical signals to the display region via various wirings.

[0004] As the uses of such display devices have become increasingly diverse, various designs have been attempted to improve the quality of the display devices. Summary of the Invention

[0005] The present disclosure aims to provide a display device that can prevent short circuits between adjacent wirings, etc. Such problems are merely exemplary, and the scope of protection of the present disclosure is not limited thereto.

[0006] According to one aspect of the present disclosure, a display device is provided, including: a first signal wiring and a second signal wiring, each extending in a first direction on a substrate and arranged in a second direction intersecting the first direction; a plurality of first metal patterns separated from each other, at least a portion of which overlaps with the first signal wiring and is electrically connected to the first signal wiring; and a plurality of second metal patterns separated from each other, at least a portion of which overlaps with the second signal wiring and is electrically connected to the second signal wiring, each of the plurality of first metal patterns and each of the plurality of second metal patterns being arranged in a zigzag pattern along the first direction.

[0007] The plurality of second metal patterns may be adjacent to portions between the plurality of first metal patterns in the first signal wiring in the second direction.

[0008] Alternatively, a spacing interval between the plurality of first metal patterns may be the same as a length of the plurality of second metal patterns in the first direction.

[0009] It may be that a spacing interval between the plurality of first metal patterns is greater than a length of the plurality of second metal patterns in the first direction.

[0010] The plurality of first metal patterns may be spaced apart from each other at the same intervals.

[0011] It may be that the plurality of second metal patterns are spaced apart from each other at the same interval, and the spaced intervals of the plurality of first metal patterns and the spaced intervals of the plurality of second metal patterns are the same.

[0012] The first signal wiring may entirely overlap at least one of the plurality of first metal patterns.

[0013] It may be that the widths of the plurality of first metal patterns in the second direction are greater than the width of the first signal wiring in the second direction.

[0014] It may be that the second metal patterns adjacent to the first metal patterns among the second metal patterns are spaced apart from the first metal patterns in the first direction and the second direction.

[0015] It may be that the lengths of the plurality of first metal patterns in the first direction are different from the lengths of the plurality of second metal patterns in the first direction.

[0016] It may be that the widths of the plurality of first metal patterns in the second direction are different from the widths of the plurality of second metal patterns in the second direction.

[0017] The display device may further include at least one insulating layer, and the insulating layer may be interposed between the first signal wiring and the plurality of first metal patterns.

[0018] Each of the plurality of first metal patterns may include a first contact plug, and the first contact plug may penetrate the at least one insulating layer and connect the plurality of first metal patterns and the first signal wiring.

[0019] It may be that the first contact plugs are respectively located at two ends of the plurality of first metal patterns.

[0020] The display device may further include a plurality of display elements arranged on the substrate, each of the plurality of display elements including a thin film transistor and a capacitor having a gate electrode of the thin film transistor as a lower electrode.

[0021] The first signal wiring and the gate electrode of the thin film transistor may be arranged on the same layer.

[0022] The plurality of first metal patterns may be arranged on the same layer as the source electrode and the drain electrode of the thin film transistor.

[0023] The plurality of first metal patterns may be arranged between the gate electrode of the thin film transistor and the source electrode and the drain electrode of the thin film transistor.

[0024] The plurality of first metal patterns may be arranged on the same layer as the upper electrode of the capacitor.

[0025] The display device may further include a scan driver driven by signals supplied from each of the first signal wiring and the second signal wiring.

[0026] Effects of the Invention

[0027] According to one embodiment of the present disclosure configured as described above, it is possible to prevent a short circuit failure or the like from occurring between adjacent wirings.

[0028] Furthermore, by reducing wiring load, display quality can be improved.

[0029] However, the scope of the present disclosure is not limited to this effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 FIG1 is a top view schematically showing a display device according to an embodiment of the present disclosure.

[0031] Figure 2 for Figure 1 An equivalent circuit diagram of a pixel included in a display device.

[0032] Figure 3 To enlarge the Figure 1 A top view of an example of the W portion.

[0033] Figure 4 To follow Figure 3 Cross-sectional view along line A1-A1′.

[0034] Figure 4 To follow Figure 1 Cross-sectional view of line A2-A2′.

[0035] Figure 5 is a cross-sectional view schematically illustrating a portion of a display device according to another embodiment of the present disclosure.

[0036] Figure 6 To enlarge the Figure 1 A top view of another example of the W portion.

[0037] Figure 7 To follow Figure 6 Cross-sectional view of line BB′.

[0038] Figure 8 To enlarge the Figure 1 A top view of another example of the W portion.

[0039] Figure 9 To follow Figure 8 Cross-sectional view of line CC′.

[0040] Description of Reference Numerals

[0041] 10: Display device

[0042] 100: Substrate

[0043] CL1, CL2, CL3, CL4: first signal wiring, second signal wiring, third signal wiring, fourth signal wiring

[0044] M1, M2, M3, M4: first metal pattern, second metal pattern, third metal pattern, fourth metal pattern

[0045] Mp1, Mp2, Mp3, Mp4: first contact plug, second contact plug, third contact plug, fourth contact plug DETAILED DESCRIPTION

[0046] The present disclosure is susceptible to various modifications and embodiments. Specific embodiments will be illustrated in the accompanying drawings and described in detail in the specific embodiments. However, this does not limit the present disclosure to specific embodiments, and the present disclosure should be understood to encompass all variations, equivalents, and alternatives within the scope of the present disclosure. When describing the present disclosure, if it is determined that a specific description of a related known technology may obscure the purpose of the present disclosure, the relevant description will be omitted.

[0047] The terms "first" and "second" used in this specification may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0048] In this specification, when a layer, film, region, plate or other part is described as being "above" or "on" another part, it includes not only the case of being "directly above" other parts, but also the case where other parts are arranged in between.

[0049] The x-axis, y-axis, and z-axis used in this specification are not limited to the three axes in a rectangular coordinate system, but can be interpreted as a broad concept including the three axes. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but can also refer to different directions that are not orthogonal to each other.

[0050] The following describes embodiments of the present disclosure in detail with reference to the accompanying drawings. When describing the drawings, substantially identical or corresponding components are denoted by the same reference numerals, and repeated descriptions thereof are omitted. To clearly illustrate various layers and regions, their thicknesses are exaggerated in the drawings. Furthermore, for ease of description, the thicknesses of some layers and regions are also exaggerated in the drawings.

[0051] Figure 1FIG. 1 is a top view schematically showing a display device according to an embodiment of the present disclosure.

[0052] Reference Figure 1 The display device 10 may be formed by bonding the first substrate 100 and the second substrate 200 together via a sealing member 600. The sealing member 600 is formed along the outer contour of the first substrate 100 and / or the second substrate 200, thereby bonding the first substrate 100 and the second substrate 200 together.

[0053] Meanwhile, the display device 10 includes a display area DA and a peripheral area PA disposed around the display area DA. The display device 10 can provide a predetermined image using light emitted from a plurality of pixels P disposed in the display area DA.

[0054] The display area DA includes pixels P connected to scan lines SL extending in a first direction (x-direction) and data lines DL extending in a second direction (y-direction) intersecting the first direction (x-direction). Each pixel P is also connected to a drive voltage line PL extending in a second direction (y-direction).

[0055] The pixels P may each include a display element such as an organic light-emitting diode (OLED). Each pixel P may emit, for example, red, green, blue, or white light via the organic light-emitting diode (OLED). The pixels P herein may be understood as pixels that emit light of any of the colors red, green, blue, and white, as described above.

[0056] Each pixel P may be electrically connected to an internal circuit disposed in the peripheral area PA. A scan driver 40, a wiring portion 50, a terminal portion 30, and the like may be disposed in the peripheral area PA.

[0057] The scan driver 40 may include multiple thin-film transistors and may provide scan signals to each pixel P via scan lines SL. The scan driver 40 may be positioned centrally on both sides of the display area DA. Some of the pixels P in the display area DA may be electrically connected to the scan driver 40 on the left side, while the remaining pixels may be electrically connected to the scan driver 40 on the right side. As another embodiment, the scan driver 40 may be positioned only on one side of the display area DA.

[0058] A wiring portion 50 is provided on one side of the scan driver 40. The wiring portion 50 is a region where wiring for transmitting signals (scanning drive signals) for driving the scan driver 40 is provided. The scanning drive signals may include a gate start signal and a plurality of clock signals. When the scanning drive signals are supplied to the scan driver 40, the scan driver 40 generates scanning signals to be provided to the pixels P.

[0059] The terminal portion 30 may be disposed on one side of the first substrate 100 . The terminal portion 30 may be exposed without being covered by the insulating layer and electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal portion 30 .

[0060] The printed circuit board PCB transmits the signal or power of the control unit (not shown) to the terminal unit 30. The control unit can provide the driving voltage ELVDD (see the following) to the power supply wiring (not shown) through the first connection wiring 11. Figure 2 ) and common voltage (ELVSS (see below) Figure 2 The driving voltage ELVDD can be supplied to each pixel P through the driving voltage line PL connected to the first power supply wiring, and the common voltage ELVSS can be supplied to the counter electrode 223 of the pixel P connected to the second power supply wiring (refer to Figure 4 The second power supply wiring is in the shape of a ring with one side open and can partially surround the display area DA. The second power supply wiring can be arranged between the scan driver 40 and the display area DA. The second power supply wiring provides a common voltage ELVSS and can also be referred to as a common voltage supply wiring.

[0061] The control signal generated in the control unit may be transmitted to the scan driver 40 and the wiring unit 50 via the printed circuit board PCB, the third connection wiring 41 and the fourth connection wiring 51. In this case, the signal transmitted to the wiring unit 50 may be transmitted to the scan driver 40.

[0062] The data driver 60 is electrically connected to the data lines DL. The data signal of the data driver 60 may be provided to each pixel P through the fourth connection wiring 51 connected to the terminal portion 30 and the data lines DL connected to the fourth connection wiring 51. Figure 1 The data driver 60 is shown to be disposed on the printed circuit board PCB, but as another embodiment, the data driver 60 may be disposed on the first substrate 100. For example, the data driver 60 may also be disposed between the terminal portion 30 and the first power supply wiring.

[0063] Figure 2 for Figure 1 An equivalent circuit diagram of a pixel included in a display device.

[0064] Reference Figure 2 The pixel P may include a pixel circuit PC connected to the scan line SL and the data line DL and a display element connected to the pixel circuit PC. As an example, the display element may be an organic light emitting diode OLED.

[0065] The pixel circuit PC may include a driving thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst. The switching thin film transistor Ts is connected to a scan line SL and a data line DL and can transmit a data signal input through the data line DL to the driving thin film transistor Td in response to a scan signal input through the scan line SL. The storage capacitor Cst is connected to the switching thin film transistor Ts and a driving voltage line PL and can store a voltage corresponding to the difference between the voltage received from the switching thin film transistor Ts and the driving voltage ELVDD supplied to the driving voltage line PL.

[0066] The driving thin-film transistor Td is connected to the driving voltage line PL and the storage capacitor Cst. It controls the driving current flowing from the driving voltage line PL to the organic light-emitting diode OLED according to the voltage stored in the storage capacitor Cst. The organic light-emitting diode OLED emits light having a predetermined brightness in response to the driving current. The organic light-emitting diode OLED can emit light of, for example, red, green, blue, or white color.

[0067] On the other hand, Figure 2 , the pixel circuit PC of the pixel P includes two thin film transistors and one storage capacitor, but the present disclosure is not limited thereto. As another embodiment, various changes can be made, for example, the pixel circuit PC of the pixel P includes three or more thin film transistors or includes two or more storage capacitors.

[0068] Figure 3 To enlarge the Figure 1 A top view of an example of the W portion, Figure 4 To show the Figure 3 The A1-A1′ line and Figure 1 Cross-sectional view of line A2-A2′.

[0069] First, refer to Figure 3 , in the substrate ( Figure 1 A plurality of signal wirings CL1, CL2, CL3, and CL4 may be arranged on the 100 of FIG. 100. In this case, the plurality of signal wirings CL1, CL2, CL3, and CL4 may be used to drive the scan driver ( Figure 1 40) is transmitted to the scan driver ( Figure 1 40) wiring.

[0070] exist Figure 3 The plurality of signal wirings CL1, CL2, CL3, and CL4 are shown to include four wirings, namely, a first signal wiring CL1, a second signal wiring CL2, a third signal wiring CL3, and a fourth signal wiring CL4. However, this is only an example, and a greater number of wirings may be connected to the scan driver ( Figure 1of 40).

[0071] Figure 3 The plurality of signal wirings CL1, CL2, CL3, and CL4 shown in FIG are adjacent wirings and extend in a first direction. In this case, the first direction may be substantially parallel to the first direction. Figure 1 The direction of the length of the scanning wiring SL shown is the x direction. However, it is not limited to this. The first direction can also be substantially parallel to the data wiring ( Figure 1 The first direction is the longitudinal direction of the DL (the length of the DL), that is, the y direction, or it may be a third direction different from the x direction and the y direction. For ease of explanation, the following description focuses on the case where the first direction is the x direction and the second direction intersecting the first direction is the y direction.

[0072] Furthermore, the plurality of signal wirings CL1 , CL2 , CL3 , and CL4 are arranged in the y direction, and may be arranged in the +y direction in the order of the first signal wiring CL1 , the second signal wiring CL2 , the third signal wiring CL3 , and the fourth signal wiring CL4 .

[0073] Taking the first signal wiring CL1 among the plurality of signal wirings CL1 , CL2 , CL3 , and CL4 as an example, a plurality of first metal patterns M1 separated from each other are arranged on the first signal wiring CL1 .

[0074] Specifically, at least a portion of the plurality of first metal patterns M1 overlaps with the first signal wiring CL1 . In this case, the plurality of first metal patterns M1 and the first signal wiring CL1 are electrically connected to each other.

[0075] Similar to the first signal wiring CL1, a plurality of spaced-apart second metal patterns M2 are arranged on the second signal wiring CL2, which is the wiring closest to the first signal wiring CL1. At least a portion of the plurality of second metal patterns M2 overlaps with and is electrically connected to the second signal wiring CL2.

[0076] The plurality of first metal patterns M1 each overlapping the first signal line CL1 and the plurality of second metal patterns M2 each overlapping the second signal line CL2 are arranged alternately to prevent defects such as short circuits between adjacent metal patterns M1 and M2.

[0077] In other words, the first metal patterns M1 and the second metal patterns M2 are arranged in a zigzag pattern along the x-direction. Here, the zigzag arrangement means that the centers of the first metal patterns M1 and the second metal patterns M2 are sequentially connected to form a zigzag line ZL.

[0078] As one embodiment, as shown in section N, multiple second metal patterns M2 can be arranged adjacent to a first portion E1 between multiple first metal patterns M1 of a first signal wiring CL1 in the y direction. Similarly, multiple first metal patterns M1 can be arranged adjacent to a second portion E2 between multiple second metal patterns M2 of a second signal wiring CL2 in the y direction. This prevents at least a portion of the first metal pattern M1 from being adjacent to at least a portion of the second metal pattern M2, thereby preventing short circuits between the two metal patterns M1 and M2.

[0079] Therefore, in order to improve the short circuit prevention effect, it is necessary to eliminate or minimize the portion where the first metal pattern M1 is adjacent to the second metal pattern M2 .

[0080] Specifically, when it is adjacent to Figure 3 When the first metal pattern M1 and the second metal pattern M2 are arranged along the virtual line L extending in the y direction shown in FIG, they can be arranged on opposite sides of each other with the virtual line L as the center. As an example, Figure 3 As shown, the edges of each of the first metal pattern M1 and the second metal pattern M2 may respectively contact the virtual line L. As another example, the edges of each of the first metal pattern M1 and the second metal pattern M2 may also be separated from the virtual line L. However, it is not completely ruled out that a portion of the first metal pattern M1 and a portion of the second metal pattern M2 may be arranged adjacent to each other. In this case, preferably, the adjacent portions are less than 50% of each of the first metal pattern M1 and the second metal pattern M2.

[0081] The plurality of first metal patterns M1 may be spaced apart at the same interval. In this case, the spacing intervals s1 between the plurality of first metal patterns M1 and the lengths d1 of the plurality of first metal patterns M1 in the x-direction may be different or the same.

[0082] In addition, the plurality of second metal patterns M2 may be spaced apart at the same interval. The spacing s2 between the plurality of second metal patterns M2 and the length d2 of the plurality of second metal patterns M2 in the x-direction may be different or the same. The spacing s2 between the plurality of second metal patterns M2 may be the same as the spacing s1 between the plurality of first metal patterns M1.

[0083] In addition, if Figure 3 As shown in the N portion of FIG. 1 , the separation interval s1 of the plurality of first metal patterns M1 and the length d2 of the plurality of second metal patterns M2 in the x-direction may be the same.

[0084] As an embodiment, the spacing s1 between the multiple first metal patterns M1 is constant along the x-direction, and the spacing s2 between the multiple second metal patterns M2 is also constant along the x-direction. When the above-mentioned spacings s1 and s2 are the same as each other, the length d1 and the spacing s1 of the multiple first metal patterns M1 in the x-direction and the length d2 and the spacing s2 of the multiple second metal patterns M2 in the x-direction may have the same value.

[0085] On the other hand, when the plurality of first metal patterns M1 overlap the first signal wiring CL1, the first signal wiring CL1 may overlap the entirety of at least one of the plurality of first metal patterns M1. Figure 3 As shown, at least one of the plurality of first metal patterns M1 may be formed on a substrate ( Figure 1 In this case, the width w2 of the first metal pattern M1 in the y direction may be smaller than the width w1 of the first signal wiring CL1 in the y direction.

[0086] The above description uses the first metal pattern M1 located on the first signal wiring CL1 and the second metal pattern M2 located on the second signal wiring CL2 as examples. However, the structure between adjacent signal wirings and the metal patterns located above them is also applicable to the third metal pattern M3 located on the third signal wiring CL3 and the fourth metal pattern M4 located on the fourth signal wiring CL4.

[0087] Below, refer to Figure 4 , according to the plurality of first metal patterns M1 and the plurality of second metal patterns M2 as shown in FIG. Figure 3 In the zigzag arrangement shown, a metal pattern can be placed at a position separated from the first metal pattern M1 by a first distance G1. That is, a gap of the first distance G1 is ensured between two adjacent metal patterns M1 and M3 to prevent short circuits.

[0088] At this time, the metal pattern spaced apart from the first metal pattern M1 by the first distance G1 may be a third metal pattern M3 overlapping the third signal wiring CL3 . Figure 4 The metal patterns separated by the first distance G1 are shown as the first metal pattern M1 and the third metal pattern M3. However, according to Figure 3 That is, in other cross-sectional views, the metal patterns separated by the first distance G1 may also be the second metal pattern M2 and the fourth metal pattern M4.

[0089] like Figure 4 As shown, at least one insulating layer may be disposed between the plurality of signal wirings CL1, CL2, CL3, CL4 and the plurality of metal patterns M1, M3, etc. Figure 1 The components arranged in the display area DA are described with reference to a cross section along the line A2 - A2 ′, and positions of the signal wiring, the metal pattern, and the insulating layer interposed therebetween are specifically described.

[0090] Referring to the A2 - A2 ′ cross section, a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC may be disposed in the display area DA.

[0091] A thin film transistor TFT, a storage capacitor Cst, and a pixel electrode 221 electrically connected thereto are formed on the substrate 100. The pixel circuit PC is disposed on the substrate 100, and the organic light emitting diode OLED may be located on the pixel circuit PC.

[0092] As an embodiment, the substrate 100 may include a polymer resin, such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), or cellulose acetate propionate (CAP), thereby providing the substrate 100 with flexibility.

[0093] As another embodiment, the substrate 100 may include a glass material with SiO2 as the main component, or may include a resin such as tempered plastic, which may have a rigid property. The substrate 100 may be a laminated structure including a layer of the above-mentioned polymer resin and a barrier layer located on the above-mentioned polymer resin layer. In this case, the flexibility of the substrate 100 can be improved. The barrier layer may include silicon nitride (SiN x ), silicon oxynitride (SiON) and silicon oxide (SiO x )wait.

[0094] A buffer layer 201 may be disposed on the substrate 100 to prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT. The buffer layer 201 may include inorganic insulators such as silicon nitride, silicon oxynitride, and silicon oxide, and may be a single layer or multiple layers.

[0095] A pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figure 4 The thin film transistor TFT shown in FIG. Figure 2 The driving thin film transistor Td or the light emission control thin film transistor is shown in this embodiment as a top gate type in which the gate electrode GE is disposed on the semiconductor layer Act with the gate insulating layer 203 interposed therebetween. However, according to another embodiment, the thin film transistor TFT may be a bottom gate type.

[0096] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like. The gate electrode GE may include a low-resistance metal substance. The gate electrode GE may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above-mentioned materials.

[0097] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium dioxide. The gate insulating layer 203 may be a single layer or multiple layers including the above materials.

[0098] The source electrode SE and the drain electrode DE may include a material with excellent electrical conductivity. The source electrode SE and the drain electrode DE may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a single layer or multiple layers including these materials. As one embodiment, the source electrode SE and the drain electrode DE may be formed as a multilayer of Ti / Al / Ti.

[0099] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 that overlap with the first interlayer insulating layer 205. The storage capacitor Cst may overlap with the thin film transistor TFT. In this regard, Figure 4 The gate electrode GE of the thin film transistor TFT is shown as the lower electrode CE1 of the storage capacitor Cst. As another embodiment, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 207.

[0100] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium dioxide. The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may be a single layer or multiple layers including the above materials.

[0101] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst can be covered by a planarization insulating layer 209. The planarization insulating layer 209 may include a substantially flat surface. The planarization insulating layer 209 may include an organic insulator such as a common general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and a mixture thereof. As an embodiment, the planarization insulating layer 209 may include polyimide. Alternatively, the planarization insulating layer 209 may include an inorganic insulator, or may include an inorganic insulator and an organic insulator.

[0102] The pixel electrode 221 may be formed on the planarization insulating layer 209. The pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). As another embodiment, the pixel electrode 221 may include a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. As yet another embodiment, the pixel electrode 221 may further include a film formed of ITO, IZO, ZnO, or In2O3 above / below the above-mentioned reflective film.

[0103] A pixel definition film 211 may be formed on the pixel electrode 221. The pixel definition film 211 includes an opening that exposes the upper surface of the pixel electrode 221 and may cover the edge of the pixel electrode 221. The pixel definition film 211 may include an organic insulating material. Alternatively, the pixel definition film 211 may include silicon nitride (SiN x ), silicon oxynitride (SiON) or silicon oxide (SiO x Alternatively, the pixel definition film 211 may include an organic insulator and an inorganic insulator.

[0104] The intermediate layer 222 includes a light-emitting layer 222b. The intermediate layer 222 may include a first functional layer 222a disposed below the light-emitting layer 222b and / or a second functional layer 222c disposed above the light-emitting layer 222b. The light-emitting layer 222b may include a high molecular weight organic material or a low molecular weight organic material that emits light of a predetermined color.

[0105] The first functional layer 222a may be a single layer or multiple layers. For example, when the first functional layer 222a is formed of a polymer, the first functional layer 222a is a single-layer hole transport layer (HTL), which may be formed of polyethylene dihydroxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 222a is formed of a low-molecular-weight material, the first functional layer 222a may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0106] The second functional layer 222c is not always present. For example, when the first functional layer 222a and the light-emitting layer 222b are formed of a polymer, the second functional layer 222c is preferably formed. The second functional layer 222c can be a single layer or multiple layers. The second functional layer 222c can include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0107] In the intermediate layer 222, the first functional layer 222a and / or the second functional layer 222c can be formed in all pixels. In the intermediate layer 222, the light-emitting layer 222b can be individually disposed in each pixel in the display area DA. The light-emitting layer 222b can be disposed within the opening of the pixel definition film 211.

[0108] The counter electrode 223 can be made of a conductive material with a low work function. For example, the counter electrode 223 may include a (semi-) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or alloys thereof. Alternatively, the counter electrode 223 may also include a layer such as ITO, IZO, ZnO or In2O3 on the (semi-) transparent layer containing the above-mentioned substances. The counter electrode 223 can be formed not only on the display area DA, but also on the peripheral area PA serving as a non-display area. The intermediate layer 222 and the counter electrode 223 can be formed by thermal evaporation.

[0109] The capping layer 230 may be located on the counter electrode 223. For example, the capping layer 230 may include LiF and may be formed by thermal evaporation. Alternatively, the capping layer 230 may include an inorganic insulator such as silicon oxide, silicon nitride, or silicon oxynitride. Alternatively, the capping layer 230 may be omitted.

[0110] A spacer 213 may be formed on the pixel definition film 211. The spacer 213 may include an organic insulator such as polyimide, or an inorganic insulator such as silicon nitride or silicon oxide, or both.

[0111] The spacer 213 may comprise a different material from the pixel definition film 211. Alternatively, the spacer 213 may comprise the same material as the pixel definition film 211. In this case, the pixel definition film 211 and the spacer 213 may be formed together in a masking process using a half-tone mask or the like. In one embodiment, the pixel definition film 211 and the spacer 213 may comprise polyimide.

[0112] Refer to Figure 4 In the A1-A1′ cross section and the A2-A2′ cross section, the plurality of signal wirings CL1, CL2, CL3, and CL4 can be arranged on the same layer as the gate electrode GE of the thin film transistor TFT. That is, the plurality of signal wirings CL1, CL2, CL3, and CL4 can be arranged on the gate insulating layer 203, which is similar to the reference Figure 1 and Figure 2 The scan lines SL described above are arranged on the same layer.

[0113] Furthermore, a plurality of metal patterns (M1, M3, etc.) can be arranged on the same layer as the source electrode SE and the drain electrode DE of the thin film transistor TFT, which can be compared with the reference Figure 1 and Figure 2 The data wiring DL described above is arranged on the same layer. Figure 4 Only the first metal pattern M1 and the third metal pattern M3 are shown in the A1-A1′ cross section. Figure 3 The second metal pattern M2 of the first metal pattern M1 and the fourth metal pattern M4 adjacent to the third metal pattern M3 may also be configured on the same layer as the source electrode SE and the drain electrode DE of the thin film transistor TFT.

[0114] At least one insulating layer interposed between the plurality of signal wirings CL1 , CL2 , CL3 , and CL4 and the plurality of metal patterns ( M1 , M3 , etc.) may include a first interlayer insulating layer 205 and a second interlayer insulating layer 207 .

[0115] At this time, the plurality of metal patterns (M1, M3, etc.) may be electrically connected to the plurality of signal wirings CL1, CL2, CL3, and CL4 provided on different layers.

[0116] Taking the first metal pattern M1 as an example, the first metal patterns M1 may respectively include first contact plugs Mp1 at both ends, and may be connected to the first signal wiring CL1 located below the first metal patterns M1 through the first contact plugs Mp1 .

[0117] Specifically, the first contact plug Mp1 passes through the first interlayer insulating layer 205 and the second interlayer insulating layer 207 which are sandwiched between multiple signal wirings CL1, CL2, CL3, CL4 and multiple metal patterns (M1, M3, etc.). For this purpose, holes corresponding to the first contact plug Mp1 can be formed in the first interlayer insulating layer 205 and the second interlayer insulating layer 207.

[0118] Thus, the scanning drive signal including the clock signal can be alternately passed through Figure 3 and transmitted to the scan driver ( Figure 1 40). At this point, the scan drive signal repeats the following process: it passes through the first signal wiring CL1 (the lower layer), rises through the first contact plug Mp1 to the first metal pattern M1 (the upper layer), moves along the first metal pattern M1 in the first direction (x direction), and then again passes through the first contact plug Mp1 to the first signal wiring CL1 (the lower layer). This process utilizes two metal layers CL1 and M1 to transmit signals, which has the advantage of reducing wiring load compared to single-layer wiring.

[0119] On the other hand, the second contact plug Mp2 connecting the second signal wiring CL2 and the second metal pattern M2, the third contact plug Mp3 connecting the third signal wiring CL3 and the third metal pattern M3, the fourth contact plug Mp4 connecting the fourth signal wiring CL4 and the fourth metal pattern M4, etc. also transmit signals by moving up and down in the first direction (x direction) in the same way as the first contact plug Mp1.

[0120] Figure 5 is a cross-sectional view schematically illustrating a portion of a display device according to another embodiment of the present disclosure.

[0121] like Figure 5 In the embodiment shown, in addition to a plurality of metal patterns (e.g. Figure 4 Except for the positions on the layers of M1, M3, etc., the embodiment is the same or similar to that shown in the figure. Figure 5 The structure of the top view of the A1-A1′ section can be Figure 3Therefore, only the features related to the position of the metal pattern on the layer will be described below, and other features refer to the above content.

[0122] Refer to Figure 5 In the A1-A1′ section and the A2-A2′ section, multiple signal wirings CL1, CL2, CL3, CL4 and Figure 4 In the same manner as in the embodiment shown in FIG, the gate electrode GE of the thin film transistor TFT can be provided on the same layer. That is, the plurality of signal wirings CL1, CL2, CL3, and CL4 can be provided on the gate insulating layer 203. Figure 1 and Figure 2 The scan lines SL described above can be arranged on the same layer.

[0123] On the other hand, Figure 4 Unlike the illustrated embodiment, a plurality of metal patterns ( M1 ′, M3 ′, etc.) may be disposed between the gate electrode GE and the source electrode SE and the drain electrode DE of the thin film transistor TFT.

[0124] As an embodiment, the plurality of first metal patterns M1′ can be arranged on the same layer as the upper electrode CE2 of the storage capacitor Cst provided in the pixel circuit PC. Figure 1 SL) are configured on the same layer, or can be connected with data wiring ( Figure 1 DL) is configured on the same layer.

[0125] at this time, Figure 5 Only the first metal pattern M1′ and the third metal pattern M3′ are shown in the A1-A1′ cross section, but in addition to these, the metal patterns (not shown) overlapping the second signal wiring CL2 and the fourth signal wiring CL4 may also be arranged on the same layer as the upper electrode CE2 of the storage capacitor Cst.

[0126] At least one insulating layer interposed between the plurality of signal wirings CL1, CL2, CL3, CL4 and the plurality of metal patterns (M1′, M3′, etc.) may include a first interlayer insulating layer 205. This reduces the number of insulating layers interposed between the plurality of signal wirings CL1, CL2, CL3, CL4 and the plurality of metal patterns (M1′, M3′, etc.), shortening the lengths of the first contact plugs Mp1′ and the third contact plugs Mp3′ provided in each of the plurality of metal patterns (M1′, M3′, etc.).

[0127] On the other hand, in order to smoothly transmit the scanning drive signal moving up and down the wiring on different layers to the scanning driver ( Figure 1 40), it is necessary to reduce the resistance of the metal patterns M1, M2, M3, and M4 in the upper layer. Figures 6 to 9 , various embodiments for reducing the resistance of the metal patterns M1, M2, M3, and M4 are described in detail.

[0128] Figure 6 To enlarge the Figure 1 A top view of another example of the W portion, Figure 7 To follow Figure 6 Cross-sectional view of line BB′.

[0129] like Figure 6 and Figure 7 In the embodiment shown in FIG, in addition to the plurality of metal patterns (e.g., Figure 4 In addition to the length of the spacing (s1, etc.) between M1, M3, etc. Figure 3 and Figure 4 Therefore, only the features related to the spacing between the metal patterns will be described below, and other features refer to the above content.

[0130] First, refer to Figure 6 In the N portion, the plurality of second metal patterns M2 can be arranged adjacent to the first portion E1 between the plurality of first metal patterns M1 of the first signal wiring CL1 in the y direction, similarly to the embodiment shown in FIG3. Similarly, the plurality of first metal patterns M1 can also be arranged adjacent to the second portion E2 between the plurality of second metal patterns M2 of the second signal wiring CL2 in the y direction.

[0131] On the other hand, Figure 3 Unlike the embodiment shown in , the separation interval s1 of the plurality of first metal patterns M1 may be different from the length d2 of the plurality of second metal patterns M2 in the x-direction.

[0132] As one embodiment, the spacing s1 between the plurality of first metal patterns M1 can be greater than the length d2 of the plurality of second metal patterns M2 in the x-direction. This increases the average spacing between the first metal patterns M1 surrounding a second metal pattern M2, further reducing the likelihood of short circuits between the two metal patterns M1 and M2.

[0133] exist Figure 6 In the N portion of FIG, the second metal pattern M2 is shown as being arranged offset to one side of the first portion E1, which is the portion between the plurality of first metal patterns M1 in the first signal wiring CL1. However, the present invention is not limited thereto. As another example, the second metal pattern M2 may be arranged in the center of the first portion E1 of the first signal wiring CL1.

[0134] The above description uses the first metal pattern M1 located on the first signal wiring CL1 and the second metal pattern M2 located on the second signal wiring CL2 as examples. However, this structure between adjacent signal wirings and the metal patterns located above them is also applicable to the third metal pattern M3 located on the third signal wiring CL3 and the fourth metal pattern M4 located on the fourth signal wiring CL4.

[0135] Below, refer to Figure 7 In the BB′ cross section, multiple signal wirings CL1, CL2, CL3, and CL4 are connected to the Figure 4 In the same manner as in the embodiment shown in FIG, the gate electrode GE of the thin film transistor TFT can be arranged on the same layer. In addition, a plurality of metal patterns (M1, M3, etc.) can be arranged on the same layer as the source electrode SE and the drain electrode DE of the thin film transistor TFT, which is also the same as in FIG. Figure 4 The embodiment shown in is the same.

[0136] However, in Figure 3 and Figure 4 In the embodiment shown in Figure 3 No matter at which position the top view is taken, a first distance G1 between metal patterns (M1 and M3, or M2 and M4) adjacent to each other in the y direction is constant.

[0137] In contrast, in this embodiment, when the Figure 6 When the display device is cut along line BB′, the first metal pattern M1 and the fourth metal pattern M4 may be exposed in the cross section. In this case, the second distance G2 between adjacent metal patterns (M1 and M4) in the y direction may be greater than the first distance G1.

[0138] In this way, by increasing the spacing interval s1 between the plurality of metal patterns (for example, M1 ), there is an advantage in that the intervals between adjacent metal patterns can be further ensured.

[0139] In addition, although Figure 6 and Figure 7 Not shown in the figure, the plurality of metal patterns M1, M2, M3, M4 and the source electrode SE and the drain electrode DE of the thin film transistor TFT may be arranged on different layers, not on the same layer. Figure 5 As shown, the plurality of metal patterns M1 , M2 , M3 , and M4 may also be arranged on the same layer as the upper electrode CE2 of the storage capacitor Cst.

[0140] Figure 8 To enlarge the Figure 1 A top view of another example of the W portion, Figure 9 To follow Figure 8 Cross-sectional view along line CC′.

[0141] exist Figure 8 and Figure 9 In the embodiment shown in FIG, except for the widths of the plurality of metal patterns M1, M2, M3, and M4, Figure 3 and Figure 4 Therefore, only the features related to the width of the metal pattern will be described below, and other features refer to the above content.

[0142] Refer to Figure 8 and Figure 9 The widths of the multiple metal patterns M1, M2, M3, and M4 can be greater than the widths of the multiple signal traces CL1, CL2, CL3, and CL4 overlapping thereunder. Specifically, taking the first metal pattern M1 as an example, the width w2′ of the first metal pattern M1 in the y direction can be greater than the width w1 of the first signal trace CL1 in the y direction.

[0143] In this way, as the widths of the metal patterns M1 , M2 , M3 , and M4 increase, the resistance of the metal patterns M1 , M2 , M3 , and M4 decreases, thereby enabling signals to be transmitted more smoothly.

[0144] However, there is a problem that the interval between adjacent metal patterns becomes smaller. Therefore, even if the metal patterns are arranged in a zigzag pattern on two adjacent signal wirings, the possibility of occurrence of short circuits and the like cannot be reduced.

[0145] Therefore, in this embodiment, if Figure 8 As shown, the spacing between the plurality of metal patterns overlapping one signal wiring is made equal to Figure 3 and Figure 6 The embodiment shown in etc. is further increased.

[0146] Taking the first metal pattern M1 as an example, the spacing interval s1 between the plurality of first metal patterns M1 may be greater than Figure 3 The spacing s1 and Figure 6 The spacing distance s1 shown in .

[0147] Furthermore, a first gap c1 may be provided to separate the edge of the first metal pattern M1 on the second signal wiring CL2 side from the second signal wiring CL2 in the y direction, and a second gap c2 may be provided to separate the edge of the first metal pattern M1 on the second metal pattern M2 side from the second metal pattern M2 in the x direction. In this case, the first gap c1 separates the first metal pattern M1 and the second signal wiring CL2 from each other, thereby reducing parasitic capacitance that may occur between the first metal pattern M1 and the second signal wiring CL2.

[0148] This structure is also applicable to the third metal pattern M3 located on the third signal wiring CL3 and the fourth metal pattern M4 located on the fourth signal wiring CL4.

[0149] In this embodiment, while reducing the resistance by increasing the widths of the plurality of metal patterns M1, M2, M3, M4, increasing the intervals (e.g., s1, c1, c2, etc.) between adjacent metal patterns or between a metal pattern and the wiring adjacent thereto can reduce the possibility of occurrence of short circuits and the like.

[0150] Although Figure 8 and Figure 9 are not shown in the figures, the plurality of metal patterns M1, M2, M3, M4 may be arranged on different layers rather than the same layer as the source electrode SE and the drain electrode DE of the thin film transistor TFT. For example, as Figure 5 shown, the plurality of metal patterns M1, M2, M3, M4 may also be arranged on the same layer as the upper electrode CE2 of the storage capacitor Cst.

[0151] Meanwhile, in embodiments such as Figure 3 shown, signal wirings with relatively small widths of overlapping metal patterns (e.g., as Figure 3 shown, w2 < w1) and signal wirings with relatively large widths of overlapping metal patterns (e.g., as Figure 8 shown, w2′ > w1) may also be appropriately combined and used.

[0152] As described above, the present disclosure has been described with reference to an embodiment shown in the accompanying drawings, but this is merely exemplary. It is understood by those of ordinary skill in the art that various modifications and variations of the embodiments can be made therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical idea of the appended claims.

Claims

1. A display device, wherein: include: The first signal wiring and the second signal wiring respectively extend continuously in a first direction on the substrate and are arranged in a second direction intersecting the first direction; a plurality of first metal patterns spaced apart from each other, at least a portion of which overlaps with the first signal wiring and is electrically connected to the first signal wiring; as well as A plurality of second metal patterns separated from each other, at least a portion of which overlaps with the second signal wiring and is electrically connected to the second signal wiring, The plurality of first metal patterns and the plurality of second metal patterns are arranged in zigzag pattern along the first direction. The spacing intervals between the plurality of first metal patterns are greater than or equal to the lengths of the plurality of second metal patterns in the first direction. A width of each of the plurality of first metal patterns in the second direction is smaller than a width of the first signal wiring in the second direction.

2. The display device according to claim 1, wherein The plurality of second metal patterns are adjacent to portions of the first signal wiring between the plurality of first metal patterns in the second direction.

3. The display device according to claim 1, wherein The plurality of first metal patterns are spaced apart from each other at the same intervals.

4. The display device according to claim 1, wherein The plurality of second metal patterns are spaced apart from each other at the same interval, and a spacing pitch of the plurality of first metal patterns is the same as a spacing pitch of the plurality of second metal patterns.

5. The display device according to claim 1, wherein The first signal wiring overlaps an entirety of at least one of the plurality of first metal patterns. The display device according to claim 1 , wherein: Second metal patterns adjacent to the first metal patterns among the second metal patterns are spaced apart from the first metal patterns in the first direction and the second direction.

7. The display device according to claim 1, wherein Lengths of the plurality of first metal patterns in the first direction are different from lengths of the plurality of second metal patterns in the first direction.

8. The display device according to claim 1, wherein Widths of the plurality of first metal patterns in the second direction are different from widths of the plurality of second metal patterns in the second direction.

9. The display device according to claim 1, wherein The display device further includes at least one insulating layer interposed between the first signal wiring and the plurality of first metal patterns.

10. The display device according to claim 9, wherein Each of the plurality of first metal patterns includes a first contact plug, and the first contact plug penetrates the at least one insulating layer and connects the plurality of first metal patterns and the first signal wiring.

11. The display device according to claim 10, wherein: The first contact plugs are respectively located at two ends of the plurality of first metal patterns.

12. The display device according to claim 1, wherein The display device further includes a plurality of display elements arranged on the substrate, each of the plurality of display elements including a thin film transistor and a capacitor having a gate electrode of the thin film transistor as a lower electrode.

13. The display device according to claim 12, wherein: The first signal wiring is arranged on the same layer as a gate electrode of the thin film transistor.

14. The display device according to claim 12, wherein: The plurality of first metal patterns are arranged on the same layer as the source electrode and the drain electrode of the thin film transistor.

15. The display device according to claim 12, wherein: The plurality of first metal patterns are arranged between the gate electrode of the thin film transistor and the source electrode and the drain electrode of the thin film transistor.

16. The display device according to claim 12, wherein: The plurality of first metal patterns are arranged on the same layer as the upper electrode of the capacitor.

17. The display device according to claim 1, wherein The display device further includes a scan driver driven by signals supplied from each of the first signal wiring and the second signal wiring.

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