Semiconductor Devices

Abstract

A semiconductor device includes a first group of active fins and a first diffusion prevention pattern. The first group of active fins are spaced apart from each other in a second direction, and each of the first group of active fins extends along a first direction different from the second direction on a first region of a substrate including a first region and a second region. The first diffusion prevention pattern extends through the first group of active fins on the first region of the substrate along the second direction. The first group of active fins includes a first active fin and a second active fin. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end portion of the second active fin in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0009725 filed on January 25, 2019, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments of the inventive concepts relate to semiconductor devices. More particularly, example embodiments of the inventive concepts relate to semiconductor devices including diffusion prevention patterns. Background Art

[0004] In order to electrically isolate adjacent standard cells of a semiconductor device, a diffusion prevention pattern may be formed. The diffusion prevention pattern may be formed by forming active fins and removing some of the active fins, or removing a gate structure and some of the active fins under the gate structure. At the boundary region between adjacent cells where the diffusion prevention pattern is formed, the width of the active region on which the active fins can be formed may be reduced, so that the number of active fins on the active region may be changed, and thus the characteristics of the active fins may be changed due to the local layout effect (LLE). Summary of the invention

[0005] Example embodiments provide semiconductor devices having enhanced characteristics.

[0006] According to some example embodiments, there is provided a semiconductor device including: a first group of active fins spaced apart from each other in a second direction on a first region of a substrate, each of the first group of active fins extending in the first direction, the first direction and the second direction being different from each other, and the substrate including a first region and a second region; and a first diffusion prevention pattern extending through the first group of active fins in the second direction on the first region of the substrate, wherein the first group of active fins includes a first active fin and a second active fin, and the first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end portion of the second active fin in the first direction.

[0007] According to some example embodiments, there is provided a semiconductor device, including: an active region on a substrate, extending along a first direction and including a first portion, a second portion, and a third portion, the first portion having a first width in a second direction substantially perpendicular to the first direction, the second portion having a second width smaller than the first width in the second direction, and the third portion being located between the first portion and the second portion and having a third width smaller than the first width and larger than the second width in the second direction; a first active fin extending to a first length in the first direction on the first portion to the third portion of the active region; and a second active fin extending to a second length smaller than the first length on the first portion of the active region, wherein a distance from a sidewall of the third portion of the active region to the first active fin in the second direction is greater than a distance from a sidewall of each of the first portion and the second portion of the active region to the first active fin in the second direction.

[0008] According to some example embodiments, there is provided a semiconductor device including: a first group of active fins spaced apart from each other in a second direction on a first region of a substrate, each of the first group of active fins extending in the first direction, the first direction and the second direction being different from each other, and the substrate including a first region and a second region, the first group of active fins including a first active fin and a second active fin; a first diffusion preventing pattern extending through a central portion of the first active fin in the second direction on the first region of the substrate so as to divide the first active fin in the first direction, and extending through an end portion of the second active fin in the first direction; and a second diffusion preventing pattern extending along the second direction on the first region of the substrate, the second diffusion preventing pattern contacting a sidewall of the first diffusion preventing pattern, wherein a bottom of the second diffusion preventing pattern is closer to the substrate in a third direction than a bottom of the first diffusion preventing pattern, and a top surface of the second diffusion preventing pattern is farther from the substrate in the third direction than a top surface of the first diffusion preventing pattern, the third direction being substantially perpendicular to a surface of the substrate.

[0009] The semiconductor device according to the present invention can reduce or prevent the instability of characteristics caused by LLE. In addition, electrical short circuits at regions with varying widths between adjacent conductive structures can be reduced or prevented. In addition, the diffusion prevention pattern formed by removing the gate structure can be formed not only in the PMOS region but also in the NMOS region, so that leakage current caused by the dummy gate structure can be reduced or prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a plan view showing a mask including a layout of some elements of a semiconductor device according to some example embodiments;

[0011] Figures 2 to 6is a plan view showing a mask including a layout of some elements of a semiconductor device according to some example embodiments;

[0012] Figures 7 to 31 are plan views and cross-sectional views illustrating stages of a method of manufacturing a semiconductor device according to some example embodiments;

[0013] Fig.32 and Fig.33 are a plan view and a cross-sectional view showing a semiconductor device according to a first comparative example;

[0014] Fig.34 is a plan view showing a semiconductor device according to a second comparative example; and

[0015] Fig.35 and Fig.36 are a plan view and a cross-sectional view showing a semiconductor device according to a third comparative example. DETAILED DESCRIPTION

[0016] The exemplary embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. Hereinafter, two directions substantially parallel to the upper surface of the substrate and intersecting each other may be referred to as a first direction and a second direction, respectively, and a direction substantially perpendicular to the upper surface of the substrate may be referred to as a third direction. In some example embodiments, the first direction and the second direction may be substantially perpendicular to each other.

[0017] Figure 1 is a plan view illustrating a mask including a layout of some elements of a semiconductor device according to some example embodiments.

[0018] Reference Figure 1 , the mask 90 may include two cells adjacent in the first direction, and may include a first region I and a second region II adjacent in the second direction. The boundary between the cells is shown by a dotted line extending along the second direction.

[0019] In some example embodiments, the mask 90 may include the first and second active fins 2 and 4, the first and second active regions 12 and 14, the gate structure 20, the first diffusion preventing pattern 30, the insulating pattern 40, the second diffusion preventing pattern 50, the first and second contact plugs 62 and 64 and / or the third contact plug 70.

[0020] In order to avoid the complexity of the drawings, only the layout of some main elements that can be formed in each unit is shown. The layout of the elements can be designed with one or more masks, and only one mask 90 is shown in the drawings. For example, considering that the layers of the elements can be formed separately, the layout of the elements can be designed with multiple masks that can overlap each other vertically.

[0021] The first and second active fins 2 and 4 may extend in the first and second regions I and II, respectively, along the first direction. The plurality of first active fins 2 may be spaced apart from each other in the second direction, and the plurality of second active fins 4 may be spaced apart from each other in the second direction.

[0022] The gate structure 20 may extend in the second direction in the first region I and the second region II to overlap the first active fin 2 and the second active fin 4 , and a plurality of gate structures 20 may be spaced apart from each other in the first direction.

[0023] The first active fin 2 and the second active fin 4 as well as the gate structure 20 are shown by dotted lines in the drawings.

[0024] The first active region 12 and the second active region 14 may extend in the first direction in the first region I and the second region II, respectively, and may include at least a portion of the first active fin 2 and the second active fin 4, respectively. In some example embodiments, the first active region 12 may include a first portion having a first width in the second direction and a second portion having a second width smaller than the first width in the second direction. Similarly, the second active region 14 may include a first portion having a third width in the second direction and a second portion having a fourth width smaller than the third width in the second direction.

[0025] In some example embodiments, a first boundary between the first portion and the second portion of the first active region 12 may be formed between two of the gate structures 20 adjacent in the first direction, and a second boundary between the first portion and the second portion of the second active region 14 may overlap one of the two adjacent gate structures 20. Therefore, the first boundary and the second boundary may not be aligned with each other in the second direction.

[0026] As will be described later, a second boundary between the first portion and the second portion of the second active region 14, that is, a portion where the width of the second active region 14 rapidly decreases, may be formed to overlap one of two gate structures 20 adjacent in the first direction, rather than being formed between the two gate structures 20. Local layout effects (LLEs) may be reduced so that characteristics (e.g., capacitance) of the second active fin 4 on the second active region 14 may be stable.

[0027] The first diffusion preventing pattern 30 may extend in the second direction and may include a boundary between cells in the first region I. In some example embodiments, the first diffusion preventing pattern 30 may include a first boundary between a first portion and a second portion of the first active region 12, and an extension length of the first diffusion preventing pattern 30 in the second direction may be less than half of an extension length of the gate structure 20 in the second direction. In addition, the first diffusion preventing pattern 30 may at least partially overlap two gate structures 20 adjacent in the first direction. A plurality of first diffusion preventing patterns 30 may be spaced apart from each other in the first direction.

[0028] The second diffusion prevention pattern 50 may extend in the second direction and may include boundaries between cells in the first region I and the second region II. In some example embodiments, the second diffusion prevention pattern 50 may include the first diffusion prevention pattern 30 therein, and the extension length of the second diffusion prevention pattern 50 in the second direction may be less than the extension length of the gate structure 20 in the second direction. In addition, the second diffusion prevention pattern 50 may cover two gate structures 20 adjacent in the first direction. A plurality of second diffusion prevention patterns 50 may be spaced apart from each other in the first direction.

[0029] As will be explained later, the second diffusion preventing pattern 50 may fill a groove that may be formed by removing the gate structure 20 and portions of the first active fin 2 and the second active fin 4 thereunder. Therefore, the second diffusion preventing pattern 50 may be formed not only in the first region I but also in the second region II, so that the dummy gate structure remaining on the first diffusion preventing pattern 30 may also be removed. Therefore, leakage current caused by the dummy gate structure may be reduced or prevented.

[0030] In some example embodiments, the insulating pattern 40 may overlap a first portion of the second portion adjacent to the second active region 14 in the second region II, and may contact an edge of the second portion of the second region to extend in the first direction. The insulating pattern 40 may overlap an edge of each of two second diffusion prevention patterns 50 adjacent in the first direction.

[0031] As will be described later, the insulating pattern 40 may fill a groove that may be formed by removing a portion of the second active fin 4 remaining on the first portion adjacent to the second portion of the second active region 14. Therefore, formation of a parasitic source / drain layer on the remaining second active fin 4 may be reduced or prevented, and thus an electrical short circuit due to the parasitic source / drain layer may be reduced or prevented.

[0032] The first contact plug 62 may extend in the second direction in the first region I to overlap one or more of the first active fins 2 , and the second contact plug 64 may extend in the second direction in the second region II to overlap one or more of the second active fins 4 .

[0033] The third contact plug 70 may overlap the gate structure 20. In some example embodiments, the third contact plug 70 may be formed at a boundary between the first region I and the second region II.

[0034] Figures 2 to 6 1 is a plan view showing a mask including a layout of some elements of a semiconductor device according to some example embodiments. In addition to some elements, these masks may be Figure 1 Therefore, the same reference numerals denote the same elements, and a repeated detailed description thereof is omitted here.

[0035] refer to Figure 2 , the insulating pattern 40 may overlap the first portion of the second portion adjacent to the second active region 14 in the second region II, and may contact the edge of the second portion of the second active region 14 to extend a given length in the first direction. However, the insulating pattern 40 may overlap only the edge of one second diffusion preventing pattern 50, and may not extend to another second diffusion preventing pattern 50 adjacent in the first direction.

[0036] The insulating pattern 40 can reduce or prevent electrical shorts with other conductive structures by removing the portion of the second active fin 4 remaining on the first portion adjacent to the second portion of the second active region 14, thereby reducing or preventing electrical shorts even if the insulating pattern 40 does not overlap with each of the edges of two adjacent second diffusion prevention patterns 50.

[0037] Reference Figure 3 When the second active region 14 has a region where the width changes rapidly except for a region adjacent to a boundary between the first portion and the second portion, the insulating pattern 40 may also cover the region.

[0038] Reference Figure 4 , the second diffusion prevention pattern 50 may include a boundary between cells in the first region I and the second region II, and may extend along the second direction. In addition, the second diffusion prevention pattern 50 may cover two gate structures 20 adjacent in the first direction. However, unlike Figure 1 Different from the embodiment of the present invention, the second diffusion preventing pattern 50 may cover only the two gate structures 20 and may not cover the first active fin 2 and the second active fin 4 therebetween.

[0039] The second diffusion preventing pattern 50 may be formed to remove the gate structure 20 and portions of the first and second active fins 2 and 4 thereunder, and thus may not cover the first and second active fins 2 and 4 between the gate structure 20 .

[0040] Reference Figure 5 , the second diffusion prevention pattern 50 may only cover the two gate structures 20, such as Figure 4 In addition, the second diffusion preventing pattern 50 may overlap only one second diffusion preventing pattern 50 and may not extend to another second diffusion preventing pattern 50 adjacent in the first direction, such as Figure 2 shown.

[0041] Reference Figure 6 , the second diffusion prevention pattern 50 may only cover the two gate structures 20, such as Figure 4 In addition, when the second active region 14 has a region where the width changes rapidly except for a region adjacent to the boundary between the first portion and the second portion, an insulating pattern 40 covering the region may also be formed.

[0042] Figures 7 to 31 are plan views and cross-sectional views showing various stages of a method of manufacturing a semiconductor device according to some example embodiments. In particular, Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.16 , Fig.21 , Fig.25 and Fig. 27 It is a floor plan. Figure 8 , Fig.10 , Fig.12 , Figure 14 to Figure 15 , Figures 17 to 20 , Figure 22 to Figure 24 , Fig.26 and Figure 28 to Figure 31 It is a cross-sectional view.

[0043] Figure 8 , Fig.12 and Fig.28 is a cross-sectional view taken along line AA′ of the corresponding plan view, Fig.10 , Figure 14 to Figure 15 , Fig.19 , Fig. 22 and Fig.29 is a cross-sectional view taken along line BB′ of the corresponding plane view, Fig.17 is a cross-sectional view taken along line CC′ of the corresponding plan view, Fig.18 , Fig. 20 , Figure 23 to Figure 24 , Fig.26 and Fig.30 is a cross-sectional view taken along line DD′ of the corresponding plan view, and Fig.31 It is a cross-sectional view taken along line EE' of the corresponding plan view.

[0044] Methods according to some example embodiments may use reference Figure 5 However, the present invention may not be limited thereto and may use reference Figures 1 to 4 or Figure 6 The mask shown is used to perform the method.

[0045] Reference Figure 7 and Figure 8 , an upper portion of the substrate 100 including the first region I and the second region II may be partially removed to form a first groove 105 , and thus first and second active fins 112 and 114 protruding from the substrate 100 may be formed in the first region I and the second region II, respectively.

[0046] The substrate 100 may include semiconductor materials such as silicon, germanium, silicon germanium, etc. and / or III-V compounds such as GaP, GaAs, GaSb, etc. In some example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0047] Hereinafter, a lower portion of the substrate 100 , ie, only a portion of the substrate 100 below the bottoms of the first and second active fins 112 and 114 , may be referred to as the substrate 100 to be distinguished from the first and second active fins 112 and 114 .

[0048] In some example embodiments, the first region I of the substrate 100 may be a negative channel metal oxide semiconductor (NMOS) region in which an NMOS transistor may be formed, and the second region II of the substrate 100 may be a positive channel metal oxide semiconductor (PMOS) region in which a PMOS transistor may be formed. The first region I and the second region II may be disposed along the second direction.

[0049] In some example embodiments, each of the first and second active fins 112 and 114 may extend to a first length in a first direction, and a plurality of first and second active fins 112 and 114 may be spaced apart from each other in a second direction.

[0050] A first isolation layer may be formed on the substrate 100 to cover the first and second active fins 112 and 114, and may be planarized until upper surfaces of the first and second active fins 112 and 114 may be exposed to form a first isolation pattern 120, which covers sidewalls of the first and second active fins 112 and 114. The first isolation pattern 120 may include an oxide, such as silicon oxide.

[0051] In some example embodiments, the planarization process may be performed by a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0052] Reference Fig. 9 and Fig.10 , an etching process may be performed using the first etching mask 132 and the second etching mask 134 that respectively expose one or more of the first active fins 112 and the second active fins 114, so that the exposed one or more of the first active fins 112 and the second active fins 114, a portion of the first isolation pattern 120 adjacent thereto, and / or an upper portion of the substrate 100 thereunder may be partially removed to form a second groove 145. The first etching mask 132 and the second etching mask 134 may be removed, and a second isolation pattern 140 may be formed to fill the second groove 145.

[0053] In some example embodiments, the bottom of the second groove 145 may be lower than the bottoms of the first and second active fins 112 and 114 , and thus the first and second active regions 102 and 104 defined by the second groove 145 may be formed on the first and second regions I and II of the substrate 100 , respectively.

[0054] Hereinafter, a lower portion of the substrate 100, that is, a portion of the substrate 100 below the bottoms of the first and second active regions 102 and 104, may be referred to as the substrate 100 so as to be distinguished from the first and second active regions 102 and 104. Therefore, the first and second active regions 102 and 104 may be formed on the substrate 100, and the first and second active fins 112 and 114 may be formed on the first and second active regions 102 and 104, respectively.

[0055] The first etch mask 132 and the second etch mask 134 may extend along the first direction on the first region I and the second region II of the substrate 100, respectively. In some example embodiments, the first etch mask 132 may include a first portion having a first width W1 in the second direction, and a second portion having a second width W2 in the second direction that is smaller than the first width W1. Similarly, the second etch mask 134 may include a first portion having a third width W3 in the second direction, and a second portion having a fourth width W4 in the second direction that is smaller than the third width W3.

[0056] In some example embodiments, a first boundary between the first portion and the second portion of the first etch mask 132 may not be aligned with a second boundary between the first portion and the second portion of the second etch mask 134 in the second direction.

[0057] In some example embodiments, when an etching process using the first etching mask 132 and the second etching mask 134 is performed, the etching gas may not be effectively provided to regions of the first etching mask 132 and the second etching mask 134 where the width in the second direction decreases rapidly, that is, regions adjacent to the first boundary and the second boundary of the first etching mask 132 and the second etching mask 134, respectively, and thus, unlike the first etching mask 132 and the second etching mask 134, the widths of the first active area 102 and the second active area 104 do not change rapidly but change smoothly.

[0058] Therefore, the first active region 102 may further include a third portion between the first portion and the second portion thereof, the width of which is reduced from the first width W1 to the second width W2, and the second active region 104 may further include a third portion between the first portion and the second portion thereof, the width of which is reduced from the third width W3 to the fourth width W4. Hereinafter, the width of the third portion of the second active region 104 may be defined by the fifth width W5.

[0059] When the second groove 145 is formed, some of the first active fins 112 and the second active fins 114 may have an extension length in the first direction, which may be shorter than the extension length of other active fins of the first active fins 112 and the second active fins 114. Hereinafter, one or more first active fins 112 having a shorter extension length may be referred to as a third active fin 116, and one or more second active fins 114 having a shorter extension length may be referred to as a fourth active fin 118. In addition, the first active fins 112 and the third active fins 116 on the first active region 102 may be referred to as a first group of active fins, and the second active fins 114 and the fourth active fins 118 on the second active region 104 may be referred to as a second group of active fins.

[0060] In some example embodiments, one or more first active fins 116 may be spaced apart from each other in the second direction, and / or one or more second active fins 118 may be spaced apart from each other in the second direction. Additionally, one or more first active fins 112 may be spaced apart from each other in the second direction, and / or one or more second active fins 114 may be spaced apart from each other in the second direction.

[0061] As described above, the first active region 102 and the second active region 104 may include a third portion, and portions of the third and fourth active fins 116 and 118 remaining on the third portion may be referred to as fifth and sixth active fins 113 and 115 , respectively.

[0062] The first etch mask 132 and the second etch mask 134 may be removed by, for example, an ashing process and / or a stripping process.

[0063] The second isolation pattern 140 may be formed by forming a second isolation layer on the first to sixth active fins 112, 114, 116, 118, 113 and / or 115, the first isolation pattern 120 and / or the substrate 100 to fill the second groove 145, and planarizing the second isolation layer until the upper surfaces of the first to sixth active fins 112, 114, 116, 118, 113 and / or 115 may be exposed. The second isolation pattern 140 may include an oxide, such as silicon oxide. In some example embodiments, the second isolation pattern 140 may include a material substantially the same as that of the first isolation pattern 120, and thus may be merged with the first isolation pattern 120. The first isolation pattern 120 and the second isolation pattern 140 may be referred to as an isolation structure.

[0064] Reference Fig.11 and Fig.12 , a first diffusion prevention pattern 160 may be formed on the first region I of the substrate 100 through the first active fin 112 , the third active fin 116 , and / or the fifth active fin 113 .

[0065] The first diffusion prevention pattern 160 is formed by the following process: removing the first active fin 112, the third active fin 116 and / or the fifth active fin 113, and / or the first isolation pattern 120 and / or the second isolation pattern 140 adjacent thereto in the second direction by an etching process using the third etching mask 150 including the first opening 153 to form a third groove 165; removing the third etching mask 150; and / or filling the third groove 165.

[0066] In some example embodiments, the first diffusion preventing pattern 160 may extend through a central portion of the first active fin 112 in the first direction, an end portion of the third active fin 116 in the first direction, and / or the fifth active fin 113. The first diffusion preventing pattern 160 may have a bottom that is substantially coplanar with or lower than bottoms of the first active fin 112, the third active fin 116, and the fifth active fin 113, and thus the first active fin 112 extending in the first direction may be separated by the first diffusion preventing pattern 160 in the first direction.

[0067] When forming the first diffusion preventing pattern 160 , the fifth active fin 113 on the third portion of the first active region 102 having a varying width in the second direction may be removed, and thus instability of characteristics (eg, capacitance) of the active fin due to LLE may be reduced or prevented.

[0068] The first diffusion preventing pattern 160 may include an oxide, eg, silicon oxide. In some example embodiments, the first diffusion preventing pattern 160 may include a material substantially the same as that of the first isolation pattern 120 and / or the second isolation pattern 140 so as to be merged therewith.

[0069] Reference Fig.13 and Fig.14 , an insulating pattern 170 may be formed through the sixth active fin 115 on the second region II of the substrate 100 .

[0070] The insulating pattern 170 may be formed by: removing the sixth active fin 115, and / or portions of the first isolation pattern 120 and / or the second isolation pattern 140 adjacent thereto to form a fourth groove 175 by an etching process using a fourth etching mask 155 including the second opening 157; removing the fourth etching mask 155; and filling the fourth groove 175.

[0071] In some example embodiments, the bottom of the insulation pattern 170 may be substantially coplanar with or lower than the bottom of the sixth active fin 115 , and thus the sixth active fin 115 may be removed by the fourth groove 175 .

[0072] If you will later Fig.32 and Fig.33 As shown, when the insulating pattern 170 is formed, the third source / drain layer 265 may not be formed on the sixth active fin 115 , so the electrical short circuit between the third source / drain layer 265 and other adjacent conductive structures may be reduced or prevented.

[0073] The insulating pattern 170 may include an oxide, eg, silicon oxide. In some example embodiments, the insulating pattern 170 may include a material substantially the same as that of the first isolation pattern 120 and / or the second isolation pattern 140 contacting the insulating pattern 170 so as to be merged therewith.

[0074] Reference Fig.15 , upper portions of the first isolation pattern 120 and the second isolation pattern 140 may be removed to expose upper portions of the first to fourth active fins 112 , 114 , 116 , and 118 .

[0075] In some example embodiments, upper portions of the first isolation pattern 120 and / or the second isolation pattern 140 may be removed by an etch-back process, and upper portions of the first diffusion prevention pattern 160 and / or the insulation pattern 170 may also be removed.

[0076] Each of the first to fourth active fins 112, 114, 116, and 118 may include: a lower active pattern whose sidewalls are covered by the first isolation pattern 120, the first diffusion prevention pattern 160, and / or the insulating pattern 170; and / or an upper active pattern protruding upward therefrom in a third direction. In the accompanying drawings, the first active fin 112 including the first lower active pattern 112b and the first upper active pattern 112a, the second active fin 114 including the second lower active pattern 114b and the second upper active pattern 114a, the third active fin 114 including the third lower active pattern 116b and the third upper active pattern 116a, and the fourth active fin 118 including the fourth lower active pattern 118b and the fourth upper active pattern 118a are shown (see FIG. 1 ). Fig.17 ).

[0077] The first impurity region 182 and / or the second impurity region 184 may be formed on the first region I and / or the second region II of the substrate 100 , respectively.

[0078] In some example embodiments, the first impurity region 182 may be formed at a portion of the first active region 102 under the first active fin 112 and / or the third active fin 116, and / or the second impurity region 184 may be formed at a portion of the second active region 104 under the second active fin 114 and / or the fourth active fin 118. The first impurity region 182 and / or the second impurity region 184 may be formed by doping p-type and / or n-type impurities, respectively.

[0079] Reference Figures 16 to 19 , a dummy gate structure 220 may be formed on the substrate 100 .

[0080] The dummy gate structure 220 may be formed by the following operations: sequentially forming a dummy gate insulating layer, a dummy gate electrode layer, and / or a dummy gate mask layer on the first active fin to the fourth active fin 112, 114, 116, and 118, the first isolation pattern 120, and / or the second isolation pattern 140, the first diffusion prevention pattern 160, and / or the insulating pattern 170; etching the dummy gate mask layer using a fifth etching mask (not shown) to form a dummy gate mask 210; and / or sequentially etching the dummy gate electrode layer and the dummy gate insulating layer using the fifth etching mask as an etching mask. Therefore, the dummy gate structure 220 may include a dummy gate insulating pattern 190, a dummy gate electrode 200, and / or a dummy gate mask 210 stacked in sequence.

[0081] The dummy gate insulating layer, the dummy gate electrode layer, and the dummy gate mask layer may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc. The dummy gate insulating layer may include an oxide such as silicon oxide, the dummy gate electrode layer may include, for example, polysilicon, and / or the dummy gate mask layer may include a nitride such as silicon nitride.

[0082] In some example embodiments, the dummy gate structure 220 may extend along the second direction, and a plurality of dummy gate structures 220 may be formed along the first direction.

[0083] Reference Fig.19 and Fig. 20 , the gate spacer 230 may be formed on the sidewalls of the dummy gate structure 220 , and / or the fin spacer 240 may be formed on the sidewalls of the first to fourth active fins 112 , 114 , 116 , and 118 .

[0084] In some example embodiments, the gate spacer 230 and / or the fin spacer 240 may be formed by forming a spacer layer on the dummy gate structure 220, the first to fourth active fins 112, 114, 116, and 118, the first and second isolation patterns 120 and 140, the first diffusion prevention pattern 160, and / or the insulating pattern 170, and anisotropically etching the spacer layer. The spacer layer may include a nitride, such as silicon nitride. Each of the gate spacer 230 and the fin spacer 240 may be referred to as an insulating spacer.

[0085] Upper portions of the first to fourth active fins 112 , 114 , 116 , and 118 adjacent to the dummy gate structure 220 may be etched to form a fifth groove 250 , and first and second source / drain layers 262 and 264 may be formed to fill the fifth groove 250 .

[0086] For example, the first to fourth active fins 112, 114, 116, and 118 may be partially removed by an etching process using the dummy gate structure 220 and the gate spacers 230 on the sidewalls thereof as an etching mask to form the fifth recess 250. The fin spacers 240 may be partially or completely removed during the etching process.

[0087] A selective epitaxial growth (SEG) process may be performed using upper surfaces of the first to fourth active fins 112 , 114 , 116 , and 118 exposed by the fifth groove 250 to form a first source / drain layer 262 and / or a second source / drain layer 264 .

[0088] In some example embodiments, disilane (Si 2 H 6) gas and a silicon source gas such as monomethylsilane (SiH 3 CH 3 ) gas) to perform the SEG process to form a single-crystal silicon carbide layer as the first source / drain layer 262 on the first region I of the substrate 100. Alternatively, only disilane (Si 2 H 6 ) gas is used to perform the SEG process to form a single crystal silicon layer. For example, phosphine (PH 3 ) gas can also be used to form a single-crystal silicon carbide layer doped with n-type impurities and / or a single-crystal silicon layer doped with n-type impurities.

[0089] In some example embodiments, dichlorosilane (SiH 2 Cl 2 ) gas and / or germanium (GeH 4 ) gas to perform the SEG process to form a single crystal silicon germanium layer as the second source / drain layer 264 on the second region II of the substrate 100. For example, diborane (B 2 H 6 ) gas can also be used to form a single crystal silicon germanium layer doped with p-type impurities.

[0090] Each of the first source / drain layer 262 and the second source / drain layer 264 may be grown in both the vertical direction and the horizontal direction, and may not only fill the fifth groove 250 but also contact a portion of the gate spacer 230. Each of the first source / drain layer 262 and the second source / drain layer 264 may have a cross section taken along the second direction, and the shape of the cross section may be a pentagon or a hexagon. When adjacent active fins among the first to fourth active fins 112, 114, 116, and 118 are spaced a short distance apart from each other, adjacent first source / drain layers 262 among the first source / drain layers 262 may merge with each other to form a single layer, and / or adjacent second source / drain layers 264 among the second source / drain layers 264 may merge with each other to form a single layer.

[0091] Reference Figure 21 to Figure 23, a first insulating interlayer 270 may be formed on the first to fourth active fins 112, 114, 116, and 118, the first isolation pattern 120, and / or the second isolation pattern 140, the first diffusion prevention pattern 160, and / or the insulating pattern 170 to cover the dummy gate structure 200, the gate spacer 230, the fin spacer 240, and / or the first source / drain layer 262 and the second source / drain layer 264. The first insulating interlayer 270 may be planarized until the top surface of the dummy gate electrode 200 of the dummy gate structure 200 may be exposed. The dummy gate mask 210 may also be removed, and the upper portion of the gate spacer 230 may also be removed. The space between the merged first source / drain layer 262 and the first isolation pattern 120 and / or the space between the merged second source / drain layer 264 and the first isolation pattern 120 may not be completely filled with the first insulating interlayer 270, and thus, an air gap 275 may be formed (see Fig.28 ). The first insulating interlayer 270 may include an oxide, such as silicon oxide.

[0092] The exposed dummy gate electrode 200 and / or the dummy gate insulating pattern 190 thereunder may be removed to form a third opening exposing the inner sidewalls of the gate spacer 230, the upper surfaces of the first to fourth active fins 112, 114, 116, and 118, the upper surfaces of the first isolation pattern 120 and / or the second isolation pattern 140, the upper surface of the first diffusion prevention pattern 160, and / or the upper surface of the insulating pattern 170. A gate structure 320 may be formed to fill the third opening.

[0093] For example, a thermal oxidation process is performed on the upper surfaces of the first to fourth active fins 112, 114, 116 and 118 exposed by the third opening to form an interface pattern 280, a gate insulation layer and / or a work function control layer can be sequentially formed on the interface pattern 280, the first isolation pattern 120 and the second isolation pattern 140, the first diffusion prevention pattern 160, the insulating pattern 170, the gate spacer 230 and / or the first insulating interlayer 270, and / or a gate electrode layer can be formed on the work function control layer to fully fill the rest of the third opening.

[0094] The gate insulating layer, the work function control layer, and the gate electrode layer may be formed by a CVD process or an ALD process. The interface pattern 280 may also be formed by a CVD process or an ALD process instead of a thermal oxidation process, and in this case, the interface pattern 280 may be formed not only on the upper surfaces of the first to fourth active fins 112, 114, 116, and 118, but also on the upper surfaces of the first isolation pattern 120 and / or the second isolation pattern 140, the upper surface of the first diffusion prevention pattern 160, the upper surface of the insulation pattern 170, and / or the inner sidewall of the gate spacer 230.

[0095] The gate electrode layer, the work function control layer and / or the gate insulating layer may be planarized until the upper surface of the first insulating interlayer 270 may be exposed to form a gate insulating pattern 290 and a work function control pattern 300 and a gate electrode 310, which are sequentially stacked on the upper surface of the interface pattern 280, the upper surface of the first isolation pattern 120 and / or the second isolation pattern 140, the upper surface of the first diffusion prevention pattern 160, the upper surface of the insulating pattern 170 and / or the inner sidewall of the gate spacer 230, and the gate electrode 310 fills the rest of the third opening on the work function control pattern 300. Therefore, the bottom and / or sidewall of the gate electrode 310 may be covered by the work function control pattern 300.

[0096] The interface pattern 280, the gate insulation pattern 290, the work function control pattern 300 and / or the gate electrode 310 stacked in sequence can form a gate structure 320, and the gate structure 320 and / or the first source / drain layer 262 and / or the second source / drain layer 264 can form NMOS and / or PMOS transistors on the first region I and / or the second region II of the substrate 100, respectively.

[0097] The interface pattern 280 may include an oxide such as silicon oxide, the gate insulation pattern 290 may include a metal oxide such as hafnium oxide, tantalum oxide, zirconium oxide, etc., the work function control pattern 300 may include a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, etc., and / or the gate electrode 310 may include a metal with low resistance such as aluminum, copper, titanium, tantalum, etc., a metal nitride and / or a metal alloy.

[0098] Reference Fig.24 , an upper portion of the gate structure 320 may be removed to form a sixth groove, and a capping pattern 330 may be formed to fill the sixth groove.

[0099] The capping pattern 330 may include nitride, for example, silicon nitride.

[0100] Reference Fig.25 and Fig.26 A sixth etching mask 340 including a fourth opening 345 can be formed on the covering pattern 330, the gate spacer 230 and / or the first insulating interlayer 270, and an etching process can be performed using the sixth etching mask until the upper surface of the substrate 100 can be exposed, so that the covering pattern 330, the gate structure 320, the gate spacer 230, the first active fin to the fourth active fin 112, 114, 116 and 118, the first active region 102 and / or the second active region 104, the first diffusion prevention pattern 160, the insulating pattern 170 and / or the first isolation pattern 120 and / or the second isolation pattern 140 can be etched to form a seventh groove 347.

[0101] After removing the sixth etch mask 340 , a second diffusion prevention pattern 350 may be formed to fill the seventh groove 347 .

[0102] In some example embodiments, the second diffusion preventing pattern 350 may be formed by removing a portion of the gate spacer 230 on one of the gate structures 320 and / or its sidewalls, and thus the second diffusion preventing pattern 350 may extend on the first region I and / or the second region II of the substrate 100 in the third direction. Fig.25 and Fig.26 It is shown that the second diffusion prevention pattern 350 is formed by removing one of the gate structures 320 at the edge of each cell adjacent in the first direction.

[0103] In addition, the second diffusion preventing patterns 350 may extend in the third direction through the first active region 102 and / or the second active region 104 and / or the first to fourth active fins 112, 114, 116, and 118. For example, one of the second diffusion preventing patterns 350 adjacent in the first direction may extend through a central portion of the second active fin 114 in the first direction so as to divide the second active fin 114 in the first direction, may extend through and contact an end portion of the fourth active fin 118 in the first direction, and may extend through the first diffusion preventing pattern 160 and the insulating pattern 170 to contact a sidewall of the first diffusion preventing pattern 160 and a sidewall of the insulating pattern 170. Another one of the second diffusion preventing patterns 350 may extend through a central portion of each of the second active fin 114 and / or the fourth active fin 118 in the first direction so as to divide each of the second active fin 114 and / or the fourth active fin 118 in the first direction, and / or may extend through the first diffusion preventing pattern 160 to contact another sidewall of the first diffusion preventing pattern 160.

[0104] When forming the second diffusion preventing pattern 350 , a portion of the sixth active fin 115 on the third portion of the second active region 104 having a varying width in the second direction may be removed, and thus instability of characteristics (eg, capacitance) of the active fin due to LLE may be reduced or prevented.

[0105] The second diffusion prevention pattern 350 can be formed by removing not only a portion of the gate structure 320 on the second region II of the substrate 100 but also a portion of the gate structure 320 on the first region I of the substrate 100, and thus leakage current due to the gate structure 320 can be reduced or prevented, which can be formed on the first diffusion prevention pattern 160 to serve only as a dummy gate structure.

[0106] The second diffusion preventing pattern 350 may include nitride, for example, silicon nitride.

[0107] Reference Figures 27 to 31 , a second insulating interlayer 360 may be formed on the first insulating interlayer 270 and / or the second diffusion prevention pattern 350, a fifth opening and / or a sixth opening may be formed through the first insulating interlayer 270 and / or the second insulating interlayer 360 to expose the upper surface of the first source / drain layer 262 and / or the second source / drain layer 264, and a first metal silicide pattern 372 and a second metal silicide pattern 374 may be respectively formed on the exposed upper surface of the first source / drain layer 262 and / or the second source / drain layer 264. The second insulating interlayer 360 may include an oxide, such as silicon oxide.

[0108] The first metal silicide pattern 372 and the second metal silicide pattern 374 may be formed by the following operations: forming a metal layer on the bottom and sidewall of the fifth opening and / or the sixth opening and / or the upper surface of the second insulating interlayer 360, heat-treating the metal layer so that the metal layer and the exposed first source / drain layer 262 and the second source / drain layer 264 may react with each other, and / or removing the unreacted portion of the metal layer. The metal layer may include, for example, cobalt, nickel, titanium, etc., so the first metal silicide pattern 372 and the second metal silicide pattern 374 may include, for example, cobalt silicide, nickel silicide, titanium silicide, etc.

[0109] A seventh opening may be formed through the second insulating interlayer 360 and / or the capping pattern 330 to expose an upper surface of the gate structure 320 , and / or first to third contact plugs 382 , 384 , and 390 may be formed to fill the fifth to seventh openings, respectively.

[0110] Each of the first to third contact plugs 382, ​​384, and 390 may include a conductive pattern (not shown) and a barrier pattern (not shown) covering a bottom and / or sidewall of the conductive pattern. For example, the conductive pattern may include a metal, and / or the barrier pattern may include a metal nitride.

[0111] A via (not shown) and / or an upper wiring (not shown) may also be formed to connect to the first to third contact plugs 382 , 384 , and 390 , thereby completing the manufacture of the semiconductor device.

[0112] In the semiconductor device manufactured by the above process, the first diffusion preventing pattern 160 may be formed at a region where the first active region 102 can have a varying width on the first region I of the substrate 100, and the second diffusion preventing pattern 350 and the insulating pattern 170 may be formed at a region where the second active region 104 can have a varying width on the second region II of the substrate 100. Therefore, instability of characteristics (e.g., capacitance) of the active fin due to LLE may be reduced or prevented.

[0113] For example, the sixth active fin 115 remaining on the area where the second active region 104 may have a varying width may be removed and replaced by the insulating pattern 170 , thereby reducing or preventing the occurrence of an electrical short with an adjacent conductive structure.

[0114] The second diffusion preventing pattern 350 may extend not only in the first region I of the substrate 100 but also in the second region II of the substrate 100 , and thus leakage current due to the dummy gate structure may be reduced or prevented.

[0115] The semiconductor device may include the following structural features.

[0116] The semiconductor device may include: a first group of active fins including a first active fin 112 and / or a third active fin 116 on a first region I of a substrate 100, the substrate 100 including the first region I and / or the second region II; and / or a first diffusion prevention pattern 160 extending through the first group of active fins in a second direction. The first diffusion prevention pattern 160 may extend through a central portion of the first active fin 112 in the first direction to divide the first active fin 112, and / or may extend through an end portion of the third active fin 116 in the first direction.

[0117] The semiconductor device may include: a second group of active fins including a second active fin 114 and / or a fourth active fin 118 on the second region II of the substrate 100; and / or a second diffusion preventing pattern 350 extending through the second group of active fins in the second direction. The second diffusion preventing pattern 350 may extend through a central portion of the second active fin 114 in the first direction to divide the second active fin 114, and / or may extend through and contact an end portion of the fourth active fin 118 in the first direction.

[0118] In some example embodiments, the second diffusion preventing pattern 350 may extend from the first region I to the second region II of the substrate 100 in the second direction to contact a sidewall of the first diffusion preventing pattern 160 .

[0119] In some example embodiments, two second diffusion preventing patterns 350 may be spaced apart from each other in the first direction. One of the second diffusion preventing patterns 350 may extend through a central portion of the second active fin 114 in the first direction to divide the second active fin 114, and / or may extend through and / or contact an end portion of the fourth active fin 118 in the first direction on the second region II of the substrate 100. In addition, one of the second diffusion preventing patterns 350 may contact a sidewall of the first diffusion preventing pattern 160 on the first region I of the substrate 100. Another of the second diffusion preventing patterns 350 may extend through a central portion of each of the second active fin 114 and the fourth active fin 118 in the first direction to divide each of the second active fin 114 and the fourth active fin 118 on the second region II of the substrate 100. In addition, another one of the second diffusion preventing patterns 350 may extend through a central portion of the first active fin 112 in the first direction to divide the first active fin 112, and / or may extend through an end portion of the third active fin 116 in the first direction to contact another sidewall of the first diffusion preventing pattern 160 on the first region I of the substrate 100.

[0120] In some example embodiments, the second group of active fins may include a plurality of fourth active fins 118 spaced apart from each other in the second direction. An insulating pattern 170 may be formed at opposite sides of fourth active fins 118 adjacent to the second active fins 114 with respect to the second diffusion preventing pattern 350 .

[0121] In some example embodiments, the second active region 104 on the second region II of the substrate 100 may protrude upward from the substrate 100 to extend in the first direction, and / or may include a first portion having a third width W3, a second portion having a fourth width W4 smaller than the third width W3, and / or a third portion between the first portion and the second portion, the third portion having a fifth width W5 smaller than the third width W3 but larger than the fourth width W4.

[0122] The second active fin 114 may extend to a first length along the first direction on the first to third portions of the second active region 104, and / or the fourth active fin 118 may be spaced apart from the second active fin 114 along the second direction on the first portion of the second active region 104, and / or may extend to a second length less than the first length along the first direction. In some example embodiments, a distance from a sidewall of the third portion of the second active region 104 to the second active fin 114 may be greater than a distance from a sidewall of each of the first and second portions of the second active region 104 to the second active fin 114.

[0123] In some example embodiments, the insulating pattern 170 may be formed on the third portion of the second active region 104 to be spaced apart from the second active fin 114 in the second direction.

[0124] Fig.32 and Fig.33 1 is a plan view and a cross-sectional view showing a semiconductor device according to a first comparative embodiment. In particular, Fig.32 is a plan view, and Fig.33 is along Fig.32 Cross-sectional view of line BB′.

[0125] In addition to the insulating pattern, the semiconductor device can be Figures 27 to 31 Therefore, the same reference numerals denote the same elements, and a detailed description thereof is omitted here.

[0126] Reference Fig.32 and Fig.33 The semiconductor device may not include the insulating pattern 170 , and thus the sixth active fin 115 including the sixth lower active pattern 115 b and the sixth upper active pattern 115 a located on the third portion of the second active region 104 where the width varies may not be removed.

[0127] Therefore, the third source / drain layer 265 may be formed on the sixth active fin 115 , which may be connected to the second source / drain layer 264 , and thus an electrical short circuit with the second contact plug 384 on the second source / drain layer 264 may occur.

[0128] Fig.34 is a plan view showing a semiconductor device according to a second comparative example.

[0129] In addition to the location of the third portion of the second active region 104, the semiconductor device may be Figures 27 to 31 The semiconductor devices are substantially the same or similar.

[0130] Reference Fig.34 , a third portion of the second active region 104 may be formed between the second diffusion prevention patterns 350 .

[0131] Therefore, the extension lengths of the fourth active fins 118 along the first direction on the second active region 104 may not be the same but different from each other, and the characteristics (eg, capacitance) of the fourth active fins 118 may be unstable.

[0132] Fig.35 and Fig.36 are a plan view and a cross-sectional view showing a semiconductor device according to a third comparative example.

[0133] Except for the position of the second diffusion preventing pattern 350, the semiconductor device can be Figures 27 to 31 The semiconductor devices are substantially the same or similar.

[0134] Reference Fig.35 and Fig.36 , the second diffusion prevention pattern 350 may be formed on the second region II of the substrate 100 instead of being formed on the first region I of the substrate 100 .

[0135] Therefore, the gate structure 320 , a portion of which is converted into the second diffusion prevention pattern 350 , may serve as a dummy gate structure, and leakage current may be generated through the dummy gate structure.

[0136] The semiconductor device described above can be applied to various types of memory devices including diffusion prevention patterns. For example, the semiconductor device can be applied to logic devices such as a central processing unit (CPU), a main processing unit (MPU), and / or an application processor (AP). In addition, the semiconductor device can be applied to a wiring structure of a volatile memory device such as a DRAM device and / or an SRAM device, and / or a non-volatile memory device such as a flash memory device, a PRAM device, an MRAM device, a ReRAM device, etc.

[0137] The foregoing is illustrative of the inventive concept and should not be construed as limiting it. Although some example embodiments have been described, it will be readily appreciated by those skilled in the art that various modifications may be made in the example embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, means-plus-function clauses are intended to include structures described herein when performing the functions described, and include not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments and other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: A first group of active fins, spaced apart from each other in a second direction on a first region of a substrate, each active fin in the first group of active fins extending along a first direction, the first direction and the second direction being different from each other, and the substrate comprising the first region and the second region; as well as A first diffusion prevention pattern extends through the first group of active fins along the second direction on the first region of the substrate, wherein: The first group of active fins includes a first active fin and a second active fin, The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin into a first portion and a second portion, and extends through and contacts an end portion of the second active fin in the first direction, and The first portion of the first active fin, the first diffusion prevention pattern, and the second portion of the first active fin are connected to each other to be continuous in the first direction.

2. The semiconductor device according to claim 1, wherein The first group of active fins includes a plurality of second active fins spaced apart from each other in the second direction, and The first diffusion prevention pattern extends through and contacts an end portion of each of the plurality of second active fins in the first direction.

3. The semiconductor device according to claim 2, further comprising: An insulating pattern is located at an opposite side of a second active fin adjacent to the first active fin among the plurality of second active fins with respect to the first diffusion preventing pattern.

4. The semiconductor device according to claim 1, further comprising: A second diffusion prevention pattern extends through a central portion of the first active fin to divide the first active fin, and extends through a central portion of the second active fin to divide the second active fin.

5. The semiconductor device according to claim 1, further comprising: a second group of active fins, on the second region of the substrate, spaced apart from each other in the second direction and extending along the first direction; as well as a second diffusion prevention pattern extending through the second group of active fins along the second direction on the second region of the substrate, wherein the second group of active fins includes a third active fin and a fourth active fin, and The second diffusion prevention pattern extends through a central portion of the third active fin in the first direction, and extends through an end portion of the fourth active fin in the first direction.

6. The semiconductor device according to claim 5, wherein: The first diffusion preventing pattern extends to the second region of the substrate along the second direction so as to be in contact with a sidewall of the second diffusion preventing pattern.

7. The semiconductor device according to claim 6, further comprising a third diffusion prevention pattern, wherein The third diffusion preventing pattern is spaced apart from the first diffusion preventing pattern in the first direction, and The third diffusion preventing pattern: On the first region of the substrate, extending through a central portion of the first active fin to divide the first active fin, and extending through a central portion of the second active fin to divide the second active fin, and On the second region of the substrate, extending through a central portion of the third active fin in the first direction to divide the third active fin, and extending through an end portion of the fourth active fin to contact another sidewall of the second diffusion preventing pattern.

8. The semiconductor device according to claim 5, wherein: A bottom of the first diffusion preventing pattern is closer to the substrate than a bottom of the second diffusion preventing pattern in a third direction, and the third direction is substantially perpendicular to a surface of the substrate.

9. The semiconductor device according to claim 5, wherein: The first diffusion preventing pattern includes nitride, and the second diffusion preventing pattern includes oxide.

10. The semiconductor device according to claim 5, further comprising: gate structures, spaced apart from each other in the first direction, extending along the second direction on the first group of active fins and the second group of active fins; as well as a source / drain layer on portions of the first set of active fins and the second set of active fins adjacent to the gate structure, Wherein, the first diffusion prevention pattern is located between the gate structures.

11. The semiconductor device according to claim 1, wherein The first region of the substrate is an NMOS region, and the second region of the substrate is a PMOS region, and The first region and the second region are arranged in the second direction.

12. A semiconductor device comprising: an active region extending along a first direction on a substrate and comprising a first portion, a second portion, and a third portion, the first portion having a first width in a second direction substantially perpendicular to the first direction, the second portion having a second width in the second direction that is smaller than the first width, and the third portion being located between the first portion and the second portion and having a third width in the second direction that is smaller than the first width and larger than the second width; a first active fin extending along the first direction to a first length on the first portion to the third portion of the active region; a second active fin extending along the first direction to a second length smaller than the first length on the first portion of the active region, and a first diffusion prevention pattern on the substrate extending through the first active fin and the second active fin along the second direction, wherein the first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin into a first portion and a second portion, and extends through and contacts an end portion of the second active fin in the first direction, The first portion of the first active fin, the first diffusion prevention pattern, and the second portion of the first active fin are connected to each other to be continuous in the first direction, and Wherein, a distance from a sidewall of the third portion of the active region to the first active fin in the second direction is greater than a distance from a sidewall of each of the first portion and the second portion of the active region to the first active fin in the second direction.

13. The semiconductor device according to claim 12, further comprising: An insulating pattern is provided on the third portion of the active region, the insulating pattern being spaced apart from the first active fin.

14. The semiconductor device according to claim 12, further comprising: A plurality of third active fins are formed on the active region and are substantially similar to the second active fins.

15. The semiconductor device according to claim 12, wherein: A bottom of the first diffusion preventing pattern is closer to the substrate than a bottom of the active region in a third direction, and the third direction is substantially perpendicular to a surface of the substrate.

16. The semiconductor device according to claim 12, further comprising: a second diffusion preventing pattern spaced apart from the first diffusion preventing pattern in the first direction, The second diffusion prevention pattern extends through a central portion of the first active fin to divide the first active fin, and extends through a central portion of the second active fin to divide the second active fin.

17. A semiconductor device comprising: A first group of active fins, spaced apart from each other in a second direction on a first region of a substrate, each of the first group of active fins extending along a first direction, the first direction and the second direction being different from each other, and the substrate comprising a first region and a second region, the first group of active fins comprising a first active fin and a second active fin; a first diffusion prevention pattern extending through a central portion of the first active fin along the second direction on the first region of the substrate to divide the first active fin in the first direction, and extending through an end portion of the second active fin in the first direction; as well as a second diffusion preventing pattern extending along the second direction on the first region of the substrate, the second diffusion preventing pattern contacting a sidewall of the first diffusion preventing pattern, wherein: A bottom of the second diffusion preventing pattern is closer to the substrate in a third direction than a bottom of the first diffusion preventing pattern, and A top surface of the second diffusion preventing pattern is farther from the substrate than a top surface of the first diffusion preventing pattern in the third direction, and the third direction is substantially perpendicular to a surface of the substrate.

18. The semiconductor device according to claim 17, further comprising: a third diffusion preventing pattern substantially similar to the second diffusion preventing pattern and spaced apart from the second diffusion preventing pattern, wherein one of the second diffusion preventing pattern and the third diffusion preventing pattern contacts a sidewall of the first diffusion preventing pattern, and The other of the second diffusion preventing pattern and the third diffusion preventing pattern extends through and contacts an end portion of the second active fin and contacts another sidewall of the first diffusion preventing pattern.

19. The semiconductor device according to claim 17, further comprising: a second group of active fins, comprising a third active fin and a fourth active fin, the third active fin and the fourth active fin being spaced apart from each other along the second direction on the second region of the substrate, each of the third active fin and the fourth active fin extending along the first direction, wherein the first region and the second region are arranged in the second direction, and The second diffusion preventing pattern extends to the second region of the substrate, extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through an end portion of the second active fin in the first direction.

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