Method for manufacturing a semiconductor device having a buried gate electrode

Abstract

A method for manufacturing a semiconductor device with a buried gate electrode is disclosed, comprising: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches intersecting the plurality of active regions and extending parallel to each other along a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0010063, filed on January 25, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a buried gate electrode. Background Art

[0004] With the rapid development of the electronics industry and the needs of users, electronic devices are becoming smaller and lighter. Therefore, due to the need for highly integrated semiconductor devices used in electronic devices, the design rules of the components of semiconductor devices are reduced. In order to manufacture highly scaled semiconductor devices, buried gate electrodes buried in semiconductor substrates have been introduced as gate electrodes. Summary of the invention

[0005] The inventive concept provides a semiconductor device, and a method of manufacturing the semiconductor device having a buried gate and exhibiting improved reliability and performance.

[0006] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a plurality of gate trenches in a substrate, the substrate having a plurality of active areas defined by a device isolation film, the plurality of gate trenches intersecting the plurality of active areas and extending in a first horizontal direction to be parallel to each other; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film, the thickness of the second gate insulating layer being less than the thickness of the first gate insulating layer; forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer; and forming a plurality of buried gate electrodes, wherein the plurality of gate insulating layers respectively cover side surfaces and bottom surfaces of lower portions of the plurality of gate trenches, and wherein the plurality of buried gate electrodes are respectively arranged on the plurality of gate insulating layers to fill lower portions of the plurality of gate trenches.

[0007] According to another aspect of the inventive concept, a method for manufacturing a semiconductor device is provided, the method comprising: forming a plurality of gate trenches in a substrate, the substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches intersecting the plurality of active regions and extending in a first horizontal direction to be parallel to each other; forming a first gate insulating layer on an exposed surface of the substrate by a first oxidation process; forming a second gate insulating layer by a second oxidation process, the second gate insulating layer conformally covering the first gate insulating layer and the device isolation film; and forming a plurality of buried gate electrodes to fill lower portions of the plurality of gate trenches, respectively, wherein the first oxidation process comprises forming a first gate insulating layer on an exposed surface of the substrate by a first oxidation process; forming a second gate insulating layer on an exposed surface of the substrate by a second oxidation process, the second gate insulating layer conformally covering the first gate insulating layer and the device isolation film; and forming a plurality of buried gate electrodes to fill lower portions of the plurality of gate trenches, respectively. 2 +H 2 An in-situ steam generation (ISSG) oxidation process is performed in the gas, and the second oxidation process includes a deposition process.

[0008] According to another aspect of the inventive concept, a method for manufacturing a semiconductor device is provided, the method comprising: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches intersecting the plurality of active regions and extending in a first horizontal direction to be parallel to each other; forming a plurality of gate insulation layers, each gate insulation layer comprising a portion of a first gate insulation layer and a portion of a second gate insulation layer, the first gate insulation layer being selectively formed on an exposed surface of the substrate, and the second gate insulation layer being formed on exposed surfaces of both the first gate insulation layer and the device isolation film and having a thickness smaller than that of the first gate insulation layer; and forming a plurality of buried gate electrodes, the plurality of buried gate electrodes extending in parallel to each other in the first horizontal direction and respectively filling lower portions of the plurality of gate trenches having the plurality of gate insulation layers therebetween, wherein a portion of each of the plurality of buried gate electrodes has a maximum width in a second direction intersecting the first direction, and the device isolation film is arranged on two opposite sides of the portion; and a portion of each of the plurality of buried gate electrodes has a minimum width in the second direction, and a cross section of each of the plurality of active regions intersected by the plurality of gate trenches is arranged on two opposite sides of the portion, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 , Figure 2 , FIG. 3A to FIG. 3D , Figure 4 , FIG. 5A to FIG. 5C , Figure 6 , 7A to 7C , Figure 8 , 9A to 9C , Fig.10 , FIG. 11A to FIG. 11C and FIG. 12A to FIG. 12Bare diagrams showing sequential processes of a method of manufacturing a semiconductor device according to example embodiments, respectively;

[0011] Fig.13 , Fig.14 and Fig.15 are flowcharts each illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0012] Fig.16 is a graph illustrating a first process of a method of manufacturing a semiconductor device according to example embodiments;

[0013] Fig.17 is a graph illustrating a third process of the method of manufacturing a semiconductor device according to example embodiments; and

[0014] Fig.18 is a schematic plan layout illustrating main components of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0015] Figures 1 to 12B are diagrams illustrating sequential processes of a method of fabricating a semiconductor device according to example embodiments.

[0016] Figure 1 is a plan view illustrating a process of forming an active region in a semiconductor substrate according to example embodiments.

[0017] Reference Figure 1 , a device isolation film 116 is formed in the substrate 110, and a plurality of active regions 118 are defined by the device isolation film 116. Each of the plurality of active regions 118 may have a relatively long island shape having a short axis and a long axis. For example, each of the plurality of active regions 118 may have a short axis and a long axis in an inclined direction relative to the first horizontal axis (X direction) and the second horizontal axis (Y direction).

[0018] For example, the substrate 110 may include silicon (Si), for example, crystalline Si, polycrystalline Si, or amorphous Si. Alternatively, the substrate 110 may include a semiconductor element, for example, germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Alternatively, the substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the substrate 110 may include a buried oxide (BOX) layer. The substrate 110 may include a conductive region, for example, a doped well or a doped structure.

[0019] The device isolation film 116 may include: a material including at least one selected from the following group, the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The device isolation film 116 may include: a single layer including an insulating film, a double layer including two insulating films, or a multilayer including a combination of at least three insulating films. For example, the device isolation film 116 may include two insulating films different from each other. For example, the device isolation film 116 may include a silicon oxide film and a silicon nitride film. For example, the device isolation film 116 may include three layers, including a silicon oxide film, a silicon nitride film, and a silicon oxide film.

[0020] Figure 2 is a plan view illustrating a process of forming a gate trench according to example embodiments, and FIG. 3A to FIG. 3D Along Figure 2 Cross-sectional views taken along lines AA', BB', CC' and DD'.

[0021] Reference Figures 2 to 3D , a plurality of gate trenches 120T are formed in the substrate 110. The plurality of gate trenches 120T may respectively have linear shapes extending parallel to each other across the plurality of active regions 118. A portion of each of the plurality of active regions 118 may be exposed at a side surface of each gate trench 120T intersecting the plurality of active regions 118. The exposed surface of each active region 118 intersecting each gate trench 120T may be referred to as a cross section of the active region 118.

[0022] For example, the plurality of gate trenches 120T may extend in the first horizontal direction (X direction) and may be arranged at substantially equal intervals in the second horizontal direction (Y direction). In some embodiments, each of the plurality of gate trenches 120T may have the same width in the second horizontal direction (Y direction).

[0023] Terms such as "same", "equal", "planar" or "coplanar" used herein when referring to orientation, layout, position, shape, size, amount or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, amount or other measurement, but are intended to include nearly the same orientation, layout, position, shape, size, amount or other measurement, such as within acceptable variations that may occur due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, terms described as "substantially the same", "substantially equal" or "substantially planar" may be exactly the same, equal or planar, or may be the same, equal or planar within acceptable variations that may occur, such as due to manufacturing processes.

[0024] In some embodiments, a pair of gate trenches 120T adjacent to each other may cross one active region 118. In some other embodiments, long-axis ends of at least some of the plurality of active regions 118 may be exposed at the side surface of each of the plurality of gate trenches 120T, but are not limited thereto, and long-axis ends of any one or at least some of the plurality of active regions 118 may not be exposed at the side surface of each of the plurality of gate trenches 120T.

[0025] In some embodiments, the device isolation film 116 and the substrate 110 may be etched separately by separate etching processes so that a step is formed at the bottom surface of each of the plurality of gate trenches 120T, whereby the etching depth of the device isolation film 116 may be different from the etching depth of the substrate 110. For example, the bottom surface of each of the plurality of gate trenches 120T may be lower in the device isolation film 116 than in the substrate 110.

[0026] In some embodiments, the device isolation film 116 may include a first device isolation film 116A and a second device isolation film 116B. The first device isolation film 116A and the second device isolation film 116B may include materials different from each other, respectively. For example, the first device isolation film 116A may include an oxide film, and the second device isolation film 116B may include a nitride film. However, according to the inventive concept, the configuration of the device isolation film 116 is not limited to the above description.

[0027] Figure 4 is a plan view illustrating a process of forming a first gate insulating layer according to example embodiments, and FIG. 5A to FIG. 5C Along Figure 4 Cross-sectional views taken along lines AA', BB' and CC'. Figure 6 is along Figure 5C The reference level LV-R shown is a cross-sectional view taken in a direction parallel to the main surface of the substrate 110, and the reference level LV-R refers to FIG. 11A to FIG. 12B The buried gate electrode 120 is shown corresponding to the level. Figure 6 Only the shape at the reference level LV-R may be shown, and shapes at levels other than the reference level LV-R, for example, a shape at the level of the bottom surface of the gate trench 120T may not be shown.

[0028] As used herein, the term “horizontal” refers to a height in a vertical direction (Z direction) from a main surface of the substrate 110 .

[0029] Reference Figures 4 to 6, a first gate insulating layer 122a is formed on the active region 118. For example, the first gate insulating layer 116 may include at least one selected from the following group, the group consisting of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO), or a high-k dielectric film having a higher dielectric constant than the silicon oxide film.

[0030] The first gate insulating layer 122a may be formed by a first process. The first gate insulating layer 122a may be selectively grown on an exposed surface of the substrate 110 including the active region 118. For example, the first process may include a thermal oxidation process. The first process may also be referred to as a first oxidation process. In some embodiments, the first oxidation process may include an in-situ steam generation (ISSG) oxidation process performed in a gas of O2+H2.

[0031] Although the first gate insulating layer 122 a is conformally formed overall, the thickness of the first gate insulating layer 122 a on the side surface of the gate trench 120T may be different from the thickness of the first gate insulating layer 122 a on the bottom surface of the gate trench 120T.

[0032] For example, when the first gate insulating layer 122a is formed by the ISSG oxidation process, the first gate insulating layer 122a can be formed at a substantially equal growth rate on both the side surface and the bottom surface of the gate trench 120T in an initial stage, and the thickness of the first gate insulating layer 122a on the substrate 110 is relatively low in the initial stage, and as the thickness of the first gate insulating layer 122a on the substrate 110 increases, the growth rate of the first gate insulating layer 122a on the side surface of the gate trench 120T can be greater than the growth rate of the first gate insulating layer 122a on the bottom surface of the gate trench 120T.

[0033] In this case, a first thickness T1 of a portion of the first gate insulating layer 122a formed on the side surface of the gate trench 120T may be greater than a second thickness T2 of a portion of the first gate insulating layer 122a formed on the bottom surface of the gate trench 120T. Therefore, the step coverage of the first gate insulating layer 122a, which represents a ratio of the thickness of the portion of the first gate insulating layer 122a on the bottom surface of the gate trench 120T relative to the thickness of the portion of the first gate insulating layer 122a on the side surface of the gate trench 120T, may be deteriorated as the thickness of the first gate insulating layer 122a increases.

[0034] In some embodiments, the first thickness T1 of the first gate insulating layer 122a may be approximately equal to or less than 1.5 times its second thickness T2 (e.g., T1≤1.5*T2). For example, when the width of the gate trench 120T in the second horizontal direction (Y direction) is tens of nanometers, the first thickness T1 of the first gate insulating layer 122a may be in the range of about 45 angstroms to about 75 angstroms, and the second thickness T2 of the first gate insulating layer 122a may be in the range of about 30 angstroms to about 50 angstroms.

[0035] Since the first gate insulating layer 122a can be selectively formed on the substrate 110 including the active area 118, a portion of the gate trench 120T can have a width reduced by the first gate insulating layer 122a, and the portion has a side surface where the active area 118 is exposed, that is, a side surface where a cross section of the active area 118 is exposed.

[0036] FIG. 7A to FIG. 8 is a cross-sectional view illustrating a process of forming a second gate insulating layer according to an example embodiment, and particularly, 7A to 7C Along the Figure 8 A cross-sectional view taken along lines AA', BB' and CC', and Figure 8 It is along 7A to 7C The reference level LV-R shown is a cross-sectional view taken in a direction parallel to the main surface of the substrate 110 . Figure 8 Only the shape at the reference level LV-R may be shown, and shapes at levels other than the reference level LV-R, for example, a shape at the level of the bottom surface of the gate trench 120T may not be shown.

[0037] Reference FIG. 7A to FIG. 8 , a second gate insulating layer 122b is formed on the exposed surfaces of both the first gate insulating layer 122a and the device isolation film 116. The second gate insulating layer 122b may include at least one selected from the following group, the group consisting of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, ONO, or a high-k dielectric film having a higher dielectric constant than the silicon oxide film. In some embodiments, the first gate insulating layer 122a may include the same material as that of the second gate insulating layer 122b. In some other embodiments, the first gate insulating layer 122a and the second gate insulating layer 122b may respectively include materials different from each other.

[0038] For example, the second gate insulating layer 122b may have a dielectric constant of about 10 to about 25. In some embodiments, the second gate insulating layer 122b may include at least one selected from the group consisting of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the second gate insulating layer 122b may include HfO 2 、Al 2 O 3 、HfAlO 3 、 2 O 3 or TiO 2 .

[0039] The second gate insulating layer 122b may be conformally formed such that the thickness of the second gate insulating layer 122b on the side surface of the gate trench 120T is substantially equal to the thickness of the second gate insulating layer 122b on the bottom surface of the gate trench 120T. In addition, the second gate insulating layer 122b may also be formed such that the thickness of the second gate insulating layer 122b on the first gate insulating layer 122a is substantially equal to the thickness of the second gate insulating layer 122b on the device isolation film 116. The thickness of the second gate insulating layer 122b may be less than the thickness of the first gate insulating layer 122a.

[0040] The second gate insulating layer 122b may cover the first gate insulating layer 122a and the device isolation film 116. The second gate insulating layer 122b may be formed by a second process. The second process may include a CMP process. The second process may also be referred to as a second oxidation process. For example, the second process may include an atomic layer deposition (ALD) process.

[0041] The first gate insulating layer 122a and the second gate insulating layer 122b together may constitute a gate insulating structure 122P. In some embodiments, when the first gate insulating layer 122a includes the same material as the material of the second gate insulating layer 122b, the interface between the first gate insulating layer 122a and the second gate insulating layer 122b may not be observed, and the gate insulating structure 122P may be observed as a single layer. In some other embodiments, when the first gate insulating layer 122a and the second gate insulating layer 122b include materials different from each other, the interface between the first gate insulating layer 122a and the second gate insulating layer 122b may be observed.

[0042] The thickness of the portion of the gate insulating structure 122P formed on the substrate 110 may be different from the thickness of the portion of the gate insulating structure 122P formed on the device isolation film 116. For example, the thickness of the portion of the gate insulating structure 122P formed on the substrate 110 may be greater than the thickness of the portion of the gate insulating structure 122P formed on the device isolation film 116.

[0043] The third thickness T3 of the gate insulating structure 122P formed on the substrate 110 at a portion corresponding to the side surface of the gate trench 120T may be different from the fourth thickness T4 of the gate insulating structure 122P formed on the substrate 110 at a portion corresponding to the bottom surface of the gate trench 120T. For example, the third thickness T3 of the gate insulating structure 122P formed on the substrate 110 at a portion corresponding to the side surface of the gate trench 120T may be greater than the fourth thickness T4 of the gate insulating structure 122P formed on the substrate 110 at a portion corresponding to the bottom surface of the gate trench 120T.

[0044] The gate insulating structure 122P may include a first gate insulating layer 122a and a second gate insulating layer 122b on the first gate insulating layer 122a. The first gate insulating layer 122a may be selectively formed only on the substrate 110, and the second gate insulating layer 122b may be formed on both the first gate insulating layer 122a and the device isolation film 116.

[0045] The portion of the gate insulating structure 122P formed on the substrate 110 may include a stacked structure of a first gate insulating layer 122a and a second gate insulating layer 122b, and the portion of the gate insulating structure 122P formed on the device isolation film 116 may include a single structure of the second gate insulating layer 122b.

[0046] The fifth thickness T5 of the gate insulating structure 122P formed on the device isolation film 116 corresponding to the side surface of the gate trench 120T may be substantially equal to the sixth thickness T6 of the gate insulating structure 122P formed on the device isolation film 116 corresponding to the bottom surface of the gate trench 120T. Therefore, the fifth thickness T5 of the gate insulating structure 122P may be the thickness of the portion of the second gate insulating layer 122b formed on the device isolation film 116 corresponding to the side surface of the gate trench 120T, and the sixth thickness T6 of the gate insulating structure 122P may be the thickness of the portion of the second gate insulating layer 122b formed on the device isolation film 116 corresponding to the bottom surface of the gate trench 120T. For example, each of the fifth thickness T5 and the sixth thickness T6 of the gate insulating structure 122P may range from about 15 angstroms to about 30 angstroms.

[0047] Since the thickness of the second gate insulating layer 122b may be less than the thickness of the first gate insulating layer 122a, and the third thickness T3 of the gate insulating structure 122P is the sum of the first thickness T1 of the first gate insulating layer 122a and the fifth thickness T5 of the second gate insulating layer 122b, the fifth thickness T5 of the gate insulating structure 122P may be less than 1 / 2 of the third thickness T3 of the gate insulating structure 122P. For example, when the first thickness T1 of the first gate insulating layer 122a is 60 angstroms and the fifth thickness T5 of the second gate insulating layer 122b is 20 angstroms, the third thickness T3 of the gate insulating structure 122P is 80 angstroms, and thus may be approximately 4 times the fifth thickness T5 of the gate insulating structure 122P.

[0048] The third thickness T3 of the gate insulating structure 122P formed on the substrate 110 corresponding to the side surface of the gate trench 120T may be substantially equal to the first thickness T1 ( Figure 5A ) and the fifth thickness T5 of the second gate insulating layer 122b, and a fourth thickness T4 of a portion of the gate insulating structure 122P formed on the substrate 110 corresponding to the bottom surface of the gate trench 120T may be substantially equal to the second thickness T2 ( Figure 5A ) and the sum of the sixth thickness T6 of the second gate insulating layer 122b.

[0049] In some embodiments, the fourth thickness T4 of the gate insulation structure 122P may be equal to or greater than 75% of the third thickness T3 thereof and less than the third thickness T3 thereof.

[0050] When the first gate insulating layer 122a is formed by a first oxidation process (e.g., a thermal oxidation process), and the second gate insulating layer 122b is formed by a second oxidation process (e.g., a deposition process), the first gate insulating layer 122a may have a relatively denser film quality than the second gate insulating layer 122b. The first gate insulating layer 122a may have good step coverage in an initial formation stage, where the first gate insulating layer 122a has a relatively low thickness, and then, as the thickness of the first gate insulating layer 122a increases, the first gate insulating layer 122a may have deteriorated step coverage.

[0051] Before forming the first gate insulating layer 122a, when another oxide film (for example, the second gate insulating layer 122b by a deposition method) is first formed on the substrate 110, even in the initial formation stage where the first gate insulating layer 122a has a relatively low thickness, since the first gate insulating layer 122a may also be affected by the thickness of the already formed second gate insulating layer 122b, the first gate insulating layer 122a may have poor step coverage similar to the case where the first gate insulating layer 122a has a relatively high thickness.

[0052] However, before forming the first gate insulating layer 122a, when another oxide film is not formed on the substrate 110, the first gate insulating layer 122a can be formed with relatively good step coverage by appropriately adjusting the thickness of the first gate insulating layer 122a. Next, the second gate insulating layer 122b can be formed on the first gate insulating layer 122a so that the thickness of the second gate insulating layer 122b is less than the thickness of the first gate insulating layer 122a, whereby the gate insulating structure 122P including the first gate insulating layer 122a and the second gate insulating layer 122b can be formed to have relatively good step coverage and relatively good film quality.

[0053] FIG. 9A to FIG. 10 is a cross-sectional view illustrating a process of forming a preliminary gate insulating layer according to an example embodiment, and particularly, 9A to 9C Along Figure 8 A cross-sectional view taken along lines AA', BB' and CC', and Fig.10 is along 9A to 9C The reference level LV-R shown is a cross-sectional view taken in a direction parallel to the main surface of the substrate 110 . Fig.10 Only the shape at the reference level LV-R may be shown, and shapes at levels other than the reference level LV-R, for example, a shape at the level of the bottom surface of the gate trench 120T may not be shown.

[0054] Reference FIG. 9A to FIG. 10The preliminary gate insulating layer 122Pa is formed by a gate insulating structure 122P including a first gate insulating layer 122a and a second gate insulating layer 122b. FIG. 7A to FIG. 8 shown.

[0055] In some embodiments, the preliminary gate insulating layer 122Pa may be formed by a third process. For example, the third process may include a thermal oxidation process, which may also be referred to as a third oxidation process. In some embodiments, the third oxidation process may include forming the preliminary gate insulating layer 122Pa by a third process. 2 +H 2 The ISSG oxidation process is carried out in the gas, or in the 2 +H 2 The gas becomes O 2 In some other embodiments, the third oxidation method may include a dry oxidation process.

[0056] In some embodiments, when the third oxidation process includes 2 +H 2 The gas becomes O 2 In the ISSG oxidation process carried out in the gas of the gas, during the process time of the third oxidation process, O 2 +H 2 The time period of the gas can be less than O 2 For example, during the process time of the third oxidation process, H 2 The time period can be relatively short.

[0057] In some embodiments, the process time of the third oxidation process may be less than the reference Figures 4 to 6 Process time of the described first oxidation process. As used herein, the process time refers to a period of time for maintaining a process temperature and a process gas for performing each of the first oxidation process and the third oxidation process, and the process time does not include a ramp-up time and a cooling time.

[0058] In some embodiments, when the first oxidation process includes 2 +H 2 The ISSG oxidation process is carried out in the gas, and the third oxidation process includes 2 +H 2 Gas or from O 2 +H 2 The gas becomes O 2 When the ISSG oxidation process is carried out in the gas of the gas, the O 2 +H 2 The time period of the gas may be shorter than the process time of O in the first oxidation process. 2 +H 2 Time period in gas.

[0059] In some other embodiments, the third process may include a thermal treatment process. For example, the thermal treatment process may be performed by a rapid thermal processing (RTP) method or an annealing method.

[0060] The third process may remove impurities included in the gate insulating structure 122P, may make the gate insulating structure 122P denser in terms of film quality, may repair interface defects between the gate insulating structure 122P and the substrate 110, and / or may repair defects between the first gate insulating layer 122a and the second gate insulating layer 122b. For example, the preliminary gate insulating layer 122Pa may be a final product obtained by removing impurities from the gate insulating structure 122P, making the gate insulating structure 122P denser in terms of film quality, and / or repairing interface defects between the gate insulating structure and the substrate 110, the gate insulating structure 122P including the first gate insulating layer 122a and the second gate insulating layer 122b.

[0061] In still other embodiments, the third process may not be performed separately, and may include: FIG. 7A to FIG. 8 The gate insulating structure 122P including the first gate insulating layer 122 a and the second gate insulating layer 122 b shown may serve as a preliminary gate insulating layer 122Pa.

[0062] The first side thickness TS1 of the portion of the preliminary gate insulating layer 122Pa formed on the substrate 110 corresponding to the side surface of the gate trench 120T may be different from the first bottom thickness TB1 of the portion of the preliminary gate insulating layer 122Pa formed on the substrate 110 corresponding to the bottom surface of the gate trench 120T. For example, the first side thickness TS1 of the portion of the preliminary gate insulating layer 122Pa formed on the substrate 110 corresponding to the side surface of the gate trench 120T may be greater than the first bottom thickness TB1 of the portion of the preliminary gate insulating layer 122Pa formed on the substrate 110 corresponding to the bottom surface of the gate trench 120T.

[0063] A second side thickness TS2 of the preliminary gate insulating layer 122Pa formed on the device isolation film 116 corresponding to the side surface of the gate trench 120T may be substantially equal to a second bottom thickness TB2 of the preliminary gate insulating layer 122Pa formed on the device isolation film 116 corresponding to the bottom surface of the gate trench 120T.

[0064] Since the third process for forming the preliminary gate insulating layer 122Pa is an oxidation process or a heat treatment process in which the time period for which the O2 gas exists in the process time is relatively short, the thickness of the preliminary gate insulating layer 122Pa can be substantially similar to the thickness of the gate insulating structure 122P, or can be a few angstroms or less than the thickness of the gate insulating structure 122P.

[0065] The first side thickness TS1 of the preliminary gate insulating layer 122Pa formed on the substrate 110 corresponding to the side surface of the gate trench 120T may be substantially equal to the third thickness T3 ( Fig. 7A ), and a first bottom thickness TB1 of a portion of the preliminary gate insulating layer 122Pa formed on the substrate 110 corresponding to the bottom surface of the gate trench 120T may be substantially equal to a fourth thickness T4 ( Fig. 7A ).

[0066] The second side thickness TS2 of the portion of the preliminary gate insulating layer 122Pa formed on the device isolation film 116 corresponding to the side surface of the gate trench 120T may be substantially equal to the fifth thickness T5 ( Figure 7B ), and the second bottom thickness TB2 of the preliminary gate insulating layer 122Pa formed on the device isolation film 116 corresponding to the bottom surface of the gate trench 120T may be substantially equal to the sixth thickness T6 ( Figure 7B ). A second side thickness TS2 of the preliminary gate insulating layer 122Pa may be substantially equal to a second bottom thickness TB2 of the preliminary gate insulating layer 122Pa.

[0067] In some embodiments, the first bottom thickness TB1 of the preliminary gate insulating layer 122Pa may be equal to or greater than 75% of the first side thickness TS1 of the preliminary gate insulating layer 122Pa and less than the first side thickness TS1 of the preliminary gate insulating layer 122Pa.

[0068] FIG. 11A to FIG. 12B is a cross-sectional view illustrating a process of forming a gate insulating layer and a buried gate electrode according to example embodiments, and in particular, FIG. 11A to FIG. 11C Along Fig.10 A cross-sectional view taken along lines A-A', B-B' and CC', Fig. 12A is along Fig.11A and Fig. 11C The reference level LV-R shown is a cross-sectional view taken in a direction parallel to the main surface of the substrate 110, and Fig. 12B yes Fig. 12A An enlarged cross-sectional view of region XIIB.

[0069] Reference FIG. 11A to FIG. 12B , a plurality of gate insulating layers 122, a plurality of buried gate electrodes 120, and a plurality of buried insulating films 126 are sequentially formed inside the plurality of gate trenches 120T in the order stated herein. In some embodiments, a capping layer 124 may be disposed between each of the plurality of buried gate electrodes 120 and each of the plurality of buried insulating films 126.

[0070] The semiconductor device 1 includes a plurality of gate insulating layers 122 and a plurality of buried gate electrodes 120 , both of which fill lower portions of a plurality of gate trenches 120T, and a plurality of buried insulating films 126 fill upper portions of the plurality of gate trenches 120T.

[0071] A plurality of gate trenches 120T may be formed to fill the inner sides thereof and cover FIG. 9A to FIG. 10 The preliminary gate electrode of the preliminary gate insulating layer 122Pa shown is then removed, and the portions of the preliminary gate insulating layer 122Pa and the preliminary gate electrode covering the top surface of the active region 118 and the top surface of the device isolation film 116, and the portions of the preliminary gate insulating layer 122Pa and the preliminary gate electrode filling the upper portions of the plurality of gate trenches 120T are removed, thereby forming a plurality of gate insulating layers 122 and a plurality of buried gate electrodes 120. The plurality of gate insulating layers 122 may be portions of the preliminary gate insulating layer 122Pa covering the sidewalls and bottom surfaces of the lower portions of the plurality of gate trenches 120T, and the plurality of buried gate electrodes 120 may be portions of the preliminary gate electrodes arranged on the plurality of gate insulating layers 122 to fill the lower portions of the plurality of gate trenches 120T.

[0072] Similar to the plurality of gate trenches 120T, the plurality of buried gate electrodes 120 may longitudinally extend in the first horizontal direction (X direction) to be parallel to each other.

[0073] In some embodiments, after forming the plurality of buried gate electrodes 120, source / drain regions may be formed in the substrate 110 on both sides of each buried gate electrode 120 (i.e., in the upper portion of each of the plurality of active regions 118 on both sides of each buried gate electrode 120). In order to form the source / drain regions, impurity ions may be implanted into the substrate 110. In some other embodiments, before forming the plurality of buried gate electrodes 120, an impurity ion implantation process for forming the source / drain regions may be performed.

[0074] The top surface of each of the plurality of buried gate electrodes 120 is at a level lower than the top surface of the substrate 110 (i.e., the top surface of the active region 118). The bottom surface of each of the plurality of buried gate electrodes 120 may have an uneven shape along the bottom surface of each of the plurality of gate trenches 120T, and a saddle-shaped fin field effect transistor (saddle-shaped FINFET) may be formed in each of the plurality of active regions 118.

[0075] Each gate insulating film 122 may include at least one selected from the following group, the group consisting of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, ONO, or a high-k dielectric film having a higher dielectric constant than the silicon oxide film. For example, each gate insulating film 122 may have a dielectric constant of about 10 to about 25. In some embodiments, each gate insulating film 122 may include at least one selected from the following group, the group consisting of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, each gate insulating film 122 may include HfO 2 、Al 2 O 3 、HfAlO 3 、 2 O 3 or TiO 2 .

[0076] A top surface of each of the plurality of buried gate electrodes 120 is at a lower level than a top surface of the substrate 110. A bottom surface of each of the plurality of buried gate electrodes 120 may have an uneven shape, and a saddle-shaped FINFET may be formed in each of the plurality of active regions 118. In some embodiments, each of the plurality of buried gate electrodes 120 includes at least one selected from the group consisting of Ti, TiN, Ta, TaN, W, WN, TiSiN, and WSiN.

[0077] In some embodiments, each of the plurality of buried gate electrodes 120 may include a core layer 120C, and a barrier layer 120B between the core layer 120C and the gate insulating layer 122. For example, the core layer 120C may include a metal material such as W, WN, TiSiN, or WSiN, or a conductive metal nitride, and the barrier layer 120B may include a metal material such as Ti, TiN, Ta, or TaN, or a conductive metal nitride.

[0078] A top surface of each of the plurality of buried insulating films 126 may be at approximately the same level as a top surface of the substrate 110, ie, a top surface of the active region 118. Each buried insulating film 126 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

[0079] The capping layer 124 may include, for example, undoped polysilicon or doped polysilicon. In some embodiments, the capping layer 124 may be omitted.

[0080] Since the gate insulating layer 122 is a part of the preliminary gate insulating layer 122Pa, the thickness of the portion of the gate insulating layer 122 formed on the substrate 110 corresponding to the side surface of the gate trench 120T may be the first side thickness TS1 of the preliminary gate insulating layer 122Pa, and the thickness of the portion of the gate insulating layer 122 formed on the substrate 110 corresponding to the bottom surface of the gate trench 120T may be the first bottom thickness TB1 of the preliminary gate insulating layer 122Pa. In addition, the thickness of the portion of the gate insulating layer 122 formed on the device isolation film 116 corresponding to the side surface of the gate trench 120T may be the second side thickness TS2 of the preliminary gate insulating layer 122Pa, and the thickness of the portion of the gate insulating layer 122 formed on the device isolation film 116 corresponding to the bottom surface of the gate trench 120T may be the second bottom thickness TB2 of the preliminary gate insulating layer 122Pa.

[0081] In some embodiments, the first bottom thickness TB1 of the gate insulating layer 122 may be equal to or greater than 75% of the first side thickness TS1 of the gate insulating layer 122 and less than the first side thickness TS1 of the gate insulating layer 122. The second side thickness TS2 of the gate insulating layer 122 may be substantially equal to the second bottom thickness TB2 of the gate insulating layer 122.

[0082] In addition, the second side thickness TS2 of the gate insulating layer 122 may be less than 1 / 2 of the first side thickness TS1 of the gate insulating layer 122. For example, the first side thickness TS1 of the gate insulating layer 122 may be 80 angstroms, and the second side thickness TS2 may be 20 angstroms, and in this case, the first side thickness TS1 of the gate insulating layer 122 may be about 4 times the second side thickness TS2 of the gate insulating layer 122.

[0083] although FIG. 11A to FIG. 12B The device isolation film 116 is shown to be significantly different from the gate insulating layer 122, but this is only used to describe the shape of the gate insulating layer 122 (e.g., the thickness of the gate insulating layer 122 varies), and the inventive concept is not limited thereto. For example, when the device isolation film 116 and the gate insulating layer 122 include materials similar to each other, respectively. For example, when each of the device isolation film 116 and the gate insulating layer 122 includes silicon oxide, the interface between the device isolation film 116 and the gate insulating layer 122 may not be observed.

[0084] The gate trench 120T may have a substantially constant width in the second horizontal direction (Y direction) and may extend longitudinally in the first horizontal direction (X direction). In addition, since the gate trench 120T is filled with the buried gate electrode 120 and the gate insulating layer 122, the width of the buried gate electrode 120 in the second horizontal direction (Y direction) may be a value obtained by subtracting the width of the gate insulating layer 122 from the width of the gate trench 120T.

[0085] The buried gate electrode 120 may include a base GB having a constant width WB and extending in a first horizontal direction (X direction) and a protrusion GT protruding from the base GB in a second horizontal direction (Y direction). The width WB of the base GB may be the minimum width of the buried gate electrode 120 .

[0086] The protrusion GT may protrude to extend from the base GB toward the device isolation film 116. Since the second side thickness TS2 of the gate insulating layer 122 is less than 1 / 2 of the first side thickness TS1 of the gate insulating layer 122, the difference between the second side thickness TS2 and the first side thickness TS1 of the gate insulating layer 122 may be greater than 1 / 2 of the first side thickness TS1 of the gate insulating layer 122. The protrusion GT may protrude in the second horizontal direction (Y direction) as much as the difference between the second side thickness TS2 and the first side thickness TS1 of the gate insulating layer 122. Therefore, the protrusion length W1 of the protrusion GT in the second horizontal direction (Y direction) may be greater than 1 / 2 of the first side thickness TS1 of the gate insulating layer 122.

[0087] The protrusion GT may protrude from the base GB toward the device isolation film 116 disposed on both sides of the base GB. The buried gate electrode 120 may have a maximum width in a portion of the buried gate electrode 120, wherein a pair of protrusions GT protruding from the base GB in two side directions are aligned in the second horizontal direction (Y direction). Therefore, in the second horizontal direction (Y direction), a portion of the buried gate electrode 120, on which the device isolation film 116 is disposed on two opposite sides of the portion, may have a maximum width, and a portion of the buried gate electrode 120, on which the cross-sections of the active region 118 are disposed on two opposite sides of the portion, may have a minimum width.

[0088] Therefore, the difference between the maximum width and the minimum width of the buried gate electrode 120 may be greater than twice the ½ of the first side thickness TS1 of the gate insulating layer 122. For example, the difference between the maximum width and the minimum width of the buried gate electrode 120 may be greater than the first side thickness TS1 of the gate insulating layer 122.

[0089] In some embodiments, a portion of the buried gate electrode 120 adjacent to the long axis end of the active region T18 may have a width greater than that of the base GB in the second horizontal direction (Y direction). For example, a portion of the buried gate electrode 120 between the active regions 118 adjacent in the X direction may have a width greater than that of the base GB in the second horizontal direction (Y direction). In a portion of the buried gate electrode 120 adjacent to the long axis end of the active region 118, a width W2 increased in the second horizontal direction (Y direction) on one side of the buried gate electrode 120 may be less than a protruding length W1 of the base GB.

[0090] Therefore, in the second horizontal direction (Y direction), a portion of the buried gate electrode 120 may have a maximum width, and the device isolation film 116 is arranged on two opposite sides of the portion, a portion of the buried gate electrode 120 may have a minimum width, and the cross-section of the active area 118 is arranged on two opposite sides of the portion, respectively, and a portion of the buried gate electrode 120 has a width between the maximum width and the minimum width, and the long axis end of the active area 118 is arranged on at least one side of the portion.

[0091] In the semiconductor device 1 according to the present invention, since the gate insulating layer 122 has relatively good step coverage, even if the first side thickness TS1, which is the thickness of the portion of the gate insulating layer 122 formed on the side surface of the gate trench 120T, is relatively low, the first bottom thickness TB1, which is the thickness of the portion of the gate insulating layer 122 formed on the bottom surface of the gate trench 120T, can also ensure a certain value or higher. Therefore, the width of the buried gate electrode 120 in the second horizontal direction (Y direction) can be increased while maintaining the characteristics of the gate insulating layer 122. In addition, since the buried gate electrode 120 has the protrusion GB, thereby allowing the width of the buried gate electrode 120 in the second horizontal direction (Y direction) to increase, the average width of the buried gate electrode 120 can be increased.

[0092] Therefore, the resistance value of the buried gate electrode 120 in the semiconductor device 1 can be reduced, so that the semiconductor device 1 can show an improved operation speed. In particular, since the first side thickness TS1, which is the thickness of the portion of the gate insulating layer 122 formed on the side surface of the gate trench 120T, can be relatively low, the overlap characteristics between the buried gate electrode 120 and the drain electrode electrically connected to the active region 118 can be improved, so that the data writing speed of the semiconductor device 1 can be improved.

[0093] In addition, a first gate insulating layer 122a having a relatively dense film quality is first formed on the substrate 110, and the thickness of the first gate insulating layer 122a is greater than the thickness of the second gate insulating layer 122b, thereby improving the insulation performance of the gate insulating layer 122. In addition, since the proportion of the second gate insulating layer 122b formed by the deposition process in the gate insulating layer 122 is reduced, the chlorine (Cl) concentration in the gate insulating layer 122 can be reduced, and the interface trap density (Nit) and the stress in the gate insulating layer 122 can also be reduced, so that the refresh characteristics of the semiconductor device 1 can be improved.

[0094] Figures 13 to 15 are flowcharts each illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0095] Fig.13 Shows that reference is not executed FIG. 9A to FIG. 10 A method of forming the gate insulating layer 122 in the case of the third process is described.

[0096] Reference Fig.13 as well as Figures 2 to 3D , a plurality of gate trenches 120T are formed in the substrate 110 (S10). The plurality of gate trenches 120T may respectively have linear shapes extending longitudinally parallel to each other across the plurality of active regions 118. A portion where each of the plurality of active regions 118 intersects with each gate trench 120T may be exposed at a side surface of each gate trench 120T.

[0097] Reference Fig.13 as well as Figures 4 to 6 , a first gate insulating layer 122a is formed on the active region 118 by a first oxidation process (S100). The first gate insulating layer 122a may be selectively grown on the substrate 110 including the active region 118. For example, the first oxidation process may include a thermal oxidation process. In some embodiments, the first oxidation process may include 2 +H 2 ISSG oxidation process performed in gas.

[0098] The first gate insulating layer 122a may be formed such that a thickness of the first gate insulating layer 122a on the side surface of the gate trench 120T is different from a thickness of the first gate insulating layer 122a on the bottom surface of the gate trench 120T. For example, a first thickness T1 of a portion of the first gate insulating layer 122a formed on the side surface of the gate trench 120T may be greater than a second thickness T2 of a portion of the first gate insulating layer 122a formed on the bottom surface of the gate trench 120T. In some embodiments, the first gate insulating layer 122a may be formed such that the first thickness T1 of the first gate insulating layer 122a is equal to or less than about 1.5 times the second thickness T2 of the first gate insulating layer 122a.

[0099] Reference Fig.13 as well as FIG. 7A to FIG. 8 , a second gate insulating layer 122b is formed on the first gate insulating layer 122a and the device isolation film 116 by a second oxidation process (S200). The thickness of the second gate insulating layer 122b may be less than the thickness of the first gate insulating layer 122a. The second gate insulating layer 122b may be conformally formed so that the thickness of the second gate insulating layer 122b on the side surface of the gate trench 120T is substantially equal to the thickness of the second gate insulating layer 122b on the bottom surface of the gate trench 120T.

[0100] The second gate insulating layer 122b may cover both the first gate insulating layer 122a and the device isolation film 116. The second gate insulating layer 122b may also be formed such that the thickness of the second gate insulating layer 122b on the first gate insulating layer 122a is substantially equal to the thickness of the second gate insulating layer 122b on the device isolation film 116.

[0101] For example, the second oxidation process may include a deposition process. In some embodiments, the second oxidation process may include, for example, an ALD process.

[0102] Reference Fig.13 as well as FIG. 11A to FIG. 12B , the first gate insulating layer 122a and the second gate insulating layer 122b are partially removed to form a gate insulating layer 122, which covers the side surface and the bottom surface of the lower portion of the gate trench 120T (S20). Next, a buried gate electrode 120 is formed to cover the gate insulating layer 122 and fill the lower portion of the gate trench 120T (S30).

[0103] Fig.14 As a reference, the FIG. 9A to FIG. 10 A method of forming the gate insulating layer 122 by a third oxidation process of the third process is described.

[0104] Reference Fig.14 as well as Figures 2 to 3D, a plurality of gate trenches 120T are formed in the substrate 110 (S10). The plurality of gate trenches 120T may respectively have linear shapes extending longitudinally parallel to each other across the plurality of active regions 118. A portion where each of the plurality of active regions 118 intersects with each gate trench 120T may be exposed at a side surface of each gate trench 120T.

[0105] Reference Fig.14 as well as Figures 4 to 6 , a first gate insulating layer 122a is formed on the active region 118 by a first oxidation process (S100). The first gate insulating layer 122a may be selectively grown on the substrate 110 including the active region 118. For example, the first oxidation process may include a thermal oxidation process. In some embodiments, the first oxidation process may include 2 +H 2 ISSG oxidation process performed in gas.

[0106] The first gate insulating layer 122a may be formed such that a thickness of the first gate insulating layer 122a on the side surface of the gate trench 120T is different from a thickness of the first gate insulating layer 122a on the bottom surface of the gate trench 120T. For example, a first thickness T1 of a portion of the first gate insulating layer 122a formed on the side surface of the gate trench 120T may be greater than a second thickness T2 of a portion of the first gate insulating layer 122a formed on the bottom surface of the gate trench 120T. In some embodiments, the first gate insulating layer 122a may be formed such that the first thickness T1 of the first gate insulating layer 122a is equal to or less than about 1.5 times the second thickness T2 of the first gate insulating layer 122a.

[0107] Reference Fig.14 as well as FIG. 7A to FIG. 8 , a second gate insulating layer 122b is formed on the first gate insulating layer 122a and the device isolation film 116 by a second oxidation process (S200). The thickness of the second gate insulating layer 122b may be less than the thickness of the first gate insulating layer 122a. The second gate insulating layer 122b may be conformally formed so that the thickness of the second gate insulating layer 122b on the side surface of the gate trench 120T is substantially equal to the thickness of the second gate insulating layer 122b on the bottom surface of the gate trench 120T.

[0108] The second gate insulating layer 122b may cover the first gate insulating layer 122a and the device isolation film 116. The second gate insulating layer 122b may also be formed such that the thickness of the second gate insulating layer 122b on the first gate insulating layer 122a is substantially equal to the thickness of the second gate insulating layer 122b on the device isolation film 116.

[0109] For example, the second oxidation process may include a deposition process. In some embodiments, the second oxidation process may include, for example, an ALD process.

[0110] Reference Fig.14 as well as FIG. 9A to FIG. 10 , a preliminary gate insulating layer 122Pa is formed from the gate insulating structure 122P including the first gate insulating layer 122a and the second gate insulating layer 122b through a third oxidation process (S300).

[0111] For example, the third oxidation process may include 2 +H 2 The ISSG oxidation process is carried out in the gas, or in the 2 +H 2 The gas becomes O 2 In some other embodiments, the third oxidation method may include a dry oxidation process.

[0112] In some embodiments, when the third oxidation process includes 2 +H 2 The gas becomes O 2 In the ISSG oxidation process carried out in the gas of the gas, during the process time of the third oxidation process, O 2 +H 2 The time period of the gas can be less than O 2 For example, during the process time of the third oxidation process, there is O in the gas. 2 The time period can be relatively short.

[0113] In some embodiments, when the first oxidation process includes 2 +H 2 The ISSG oxidation process is carried out in the gas, and the third oxidation process includes 2 +H 2 Gas or from O 2 +H 2 The gas becomes O 2 When the ISSG oxidation process is carried out in the gas of the gas, the O 2 +H 2 The time period of the gas may be shorter than the process time of O in the first oxidation process. 2 +H 2 Time period in gas.

[0114] In some embodiments, a process time of the third oxidation process may be less than a process time of the first oxidation process.

[0115] refer to Fig.14 as well as FIG. 11A to FIG. 12B, the preliminary gate insulating layer 122Pa is partially removed to form a gate insulating layer 122, which covers the side surface and the bottom surface of the lower portion of the gate trench 120T (S22). Next, a buried gate electrode 120 is formed to cover the gate insulating layer 122 and fill the lower portion of the gate trench 120T (S30).

[0116] Fig.15 As a reference, the FIG. 9A to FIG. 10 The third process is described as a method of forming the gate insulating layer 122 by a thermal treatment process.

[0117] Reference Fig.15 as well as Figures 2 to 3D , a plurality of gate trenches 120T are formed in the substrate 110 (S10). The plurality of gate trenches 120T may respectively have linear shapes extending longitudinally parallel to each other across the plurality of active regions 118. A portion where each of the plurality of active regions 118 intersects with each gate trench 120T may be exposed at a side surface of each gate trench 120T.

[0118] Reference Fig.15 as well as Figures 4 to 6 , a first gate insulating layer 122a is formed on the active region 118 by a first oxidation process (S100). The first gate insulating layer 122a may be selectively grown on the substrate 110 including the active region 118. For example, the first oxidation process may include a thermal oxidation process. In some embodiments, the first oxidation process may include 2 +H 2 ISSG oxidation process performed in gas.

[0119] The first gate insulating layer 122a may be formed such that a thickness of the first gate insulating layer 122a on the side surface of the gate trench 120T is different from a thickness of the first gate insulating layer 122a on the bottom surface of the gate trench 120T. For example, a first thickness T1 of a portion of the first gate insulating layer 122a formed on the side surface of the gate trench 120T may be greater than a second thickness T2 of a portion of the first gate insulating layer 122a formed on the bottom surface of the gate trench 120T. In some embodiments, the first gate insulating layer 122a may be formed such that the first thickness T1 of the first gate insulating layer 122a is equal to or less than about 1.5 times the second thickness T2 of the first gate insulating layer 122a.

[0120] Reference Fig.15 as well as FIG. 7A to FIG. 8, a second gate insulating layer 122b is formed on the first gate insulating layer 122a and the device isolation film 116 by a second oxidation process (S200). The thickness of the second gate insulating layer 122b may be less than the thickness of the first gate insulating layer 122a. The second gate insulating layer 122b may be conformally formed so that the thickness of the second gate insulating layer 122b on the side surface of the gate trench 120T is substantially equal to the thickness of the second gate insulating layer 122b on the bottom surface of the gate trench 120T.

[0121] The second gate insulating layer 122b may cover the first gate insulating layer 122a and the device isolation film 116. The second gate insulating layer 122b may also be formed such that the thickness of the second gate insulating layer 122b on the first gate insulating layer 122a is substantially equal to the thickness of the second gate insulating layer 122b on the device isolation film 116.

[0122] For example, the second oxidation process may include a deposition process. In some embodiments, the second oxidation process may include, for example, an ALD process.

[0123] Reference Fig.15 as well as FIG. 9A to FIG. 10 , a preliminary gate insulating layer 122Pa is formed from the gate insulating structure 122P including the first gate insulating layer 122a and the second gate insulating layer 122b through a thermal treatment process (S310).

[0124] For example, the heat treatment process may be performed by an RTP method or an annealing method.

[0125] refer to Fig.15 as well as FIG. 11A to FIG. 12B , the preliminary gate insulating layer 122Pa is partially removed to form a gate insulating layer 122, which covers the side surface and the bottom surface of the lower portion of the gate trench 120T (S24). Next, a buried gate electrode 120 is formed to cover the gate insulating layer 122 and fill the lower portion of the gate trench 120T (S30).

[0126] Fig.16 is a graph illustrating a first process of a method of manufacturing a semiconductor device according to example embodiments, and Fig.17 is a graph illustrating a third process of the method of fabricating a semiconductor device according to example embodiments.

[0127] refer to Fig.16 and Fig.17 The first process Process 1 can be in O 2 +H 2 The ISSG oxidation process is performed in the gas, and the third process Process 3 can be performed in the gas from O 2 +H 2The gas becomes O 2 The ISSG oxidation process is carried out in the gas.

[0128] The process time of the first process Process 1 may be a first time period T1, and the process time of the third process Process 3 may be a sum of a second time period T2 and a third time period T3. Here, the process time refers to a time period for maintaining a process temperature and a process gas for performing each of the first process Process 1 and the third process Process 3, and the process time does not include a ramp-up time and a cooling time.

[0129] The first process Process1 can be in 2 +H 2 The gas is in the first time period T1, and the third process Process3 can be in O 2 +H 2 The gas is in the second time period T2 and is in H 2 In the third process Process 3, the third time period T3 may be less than the second time period T2, and each of the second time period T2 and the third time period T3 may be less than the first time period T1. In some embodiments, the sum of the second time period T2 and the third time period T3 may be less than the first time period T1.

[0130] For example, the first time period T1, the second time period T2, and the third time period T3 may be about 40 seconds, about 1 second, and about 20 seconds, respectively. However, this is merely an example, and the inventive concept is not limited thereto.

[0131] The oxygen supply period (i.e., O) in the process time of the third process Process 3 2 +H 2 The second time period T2 of the gas supply can be relatively compared to the oxygen supply time period (i.e., O) in the process time of the first process Process 1. 2 +H 2 Therefore, after the third process Process3, the gate insulating layer 122Pa ( FIG. 9A to FIG. 10 ) may have a thickness that is almost similar to that of the gate insulating structure 122P or be greater than that of the gate insulating structure 122P by a few angstroms or less.

[0132] For example, refer to Figures 1 to 12B and Fig.14The thickness of the described gate insulating layer 122 is basically determined by the first process Process 1 and the second process, and the third process Process 3 may remove impurities included in the gate insulating structure 122P, densify the gate insulating layer 122, or repair interface defects between the gate insulating structure 122P and the substrate 110 or defects between the first gate insulating layer 122a and the second gate insulating layer 122b, and may hardly affect the thickness of the gate insulating layer 122. Therefore, even if the third process Process 3 is performed, the step coverage of the gate insulating layer 122 may be maintained without any major change.

[0133] Fig.18 is a schematic plan layout showing main components of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to example embodiments. Fig.18 , reference will be omitted Figures 1 to 17 Repeat description given.

[0134] Reference Fig.18 , the semiconductor device 2 includes a device isolation film 116 defining a plurality of active regions 118 in a substrate 110. Each of the plurality of active regions 118 may have a relatively long island shape having a short axis and a long axis. For example, each of the plurality of active regions 118 may have a short axis and a long axis in an inclined direction relative to the first horizontal axis (X direction) and the second horizontal axis (Y direction). The plurality of gate trenches 120T may respectively have a linear shape extending longitudinally parallel to each other on the first horizontal axis (X direction) across the plurality of active regions 118. The plurality of buried gate electrodes 120 may be respectively arranged in the plurality of gate trenches 120T to extend parallel to each other on the first horizontal axis (X direction) across the plurality of active regions 118. The plurality of gate insulating layers 122 may each be arranged between each of the plurality of gate trenches 120T and each of the plurality of buried gate electrodes 120.

[0135] Since a portion of each of the plurality of buried gate electrodes 120 having two opposite sides disposed with the device isolation film 116 in the second horizontal axis (Y direction) may have an increased width, an average width of each buried gate electrode 120 may be increased.

[0136] A plurality of bit lines BL may be arranged above the buried gate electrode 120 to extend parallel to each other on a second horizontal axis (Y direction) intersecting the first horizontal axis (X direction). Each of the plurality of bit lines BL may be connected to each of the plurality of active regions ACT via a direct contact DC.

[0137] The plurality of storage contacts SC may each connect the lower electrode SN of the capacitor on each bit line BL to each active region 118. Each of the plurality of storage contacts SC may include: a buried contact disposed between two adjacent bit lines BL among the plurality of bit lines BL; and a conductive landing pad disposed on the buried contact. The conductive landing pad constituting each storage contact SC may at least partially overlap the buried contact.

[0138] In some embodiments, the direct contact DC may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. In some embodiments, the direct contact DC may include an epitaxial silicon layer.

[0139] In some embodiments, although each of the plurality of bit lines BL may include a lower conductive layer, an intermediate conductive layer, and an upper conductive layer, which are sequentially formed in the order described on the substrate 110, the inventive concept is not limited thereto. For example, each of the plurality of bit lines BL may include a single-layer, double-layer, or four-layer or higher stacked structure.

[0140] The top surface of the lower conductive layer and the top surface of the direct contact portion DC may extend on the same plane. In some embodiments, the lower conductive layer may include conductive polysilicon. Each of the intermediate conductive layer and the upper conductive layer may include TiN, TiSiN, W, tungsten silicide, or a combination thereof. For example, the intermediate conductive layer may include TiN and / or TiSiN, and the upper conductive layer may include W. A plurality of insulating capping patterns may be arranged on a plurality of bit lines BL, respectively. Each of the plurality of insulating capping patterns may include, for example, a silicon nitride film. A plurality of storage contacts SC are spaced apart from a plurality of bit lines BL, and a plurality of insulating spacers SPC1 are provided between the plurality of storage contacts SC and the plurality of bit lines BL.

[0141] The plurality of buried contacts respectively constituting the plurality of storage contacts SC may respectively have a pillar shape extending on the substrate 110 in a vertical direction (Z direction) along the spaces between the plurality of bit lines BL. A bottom surface of each of the plurality of buried contacts may contact each active region 118. A portion of each of the plurality of buried contacts may be located at a level lower than the top surface of the substrate 110 to be buried in the substrate 110. Each of the plurality of buried contacts may include a semiconductor material doped with impurities, a metal, a conductive metal nitride, or a combination thereof, but is not limited thereto.

[0142] The plurality of conductive landing pads respectively constituting the plurality of storage contacts SC may each include a conductive barrier film and a conductive layer. The conductive barrier film may include Ti, TiN, or a combination thereof. The conductive layer may include a metal, a metal nitride, conductive polysilicon, or a combination thereof. For example, the conductive layer may include tungsten (W).

[0143] The plurality of conductive grounding pads LP may have a plurality of island pattern shapes, respectively. The plurality of conductive landing pads may be electrically insulated from each other by an insulating film filling spaces around the plurality of conductive landing pads. The insulating film may include a silicon nitride film, a silicon oxide film, or a combination thereof.

[0144] A plurality of metal silicide films may each be arranged between a plurality of buried contacts and a plurality of conductive landing pads. In each of the plurality of storage contacts SC, the metal silicide film and the conductive landing pad may overlap vertically with the buried contact. In some embodiments, the metal silicide film may include cobalt silicide, nickel silicide, or manganese silicide, without limitation thereto. Each of the plurality of metal silicide films may be connected to the buried contact via the metal silicide film.

[0145] although Fig.18 A dynamic random access memory (DRAM) device is shown as an example of a semiconductor device, but the semiconductor device according to the inventive concept is not limited to the DRAM device. For example, the semiconductor device according to the inventive concept may be any semiconductor device having a buried gate electrode 120.

[0146] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches intersecting the plurality of active regions and extending in a first horizontal direction to be parallel to each other; selectively forming a first gate insulating layer on the exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film, wherein the thickness of the second gate insulating layer is smaller than the thickness of the first gate insulating layer; forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer; as well as forming a plurality of buried gate electrodes, The plurality of gate insulating layers respectively cover the side surfaces and bottom surfaces of the lower portions of the plurality of gate trenches. The plurality of buried gate electrodes are respectively arranged on the plurality of gate insulating layers to fill the lower portions of the plurality of gate trenches, and Each of the plurality of buried gate electrodes includes a base and a protrusion, the base extending in the first horizontal direction and having a constant width in a second horizontal direction perpendicular to the first horizontal direction, and the protrusion protruding from the base in the second horizontal direction.

2. The method according to claim 1, wherein: A thickness of a portion of the first gate insulating layer disposed on a side surface of each of the plurality of gate trenches is greater than a thickness of a portion of the first gate insulating layer disposed on a bottom surface of each of the plurality of gate trenches.

3. The method according to claim 2, wherein: The thickness of a portion of the second gate insulating layer disposed on the side surface of each of the plurality of gate trenches is equal to the thickness of a portion of the second gate insulating layer disposed on the bottom surface of each of the plurality of gate trenches.

4. The method according to claim 1, wherein: The protrusion protrudes to extend from the base toward the device isolation film.

5. The method according to claim 1, wherein: A protruding length of the protrusion from the base in the second horizontal direction is greater than 1 / 2 of a thickness of a portion of each of the plurality of gate insulating layers covering a side surface of a lower portion of each of the plurality of gate trenches.

6. The method according to claim 1, wherein: A portion of each of the plurality of buried gate electrodes has a maximum width in the second horizontal direction perpendicular to the first horizontal direction, and the device isolation film is disposed on two opposite sides of the portion.

7. The method according to claim 1, wherein: A difference between a maximum width and a minimum width of each of the plurality of buried gate electrodes in the second horizontal direction perpendicular to the first horizontal direction is greater than a thickness of a portion of each of the plurality of gate insulating layers covering a side surface of a lower portion of each of the plurality of gate trenches.

8. The method according to claim 1, wherein: A portion of each of the plurality of buried gate electrodes has a minimum width in the second horizontal direction perpendicular to the first horizontal direction, and a cross section of each of the plurality of active regions crossing the plurality of gate trenches is arranged on two opposite sides of the portion.

9. The method according to claim 1, wherein: The first gate insulating layer is formed by an in-situ steam generation (ISSG) oxidation process performed in an O 2 +H 2 gas.

10. The method according to claim 1, wherein: The second gate insulating layer is formed by an atomic layer deposition (ALD) process.

11. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches intersecting the plurality of active regions and extending in a first horizontal direction to be parallel to each other; forming a first gate insulating layer on the exposed surface of the substrate by a first oxidation process; forming a second gate insulating layer by a second oxidation process, wherein the second gate insulating layer covers the first gate insulating layer and the device isolation film; as well as forming a plurality of buried gate electrodes to fill lower portions of the plurality of gate trenches respectively, wherein the first oxidation process comprises an in-situ steam generation (ISSG) oxidation process in an O2+H2 gas, and the second oxidation process comprises a deposition process, and The method further includes: after forming the second gate insulating layer, performing a third oxidation process, wherein the third oxidation process includes an ISSG oxidation process performed in a gas that is changed from O2+H2 gas to O2 gas.

12. The method according to claim 11, wherein: A process time of the third oxidation process is shorter than a process time of the first oxidation process.

13. The method according to claim 11, wherein: In the process time of the third oxidation process, a time period of the O2+H2 gas is shorter than a time period of the O2 gas.

14. The method according to claim 11, wherein: The sum of the thicknesses of the first gate insulating layer and the second gate insulating layer formed on the substrate corresponding to the bottom surface of each of the multiple gate trenches is equal to or greater than 75% of the sum of the thicknesses of the first gate insulating layer and the second gate insulating layer formed on the substrate corresponding to the side surface of each of the multiple gate trenches.

15. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches intersecting the plurality of active regions and extending in a first direction to be parallel to each other; forming a plurality of gate insulating layers respectively by sequentially forming a first gate insulating layer and a second gate insulating layer on the exposed surface of the substrate based on different oxidation methods; as well as forming a plurality of buried gate electrodes extending parallel to each other in the first direction and filling lower portions of the plurality of gate trenches respectively, wherein the plurality of gate insulating layers are between the plurality of buried gate electrodes and the plurality of gate trenches, wherein the sum of the thicknesses of the first gate insulating layer and the second gate insulating layer formed on the substrate corresponding to the bottom surface of each of the plurality of gate trenches is equal to or greater than 75% of the sum of the thicknesses of the first gate insulating layer and the second gate insulating layer formed on the substrate corresponding to the side surface of each of the plurality of gate trenches, and wherein a first portion of each of the plurality of buried gate electrodes has a first width in a second direction intersecting the first direction, the device isolation film is arranged on two opposite sides of the first portion, and a second portion of each of the plurality of buried gate electrodes has a second width in the second direction, and a cross-section of each of the plurality of active regions intersecting the plurality of gate trenches is respectively arranged on two opposite sides of the second portion.

16. The method according to claim 15, in, The first gate insulating layer is formed by using an in-situ steam generation (ISSG) oxidation process performed in an O 2 +H 2 gas.

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