Timer circuit for dual-channel motor controller

Abstract

A timer circuit for a dual-channel motor controller includes two motor controllers, each generating a PWM drive signal having a period defined by a corresponding timer of the timer circuit. The timer circuit includes: a first processing circuit associated with a first motor controller and including a first oscillator circuit and a first timer, wherein the first timer outputs a first timer signal whenever the oscillator circuit completes a set integer N oscillations; and a second processing circuit associated with a second motor controller and including a second oscillator circuit. The second processing circuit includes a timer signal output whenever the oscillator circuit completes an integer N oscillations. * The second timer outputs the second timer signal during the second oscillation and calculates N. * The value of N * The value depends on the difference between the frequencies of the first oscillator circuit and the second oscillator circuit required to match the period of the second timer signal with the period of the first timer signal.

Description

Technical Field

[0001] This invention relates to improvements to timer circuits used with dual-channel motor controllers, and to dual-channel motor controllers including timer circuits. It particularly, but not exclusively, relates to motor controllers for electric power steering systems. Background Technology

[0002] A known motor control circuit for a multiphase electric motor is provided, in which an analog waveform (typically a set of three or more sinusoidal waveforms, out of phase with each other, one of which is for each phase of the motor) required to drive the motor phases is converted into a digital signal using pulse width modulation (PWM). The PWM signal is then used to drive a set of switching devices, typically MOSFET transistors, which alternately connect each phase to a positive or negative power supply defined by the PWM signal state.

[0003] For applications requiring high reliability, a dual-channel motor control circuit is known. This circuit provides two motor controllers, one designated as the master motor controller and the other as the slave motor controller. Each controller can generate a set of PWM drive signals for the motor. During normal operation, the signals from the master motor controller are used, and if the master motor controller fails, the slave motor controller is used to drive the motor.

[0004] In a further extension of the dual-channel arrangement, the motor can also be dual-wound, meaning it has two completely independent sets of phase windings. Each of the two motor controllers can drive one set of windings. Therefore, if the main controller or the main winding fails, the slave controller can still operate using the slave winding, even if the motor is operating at half power.

[0005] Motor controllers can generate PWM signals in several ways. Regardless of the method chosen, an appropriate period needs to be set for the PWM waveform. This is achieved by providing a reference timer signal to the PWM waveform generator of each motor controller. The PWM waveform generator creates a set of PWM signals suitable for the PWM period.

[0006] In a fully robust arrangement with independent dual-channel controllers, two reference timers can be provided, each operating independently of the others, and each providing a reference timer signal to a corresponding PWM waveform generator. Ideally, the two timers should be closely synchronized, so that they are in phase, and ideally, the periods set by each timer should also be the same. This allows the slave motor controller to smoothly take over the master controller in the event of a failure. This is also a requirement when the motor is a wound-rotor motor, because any difference in the periods of the two timer signals during normal operation will cause the motor to malfunction.

[0007] In practical setups, each reference timer signal is generated from an oscillator circuit, such as a crystal oscillator whose output is increased via a phase-locked loop to enhance the crystal oscillator frequency. Typical oscillator circuits have output frequencies too high to directly define the period of the PWM signal; therefore, the frequency is reduced so that each cycle of the timer corresponds to multiple cycles of the oscillator. For example, a PWM period equal to 500 cycles of the oscillator circuit output can be used.

[0008] With each channel powered by a separate crystal oscillator, the applicant noted that the two reference timers could become slightly out of sync due to many factors, such as the effect of temperature on the oscillators. One object of the present invention is to improve upon the problems that can arise if the timer frequencies are not carefully matched. Summary of the Invention

[0009] According to a first aspect of the invention, a timer circuit for use with a dual-channel motor controller is provided, comprising a first motor controller and a second motor controller, each motor controller generating a PWM drive signal having a period defined by a corresponding timer of the timer circuit, wherein the timer circuit comprises:

[0010] A first processing circuit, associated with a first motor controller, includes a first oscillator circuit and a first timer, wherein the first timer outputs a first timer signal whenever the oscillator circuit completes a set integer N oscillations.

[0011] The second processing circuit, associated with the second motor controller, includes a second oscillator circuit.

[0012] The second processing circuit also includes a second timer, which is activated whenever the oscillator circuit completes an integer N. * During the second oscillation, the second timer outputs a second timer signal, and the second processing circuit includes calculating N. * The unit for calculating the value of N *The value depends on the difference between the frequencies of the first oscillator circuit and the second oscillator circuit required to match the period of the second timer signal with the period of the first timer signal.

[0013] The applicant has recognized that two perfectly matched oscillator circuits will produce the same number of cycles in a given elapsed time, and in this case, the timer circuit will output N and N... * The values ​​of are set to be equal. However, in the case of imperfect oscillators, depending on the corresponding frequencies of the two oscillator circuits, N can be... * The value is set to be slightly greater than or slightly less than the value of N.

[0014] The first processing circuit may further include: a first counter that counts the number of oscillations M of the first oscillator circuit over a first elapsed time, the first elapsed time starting from a predetermined start time and ending when the counter has counted M cycles of the oscillator; and a transmitter that outputs a trigger signal once the counter reaches the value M. The second processing circuit further includes: a receiver that receives the trigger signal; and a second counter that determines the number of oscillations M of the second oscillator circuit over the elapsed time corresponding to the first elapsed time. * Furthermore, the computational unit of the second processing circuit can be configured to calculate values ​​depending on M and M * The difference of N values * The value of N makes N * It is the integer number of cycles of the second oscillator required to match the period of the second timer signal with the period of the first timer signal.

[0015] The predetermined start time of the first counter can correspond to the time of the next oscillation of the first oscillator circuit after the trigger signal is generated. This may repeat indefinitely, thus periodically sending the trigger signal. The start time of the second counter can also correspond to the time of the next oscillation of the second oscillator circuit after the trigger signal is received. This is a convenient method to ensure that the two counters start and stop simultaneously.

[0016] In an alternative, the first processing circuit can generate a start signal that initiates the counting of both counters, and this count can be sent to the second circuit. In a modification, the second processing circuit can generate a start signal and send it to the first processing circuit. A receiver is then required as part of the first processing circuit. Once the start signal is received by the first circuit, the first count can begin on the next cycle of the oscillator circuit.

[0017] Of course, instead of starting the elapsed time at the beginning of the next cycle of the oscillator circuit, a fixed delay can be introduced, such as 2 or 3 or more cycles, or a fixed time, such as 1 second or longer.

[0018] The computing unit can calculate N as follows: * Value:

[0019] N * =N×(M) * / M)

[0020] Where, N * It is the period of the second timer in the oscillator circuit cycle;

[0021] N is the period of the first timer, which represents an integer number of cycles of the first oscillator circuit;

[0022] M is the number of cycles of the first oscillator circuit within a fixed elapsed time period; and

[0023] M * It is the number of cycles counted by the second oscillator circuit within the same elapsed time period.

[0024] Each of the oscillator circuits may include a crystal oscillator or a resonator. The oscillator circuit may also include a phase-locked loop (PLL) that receives the output of the oscillator or resonator and generates a boosted oscillation signal. The output of the oscillator circuit may include a set of pulses, each pulse being counted and representing one cycle. Alternatively, the output may be a square wave, and each cycle may correspond to the timing of each leading edge, each trailing edge, or each edge, regardless of whether it is a trailing edge or a leading edge.

[0025] The first and second processing circuits may include independent circuits, or they may include a portion of a single common processing circuit. Their circuitry may, for example, include a computer program stored in a region of electronic memory running on the processing unit or microcontroller.

[0026] The value of M can be chosen to be greater than the value of N, and can be 3 times, 4 times, or even more. The longer the chosen elapsed time, the more noticeable any slight frequency changes between the two oscillators will be, because M and M... * The deviation in the value will be even greater.

[0027] The first processing circuit can be used as a master timer circuit and can be assumed to have an oscillator, which is used as the master device to set the periods of the two timer signals. In use, the configuration of the first and second processing circuits can be reversed, such that the second processing circuit generates a trigger signal and sets the elapsed time, and the first processing circuit determines the period of the first timer signal from the trigger signal.

[0028] To achieve this, the second processing circuit may further include: a third counter that counts the number of oscillations M of the second oscillator circuit over a first elapsed time, the first elapsed time starting from a predetermined start time and ending when the counter has counted a predetermined M cycles of the oscillator; and a transmitter that outputs a trigger signal once the counter reaches the value M.

[0029] The first processing circuit may further include: a receiver that receives a trigger signal; and a processor that determines the number of oscillations M of the first oscillator at an elapsed time corresponding to a first elapsed time. * ,and

[0030] The first processing circuit may include a calculation unit that, in use, calculates values ​​depending on the value of M and M'. * The difference of N values * The value of N makes N * It is the integer number of cycles of the first oscillator required to match the period of the first timer signal with the period of the second timer signal.

[0031] The third counter can be the same as the second counter. The fourth counter can be the same as the first counter.

[0032] The trigger signal can encode the value of M, or it can include only the value of M.

[0033] According to a second aspect, the present invention provides a motor drive circuit including a timer of the first aspect, the circuit including two motor controllers as independent channels, each motor controller generating a set of PWM signals, the period of which is set by a corresponding timer signal of two timer signals of the timer circuit.

[0034] According to a third aspect, the present invention provides a method for operating two timers, each of which is driven by a corresponding oscillator circuit, wherein the period of the first timer corresponds to the elapsed time between N cycles of the first oscillator circuit, and the period of the second timer corresponds to the elapsed time between N cycles of the second oscillator circuit. * The method includes the following: the elapsed time between iterations.

[0035] The number of cycles M of the first oscillator circuit within the defined number of cycles is counted over time.

[0036] The number of cycles M of the second oscillator circuit occurring within the same elapsed time. * To count; and

[0037] Based on the value of M and M * Calculate the difference of N values * The value of . Attached Figure Description

[0038] An embodiment of the invention will now be illustrated by way of example only, with reference to the accompanying drawings, in which the following figures are shown:

[0039] Figure 1 This is a schematic diagram of a motor and control system including a timer circuit within the scope of the first aspect of the present invention;

[0040] Figure 2 This is a block diagram showing the key parts of the timer circuit;

[0041] Figure 3 This is a flowchart illustrating the operation of the timer circuit when the first timer circuit is used as the main circuit; and

[0042] Figure 4 When the second timer circuit is used as the main circuit, it is in conjunction with... Figure 3 Equivalent flowchart. Detailed Implementation

[0043] like Figure 1 As shown, the motor and control system include a motor with two independent sets of phase windings. Each set of phase windings is driven by a corresponding channel of a dual-channel motor controller.

[0044] The dual-channel motor controller includes a timer circuit according to the first aspect of the present invention, and comprises two independent microcontrollers. Each microcontroller includes software that implements motor controller functions and PWM generation functions. The motor controller function calculates the target motor phase voltage based on the motor's operating conditions, and the PWM generation function converts the target motor phase voltage into a PWM duty cycle. Each microcontroller has a hardware timer module that can output the PWM duty cycle as a waveform to the drive circuit.

[0045] In this example, each motor controller generates three out-of-phase PWM signals to drive the three-phase motor. Two motor controllers are configured as master controllers, which provide drive signals to the motor bridge of the three-phase motor during normal operation, while the third motor controller is configured as a slave controller and does not drive the motor bridge during normal operation. If the master motor controller fails, the slave motor drive circuit may take over the drive of the motor bridge if the master motor controller is disabled.

[0046] The PWM signal for each channel is synchronized with a timer signal from a timer. The timer signal is fed to hardware that implements a phase-locked loop (PLL) manager function, which is implemented within each microcontroller. In this example, the timer signal output from the hardware timer of each microcontroller comes from a crystal or resonator. The crystal or resonator operates at a relatively low frequency (e.g., 20 MHz), and the microcontroller's hardware PLL component acts as a frequency multiplier to boost it to a higher frequency (e.g., 200 MHz).

[0047] In the example shown, each motor controller generates a PWM signal synchronized with a corresponding timer signal output from a hardware timer, thus providing two timers. The timers are independent and generated from a corresponding oscillator crystal and a hardware PLL, as described above.

[0048] Two timers, providing timer signals to two motor controllers, constitute part of a timer circuit implemented across two microcontrollers and are controlled by this timer circuit. This timer circuit is arranged as a dual-channel circuit, with one channel associated with each channel of the motor control circuit. The timer circuit is arranged according to an embodiment of the invention, and... Figure 2 The functional components of the timer circuit are schematically shown in the diagram.

[0049] The timer circuit includes two processing circuits. In this example, the first processing circuit forms part of a first motor controller, and the second forms part of a second motor controller.

[0050] The first processing circuit includes a first oscillator circuit composed of an XTAL and a hardware PLL, a first timer, a first counter, and a transmitter for sending a trigger signal to the second processing circuit. The second processing circuit includes a second oscillator circuit composed of a second XTAL and a second hardware PLL, a second timer, a second counter, a receiver for receiving signals sent from the first circuit, and a computing unit.

[0051] When the first timer acts as the master timer and the second timer acts as the slave timer, the operation of each functional part of the timer circuit is as follows: Figure 3 As shown.

[0052] Each time the oscillator circuit completes a set integer N oscillations, the first processing circuit outputs a first timer signal. In this example, this number is set to 500 cycles. This defines the timer signal provided to the software PLL. In this example, the timer signal has a square wave form with a period of M. However, the timer signal can also have the form of a series of pulses spaced at periods of M. Other options will be apparent to those skilled in the art.

[0053] A first counter counts the oscillations of a first oscillator circuit (the output of a first hardware PLL) over a first elapsed time, which begins at a predetermined start time and ends when the counter has counted a predetermined number of M cycles. In this example, the value of M is set to 2000, exactly four times the value of N. Once the value M is reached, the counter resets and starts counting again. This can be repeated continuously during the on-time of the timer circuit, or only during a test cycle that can be set automatically or manually by the user. For example, a test cycle occurs whenever the motor control circuit is turned on. The count defines a trigger signal whose period is longer than the period of the timer signal.

[0054] Once the trigger signal has been generated, the transmitter will send the trigger signal encoded with the value M to the second processing circuit.

[0055] The second processing circuit associated with the second motor controller includes a receiver for receiving trigger signals, a second oscillator, a second counter, and a calculation unit.

[0056] The receiver receives the trigger signal, and then the processor of the second processing unit determines the number of oscillations M of the second oscillator that occurred at the same elapsed time corresponding to the first elapsed time. * Therefore, the second counter of the second processing unit starts counting simultaneously with the first counter, and stops counting once a trigger signal is received. Then, the value M of the second counter is... * The value M, encoded in the trigger signal, is fed to the computing unit. The computing unit calculates the result depending on M and M. * The ratio of N * The value of N makes N * It is the integer number of cycles of the second oscillator required to match the period of the second timer signal with the period of the first timer signal.

[0057] Then, the second processing circuit uses the value N * This is used to set the frequency of the second timer signal, thereby ensuring that the frequencies of the first and second timers match.

[0058] In mathematics, the computational unit in this example performs the following calculations:

[0059] N * =N.(M * / M)

[0060] Therefore, the trigger signal can be viewed as performing two functions:

[0061] 1) Allows synchronization of two software control algorithms at a coarse level (typically ~10ns) set by the value of count M; and

[0062] 2) Observe the period of the trigger signal based on the oscillator circuit count, and adjust the period of the second timer signal according to the PWM edge position and timer reload value to achieve the same overall timing across channels (typical granularity is about 10ns).

[0063] exist Figure 4 In the variant shown, the second circuit can act as the master device, while the first signal processing unit can act as the slave device. This requires the second processing unit to set the cyclic value M for the second timer signal and generate a trigger signal. The first processing unit must receive the trigger signal and sequentially calculate the value N. * To be applied to the first timer.

Claims

1. A timer circuit for use with a dual-channel motor controller, comprising a first motor controller and a second motor controller, each motor controller generating a PWM drive signal having a period defined by a corresponding timer of the timer circuit, wherein the timer circuit comprises: A first processing circuit, associated with the first motor controller, includes a first oscillator circuit and a first timer, wherein the first timer outputs a first timer signal whenever the first oscillator circuit completes a set integer N oscillations. The second processing circuit, associated with the second motor controller, includes a second oscillator circuit. The second processing circuit also includes a second timer, which is activated whenever the second oscillator circuit completes an integer... During the second oscillation, the second timer outputs a second timer signal, and the second processing circuit includes calculation... The unit for calculating the value of, the The value depends on the difference in frequencies between the first oscillator circuit and the second oscillator circuit required to match the period of the second timer signal with the period of the first timer signal. The first processing circuit further includes: a first counter that counts the number of oscillations M of the first oscillator circuit over a first elapsed time, the first elapsed time starting from a predetermined start time and ending when the first counter has counted M cycles of the first oscillator circuit; and a transmitter that outputs a trigger signal once the first counter reaches the value M. The second processing circuit further includes: a receiver that receives the trigger signal; and a second counter that determines the number of oscillations of the second oscillator circuit over an elapsed time corresponding to the first elapsed time. ;as well as The calculation unit of the second processing circuit is configured to calculate the value depending on the value of M and the The difference in value The value of makes M is the integer number of cycles of the second oscillator circuit required to match the period of the second timer signal with the period of the first timer signal, wherein the value of M is selected to be greater than the value of N.

2. The timer circuit according to claim 1, wherein, The predetermined start time of the first counter corresponds to the time of the next oscillation of the first oscillator circuit after the generation of the trigger signal.

3. The timer circuit according to claim 2, wherein, The start time of the second counter corresponds to the time of the next oscillation of the second oscillator circuit after the trigger signal is received.

4. The timer circuit according to claim 1, wherein, The first processing circuit is configured to generate a start signal for starting the count of the two counters and send the start signal to the second processing circuit.

5. The timer circuit according to claim 1, wherein, The second processing circuit is configured to generate a start signal for starting the count of the two counters and send the start signal to the first processing circuit.

6. The timer circuit according to claim 1, wherein, The calculation unit uses equations To calculate the The value of .

7. The timer circuit according to claim 1, wherein, Each of the oscillator circuits includes a crystal oscillator and a phase-locked loop.

8. The timer circuit according to claim 7, wherein, The crystal oscillator has a frequency in the range of 10 MHz to 20 MHz, and wherein the phase-locked loop increases the oscillation frequency to the range of 100 MHz to 200 MHz.

9. The timer circuit according to claim 1, wherein, The first processing circuit and the second processing circuit include independent circuits.

10. The timer circuit according to claim 1, wherein, In use, the configurations of the first processing circuit and the second processing circuit can be reversed, such that the second processing circuit generates the trigger signal and sets the first elapsed time, and the first processing circuit determines the period of the first timer signal from the trigger signal.

11. The timer circuit according to claim 10, wherein, The second processing circuit further includes: a third counter that counts the number of oscillations M of the second oscillator circuit over a first elapsed time, the first elapsed time starting from a predetermined start time and ending when the third counter has counted a predetermined M cycles of the second oscillator circuit; and a transmitter that outputs a trigger signal once the third counter reaches the value M.

12. The timer circuit according to claim 10, wherein, The first processing circuit further includes: a receiver for receiving the trigger signal; and a processor for determining the number of oscillations of the first oscillator circuit over an elapsed time corresponding to the first elapsed time. ,and The first processing circuit includes a calculation unit, which calculates, during use, a value that depends on the value of M and the... The ratio of values The value of makes It is the integer number of cycles of the first oscillator circuit required to match the period of the first timer signal with the period of the second timer signal.

13. A motor drive circuit comprising a timer circuit according to any one of claims 1 to 12, the motor drive circuit comprising two motor controllers as independent channels, each motor controller generating a set of PWM signals, the period of the set of PWM signals being set by a corresponding timer signal of two timer signals of the timer circuit.

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