Wiring structure and method for manufacturing the same

Abstract

A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesive layer, and at least one external via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesive layer is between the upper conductive structure and the lower conductive structure to join the upper conductive structure and the lower conductive structure together. The external via extends through at least a portion of the upper conductive structure and the adhesive layer and electrically connects the circuit layer of the lower conductive structure.

Description

Technical Field

[0001] This disclosure relates to a wiring structure and a method of manufacturing it, and more particularly to a wiring structure comprising at least two conductive structures attached together by an adhesive layer, and a method for manufacturing said wiring structure. Background Technology

[0002] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips integrate an increasing number of electronic components to achieve better electrical performance and more functions. Correspondingly, semiconductor chips have more input / output (I / O) connections. To manufacture semiconductor packages containing semiconductor chips with an increased number of I / O connections, the circuit layers of the semiconductor substrate supporting the semiconductor chips may need to be increased accordingly. Therefore, the thickness of the semiconductor substrate may increase, and the yield of the semiconductor substrate may decrease. Summary of the Invention

[0003] In some embodiments, a wiring structure includes an upper conductive structure, a lower conductive structure, an adhesive layer, and at least one external via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesive layer is located between the upper and lower conductive structures to bond the upper and lower conductive structures together. The external via penetrates at least a portion of the upper conductive structure and the adhesive layer, and electrically connects to the circuit layer of the lower conductive structure.

[0004] In some embodiments, a method for manufacturing a wiring structure includes: (a) providing a lower conductive structure comprising at least one circuit layer including at least one dielectric layer and a contact dielectric layer; (b) providing an upper conductive structure comprising at least one circuit layer including at least one dielectric layer and a contact dielectric layer; and (c) attaching the upper conductive structure to the lower conductive structure. Attached Figure Description

[0005] When read in conjunction with the accompanying drawings, various aspects of some embodiments of this disclosure can be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0006] Figure 1 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0007] Figure 2 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0008] Figure 2AA top view showing an example of a reference mark of the upper conductive structure of some embodiments of this disclosure.

[0009] Figure 2B A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of this disclosure.

[0010] Figure 2C show Figure 2A The reference mark of the upper conductive structure and Figure 2B A top view of a composite image of the reference marks on the lower conductive structure.

[0011] Figure 2D A top view showing an example of a reference mark of the upper conductive structure of some embodiments of this disclosure.

[0012] Figure 2E A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of this disclosure.

[0013] Figure 2F show Figure 2D The reference mark of the upper conductive structure and Figure 2E A top view of a composite image of the reference marks on the lower conductive structure.

[0014] Figure 2G A top view showing an example of a reference mark of the upper conductive structure of some embodiments of this disclosure.

[0015] Figure 2H A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of this disclosure.

[0016] Figure 2I show Figure 2G The reference mark of the upper conductive structure and Figure 2H A top view of a composite image of the reference marks on the lower conductive structure.

[0017] Figure 3 A cross-sectional view showing the connection between the package structure and the substrate.

[0018] Figure 4 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0019] Figure 5 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0020] Figure 6 A cross-sectional view showing the connection between the package structure and the substrate.

[0021] Figure 7 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0022] Figure 8 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0023] Figure 9 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0024] Figure 10 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0025] Figure 11 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0026] Figure 12 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0027] Figure 13 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0028] Figure 14 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0029] Figure 15 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0030] Figure 16 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0031] Figure 17 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0032] Figure 18 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0033] Figure 19 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0034] Figure 20 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0035] Figure 21 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0036] Figure 22 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0037] Figure 23 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0038] Figure 24 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0039] Figure 25 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0040] Figure 26 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0041] Figure 27 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0042] Figure 28 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0043] Figure 29 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0044] Figure 30 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0045] Figure 31 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0046] Figure 32 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0047] Figure 33 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0048] Figure 34 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0049] Figure 35 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0050] Figure 36This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0051] Figure 37 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0052] Figure 38 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0053] Figure 39 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0054] Figure 40 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0055] Figure 41 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0056] Figure 42 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0057] Figure 43 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0058] Figure 44 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0059] Figure 45 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0060] Figure 46 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0061] Figure 47 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0062] Figure 48 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0063] Figure 49 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0064] Figure 50This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0065] Figure 51 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0066] Figure 52 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0067] Figure 53 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0068] Figure 54 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0069] Figure 55 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0070] Figure 56 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0071] Figure 57 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0072] Figure 58 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0073] Figure 59 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures. Detailed Implementation

[0074] Throughout the drawings and detailed description, common reference numerals are used to indicate the same or similar components. Embodiments of this disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0075] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0076] To meet the increased I / O count requirements, the number of dielectric layers on the substrate must be increased. In some embodiments, the manufacturing process of the core substrate may include the following steps. First, a core with two copper foils disposed on both sides of the core is provided. Subsequently, multiple dielectric layers and multiple circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in one dielectric layer. Therefore, the core substrate may include multiple stacked dielectric layers and multiple circuit layers embedded in the dielectric layers on both sides of the core. Because the linewidth / spacing (L / S) of the circuit layers of such a core substrate can be greater than or equal to 10 micrometers (μm) / 10 μm, the number of dielectric layers of such a core substrate must be relatively large. Although the manufacturing cost of such a core substrate is lower, the manufacturing yield of the circuit layers and dielectric layers of such a core substrate is also lower, thus the yield of such a core substrate is low. In addition, the dielectric layers are relatively thick, therefore, such a core substrate is relatively thick. In a comparative embodiment, if the package has 10,000 I / O counts, then such a core substrate may require twelve layers of circuit layers and dielectric layers. The manufacturing yield of one layer (comprising a circuit layer and a dielectric layer) of this type of core substrate can be 90%. Therefore, the yield of this type of core substrate can be (0.9). 12 =28.24%.

[0077] To address the above issues, in some embodiments, a coreless substrate is provided. The coreless substrate may include multiple dielectric layers and multiple fan-out circuit layers. In some embodiments, the fabrication process of the coreless substrate may include the following steps: First, a carrier is provided. Subsequently, multiple dielectric layers and multiple fan-out circuit layers are formed or stacked on the surface of the carrier. A fan-out circuit layer may be embedded within a dielectric layer. Subsequently, the carrier is removed. Therefore, the coreless substrate may consist only of multiple stacked dielectric layers and multiple fan-out circuit layers embedded within the dielectric layers. Because the linewidth / spacing (L / S) of the fan-out circuit layers in such a coreless substrate can be less than or equal to 2 μm / 2 μm, the number of dielectric layers in such a coreless substrate can be reduced. Furthermore, the fabrication yield of the fan-out circuit layers and dielectric layers in such a coreless substrate is high. For example, the fabrication yield of one layer (including one fan-out circuit layer and one dielectric layer) in such a coreless substrate can be 99%. However, the fabrication cost of such a coreless substrate is relatively high.

[0078] At least some embodiments of this disclosure provide wiring structures with an acceptable trade-off between yield and manufacturing cost. In some embodiments, the wiring structure includes an upper conductive structure and a lower conductive structure bonded to the upper conductive structure via an adhesive layer. At least some embodiments of this disclosure further provide techniques for manufacturing the wiring structures.

[0079] Figure 1 This diagram shows a cross-sectional view of a wiring structure 1 according to some embodiments of the present disclosure. The wiring structure 1 includes an upper conductive structure 2, a lower conductive structure 3, an adhesive layer 12, and at least one external via 14.

[0080] The upper conductive structure 2 includes at least one dielectric layer (including, for example, two first dielectric layers 20 and one second dielectric layer 26) and at least one circuit layer (including, for example, three first circuit layers 24 and one second circuit layer 28) in contact with the dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26). In one embodiment, the upper conductive structure 2 may resemble a coreless substrate and may be wafer-type, panel-type, or strip-type. The upper conductive structure 2 has a top surface 21 and a bottom surface 22 opposite to the top surface 21, and defines a single via 23. The upper conductive structure 2 includes multiple dielectric layers (e.g., two first dielectric layers 20 and one second dielectric layer 26), multiple circuit layers (e.g., three first circuit layers 24 and one second circuit layer 28), and at least one internal via 25. The dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) are stacked on top of each other. For example, the second dielectric layer 26 is disposed on the first dielectric layer 20, and therefore, the second dielectric layer 26 is the topmost dielectric layer. In one embodiment, the material of the dielectric layer (e.g., the first dielectric layer 20 and the second dielectric layer 26) is transparent and can be seen through by the human eye or a machine. That is, the markings set on the bottom surface 22 adjacent to the upper conductive structure 2 can be identified or detected by the human eye or a machine from the top surface 21 of the upper conductive structure 2.

[0081] Furthermore, each of the first dielectric layers 20 has a top surface 201 and a bottom surface 202 opposite to the top surface 201, and defines a via 203 having an inner surface 2031. The second dielectric layer 26 has a top surface 261 and a bottom surface 262 opposite to the top surface 261, and defines a via 263 having an inner surface 2631. The bottom surface 262 of the second dielectric layer 26 is disposed on and in contact with the top surface 201 of the first dielectric layer 20. Therefore, the top surface 21 of the upper conductive structure 2 is the top surface 261 of the second dielectric layer 26, and the bottom surface 22 of the upper conductive structure 2 is the bottom surface 202 of the bottommost first dielectric layer 20.

[0082] like Figure 1As shown, each via 203 of the first dielectric layer 20 gradually narrows downwards, meaning the top portion of the via 203 is larger than the bottom portion. The via 263 of the second dielectric layer 26 also gradually narrows downwards, meaning the top portion of the via 263 is larger than the bottom portion. Furthermore, the via 263 of the second dielectric layer 26 is aligned with and communicates with the via 203 of the first dielectric layer 20. The bottom portion of the via 263 of the second dielectric layer 26 is configured to be adjacent to or connected to the top portion of the via 203 of the first dielectric layer 20 beneath the second dielectric layer 26. The size of the bottom portion of the via 263 of the second dielectric layer 26 is substantially equal to the size of the top portion of the via 203 of the first dielectric layer 20 beneath the second dielectric layer 26. Therefore, the inner surface 2631 of the via 263 of the second dielectric layer 26 is coplanar with or aligned with the inner surface 2031 of the via 203 of the first dielectric layer 20. It should be noted that the aforementioned "coplanar" surfaces do not necessarily need to be flat. In one embodiment, the inner surface 2631 of the via 263 of the second dielectric layer 26 and the inner surface 2031 of the via 203 of the first dielectric layer 20 are curved surfaces and are part of the inner surface 231 of the large single via 23 for accommodating the external via 14. The via 263 of the second dielectric layer 26 and the via 203 of the first dielectric layer 20 are configured together as part of the single via 23. Figure 1 As shown, the cross-sections of the inner surface 2631 of the via 263 in the second dielectric layer 26 and one side of the inner surface 2031 of the via 203 in the first dielectric layer 20 are substantially straight line segments. That is, the cross-sections of the inner surface 2631 of the via 263 in the second dielectric layer 26 and one side of the inner surface 2031 of the via 203 in the first dielectric layer 20 can extend along the same substantially straight line. A single via 23 penetrates the upper conductive structure 2; that is, the single via 23 extends from the top surface 21 of the upper conductive structure 2 to the bottom surface 22 of the upper conductive structure 2. The single via 23 gradually narrows downwards.

[0083] The first circuit layer 24 may be a fan-out circuit layer, and the L / S ratio of the first circuit layer 24 may be less than or equal to 2μm / 2μm, or less than or equal to 1.8μm / 1.8μm. Each first circuit layer 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. In one embodiment, the first circuit layer 24 is embedded in the first dielectric layer 20, and the top surface 241 of the first circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. In one embodiment, the first circuit layer 24 may include a seed layer 243 and a conductive metal material disposed on the seed layer 243. Figure 1As shown, the bottommost first circuit layer 24 is disposed on the bottom surface 22 of the upper conductive structure 2 (i.e., the bottom surface 202 of the bottommost first dielectric layer 20) and protrudes from the bottom surface 22. Furthermore, the second circuit layer 28 is disposed on the top surface 21 of the upper conductive structure 2 (i.e., the top surface 261 of the second dielectric layer 26) and protrudes from the top surface 21. The L / S ratio of the second circuit layer 28 can be greater than or equal to the L / S ratio of the first circuit layer 24. Figure 1 As shown in the embodiment, there is no horizontal circuit layer in the second dielectric layer 26.

[0084] The upper conductive structure 2 includes a plurality of internal vias 25. Some internal vias 25 are disposed between two first circuit layers 24 to electrically connect the two first circuit layers 24. Some internal vias 25 are disposed between the first circuit layer 24 and the second circuit layer 28 to electrically connect the first circuit layer 24 and the second circuit layer 28. In one embodiment, the internal via 25 may include a seed layer 251 and a conductive metal material disposed on the seed layer 251. In one embodiment, the internal via 25 and the first circuit layer 24 may be integrally formed. The internal via 25 gradually narrows upward. That is, the size (e.g., width) of the top portion of the internal via 25 is smaller than the size (e.g., width) of the bottom portion of the internal via 25. In one embodiment, the maximum width of the internal via 25 may be approximately 25 μm.

[0085] The lower conductive structure 3 includes at least one dielectric layer (including, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) and at least one circuit layer (including, for example, a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a') contacting the dielectric layer (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a). In one embodiment, the lower conductive structure 3 may be similar to a core substrate further including a core portion 37, and may be wafer type, panel type, or strip type. The lower conductive structure 3 has a top surface 31 and a bottom surface 32 opposite to the top surface 31. The lower conductive structure 3 includes multiple dielectric layers (e.g., a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a), multiple circuit layers (e.g., a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a'), and at least one internal via (e.g., multiple upper vias 35 and multiple lower vias 35a).

[0086] The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371, and defines a plurality of through holes 373 extending through the core portion 37. Interconnect vias 39 are disposed or formed in the through holes 373 for vertical interconnection. In one embodiment, the interconnect via 39 includes a base metal layer 391 and an insulating material 392. The base metal layer 391 is disposed or formed on the sidewalls of the through holes 373 and defines a central through hole. The insulating material 392 fills the central through hole defined by the base metal layer 391. In one embodiment, the interconnect via 39 may consist only of a monolithic metal material filling the through hole 373.

[0087] A first upper dielectric layer 30 is disposed on the top surface 371 of the core portion 37, and has a top surface 301 and a bottom surface 302 opposite to the top surface 301. Therefore, the bottom surface 302 of the first upper dielectric layer 30 can contact the top surface 371 of the core portion 37. A second upper dielectric layer 36 is stacked or disposed on the first upper dielectric layer 30, and has a top surface 361 and a bottom surface 362 opposite to the top surface 361. Therefore, the bottom surface 362 of the second upper dielectric layer 36 can contact the top surface 301 of the first upper dielectric layer 30, and the second upper dielectric layer 36 is the topmost dielectric layer. In addition, a first lower dielectric layer 30a is disposed on the bottom surface 372 of the core portion 37, and has a top surface 301a and a bottom surface 302a opposite to the top surface 301a. Therefore, the top surface 301a of the first lower dielectric layer 30a can contact the bottom surface 372 of the core portion 37. A second lower dielectric layer 36a is stacked or disposed on the first lower dielectric layer 30a, and has a top surface 361a and a bottom surface 362a opposite to the top surface 361a. Therefore, the top surface 361a of the second lower dielectric layer 36a can contact the bottom surface 302a of the first lower dielectric layer 30a, and the second lower dielectric layer 36a is the bottommost dielectric layer. Figure 1 As shown, the top surface 31 of the lower conductive structure 3 is the top surface 361 of the second upper dielectric layer 36, and the bottom surface 32 of the lower conductive structure 3 is the bottom surface 362a of the second lower dielectric layer 36a.

[0088] The thickness of the dielectric layer of the upper conductive structure 2 (e.g., the first dielectric layer 20 and the second dielectric layer 26) is less than or equal to 40% of the thickness of the dielectric layer of the lower conductive structure 3 (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a and the second lower dielectric layer 36a). For example, the thickness of the dielectric layer of the upper conductive structure 2 (e.g., the first dielectric layer 20 and the second dielectric layer 26) may be less than or equal to 7 μm, and the thickness of the dielectric layer of the lower conductive structure 3 (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a and the second lower dielectric layer 36a) may be approximately 40 μm.

[0089] The L / S ratio of the first upper circuit layer 34 can be greater than or equal to 10 μm / 10 μm. Therefore, the L / S ratio of the first upper circuit layer 34 can be greater than or equal to five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2. The first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In one embodiment, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37 and is covered by the first upper dielectric layer 30. The bottom surface 342 of the first upper circuit layer 34 can contact the top surface 371 of the core portion 37. In one embodiment, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be made of copper foil. The second metal layer 344 is disposed on the first metal layer 343 and may be an electroplated copper layer. A third metal layer 345 is disposed on the second metal layer 344, and may be an electroplated copper layer. In one embodiment, the third metal layer 345 may be omitted.

[0090] The L / S ratio of the second upper circuit layer 38 can be greater than or equal to 10 μm / 10 μm. Therefore, the L / S ratio of the second upper circuit layer 38 can be substantially equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2. The second upper circuit layer 38 has a top surface 381 and a bottom surface 382 opposite to the top surface 381. In one embodiment, the second upper circuit layer 38 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 and is covered by the second upper dielectric layer 36. The bottom surface 382 of the second upper circuit layer 38 can contact the top surface 301 of the first upper dielectric layer 30. In one embodiment, the second upper circuit layer 38 is electrically connected to the first upper circuit layer 34 through an upper via 35. That is, the upper via 35 is disposed between the second upper circuit layer 38 and the first upper circuit layer 34 to electrically connect the second upper circuit layer 38 and the first upper circuit layer 34. In one embodiment, the second upper circuit layer 38 and the upper via 35 are integrally formed. The upper via 35 gradually narrows downwards.

[0091] In another embodiment, the second upper circuit layer 38' is disposed on the top surface 361 of the second upper dielectric layer 36 and protrudes from the top surface 361. In one embodiment, the second upper circuit layer 38 is electrically connected to the second upper circuit layer 38' through an upper via 35. That is, the upper via 35 is disposed between the two second upper circuit layers 38 and 38' to electrically connect the two second upper circuit layers 38 and 38'. In one embodiment, the second upper circuit layer 38' and the upper via 35 are integrally formed.

[0092] The L / S ratio of the first lower circuit layer 34a can be greater than or equal to 10 μm / 10 μm. Therefore, the L / S ratio of the first lower circuit layer 34a can be greater than or equal to five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2. The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In one embodiment, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37 and is covered by a first lower dielectric layer 30a. The top surface 341a of the first lower circuit layer 34a can contact the bottom surface 372 of the core portion 37. In one embodiment, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a, and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be made of copper foil. The second metal layer 344a is disposed on the first metal layer 343a and may be an electroplated copper layer. The third metal layer 345a is disposed on the second metal layer 344a, and may be an electroplated copper layer. In one embodiment, the third metal layer 345a may be omitted.

[0093] The L / S ratio of the second lower circuit layer 38a can be greater than or equal to 10 μm / 10 μm. Therefore, the L / S ratio of the second lower circuit layer 38a can be substantially equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2. The second lower circuit layer 38a has a top surface 381a and a bottom surface 382a opposite to the top surface 381a. In one embodiment, the second lower circuit layer 38a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a and is covered by the second lower dielectric layer 36a. The top surface 381a of the second lower circuit layer 38a can contact the bottom surface 302a of the first lower dielectric layer 30a. In one embodiment, the second lower circuit layer 38a is electrically connected to the first lower circuit layer 34a through a lower via 35a. That is, the lower via 35a is disposed between the second lower circuit layer 38a and the first lower circuit layer 34a to electrically connect the second lower circuit layer 38a and the first lower circuit layer 34a. In one embodiment, the second lower circuit layer 38a and the lower via 35a are integrally formed. The lower via 35a gradually narrows upwards.

[0094] In another embodiment, the second lower circuit layer 38a' is disposed on the bottom surface 362a of the second lower dielectric layer 36a and protrudes from the bottom surface 362a. In one embodiment, the second lower circuit layer 38a' is electrically connected to the second upper circuit layer 38 through a lower via 35a. That is, the lower via 35a is disposed between the two second lower circuit layers 38a and 38a' to electrically connect the two second lower circuit layers 38a and 38a'. In one embodiment, the second lower circuit layer 38a' and the lower via 35a are integrally formed.

[0095] In one embodiment, the interconnect via 39 electrically connects the first upper circuit layer 34 and the first lower circuit layer 34a. The base metal layer 391 of the interconnect via 39, the second metal layer 344 of the first upper circuit layer 34, and the second metal layer 344a of the first lower circuit layer 34a can be formed integrally and simultaneously.

[0096] An adhesive layer 12 is located between the upper conductive structure 2 and the lower conductive structure 3 to bond the upper conductive structure 2 and the lower conductive structure 3 together. That is, the adhesive layer 12 adheres to the bottom surface 22 of the upper conductive structure 2 and the top surface 31 of the lower conductive structure 3. The adhesive layer 12 has a top surface 121 and a bottom surface 122 opposite to the top surface 121, and defines at least one through-hole 123 having an inner surface 1231. The top surface 121 of the adhesive layer 12 is in contact with the bottom surface 22 of the upper conductive structure 2 (that is, the bottom surface 22 of the upper conductive structure 2 is attached to the top surface 121 of the adhesive layer 12), and the bottom surface 122 of the adhesive layer 12 is in contact with the top surface 31 of the lower conductive structure 3. Therefore, the bottommost first circuit layer 24 of the upper conductive structure 2 and the second upper circuit layer 38' of the lower conductive structure 3 are embedded in the adhesive layer 12. In one embodiment, the bonding force between the two dielectric layers (e.g., the two first dielectric layers 20) of the upper conductive structure 2 is greater than the bonding force between the dielectric layer (e.g., the bottom first dielectric layer 20) of the upper conductive structure 2 and the adhesive layer 12. The surface roughness of the boundary between the two dielectric layers (e.g., the two first dielectric layers 20) of the upper conductive structure 2 is greater than the surface roughness of the boundary between the dielectric layer (e.g., the bottom first dielectric layer 20) of the upper conductive structure 2 and the adhesive layer 12.

[0097] In one embodiment, the material of the adhesive layer 12 is transparent and can be seen through by the human eye or a machine. That is, the markings set on the top surface 31 adjacent to the lower conductive structure 3 can be identified or detected by the human eye or a machine from the top surface 21 of the upper conductive structure 2.

[0098] The via 123 penetrates the adhesive layer 12. In one embodiment, the via 123 of the adhesive layer 12 penetrates the bottommost first circuit layer 24 of the upper conductive structure 2 and stops at the topmost circuit layer (i.e., the second upper circuit layer 38') of the lower conductive structure 3. That is, the via 123 of the adhesive layer 12 does not penetrate the topmost circuit layer (i.e., the second upper circuit layer 38') of the lower conductive structure 3. The via 123 of the adhesive layer 12 may expose a portion of the topmost circuit layer (i.e., the top surface of the second upper circuit layer 38') of the lower conductive structure 3. Figure 1As shown, the via 123 of the adhesive layer 12 gradually narrows downwards, meaning that the size of the top portion of the via 123 is larger than the size of the bottom portion. Furthermore, the via 123 of the adhesive layer 12 is aligned with and communicates with the via 203 of the first dielectric layer 20 and the via 263 of the second dielectric layer 26. The bottom portion of the via 203 of the bottommost first dielectric layer 20 is positioned adjacent to or connected to the top portion of the via 123 of the adhesive layer 12. The size of the bottom portion of the via 203 of the bottommost first dielectric layer 20 is substantially equal to the size of the top portion of the via 123 of the adhesive layer 12. Therefore, the inner surface 1231 of the via 123 of the adhesive layer 12 is coplanar or aligned with the inner surface 2031 of the via 203 of the first dielectric layer 20 and the inner surface 2631 of the via 263 of the second dielectric layer 26. In one embodiment, the inner surface 1231 of the through-hole 123 of the adhesive layer 12 is a curved surface and is part of the inner surface 231 of a large single through-hole 23 for receiving the external via 14. The through-hole 123 of the adhesive layer 12, the through-hole 203 of the first dielectric layer 20, and the through-hole 263 of the second dielectric layer 26 are collectively configured as a single through-hole 23. Therefore, the single through-hole 23 includes the through-hole 123 of the adhesive layer 12, the through-hole 203 of the first dielectric layer 20, and the through-hole 263 of the second dielectric layer 26.

[0099] like Figure 1 As shown, the cross-sections of one side of the via 123 of the adhesive layer 12, the inner surface 2031 of the via 203 of the first dielectric layer 20, and the inner surface 2631 of the via 263 of the second dielectric layer 26 are substantially straight line segments. That is, the cross-sections of one side of the inner surface 1231 of the via 123 of the adhesive layer 12, the inner surface 2031 of the via 203 of the first dielectric layer 20, and the inner surface 2631 of the via 263 of the second dielectric layer 26 can extend along the same substantially straight line. A single via 23 penetrates the upper conductive structure 2 and the adhesive layer 12; that is, a single via 23 extends from the top surface 21 of the upper conductive structure 2 to the bottom portion of the adhesive layer 12 to expose a portion of the topmost circuit layer of the lower conductive structure 3 (i.e., the top surface of the second upper circuit layer 38'). The single via 23 gradually narrows downwards. The maximum width of a single via 23 can be approximately 25 μm to 60 μm.

[0100] An external via 14 is formed or disposed in a single through-hole 23. Therefore, the external via 14 penetrates at least a portion of the upper conductive structure 2 and the adhesive layer 12, and is electrically connected to the topmost circuit layer of the lower conductive structure 3 (i.e., the top surface of the second upper circuit layer 38'). Figure 1As shown, the external via 14 penetrates and contacts the bottommost first circuit layer 24 of the upper conductive structure 2, and stops on and contacts a portion of the topmost circuit layer (i.e., the top surface of the second upper circuit layer 38') of the lower conductive structure 3. The external via 14 extends from the top surface 21 of the upper conductive structure 2 to the bottom surface 122 of the adhesive layer 12. Therefore, the external via 14 extends to contact a portion of the lower conductive structure 3, and the external via 14 does not penetrate the lower conductive structure 3. In addition, the external via 14 gradually narrows downward, that is, the size of the top portion of the external via 14 is larger than the size of the bottom portion of the external via 14. Therefore, the direction of the gradual narrowing of the internal via 25 of the upper conductive structure 2 is different from the direction of the gradual narrowing of the external via 14. In one embodiment, the external via 14 is a monolithic structure or an integral structure, and the surrounding surface of the external via 14 is a substantially continuous plane. The external via 14 and the second circuit layer 28 can be integrally formed.

[0101] like Figure 1 As shown in the embodiment, the wiring structure 1 is a combination of an upper conductive structure 2 and a lower conductive structure 3, wherein the first circuit layer 24 of the upper conductive structure 2 has fine pitch, high yield, and low thickness; and the circuit layers of the lower conductive structure 3 (e.g., a first upper circuit layer 34, second upper circuit layers 38, 38', a first lower circuit layer 34a, and second lower circuit layers 38a, 38a') have low manufacturing cost. Therefore, the wiring structure 1 has an acceptable trade-off between yield and manufacturing cost, and the wiring structure 1 has a relatively low thickness. In one embodiment, if the package has 10,000 I / Os, then the wiring structure 1 only requires three first circuit layers 24 of the upper conductive structure 2 and six circuit layers of the lower conductive structure 3 (e.g., a first upper circuit layer 34, second upper circuit layers 38, 38', a first lower circuit layer 34a, and second lower circuit layers 38a, 38a'). The manufacturing yield of one layer of the first circuit layer 24 of the upper conductive structure 2 can be 99%, and the manufacturing yield of one layer of the circuit layer of the lower conductive structure 3 (e.g., the first upper circuit layer 34, the second upper circuit layers 38, 38', the first lower circuit layer 34a, and the second lower circuit layers 38a, 38a') can be 90%. Therefore, the yield of the wiring structure 1 can be improved. Furthermore, during the manufacturing process, the lower conductive structure 3 and the upper conductive structure 2 can be tested separately before being bonded together. Therefore, only known good lower conductive structures 3 and known good upper conductive structures 2 can be bonded together. Defective (or unqualified) lower conductive structures 3 and defective (or unqualified) upper conductive structures 2 can be discarded. Therefore, the yield of the wiring structure 1 can be further improved.

[0102] Figure 2A cross-sectional view of a wiring structure 1a, representing some embodiments of this disclosure, is shown. The wiring structure 1a is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2a and the lower conductive structure 3a. For example... Figure 2 As shown, both the upper conductive structure 2a and the lower conductive structure 3a are strip structures. Therefore, the wiring structure 1a is a strip structure. In one embodiment, the lower conductive structure 3a may be a panel structure carrying multiple strip upper conductive structures 2a. Therefore, the wiring structure 1a is a panel structure. The upper conductive structure 2a has at least one chip bonding region 41 for receiving at least one semiconductor chip 42. Figure 3 Furthermore, from a top view, the length (e.g., 240 mm) of the upper conductive structure 2a is greater than its width (e.g., 95 mm). Additionally, from a top view, the length of the lower conductive structure 3a is greater than its width. Furthermore, the lateral peripheral surface 27 of the upper conductive structure 2a is not coplanar with the lateral peripheral surface 33 of the lower conductive structure 3a. In one embodiment, during the manufacturing process, both the lower conductive structure 3a and the upper conductive structure 2a can be known good strip structures. Alternatively, the upper conductive structure 2a can be a known good strip structure, and the lower conductive structure 3a can be a known good panel structure. Therefore, the yield of the wiring structure 1a can be further improved.

[0103] like Figure 2 As shown, the upper conductive structure 2a has at least one fiducial mark 43 at its corner, and the lower conductive structure 3a has at least one fiducial mark 45 at its corner. During the manufacturing process, the fiducial mark 43 of the upper conductive structure 2a is aligned with the fiducial mark 45 of the lower conductive structure 3a to determine the relative positions of the upper conductive structure 2a and the lower conductive structure 3a. In one embodiment, the fiducial mark 43 of the upper conductive structure 2a is disposed on the bottom surface 22 of the upper conductive structure 2a (i.e., the bottom surface 202 of the bottommost first dielectric layer 20) and protrudes from the bottom surface 22. The fiducial mark 43 and the bottommost first circuit layer 24 may be on the same layer and may be formed simultaneously. In addition, the fiducial mark 45 of the lower conductive structure 3a is disposed on the top surface 31 of the lower conductive structure 3a (i.e., the top surface 361 of the second upper dielectric layer 36) and protrudes from the top surface 31. The fiducial mark 45 and the second upper circuit layer 38' may be on the same layer and may be formed simultaneously.

[0104] Figure 2A A top view showing an example of a reference mark 43a of the upper conductive structure 2a according to some embodiments of the present disclosure. The reference mark 43a of the upper conductive structure 2a is cross-shaped.

[0105] Figure 2B This is a top view showing an example of a reference mark 45a of the lower conductive structure 3a according to some embodiments of the present disclosure. The reference mark 45a of the lower conductive structure 3a includes four squares at the four corners.

[0106] Figure 2C show Figure 2A The reference mark 43a of the upper conductive structure 2a and Figure 2B The combined image is a top view of the reference mark 45a of the lower conductive structure 3a. When the upper conductive structure 2a is precisely aligned with the lower conductive structure 3a, the combined image shows the complete reference mark 43a and the complete reference mark 45a, as shown. Figure 2C As shown. That is to say, reference mark 43a does not cover reference mark 45a.

[0107] Figure 2D This is a top view showing an example of a reference mark 43b of the upper conductive structure 2a according to some embodiments of the present disclosure. The reference mark 43b of the upper conductive structure 2a is an inverted "L" shape.

[0108] Figure 2E A top view showing an example of a reference mark 45b of the lower conductive structure 3a according to some embodiments of the present disclosure. The reference mark 45b of the lower conductive structure 3a is a substantially inverted "L" shape equal to the reference mark 43b of the upper conductive structure 2a.

[0109] Figure 2F show Figure 2D The reference mark 43b of the upper conductive structure 2a and Figure 2E The combined image is a top view of the reference mark 45b of the lower conductive structure 3a. When the upper conductive structure 2a and the lower conductive structure 3a are precisely aligned, the combined image only shows the reference mark 43b of the upper conductive structure 2a, as shown. Figure 2F As shown. That is to say, reference mark 43b completely covers reference mark 45b.

[0110] Figure 2G A top view showing an example of a reference mark 43c of the upper conductive structure 2a according to some embodiments of this disclosure. The reference mark 43c of the upper conductive structure 2a is a circle.

[0111] Figure 2H This is a top view showing an example of a reference mark 45c of the lower conductive structure 3a according to some embodiments of the present disclosure. The reference mark 45c of the lower conductive structure 3a is a circle larger than the reference mark 43c of the upper conductive structure 2a.

[0112] Figure 2I show Figure 2GThe reference mark 43c of the upper conductive structure 2a and Figure 2H A top view of the combined image of the reference mark 45c of the lower conductive structure 3a. When the upper conductive structure 2a and the lower conductive structure 3a are precisely aligned, the combined image shows two concentric circles, as... Figure 2I As shown. That is, the reference mark 43c is set at the center of the reference mark 45c.

[0113] Figure 3 A cross-sectional view showing the bonding of package structure 4 and substrate 46. Package structure 4 includes wiring structure 1b, semiconductor chip 42, multiple first connection elements 44 and multiple second connection elements 48. Figure 3 The wiring structure 1b is similar to Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2b and the lower conductive structure 3b. Both the upper conductive structure 2b and the lower conductive structure 3b are dies and can be individually divided simultaneously. Therefore, wiring structure 1b is a unitary structure. That is, the lateral peripheral surface 27b of the upper conductive structure 2b, the lateral peripheral surface 33b of the lower conductive structure 3b, and the lateral peripheral surface of the adhesive layer 12 are substantially coplanar with each other. The semiconductor chip 42 is electrically connected and bonded to the second circuit layer 28 of the upper conductive structure 2b via a first connecting element 44 (e.g., solder or bump). The second upper circuit layer 38' of the lower conductive structure 3b is electrically connected and bonded to the substrate 46 (e.g., motherboard, such as a PCB board) via a second connecting element 48 (e.g., solder or bump).

[0114] Figure 4 A cross-sectional view of a wiring structure 1c according to some embodiments of the present disclosure is shown. The wiring structure 1c is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2c and the lower conductive structure 3c. In the upper conductive structure 2c, the second dielectric layer 26 is replaced by the topmost first dielectric layer 20, and the second circuit layer 28 is replaced by the topmost first circuit layer 24. The topmost first circuit layer 24 may not include a seed layer and can be electrically connected to the lower first circuit layer 24 through an internal via 25. The top surface 241 of the topmost first circuit layer 24 may be substantially coplanar with the top surface 21 of the upper conductive structure 2c (i.e., the top surface 201 of the topmost first dielectric layer 20). Therefore, the top surface 241 of the topmost first circuit layer 24 can be exposed from the top surface 21 of the upper conductive structure 2c (i.e., the top surface 201 of the topmost first dielectric layer 20). An external via 14 can penetrate and contact the topmost first circuit layer 24. In addition, the bottommost first dielectric layer 20 may cover the bottommost first circuit layer 24. Therefore, the entire bottom surface 22 of the upper conductive structure 2c (i.e., the bottom surface 202 of the bottommost first dielectric layer 20) is substantially flat.

[0115] In the lower conductive structure 3c, the second upper dielectric layer 36 and the second upper circuit layers 38 and 38' are omitted. Therefore, the top surface 31 of the lower conductive structure 3c is the top surface 301 of the first upper dielectric layer 30, which is substantially flat. In addition, it further includes two additional second lower dielectric layers 36a and two additional second lower circuit layers 38a'.

[0116] The adhesive layer 12 adheres to the bottom surface 22 of the upper conductive structure 2c and the top surface 31 of the lower conductive structure 3c. Therefore, the entire top surface 121 and the entire bottom surface 122 of the adhesive layer 12 are substantially flat. The adhesive layer 12 does not include or contact any horizontal circuit layer. That is, no horizontal circuit layer is disposed or embedded in the adhesive layer 12. An external via 14 penetrates the upper conductive structure 2c and the adhesive layer 12, and further extends into a portion of the lower conductive structure 3c (i.e., the first upper dielectric layer 30) to contact the first upper circuit layer 34.

[0117] Figure 5 A cross-sectional view of a wiring structure 1d, representing some embodiments of this disclosure, is shown. The wiring structure 1d is similar to... Figure 4 The wiring structure 1c shown differs in the structure of the upper conductive structure 2d and the lower conductive structure 3d. For example... Figure 5 As shown, both the upper conductive structure 2d and the lower conductive structure 3d are strip structures. Therefore, the wiring structure 1d is a strip structure. In one embodiment, the lower conductive structure 3d can be a panel structure carrying multiple strip upper conductive structures 2d. Therefore, the wiring structure 1d is a panel structure. That is, the upper conductive structure 2d has at least one chip bonding region 41d for receiving at least one semiconductor chip 42. Figure 6 Furthermore, from a top view, the length (e.g., 240 mm) of the upper conductive structure 2d is greater than the width (e.g., 95 mm) of the lower conductive structure 3d. Additionally, from a top view, the length of the lower conductive structure 3d is greater than the width of the lower conductive structure 3d. Furthermore, the lateral peripheral surface 27d of the upper conductive structure 2d is not coplanar with the lateral peripheral surface 33d of the lower conductive structure 3d. In one embodiment, during the manufacturing process, both the lower conductive structure 3d and the upper conductive structure 2d can be known good strip structures. Alternatively, the upper conductive structure 2d can be a known good strip structure, and the lower conductive structure 3d can be a known good panel structure. Therefore, the yield of the wiring structure 1d can be further improved.

[0118] like Figure 5As shown, the upper conductive structure 2d has at least one reference mark 43d at its corner, and the lower conductive structure 3d has at least one reference mark 45d at its corner. During the manufacturing process, the reference mark 43d of the upper conductive structure 2d is aligned with the reference mark 45d of the lower conductive structure 3d to determine the relative positions of the upper conductive structure 2d and the lower conductive structure 3d. In one embodiment, the reference mark 43d and the bottommost first circuit layer 24 may be on the same layer and may be formed simultaneously. Alternatively, the reference mark 45d and the first upper circuit layer 34 may be on the same layer and may be formed simultaneously.

[0119] Figure 6 A cross-sectional view showing the bonding of package structure 4a and substrate 46. Package structure 4a includes wiring structure 1e, semiconductor chip 42, a plurality of first connection elements 44 and a plurality of second connection elements 48. Figure 6 The wiring structure 1e is similar to Figure 4 The wiring structure 1c shown differs in the structure of the upper conductive structure 2e and the lower conductive structure 3e. Both the upper conductive structure 2e and the lower conductive structure 3e are dies and can be individually divided simultaneously. Therefore, the wiring structure 1e is a unitary structure. That is, the lateral peripheral surface 27e of the upper conductive structure 2e, the lateral peripheral surface 33e of the lower conductive structure 3e, and the lateral peripheral surface of the adhesive layer 12 are substantially coplanar with each other. The semiconductor chip 42 is electrically connected and bonded to the topmost first circuit layer 24 of the upper conductive structure 2e via a first connecting element 44 (e.g., solder or bump). The bottommost second upper circuit layer 38' of the lower conductive structure 3e is electrically connected and bonded to the substrate 46 (e.g., motherboard, such as a PCB board) via a second connecting element 48 (e.g., solder or bump).

[0120] Figures 7 to 44 This disclosure illustrates one or more stages of some embodiments of a method for manufacturing wiring structures. In some embodiments, the method is used to manufacture... Figure 1 The wiring structure 1 shown, and / or Figure 3 The encapsulation structure shown is 4.

[0121] refer to Figures 7 to 26 A lower conductive structure 3 is provided. The lower conductive structure 3 is manufactured as follows. (See reference) Figure 7 A core portion 37 is provided, having a top copper foil 50 and a bottom copper foil 52. The core portion 37 can be of wafer type, panel type, or strip type. The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371. The top copper foil 50 is disposed on the top surface 371 of the core portion 37, and the bottom copper foil 52 is disposed on the bottom surface 372 of the core portion 37.

[0122] refer to Figure 8 Multiple through holes 373 are formed by drilling or other suitable techniques to penetrate the core portion 37, the top copper foil 50, and the bottom copper foil 52.

[0123] refer to Figure 9 A second metal layer 54 is formed or disposed on the sidewalls of the top copper foil 50, the bottom copper foil 52, and the through hole 373 by electroplating or other suitable techniques. A portion of the second metal layer 54 on the sidewall of the through hole 373 defines the central through hole.

[0124] refer to Figure 10 The insulating material 392 is filled into the central through hole defined by the second metal layer 54.

[0125] refer to Figure 11 The top third metal layer 56 and the bottom third metal layer 56a are formed or disposed on the second metal layer 54 by electroplating or other suitable techniques. The third metal layers 56 and 56a cover the insulating material 392.

[0126] refer to Figure 12 A top photoresist layer 57 is formed or disposed on a top third metal layer 56, and a bottom photoresist layer 57a is formed or disposed on a bottom third metal layer 56a. Subsequently, the photoresist layers 57 and 57a are patterned by exposure and development.

[0127] refer to Figure 13 The portions of the top copper foil 50, second metal layer 54, and top third metal layer 56 not covered by the top photoresist layer 57 are removed using etching or other suitable techniques. The portions of the top copper foil 50, second metal layer 54, and top third metal layer 56 covered by the top photoresist layer 57 are retained to form the first upper circuit layer 34. Simultaneously, the portions of the bottom copper foil 52, second metal layer 54, and bottom third metal layer 56a not covered by the bottom photoresist layer 57a are removed using etching or other suitable techniques. The portions of the bottom copper foil 52, second metal layer 54, and bottom third metal layer 56a covered by the bottom photoresist layer 57a are retained to form the first lower circuit layer 34a. Meanwhile, portions of the second metal layer 54 and insulating material 392 disposed in the via 373 form interconnect vias 39. Figure 13As shown, the first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In one embodiment, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37. The bottom surface 342 of the first upper circuit layer 34 is in contact with the top surface 371 of the core portion 37. In one embodiment, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be made of a top copper foil 50. The second metal layer 344 is disposed on the first metal layer 343 and may be an electroplated copper layer made of the second metal layer 54. The third metal layer 345 is disposed on the second metal layer 344 and may be an electroplated copper layer made of a top third metal layer 56.

[0128] The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In one embodiment, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37. The top surface 341a of the first lower circuit layer 34a is accessible to the bottom surface 372 of the core portion 37. In one embodiment, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a, and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be made of bottom copper foil 52. The second metal layer 344a is disposed on the first metal layer 343a and may be an electroplated copper layer made of the second metal layer 54. The third metal layer 345a is disposed on the second metal layer 344a and may be an electroplated copper layer made of bottom third metal layer 56a. The interconnect via 39 includes a base metal layer 391 made of the second metal layer 54 and an insulating material 392. In one embodiment, the interconnect via 39 may consist solely of a monolithic metal material filling the via 373. The interconnect via 39 electrically connects the first upper circuit layer 34 and the first lower circuit layer 34a.

[0129] refer to Figure 14 The top photoresist layer 57 and the bottom photoresist layer 57a are removed by stripping techniques or other suitable techniques.

[0130] refer to Figure 15 A first upper dielectric layer 30 is formed or disposed on the top surface 371 of the core portion 37 using lamination technology or other suitable techniques, to cover the top surface 371 of the core portion 37 and the first upper circuit layer 34. Simultaneously, a first lower dielectric layer 30a is formed or disposed on the bottom surface 372 of the core portion 37 using lamination technology or other suitable techniques, to cover the bottom surface 372 of the core portion 37 and the first lower circuit layer 34a.

[0131] refer to Figure 16At least one via 303 is formed by drilling or other suitable techniques to penetrate the first upper dielectric layer 30 and expose a portion of the first upper circuit layer 34. Simultaneously, at least one via 303a is formed by drilling or other suitable techniques to penetrate the first lower dielectric layer 30a and expose a portion of the first lower circuit layer 34a.

[0132] refer to Figure 17 A top metal layer 58 is formed on the first upper dielectric layer 30 and in the via 303 using electroplating or other suitable techniques to form an upper via 35. Simultaneously, a bottom metal layer 60 is formed on the first lower dielectric layer 30a and in the via 303a using electroplating or other suitable techniques to form a lower via 35a. Figure 17 As shown, the upper guide hole 35 gradually narrows downwards, and the lower guide hole 35a gradually narrows upwards.

[0133] refer to Figure 18 A top photoresist layer 59 is formed or disposed on a top metal layer 58, and a bottom photoresist layer 59a is formed or disposed on a bottom metal layer 60. Subsequently, the photoresist layers 59 and 59a are patterned by exposure and development.

[0134] refer to Figure 19 The portion of the top metal layer 58 not covered by the top photoresist layer 59 is removed using etching or other suitable techniques. The portion of the top metal layer 58 covered by the top photoresist layer 59 is retained to form the second upper circuit layer 38. Simultaneously, the portion of the bottom metal layer 60 not covered by the bottom photoresist layer 59a is removed using etching or other suitable techniques. The portion of the bottom metal layer 60 covered by the bottom photoresist layer 59a is retained to form the second lower circuit layer 38a.

[0135] refer to Figure 20 The top photoresist layer 59 and the bottom photoresist layer 59a are removed by stripping techniques or other suitable techniques.

[0136] refer to Figure 21 A second upper dielectric layer 36 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 using lamination technology or other suitable techniques, to cover the top surface 301 of the first upper dielectric layer 30 and the second upper circuit layer 38. Simultaneously, a second lower dielectric layer 36a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a using lamination technology or other suitable techniques, to cover the bottom surface 302a of the first lower dielectric layer 30a and the second lower circuit layer 38a.

[0137] refer to Figure 22At least one via 363 is formed by drilling or other suitable techniques to penetrate the second upper dielectric layer 36 and expose a portion of the second upper circuit layer 38. Simultaneously, at least one via 363a is formed by drilling or other suitable techniques to penetrate the second lower dielectric layer 36a and expose a portion of the second lower circuit layer 38a.

[0138] refer to Figure 23 A top metal layer 62 is formed on the second upper dielectric layer 36 and in the via 363 by electroplating or other suitable techniques to form an upper via 35. Simultaneously, a bottom metal layer 64 is formed on the second lower dielectric layer 36a and in the via 363a by electroplating or other suitable techniques to form a lower via 35a.

[0139] refer to Figure 24 A top photoresist layer 63 is formed or disposed on a top metal layer 62, and a bottom photoresist layer 63a is formed or disposed on a bottom metal layer 64. Subsequently, the photoresist layers 63 and 63a are patterned by exposure and development.

[0140] refer to Figure 25 The portion of the top metal layer 62 not covered by the top photoresist layer 63 is removed using etching or other suitable techniques. The portion of the top metal layer 62 covered by the top photoresist layer 63 is retained to form the second upper circuit layer 38'. Simultaneously, the portion of the bottom metal layer 64 not covered by the bottom photoresist layer 63a is removed using etching or other suitable techniques. The portion of the bottom metal layer 64 covered by the bottom photoresist layer 63a is retained to form the second lower circuit layer 38a'.

[0141] refer to Figure 26 The top photoresist layer 63 and the bottom photoresist layer 63a are removed using a stripping technique or other suitable technique. Simultaneously, the lower conductive structure 3 is formed, and dielectric layers (including a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) are cured. Subsequently, the electrical characteristics of the lower conductive structure 3 are tested (e.g., open circuit / short circuit).

[0142] refer to Figures 27 to 37 An upper conductive structure 2 is provided. The upper conductive structure 2 is manufactured as follows. (See reference...) Figure 27 A carrier 65 is provided. The carrier 65 can be a glass carrier and can be of wafer type, panel type or strip type.

[0143] refer to Figure 28 A release layer 66 is coated on the bottom surface of the carrier 65.

[0144] refer to Figure 29A conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 by physical vapor deposition (PVD) or other suitable techniques.

[0145] refer to Figure 30 A second dielectric layer 26 is formed on the conductive layer 67 by coating technology or other suitable technology.

[0146] refer to Figure 31 At least one via 264 is formed by exposure and development techniques or other suitable techniques to penetrate the second dielectric layer 26 and expose a portion of the conductive layer 67.

[0147] refer to Figure 32 A seed layer 68 is formed on the bottom surface 262 of the second dielectric layer 26 and in the via 264 by physical vapor deposition (PVD) or other suitable techniques.

[0148] refer to Figure 33 A photoresist layer 69 is formed on the seed layer 68. Subsequently, the photoresist layer 69 is patterned using exposure and development techniques or other suitable techniques to expose portions of the seed layer 68. The photoresist layer 69 defines a plurality of openings 691. Some of the openings 691 in the photoresist layer 69 correspond to vias 264 in the second dielectric layer 26.

[0149] refer to Figure 34 Conductive metal material 70 is formed in the opening 691 of the photoresist layer 69 and on the seed layer 68 by electroplating or other suitable techniques.

[0150] refer to Figure 35 The photoresist layer 69 is removed by stripping or other suitable techniques.

[0151] refer to Figure 36 The portion of the seed layer 68 not covered by the conductive metal material 70 is removed by etching or other suitable techniques. Simultaneously, a first circuit layer 24 and at least one internal via 25 are formed. The first circuit layer 24 may be a fan-out circuit layer, and the L / S ratio of the first circuit layer 24 may be less than or equal to 2μm / 2μm, or less than or equal to 1.8μm / 1.8μm. The first circuit layer 24 is disposed on the bottom surface 262 of the second dielectric layer 26. In one embodiment, the first circuit layer 24 may include a seed layer 243 made of the seed layer 68 and a conductive metal material disposed on the seed layer 243. The internal via 25 is disposed in a via 264 of the second dielectric layer 26. In one embodiment, the internal via 25 may include a seed layer 251 and a conductive metal material disposed on the seed layer 251. The internal via 25 gradually narrows upwards.

[0152] refer to Figure 37 By repeating Figures 30 to 36In this stage, multiple first dielectric layers 20 and multiple first circuit layers 24 are formed. In one embodiment, the first circuit layer 24 is embedded in the first dielectric layer 20, and the top surface 241 of the first circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. At this time, the upper conductive structure 2 is formed, and the dielectric layers (including the first dielectric layer 20 and the second dielectric layer 26) are cured. Subsequently, the electrical characteristics of the upper conductive structure 2 are tested (e.g., open circuit / short circuit).

[0153] refer to Figure 38 An adhesive layer 12 is formed or disposed on the top surface 31 of the lower conductive structure 3.

[0154] refer to Figure 39 The upper conductive structure 2 is attached to the lower conductive structure 3 via an adhesive layer 12. In one embodiment, a known good upper conductive structure 2 is attached to a known good lower conductive structure 3. The adhesive layer 12 is then cured. In one embodiment, the upper conductive structure 2 can be pressed against the lower conductive structure 3. Therefore, the thickness of the adhesive layer 12 is determined by the gap between the upper conductive structure 2 and the lower conductive structure 3. The top surface 121 of the adhesive layer 12 is in contact with the bottom surface 22 of the upper conductive structure 2 (that is, the bottom surface 22 of the upper conductive structure 2 is attached to the top surface 121 of the adhesive layer 12), and the bottom surface 122 of the adhesive layer 12 is in contact with the top surface 31 of the lower conductive structure 3. Therefore, the bottommost first circuit layer 24 of the upper conductive structure 2 and the second upper circuit layer 38' of the lower conductive structure 3 are embedded in the adhesive layer 12. In one embodiment, the bonding force between the two dielectric layers (e.g., the two first dielectric layers 20) of the upper conductive structure 2 is greater than the bonding force between the dielectric layer (e.g., the bottom first dielectric layer 20) of the upper conductive structure 2 and the adhesive layer 12. The surface roughness of the boundary between the two dielectric layers (e.g., the two first dielectric layers 20) of the upper conductive structure 2 is greater than the surface roughness of the boundary between the dielectric layer (e.g., the bottom first dielectric layer 20) of the upper conductive structure 2 and the adhesive layer 12.

[0155] refer to Figure 40 Remove the carrier 65, release layer 66 and conductive layer 67 to expose a portion of the internal via 25.

[0156] refer to Figure 41At least one through-hole 23 is formed by drilling to penetrate at least a portion of the upper conductive structure 2 and the adhesive layer 12, exposing the circuit layer of the lower conductive structure 3 (i.e., the second upper circuit layer 38'). The through-hole 23 may include through-holes 263 of the second dielectric layer 26, multiple through-holes 203 of the first dielectric layer 20, and through-holes 123 of the adhesive layer 12. In one embodiment, the through-hole 23 penetrates the bottommost first circuit layer 24 of the upper conductive structure 2 and stops at the topmost circuit layer of the lower conductive structure 3 (i.e., the second upper circuit layer 38'). That is, the through-hole 23 does not penetrate the topmost circuit layer of the lower conductive structure 3 (i.e., the second upper circuit layer 38'). The through-hole 23 may expose a portion of the topmost circuit layer of the lower conductive structure 3 (i.e., the top surface of the second upper circuit layer 38'). Figure 41 As shown, the via 23 gradually narrows downwards, meaning that the size of the top portion of the via 23 is larger than the size of the bottom portion. Furthermore, the inner surface 1231 of the via 123 in the adhesive layer 12 is coplanar or aligned with the inner surface 2031 of the via 203 in the first dielectric layer 20 and the inner surface 2631 of the via 263 in the second dielectric layer 26. Therefore, the cross-sections on one side of the via 123 in the adhesive layer 12, the inner surface 2031 of the via 203 in the first dielectric layer 20, and the inner surface 2631 of the inner surface 263 in the second dielectric layer 26 are substantially straight line segments. That is, the cross-sections on one side of the inner surface 1231 of the via 123 in the adhesive layer 12, the inner surface 2031 of the via 203 in the first dielectric layer 20, and the inner surface 2631 of the inner surface 263 in the second dielectric layer 26 can extend along the same substantially straight line. In other words, the inner surface of a single via 23 can be a substantially smooth or continuous surface. The individual via 23 gradually narrows downwards. The maximum width of an individual via 23 can be approximately 25 μm to 60 μm.

[0157] refer to Figure 42 A metal layer 72 is formed on the top surface 21 of the upper conductive structure 2 and in the through hole 23 by electroplating or other suitable techniques, so as to form at least one external guide hole 14 in the through hole 23.

[0158] refer to Figure 43 A top photoresist layer 73 is formed or disposed on the metal layer 72, and a bottom photoresist layer 73a is formed or disposed on the bottom surface 32 of the lower conductive structure 3. Subsequently, the top photoresist layer 73 is patterned by exposure and development techniques or other suitable techniques.

[0159] refer to Figure 44The portion of the metal layer 72 not covered by the top photoresist layer 73 is removed using etching or other suitable techniques. The portion of the metal layer 72 covered by the top photoresist layer 73 is retained to form the second circuit layer 28. Subsequently, the top photoresist layer 73 and the bottom photoresist layer 73a are removed using stripping or other suitable techniques to obtain... Figure 1 Wiring structure 1.

[0160] In one embodiment, semiconductor chip 42 ( Figure 3 The second circuit layer 28 of the upper conductive structure 2 is electrically connected and bonded to it via multiple first connecting elements 44 (e.g., solder or bumps). Subsequently, the upper conductive structure 2, the adhesive layer 12, and the lower conductive structure 3 are simultaneously separated to form... Figure 3 The package structure 4 shown is a wiring structure 1b and a semiconductor chip 42. Figure 3 The wiring structure 1b includes a monomerized upper conductive structure 2b and a monomerized lower conductive structure 3b. That is, the lateral peripheral surface 27b of the upper conductive structure 2b, the lateral peripheral surface 33b of the lower conductive structure 3b, and the lateral peripheral surface of the adhesive layer 12 are substantially coplanar with each other. Subsequently, the second upper circuit layer 38' of the lower conductive structure 3b is electrically connected and bonded to the substrate 46 (e.g., motherboard, such as a PCB board) via a second connecting element 48 (e.g., solder or bump).

[0161] Figures 45 to 48 This disclosure illustrates one or more stages of some embodiments of a method for manufacturing wiring structures. In some embodiments, the method is used for manufacturing... Figure 2 The wiring structure 1a is shown. The initial stage of the process described is related to... Figures 7 to 37 The stages described are the same or similar. Figure 45 Depicting Figure 37 The stage following the stage described.

[0162] refer to Figure 45 Simultaneously, a reference mark 43 and a bottom first circuit layer 24 are formed, and the two are on the same layer. Therefore, the reference mark 43 is disposed on the bottom surface 22 of the upper conductive structure 2 and protrudes from the bottom surface 22. Subsequently, the upper conductive structure 2, the carrier 65, the release layer 66, and the conductive layer 67 are simultaneously cut to form a plurality of strips 2'. Each strip 2' includes an upper conductive structure 2a that is a strip structure. Subsequently, the strips 2' are tested. Alternatively, the upper conductive structure 2 can be tested before the cutting process.

[0163] refer to Figure 46Simultaneously, a reference mark 45 and a second upper circuit layer 38' are formed, and the two are on the same layer. Therefore, the reference mark 45 is provided on the top surface 31 of the lower conductive structure 3 and protrudes from the top surface 31. The lower conductive structure 3 has multiple strip regions 3'. Subsequently, the strip regions 3' are tested. Subsequently, an adhesive layer 12 is formed or provided on the top surface 31 of the lower conductive structure 3.

[0164] refer to Figure 47 The upper conductive structure 2a is attached to the strip region 3' of the lower conductive structure 3 via an adhesive layer 12. The upper conductive structure 2a faces and is attached to the lower conductive structure 3. During the attachment process, the reference mark 43 of the upper conductive structure 2a is aligned with the reference mark 45 of the lower conductive structure 3 to determine the relative positions of the upper conductive structure 2a and the lower conductive structure 3. In one embodiment, only known good strips 2' are attached to the known good strip region 3' of the lower conductive structure 3. For example, wiring structure 1a ( Figure 2 The desired yield can be set to 80%. That is, (yield of the upper conductive structure 2a) * (yield of the strip region 3' of the lower conductive structure 3) must be greater than or equal to 80%. If the yield of the upper conductive structure 2a (or strip 2') is less than the predetermined yield, for example, 80% (which is defined as a defective or unqualified component), then the defective (or unqualified) upper conductive structure 2a (or strip 2') is discarded. If the yield of the upper conductive structure 2a (or strip 2') is greater than the predetermined yield, for example, 80% (which is defined as a known good or qualified component), then a known good upper conductive structure 2a (or strip 2') can be used. Additionally, if the yield of the strip region 3' of the lower conductive structure 3 is less than the predetermined yield, for example, 80% (which is defined as a defective or unqualified component), then the defective (or unqualified) strip region 3' is marked and will not be bonded to any strip 2'. If the yield of the strip region 3' of the lower conductive structure 3 is greater than a predetermined yield, for example, 80% (which is defined as a known good component or a qualified component), then a known good upper conductive structure 2a (or strip 2') can be bonded to the known good strip region 3' of the lower conductive structure 3. It should be noted that an upper conductive structure 2a (or strip 2') with a yield of 80% cannot be bonded to the strip region 3' of the lower conductive structure 3 with a yield of 80%, because the wiring structure 1a ( Figure 2 The yield obtained is 64%, which is lower than the expected yield of 80%. The upper conductive structure 2a (or strip 2') with an 80% yield must be bonded to the strip region 3' of the lower conductive structure 3 with a 100% yield. Therefore, the wiring structure 1a ( Figure 2The yield obtained can be 80%. Additionally, the upper conductive structure 2a (or strip 2') with a yield of 90% can be bonded to the strip region 3' of the lower conductive structure 3 with a yield greater than 90%, because the wiring structure 1a ( Figure 2 The yield rate can be greater than 80%.

[0165] refer to Figure 48 The adhesive layer 12 is then cured. Subsequently, the carrier 65, release layer 66, and conductive layer 67 are removed. Figure 48 The stages described are similar to the stages that follow. Figures 41 to 44 The stages depicted. Subsequently, the lower conductive structure 3 and adhesive layer 12 are cut along the strip region 3' to obtain Figure 2 Wiring structure 1a.

[0166] Figures 49 to 59 This disclosure illustrates one or more stages of some embodiments of a method for manufacturing wiring structures. In some embodiments, the method is used for manufacturing... Figure 4 The wiring structure 1c shown. The initial stage of the process described is related to... Figures 7 to 15 The stages described are the same or similar. Figure 49 Depicting Figure 15 The stage following the stage described.

[0167] refer to Figures 49 to 51 A lower conductive structure 3c is provided. The lower conductive structure 3c is manufactured as follows. (Reference) Figure 49 At least one via 303a is formed by drilling or other suitable techniques to penetrate the first lower dielectric layer 30a and expose a portion of the first lower circuit layer 34a. It should be noted that no vias are formed on the first upper dielectric layer 30.

[0168] refer to Figure 50 A second lower circuit layer 38a is formed or disposed on the first lower dielectric layer 30a. Subsequently, three second lower dielectric layers 36a and two second lower circuit layers 38a' are formed or disposed on the first lower dielectric layer 30a.

[0169] refer to Figure 51 A bottom lower circuit layer 38a' is formed or disposed on the bottom second lower dielectric layer 36a to obtain a lower conductive structure 3c. In the lower conductive structure 3c, the top surface 31 of the lower conductive structure 3c is the top surface 301 of the first upper dielectric layer 30, which is substantially flat.

[0170] refer to Figures 52 to 55 An upper conductive structure 2c is provided. The upper conductive structure 2c is manufactured as follows. (See reference) Figure 52A carrier 65 is provided. A release layer 66 is coated on the bottom surface of the carrier 65. A conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 by physical vapor deposition (PVD) or other suitable techniques. Subsequently, a topmost first circuit layer 24 is formed on the conductive layer 67.

[0171] refer to Figure 53 The topmost first dielectric layer 20 is formed on the conductive layer 67 by coating technology or other suitable technology to cover the topmost first circuit layer 24.

[0172] refer to Figure 54 At least one via 204 is formed by exposure and development techniques or other suitable techniques to penetrate the first dielectric layer 20 and expose a portion of the conductive layer 67.

[0173] refer to Figure 55 Multiple first dielectric layers 20, multiple first circuit layers 24, and multiple internal vias 25 are formed on the topmost first dielectric layer 20 to obtain the upper conductive structure 2c. For example... Figure 55 As shown, the bottom first dielectric layer 20 can cover the bottom first circuit layer 24. Therefore, the entire bottom surface 22 of the upper conductive structure 2c (i.e., the bottom surface 202 of the bottom first dielectric layer 20) is substantially flat.

[0174] refer to Figure 56 An adhesive layer 12 is formed or disposed on the top surface 31 of the lower conductive structure 3.

[0175] refer to Figure 57 The upper conductive structure 2c is attached to the lower conductive structure 3c via an adhesive layer 12. In one embodiment, a known good upper conductive structure 2c is attached to a known good lower conductive structure 3c. The adhesive layer 12 is then cured. The adhesive layer 12 adheres to the bottom surface 22 of the upper conductive structure 2c and the top surface 31 of the lower conductive structure 3c. Therefore, the entire top surface 121 and the entire bottom surface 122 of the adhesive layer 12 are substantially flat. The adhesive layer 12 does not include or contact any horizontal circuit layer. That is, no horizontal circuit layer is provided or embedded in the adhesive layer 12.

[0176] refer to Figure 58 Remove the carrier 65, release layer 66, and conductive layer 67 to expose the internal via 25 and a portion of the topmost first dielectric layer 20. The top surface 241 of the topmost first circuit layer 24 may be substantially coplanar with the top surface 201 of the topmost first dielectric layer 20.

[0177] refer to Figure 59At least one through-hole 23 is formed by drilling to penetrate at least a portion of the upper conductive structure 2c, the adhesive layer 12, and a portion of the lower conductive structure 3c (e.g., the first upper dielectric layer 30), exposing the circuit layer of the lower conductive structure 3c (e.g., the first upper circuit layer 34). The through-hole 23 may further penetrate a portion of the topmost first circuit layer 24 of the upper conductive structure 2c. Subsequently, a conductive metal material is formed or disposed in the through-hole 23 to form an external via 14, and to obtain... Figure 4 Wiring structure 1c.

[0178] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” “below,” etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, the limitation being that the advantage of the embodiments of this disclosure is not affected by such arrangement.

[0179] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation clearly occurred and examples in which the event or situation is very close to occurring. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same or equal.

[0180] If the displacement between two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar.

[0181] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple indicators.

[0182] As used herein, the terms “conductive,” “electrically conductive,” and “electrical conductivity” refer to the ability to conduct electric current. Conductive materials are generally those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0183] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0184] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Artistic representations in this disclosure may differ from actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A wiring structure comprising: The upper conductive structure includes multiple dielectric layers, multiple circuit layers, and at least one internal via disposed between two circuit layers to electrically connect the two circuit layers. The internal via gradually narrows upwards, and the material of the multiple dielectric layers is transparent. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; An adhesive layer is located between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together; as well as At least one via penetrates at least a portion of the upper conductive structure and the adhesive layer, and is electrically connected to the circuit layer of the lower conductive structure, the via gradually narrowing downwards; In the lower conductive structure, the line spacing of the circuit layer is greater than or equal to five times the line spacing of the circuit layer of the upper conductive structure, and each of the plurality of dielectric layers of the upper conductive structure defines a via with an inner surface. The adhesive layer defines a via with an inner surface, and the inner surface of the via of the adhesive layer and the inner surface of each via of the plurality of dielectric layers are coplanar with each other. The via of the adhesive layer and the via of the plurality of dielectric layers are configured together to form a single via to accommodate the via, and the material of the adhesive layer is transparent.

2. The wiring structure according to claim 1, wherein the cross-section of the inner surface of the through-hole of the adhesive layer and the inner surface of the through-hole of each of the plurality of dielectric layers is a substantially straight line segment.

3. The wiring structure of claim 1, wherein the via extends to contact a portion of the lower conductive structure.

4. The wiring structure according to claim 1, wherein the via contacts the topmost circuit layer of the lower conductive structure.

5. The wiring structure according to claim 1, wherein the via is a single-piece structure.

6. The wiring structure according to claim 1, wherein the upper conductive structure has a top surface and a bottom surface, the adhesive layer has a top surface and a bottom surface, the bottom surface of the upper conductive structure is attached to the top surface of the adhesive layer, the via extends from the top surface of the upper conductive structure to the bottom surface of the adhesive layer, and the surrounding surface of the via is a substantially continuous plane.

7. The wiring structure of claim 1, wherein the adhesive layer has a top surface and a bottom surface, and the entire top surface and the entire bottom surface of the adhesive layer are substantially flat.

8. The wiring structure according to claim 1, wherein the bonding force between the two dielectric layers of the upper conductive structure is greater than the bonding force between the dielectric layer of the upper conductive structure and the adhesive layer.

9. The wiring structure according to claim 1, wherein the surface roughness of the boundary between the two dielectric layers of the upper conductive structure is greater than the surface roughness of the boundary between the dielectric layer of the upper conductive structure and the adhesive layer.

10. The wiring structure according to claim 1, wherein the lower conductive structure comprises a plurality of dielectric layers, and the thickness of the plurality of dielectric layers of the upper conductive structure is less than the thickness of the plurality of dielectric layers of the lower conductive structure.

11. The wiring structure according to claim 1, wherein the lower conductive structure includes a core portion, and the at least one dielectric layer of the lower conductive structure is disposed on the core portion.

12. The wiring structure according to claim 1, wherein the line spacing of the circuit layer of the lower conductive structure is greater than or equal to 10 micrometers, and the line spacing of the circuit layer of the upper conductive structure is less than or equal to 2 micrometers.

13. The wiring structure of claim 1, wherein along the thickness axis of the stacked layers and the transverse axis perpendicular to the thickness axis, the internal guide hole gradually narrows in the upward direction along the thickness axis, and the at least one guide hole includes at least one external guide hole that gradually narrows in the downward direction along the thickness axis, wherein the upward direction and the downward direction are opposite directions along the thickness axis.

14. The wiring structure according to claim 1, wherein the surrounding surface of the adhesive layer is substantially coplanar with the surrounding surface of the upper conductive structure.

15. The wiring structure according to claim 1, wherein, viewed from a top view, the size of the adhesive layer is substantially equal to the size of the upper conductive structure.

16. The wiring structure of claim 1, wherein the upper conductive structure has a top surface, a portion of which is exposed to air.

17. The wiring structure of claim 1, wherein the upper conductive structure has at least one reference mark at its corner, the lower conductive structure has at least one reference mark at its corner, and the reference mark of the upper conductive structure is aligned with the reference mark of the lower conductive structure.

18. The wiring structure according to claim 1, wherein the plurality of circuit layers of the upper conductive structure includes a bottom circuit layer and a top circuit layer, the bottom circuit layer is disposed on the bottom surface of the upper conductive structure, the top circuit layer is disposed on the top surface of the upper conductive structure, and the via and the top circuit layer are integrally formed.

19. The wiring structure of claim 18, wherein the bottommost circuit layer is embedded in the adhesive layer.

20. The wiring structure according to claim 18, wherein the line spacing of the topmost circuit layer is greater than the line spacing of the bottommost circuit layer.

21. The wiring structure according to claim 1, wherein the lower conductive structure comprises a plurality of circuit layers, the plurality of circuit layers including a topmost circuit layer, the topmost circuit layer being disposed on the top surface of the lower conductive structure, and the topmost circuit layer being embedded in the adhesive layer.

22. The wiring structure of claim 21, wherein the vias of the adhesive layer do not penetrate the topmost circuit layer of the lower conductive structure.

23. The wiring structure of claim 21, wherein the via does not penetrate the topmost circuit layer of the lower conductive structure.

24. The wiring structure according to claim 1, wherein the internal via includes a seed layer, the seed layer being exposed on the top surface of the upper conductive structure.

25. The wiring structure according to claim 1, wherein the lateral peripheral surface of the upper conductive structure is not coplanar with the lateral peripheral surface of the lower conductive structure.

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