Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a method for manufacturing a semiconductor device. A semiconductor device includes a semiconductor substrate, which includes a first epitaxial layer having a first surface and a second surface, a second epitaxial layer, a buried region formed to pass through the first epitaxial layer and the second epitaxial layer, and a gate electrode. The second epitaxial layer includes a drain region, a source region, a body region, a drift region, a first region, and a second region. The first region is formed at least below the drain region. The second region has a first end and a second end in the channel length direction. The first end is located between the body region and the drain region in the channel length direction. The second region extends from the first end toward the second end so that the second end extends at least below the source region. The impurity concentration of the second region is greater than the impurity concentration of the first region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2019-021292 filed on February 8, 2019 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-152559

[0006] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2011-3608

[0007] [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2013-115166

[0008] Patent Document 1 describes a semiconductor device including an LDMOS transistor.

[0009] The semiconductor device disclosed in Patent Document 1 includes a semiconductor substrate, a gate dielectric film and a gate electrode. The semiconductor substrate includes a supporting substrate, an epitaxial layer formed on the supporting substrate and a buried region. The conductive type of the supporting substrate and the conductive type of the epitaxial layer are p-type. The buried region is formed to pass through the supporting substrate and the epitaxial layer. The conductive type of the buried region is n-type.

[0010] The epitaxial layer has a first surface and a second surface. The first surface is the surface of the epitaxial layer on the supporting substrate side. The second surface is the opposite surface of the first surface. The second surface is the main surface of the semiconductor substrate. In the epitaxial layer, a source region, a drain region, a well region, a drift region, a first region, and a second region are formed.

[0011] The source region is formed on the second surface. The drain region is formed on the second surface and is separated from the source region. The well region is formed on the second surface so that the well region surrounds the source region. The drift region is formed on the second surface so that the drift region surrounds the drain region. The conductivity type of the source region, the drain region, and the drift region is n-type, and the conductivity type of the well region is p-type. In the following, the second surface between the source region and the drift region is a channel region.

[0012] The first region is located below the drain region. The second region has one end and the other end in the channel length direction (the direction from the source region toward the drain region). One end of the second region is located between the body region and the drain region in the channel length direction. The other end of the second region is located below the source region. The first region is located between the drain region and the first surface in the thickness direction (the direction from the first surface toward the second surface). The second region is farther from the first surface than the first region in the thickness direction. The conductivity type of the first region and the second region is p-type. The impurity concentration of the second region is greater than the impurity concentration of the first region.

[0013] The gate electrode faces the channel region, and the gate electrode is insulated from the gate dielectric film. The source region, the drain region, the well region, the drift region, the gate dielectric film, and the gate electrode constitute an LDMOS transistor.

[0014] Patent Document 2 and Patent Document 3 also each disclose a semiconductor device in which an LDMOS transistor is formed. Summary of the invention

[0015] In the semiconductor device disclosed in Patent Document 1, the on-state breakdown voltage of the LDMOS transistor can be increased by the second region. The semiconductor device of Patent Document 1 includes a parasitic npn transistor having a drain region as a collector, a well region as a base, and a source region as an emitter. In the semiconductor device described in Patent Document 1, since the second region is farther from the first surface than the first region, the rise in the potential of the well region caused by the potential of the buried region cannot be fully suppressed. When the potential of the well region rises, the parasitic npn transistor works and the on-state breakdown voltage decreases, so the on-state resistance of the LDMOS in the semiconductor device disclosed in Patent Document 1 has room for improvement.

[0016] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0017] The semiconductor device according to the embodiment includes: a first epitaxial layer of a first conductivity type, having a first surface and a second surface opposite to the first surface; a second epitaxial layer of the first conductivity type, formed on the second surface and having a third surface facing the second surface and a fourth surface opposite to the third surface; a buried region of a second conductivity type opposite to the first conductivity type, formed to pass through the first epitaxial layer and the second epitaxial layer; and a gate electrode. The second epitaxial layer includes a drain region, a source region, a body region, a drift region, a first region, and a second region. The drain region is formed on the fourth surface. The source region is formed on the fourth surface separated from the drain region. The drift region is formed on the fourth surface so that the drift region surrounds the drain region. The body region is formed on the fourth surface so that the body region surrounds the source region. In the thickness direction (i.e., the direction from the third surface toward the fourth surface), the first region is formed at a position closer to the buried region than the drift region. In the thickness direction, the second region is formed at a position closer to the buried region than the first region. The conductivity type of the body region, the first region, and the second region is the first conductivity type. The conductivity type of the drain region, the source region and the drift region is the second conductivity type. The first region is formed at least below the drain region. In the channel length direction from the source region toward the drain region, the second region has a first end and a second end opposite to the first end. The first end is located between the body region and the drain region in the channel length direction. The second region extends from the first end toward the second end so that the second end reaches at least below the source region. The impurity concentration of the second region is greater than the impurity concentration of the first region. The gate electrode faces the fourth surface between the source region and the drift region and is insulated.

[0018] According to the semiconductor device according to the embodiment, the on-state breakdown voltage of the LDMOS transistor can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram showing a circuit configuration of a semiconductor device according to a first embodiment.

[0020] Figure 2 is a plan view of the semiconductor device according to the first embodiment.

[0021] Figure 3 It is along Figure 2 Cross-sectional view obtained along line III-III.

[0022] Figure 4 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment.

[0023] Figure 5 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment.

[0024] Figure 6is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment.

[0025] Figure 7 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment.

[0026] Figure 8 is a cross-sectional view of the semiconductor device according to the first embodiment when the transistor Tr is composed of a plurality of fingers.

[0027] Fig. 9 are process diagrams illustrating a method for manufacturing the semiconductor device according to the first embodiment.

[0028] Fig.10 is a cross-sectional view of the semiconductor device according to the first embodiment in the semiconductor substrate providing step S1 .

[0029] Fig.11 is a cross-sectional view of the semiconductor device according to the first embodiment in the first ion implantation step S2.

[0030] Fig.12 is a cross-sectional view of the semiconductor device according to the first embodiment in the second ion implantation step S3.

[0031] Fig.13 is a cross-sectional view of the semiconductor device according to the first embodiment in the third ion implantation step S4.

[0032] Fig.14 is a cross-sectional view of the semiconductor device according to the first embodiment in the fourth ion implantation step S5 .

[0033] Fig.15 is a cross-sectional view of the semiconductor device according to the first embodiment in the fifth ion implantation step S6.

[0034] Fig.16 is a cross-sectional view of the semiconductor device according to the first embodiment in the first insulating isolation film forming step S7.

[0035] Fig.17 is a cross-sectional view of the semiconductor device according to the first embodiment in the gate dielectric film forming step S8.

[0036] Fig.18 is a cross-sectional view of the semiconductor device according to the first embodiment in the gate forming step S9.

[0037] Fig.19 is a cross-sectional view of the semiconductor device according to the first embodiment in the sixth ion implantation step S10 .

[0038] Fig. 20is a cross-sectional view of the semiconductor device according to the first embodiment in the sidewall spacer forming step S11 .

[0039] Fig.21 is a cross-sectional view of the semiconductor device according to the first embodiment in the seventh ion implantation step S12.

[0040] Fig. 22 is a cross-sectional view of the semiconductor device according to the first embodiment in the interlayer insulating film forming step S13.

[0041] Fig.23 is a cross-sectional view of the semiconductor device according to the first embodiment in the second insulating film forming step S14.

[0042] Fig.24 is a cross-sectional view of the semiconductor device according to the first embodiment in the contact plug forming step S15 .

[0043] Fig.25 It is an explanatory diagram of a simulation when the second region DIF2 is formed.

[0044] Fig.26 It is an explanatory diagram of a simulation when the second region DIF2 is not formed.

[0045] Fig. 27 is a cross-sectional view of a semiconductor device according to a second embodiment.

[0046] Fig.28 1 and 2 are process diagrams showing a method for manufacturing a semiconductor device according to a second embodiment.

[0047] Fig.29 is a cross-sectional view of a semiconductor device according to a third embodiment.

[0048] Fig.30 are process diagrams showing a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0049] The details of the embodiment will be described with reference to the accompanying drawings. In the following drawings, the same or corresponding components are denoted by the same reference numerals, and their description will not be repeated.

[0050] (First embodiment)

[0051] Hereinafter, a semiconductor device according to a first embodiment will be described.

[0052] (Circuit Configuration of Semiconductor Device According to First Embodiment)

[0053] like Figure 1As shown, the semiconductor device according to the first embodiment includes, for example, a drive circuit DRC, a pre-drive circuit PDC, an emulation circuit ANC, a power supply circuit PWC, and an input / output circuit IOC. Among them, for example, the drive circuit DRC includes a transistor Tr. The transistor Tr is an LDMOS transistor.

[0054] (Configuration of LDMOS Transistor in Semiconductor Device According to First Embodiment)

[0055] like Figure 2 and Figure 3 As shown, in the region where the transistor Tr is formed, the semiconductor device according to the first embodiment includes a semiconductor substrate SUB, insulating isolation films ISL1 and ISL2, a gate dielectric film GI, and a gate electrode GE. In the region where the transistor Tr is formed, the semiconductor device according to the first embodiment also includes a sidewall spacer SWS, an interlayer insulating film ILD, an insulating isolation film ISL3, contact plugs CP1, contact plugs CP2, contact plugs CP3, wirings WL1, and wirings WL2.

[0056] The semiconductor substrate SUB includes an epitaxial layer EP1, an epitaxial layer EP2 and a buried region BL. The epitaxial layer EP1 and the epitaxial layer EP2 are formed of, for example, single crystal silicon (Si) doped with impurities. The conductivity type of the epitaxial layer EP1 and the epitaxial layer EP2 is a first conductivity type. The first conductivity type is, for example, a p-type. The epitaxial layer EP1 has a first surface F1 and a second surface F2. The second surface F2 is an opposite surface to the first surface F1. The epitaxial layer EP2 has a third surface F3 and a fourth surface F4. The fourth surface F4 is an opposite surface to the third surface F3.

[0057] Epitaxial layer EP2 is formed on epitaxial layer EP1. More specifically, epitaxial layer EP2 is formed on second surface F2. Third surface F3 is opposite to second surface F2. That is, fourth surface F4 constitutes the main surface of semiconductor substrate SUB.

[0058] The buried region BL is formed to pass through the epitaxial layer EP1 and the epitaxial layer EP2. The conductivity type of the buried region BL is the second conductivity type. The second conductivity type is the opposite conductivity type of the first conductivity type. That is, if the first conductivity type is the p-type, the second conductivity type is the n-type. The epitaxial layer EP1 and the epitaxial layer EP2 are electrically isolated from each other by the buried region BL.

[0059] A drain region DRA, a source region SR, a drift region DRI, a body region BR, and a body contact region BCR are formed in the epitaxial layer EP2 .

[0060] The drain region DRA is formed in the fourth surface F4. The source region SR is formed on the fourth surface F4 away from the drain region DRA. The source region SR has a first portion SRa and a second portion SRb. The first portion SRa is closer to the drain region DRA than the second portion SRb. The impurity concentration of the first portion SRa is less than the impurity concentration of the second portion SRb. In other words, the source region SR has a lightly doped diffusion (LDD) structure. The conductivity type of the drain region DRA and the source region SR is the second conductivity type.

[0061] The drift region DRI is formed on the fourth surface F4 such that the drift region DRI surrounds the drain region DRA. The conductivity type of the drift region DRI is the second conductivity type. The impurity concentration of the drift region DRI is lower than the impurity concentration of the drain region DRA.

[0062] The body region BR is formed on the fourth surface F4 such that the body region BR surrounds the source region SR. The conductivity type of the body region BR is the first conductivity type. The impurity concentration of the body region BR is greater than the impurity concentration of the epitaxial layer EP2.

[0063] The body contact region BCR is formed on the fourth surface F4. The body contact region BCR is arranged adjacent to the source region SR on the side opposite to the drain region DRA. The body contact region BCR is surrounded by the body region BR. The conductivity type of the body contact region BCR is the first conductivity type. The impurity concentration of the body contact region BCR is greater than the impurity concentration of the body region BR.

[0064] The trench TR1 is formed on the fourth surface F4. The trench TR1 extends from the fourth surface F4 toward the third surface F3. The trench TR1 is located between the drain region DRA and the source region SR so that the trench TR1 is surrounded by the drift region DRI. The insulating isolation film ISL1 is buried in the trench TR1. The insulating isolation film ISL1 is formed of, for example, silicon oxide (SiO2). The trench TR1 and the insulating isolation film ISL1 have a shallow trench isolation (STI) structure. The insulating isolation film ISL1 (trench TR1) is formed so that the insulating isolation film ISL1 surrounds the drain region DRA in a plan view (see Figure 2 ). The insulating isolation film ISL1 may be a local oxidation of silicon (LCOS).

[0065] A trench TR2 is formed on the fourth surface F4. Compared to the source region SR, the trench TR2 is positioned adjacent to the body contact region BCR on the other side. The trench TR2 extends from the fourth surface F4 toward the third surface F3. The trench TR2 is surrounded by the body region BR. The insulating isolation film ISL2 is buried in the trench TR2. The insulating isolation film ISL2 is formed of, for example, silicon oxide. The trench TR2 and the insulating isolation film ISL2 have an STI structure. The insulating isolation film ISL2 (trench TR2) is formed so that the insulating isolation film ISL2 surrounds the body contact region BCR in a plan view. The insulating isolation film ISL2 may be LOCOS.

[0066] The gate dielectric film GI is formed on the fourth surface F4 between the source region SR and the trench TR1. The gate dielectric film GI is formed of, for example, silicon oxide.

[0067] The gate electrode GE is formed on the gate dielectric film GI. The gate electrode GE may extend above the insulating isolation film ISL1. The gate electrode GE faces the channel region (the fourth surface F4 arranged between the source region SR and the drift region DRI) while being insulated from the channel region by the gate dielectric film GI. The gate electrode GE is formed of, for example, polysilicon doped with impurities.

[0068] The drain region DRA, the source region SR, the drift region DRI, the body region BR, the gate dielectric film GI, and the gate electrode GE constitute the transistor Tr.

[0069] The sidewall spacer SWS is formed on the first portion SRa so that the sidewall spacer SWS is in contact with the first side surface of the gate electrode GE. The sidewall spacer SWS is formed on the insulating isolation film ISL1 so that the sidewall spacer SWS is in contact with the second side surface of the gate electrode GE. The second side surface is a side surface of the gate electrode GE opposite to the first side surface of the gate electrode GE. The sidewall spacer SWS is formed of, for example, a stacked film of silicon oxide and silicon nitride (Si3N).

[0070] The interlayer insulating film ILD is formed on the fourth surface F4 so that the interlayer insulating film ILD covers the gate electrode GE and the sidewall spacer SWS. The interlayer insulating film ILD is formed of, for example, silicon oxide.

[0071] A trench TR3 is formed in the interlayer insulating film ILD, the semiconductor substrate SUB and the insulating isolation film ISL2. The trench TR3 extends from the fourth surface F4 toward the first surface F1 in the semiconductor substrate SUB. The trench TR3 is formed so that the trench TR3 penetrates the buried region BL. From another angle, the interlayer insulating film ILD, the insulating isolation film ISL2, the body region BR, the epitaxial layer EP2, the buried region BL and the epitaxial layer EP1 are exposed from the side surface of the trench TR3. The insulating isolation film ISL3 is buried in the trench TR3. The insulating isolation film ISL3 is formed of, for example, silicon oxide. The trench TR3 and the insulating isolation film ISL3 are formed in a deep trench isolation (DTI) structure. The insulating isolation film ISL3 (trench TR3) is formed so that the insulating isolation film ISL3 surrounds the transistor Tr in a plan view.

[0072] The contact plugs CP1, CP2 and CP3 are formed in the interlayer insulating film ILD. More specifically, the contact plugs CP1, CP2 and CP3 are buried in contact holes formed in the interlayer insulating film ILD. The contact plugs CP1, CP2 and CP3 are electrically connected to the drain region DRA, the source region SR and the body contact region BCR, respectively. The contact plugs CP1, CP2 and CP3 are formed, for example, of tungsten (W).

[0073] The wiring WL1 and the wiring WL2 are formed on the interlayer insulating film ILD. The wiring WL1 is electrically connected to the contact plug CP1, and the wiring WL2 is electrically connected to the contact plug CP2 and the contact plug CP3. The wiring WL1 and the wiring WL2 are formed of, for example, aluminum (Al) alloy, copper (Cu) alloy, or the like.

[0074] The epitaxial layer EP2 further includes a first region DIF1, a second region DIF2, and a third region DIF3 in the semiconductor device according to the first embodiment. The conductivity type of the first region DIF1, the second region DIF2, and the third region DIF3 is the first conductivity type.

[0075] The impurity concentration of the second region DIF2 is greater than the impurity concentration of the first region DIF1. The impurity concentration of the third region DIF3 is greater than the impurity concentration of the first region DIF1. Preferably, the impurity concentration of the third region DIF3 is greater than the impurity concentration of the second region DIF2. The impurity concentrations of the first region DIF1, the second region DIF2 and the third region DIF3 are greater than the impurity concentration of the epitaxial layer EP2.

[0076] The first region DIF1 is closer to the third surface F3 than the drift region DRI and the body region BR in the thickness direction of the epitaxial layer EP2 (the direction from the third surface F3 to the fourth surface F4). From another perspective, the first region DIF1 is closer to the buried region BL than the drift region DRI and the body region BR in the thickness direction of the epitaxial layer EP2. The first region DIF1 is formed to pass through the region in which the transistor Tr is formed.

[0077] In the thickness direction of the epitaxial layer EP2, the second region DIF2 is closer to the third surface F3 than the first region DIF1, that is, closer to the buried region BL than the first region DIF1. The second region DIF2 has a first end and a second end in the channel length direction. The second end is the other end of the first end.

[0078] In the channel length direction, the first end of the second region DIF2 is located between the body region BR and the drain region DRA. The second region DIF2 extends from the first end toward the second end so that the second end reaches the trench TR3. That is, the second region DIF2 is formed so that the second region DIF2 avoids the lower position of the drain region DRA.

[0079] In the thickness direction of the epitaxial layer EP2, the third region DIF3 is closer to the third surface F3 (buried region BL) than the drift region DRI and the body region BR, and is arranged to be farther away from the third surface F3 (buried region BL) than the first region DIF1. The third region DIF3 has a first end and a second end in the channel length direction. The second end is the other end of the first end.

[0080] In the channel length direction, the first end of the third region DIF3 is located between the body region BR and the drain region DRA. The third region DIF3 extends from the first end toward the second end so that the second end reaches the trench TR3. That is, the third region DIF3 is formed so that the third region DIF3 avoids the lower portion of the drain region DRA.

[0081] like Figures 4 to 6 As shown, the first region DIF1 may not be formed to pass through the region where the transistor Tr is formed. More specifically, the first region DIF1 may be formed at least under the drain region DRA.

[0082] like Figure 5 and Figure 6 As shown, the second region DIF2 may not extend so that the second end reaches the trench TR3. More specifically, the second region DIF2 may extend from the first end so that the second end extends at least below the source region SR. From another perspective, the second region DIF2 may be formed at least below the channel region SR and the source region SR.

[0083] like Figure 6 and Figure 7 As shown, the epitaxial layer EP2 may not include the third region DIF3.

[0084] In the above description, the number of fingers of the transistor Tr (LDMOS transistor) is 1, but as Figure 8 As shown, the number of fingers of the transistor Tr may be 2 or more. When the number of fingers of the transistor Tr is plural, the third region DIF3 (in Figure 8 In the embodiment, the third region DIF3 at the center (channel) may have both ends respectively between the body region BR and the drain region DRA.

[0085] like Fig. 9 As shown, the method for manufacturing a semiconductor device according to the first embodiment includes a semiconductor substrate providing step S1, a first ion implantation step S2, a second ion implantation step S3, a third ion implantation step S4, a fourth ion implantation step S5, a fifth ion implantation step S6, a first insulating isolation film forming step S7, a gate dielectric film forming step S8 and a gate electrode forming step S9. The method for manufacturing a semiconductor device according to the first embodiment also includes a sixth ion implantation step S10, a sidewall spacer forming step S11, a seventh ion implantation step S12, an interlayer insulating film forming step S13, a second insulating isolation film forming step S14, a contact plug forming step S15 and a wiring forming step S16.

[0086] like Fig.10 As shown, in the semiconductor substrate providing step S1, a semiconductor substrate SUB is provided. In the semiconductor substrate providing step S1, first, a semiconductor substrate including an epitaxial layer EP1 is provided. Secondly, in the semiconductor substrate providing step S1, ion implantation of the second surface F2 is performed. As a result, a buried region BL is formed. Thirdly, in the semiconductor substrate providing step S1, epitaxial growth of an epitaxial layer EP2 is performed on the epitaxial layer EP1. As described above, a semiconductor substrate SUB including an epitaxial layer EP1, an epitaxial layer EP2 and a buried region BL is provided. In addition, by diffusing impurities associated with the heat treatment for forming the epitaxial layer EP2 (as well as heat treatment in subsequent steps), the buried region BL is eventually formed by penetrating the epitaxial layer EP1 and the epitaxial layer EP2.

[0087] like Fig.11 As shown, in the first ion implantation step S2, ion implantation for forming the second region DIF2 is performed. Fig.12 As shown, in the second ion implantation step S3, ion implantation for forming the first region DIF1 is performed. Fig.13 As shown, in the third ion implantation step S4, ion implantation for forming the third region DIF3 is performed.

[0088] like Fig.14 As shown, in the fourth ion implantation step S5, ion implantation for forming the body region BR is performed. Fig.15 As shown, in the fifth ion implantation step S6, ion implantation for forming the drift region DRI is performed. For example, the first ion implantation step S2 to the fifth ion implantation step S6 are performed using a photoresist as a mask.

[0089] like Fig.16 As shown, in the first insulating isolation film forming step S7, an insulating isolation film ISL1 and an insulating isolation film ISL2 are formed. In the first insulating isolation film forming step S7, trenches TR1 and TR2 are first formed. Trench TR1 and trench TR2 are formed by anisotropic dry etching (eg, reactive ion etching (RIE)).

[0090] Secondly, in the first insulating isolation film forming step S7, the material constituting the insulating isolation film ISL1 and the insulating isolation film ISL2 is embedded in the trench TR1 and the trench TR2. The insulating isolation film ISL1 and the material constituting the insulating isolation film ISL2 are buried in the trench TR1 and the trench TR2 by, for example, chemical vapor deposition (CVD) or the like. Thirdly, in the first insulating isolation film forming step S7, the material constituting the insulating isolation film ISL1 and the insulating isolation film ISL2 protruding from the trench TR1 and the trench TR2 is removed by chemical mechanical polishing (CMP) or the like.

[0091] like Fig.17 As shown, in the gate dielectric film forming step S8, the gate dielectric film GI is formed. For example, the gate dielectric film forming step S8 is performed by thermally oxidizing the fourth surface F4 of the epitaxial layer EP2.

[0092] like Fig.18 As shown, in the gate electrode forming step S9, the gate electrode GE is formed. In the gate electrode forming step S9, first, a material constituting the gate electrode GE is deposited by CVD or the like. Next, in the gate electrode forming step S9, the material constituting the formed gate electrode GE is patterned by anisotropic dry etching using a photoresist formed by photolithography.

[0093] like Fig.19 As shown, in the sixth ion implantation step S10, the first portion SRa is formed. The sixth ion implantation step S10 is performed using the gate electrode GE as a mask.

[0094] like Fig. 20As shown, in the sidewall spacer forming step S11, the sidewall spacer SWS is formed. First, in the sidewall spacer forming step S11, the material constituting the sidewall spacer SWS is deposited by CVD or the like. Second, in the sidewall spacer forming step S11, the material constituting the deposited sidewall spacer SWS is etched back.

[0095] like Fig.21 As shown, in the seventh ion implantation step S12, a source region SR (more specifically, a second portion SRb), a drain region DRA, and a body contact region BCR are formed. The seventh ion implantation step S12 is performed using the gate electrode GE, the sidewall spacer SWS, and the photoresist as a mask.

[0096] like Fig. 22 As shown, in the interlayer insulating film forming step S13, an interlayer insulating film ILD is formed. In the interlayer insulating film forming step S13, first, a material constituting the interlayer insulating film ILD is deposited by CVD or the like. Next, in the interlayer insulating film forming step S13, the material constituting the interlayer insulating film ILD formed by CMP or the like is planarized.

[0097] like Fig.23 As shown, in the second insulating isolation film forming step S14, an insulating isolation film ISL3 is formed. In the second insulating isolation film forming step S14, first, a trench TR3 is formed. The trench TR3 is formed by anisotropic dry etching. Secondly, in the second insulating isolation film forming step S14, a material constituting the insulating isolation film ISL3 is embedded in the trench TR3 by CVD or the like. Thirdly, in the second insulating isolation film forming step S14, a material constituting the insulating isolation film ISL3 protruding from the trench TR3 is removed by CMP or the like.

[0098] like Fig.24 As shown, in the contact plug forming step S15, contact plugs CP1, contact plugs CP2 and contact plugs CP3 are formed. In the contact plug forming step S15, first, a contact hole is formed in the interlayer insulating film ILD. For example, the contact hole is formed by anisotropic dry etching. Secondly, in the contact plug forming step S15, the materials constituting the contact plugs CP1, contact plugs CP2 and contact plugs CP3 are buried in the contact holes by CVD or the like. Thirdly, in the contact plug forming step S15, the materials constituting the contact plugs CP1, contact plugs CP2 and contact plugs CP3 protruding from the contact holes are removed by CMP or the like.

[0099] In the wiring forming step S16, the wiring WL1 and the wiring WL2 are formed. In the wiring forming step S16, first, the material constituting the wiring WL1 and the wiring WL2 is deposited by a method such as sputtering. Next, in the wiring forming step S16, the material constituting the deposited wiring WL1 and the wiring WL2 is patterned by anisotropic dry etching using a photoresist formed by photolithography. As described above, the wiring WL1 and the wiring WL2 are formed according to the above. Figure 3 The semiconductor device of the first embodiment is shown.

[0100] As described above, in the semiconductor device according to the first embodiment, the first region DIF1 is formed at least below the drain region DRA, and the impurity concentration of the first region DIF1 is small. Therefore, when a positive potential is applied to the drain region DRA, punch-through is likely to occur between the drift region DRI and the buried region BL. When the gap between the drift region DRI and the buried region BL is punched through, the potential applied to the drain region DRA is shared by the drain region DRA, the drift region DRI, and the buried region BL, and therefore, the semiconductor device according to the first embodiment can improve the off-state withstand voltage.

[0101] In the semiconductor device according to the first embodiment, the potential applied to the drain region DRA by punch-through between the drift region DRI and the buried region BL is also shared by the buried region BL, and as a result, the potential of the buried region BL tends to rise. When the potential of the buried region BL rises, the depletion layer tends to extend from the buried region BL to the body region BR, and the potential of the body region BR tends to rise.

[0102] The semiconductor device according to the first embodiment includes a parasitic npn transistor having a drain region DRA as a collector, a body region BR as a base, and a source region SR as an emitter. Therefore, if the potential of the body region BR rises, the parasitic npn transistor operates and the on-state breakdown voltage may decrease.

[0103] However, as described above, the semiconductor device according to the first embodiment includes the second region DIF2, which extends so that the second end DIF2b reaches at least below the source region SR. Because the second region DIF2 has a high impurity concentration and is arranged close to the buried region BL, even if the potential of the buried region BL rises, it is difficult for the depletion layer to extend from the buried region BL to the body region BR. That is, in the semiconductor device according to the first embodiment, the potential of the body region BR is hardly increased, and the reduction of the on-state breakdown voltage is suppressed.

[0104] Fig.25 2 shows the simulation result performed by the process CAD (TCAD) when the second region DIF2 is formed, Fig.26 FIG. 4 shows the simulation result performed by TCAD when the second region DIF2 is not formed. Fig.25 and Fig.26 In FIG. 1 , equipotential lines are indicated by dotted lines at intervals of 2 V. In these simulations, the potential applied to the drain region DRA is set to 70 V, and the potential applied to the gate electrode GE is set to 4 V.

[0105] like Fig.25 and Fig.26 As shown, when the second region DIF2 is not formed, the potential of the body region BR is increased by the potential of the buried region BL, and when the second region DIF2 is formed, the increase in the potential of the body region BR due to the potential of the buried region BL is suppressed.

[0106] Since the first end of the second region DIF2 is arranged between the body region BR and the drain region DRA in the channel length direction (i.e., formed to avoid the lower part of the drain region DRA), when a positive potential is applied to the drain region DRA, the off-state breakdown voltage can be maintained without preventing punch-through between the drift region DRI and the buried region BL.

[0107] In the semiconductor device according to the first embodiment, since the first region DIF1 is formed at least under the drain region DRA, when a negative potential is applied to the drain region DRA, it is difficult to penetrate between the drift region and the buried region BL. Therefore, according to the semiconductor device of the first embodiment, the negative input breakdown voltage can be improved.

[0108] The semiconductor device according to the first embodiment further includes a parasitic npn transistor including a buried region BL as a collector, a body region BR as a base, and a source region SR as an emitter. In the semiconductor device according to the first embodiment, since the parasitic npn transistor hardly operates by suppressing a potential rise in the body region BR, substrate injection is hardly caused, and leakage current when the body diode is intentionally operated can be reduced.

[0109] In the semiconductor device according to the first embodiment, even if the impurity concentration of the drift region DRI increases, or even if the impurity concentration of the drift region DRI increases due to the reduced surface field (RESURF) effect of the third region DIF3, the drift region DRI is easily depleted. That is, in the semiconductor device according to the first embodiment, the on-resistance can be reduced while maintaining the off-withstand voltage of the transistor Tr.

[0110] The conductivity near the side surface of the trench TR3 is the first conductivity type. It is considered that this is caused by the deposition caused by the etching of the buried region BL adhering to the side surface of the trench TR3 when the etching of the buried region BL is performed in the second insulating isolation film forming step S14. In the semiconductor device according to the first embodiment, since the first region DIF1, the second region DIF2, and the third region DIF3 extend so that the first region DIF1, the second region DIF2, and the third region DIF3 are in contact with the side surface of the trench TR3, the reduction of the negative input breakdown voltage caused by the punch-through between the drift region DRI and the side surface of the trench TR3 can be suppressed.

[0111] In the semiconductor device according to the first embodiment, when substrate injection occurs in a region other than the region where the transistor Tr is formed, electrons are annihilated by recombination in the second region DIF2 at the deepest position, and are also annihilated by recombination in the first region DIF1 and the third region DIF3. Therefore, in the semiconductor device according to the first embodiment, the influence of substrate injection from a region other than the region where the transistor Tr is formed can be reduced.

[0112] In the semiconductor device according to the first embodiment, since the second region DIF2 is in contact with the trench TR3 and located near the buried region BL, an increase in the potential of the buried region BL located near the trench TR3 can be suppressed. As a result, according to the semiconductor device of the first embodiment, the reliability of the insulating isolation film ISL3 can be improved.

[0113] (Second embodiment)

[0114] Hereinafter, a semiconductor device according to a second embodiment will be described. Here, the difference from the semiconductor device according to the first embodiment will be mainly described, and the description will not be repeated.

[0115] (Configuration of Semiconductor Device According to Second Embodiment)

[0116] The semiconductor device according to the second embodiment includes: a semiconductor substrate SUB, an insulating isolation film ISL1 and an insulating isolation film ISL2, a gate dielectric film GI, a gate electrode GE, a sidewall spacer SWS, an interlayer insulating film ILD, an insulating isolation film ISL3, a contact plug CP1, a contact plug CP2, a contact plug CP3, a wiring WL1 and a wiring WL2. The semiconductor substrate SUB includes an epitaxial layer EP1, an epitaxial layer EP2 and a buried region BL.

[0117] The epitaxial layer EP2 includes a drain region DRA, a source region SR, a drift region DRI, a body region BR, a body contact region BCR, a first region DIF1, a second region DIF2, and a third region DIF3. In these respects, the semiconductor device according to the second embodiment is similar to the configuration of the semiconductor device according to the first embodiment.

[0118] However, in the semiconductor device according to the second embodiment, as Fig. 27 As shown, both end positions of the first region DIF1 in the channel length direction are formed to coincide with both end positions of the drift region DRI in the channel length direction. In this respect, the configuration of the semiconductor device according to the second embodiment is different from that of the semiconductor device according to the first embodiment.

[0119] (Method of Manufacturing Semiconductor Device According to Second Embodiment)

[0120] like Fig.28 As shown, the method for manufacturing a semiconductor device according to the second embodiment includes a semiconductor substrate providing step S1, a first ion implantation step S2, a second ion implantation step S3, a third ion implantation step S4, a fourth ion implantation step S5, a first insulating isolation film forming step S7, a gate dielectric film forming step S8, and a gate electrode forming step S9. The method for manufacturing a semiconductor device according to the second embodiment also includes a sixth ion implantation step S10, a sidewall spacer forming step S11, a seventh ion implantation step S12, an interlayer insulating film forming step S13, a second insulating isolation film forming step S14, a contact plug forming step S15, and a wiring forming step S16. In these aspects, the method for manufacturing a semiconductor device according to the second embodiment is different from the method for manufacturing a semiconductor device according to the first embodiment.

[0121] However, the method for manufacturing a semiconductor device according to the second embodiment is different from the method for manufacturing a semiconductor device according to the first embodiment because the method for manufacturing a semiconductor device according to the second embodiment does not include the fifth ion implantation step S6. In the semiconductor device according to the second embodiment, since the positions of both ends of the first region DIF1 in the channel length direction coincide with the positions of both ends of the drift region DRI in the channel length direction, the first region DIF1 and the drift region DRI can be formed using the same mask by changing the type of ions to be implanted in the second ion implantation step S3 and the implantation depth.

[0122] (Effects of Semiconductor Device According to Second Embodiment)

[0123] In the semiconductor device according to the second embodiment, since the first region DIF1 and the drift region DRI can be formed by ion implantation using the same mask, the manufacturing process can be simplified.

[0124] (Third Embodiment)

[0125] Hereinafter, a semiconductor device according to a third embodiment will be described. Here, the difference from the semiconductor device according to the first embodiment will be mainly described, and the description will not be repeated.

[0126] (Configuration of Semiconductor Device According to Third Embodiment)

[0127] The semiconductor device according to the third embodiment includes: a semiconductor substrate SUB; an insulating isolation film ISL1 and an insulating isolation film ISL2; a gate dielectric film GI; a gate electrode GE; a sidewall spacer SWS; an interlayer insulating film ILD; an insulating isolation film ISL3; a contact plug CP1; a contact plug CP2; a contact plug CP3, a wiring WL1, and a wiring WL2. The semiconductor substrate SUB has an epitaxial layer EP1 and an epitaxial layer EP2 in the semiconductor substrate SUB. The epitaxial layer EP1 has a buried region BL.

[0128] The epitaxial layer EP2 includes a drain region DRA, a source region SR, a drift region DRI, a body region BR, a body contact region BCR, a first region DIF1, a second region DIF2, and a third region DIF3. In these respects, the semiconductor device according to the third embodiment is similar to the configuration of the semiconductor device according to the first embodiment.

[0129] However, in the semiconductor device according to the third embodiment, as Fig.29 As shown, both end positions of the second region DIF2 in the channel length direction are formed to coincide with both end positions of the third region DIF3 in the channel length direction. In this respect, the configuration of the semiconductor device according to the third embodiment is different from that of the semiconductor device according to the first embodiment.

[0130] (Method of Manufacturing Semiconductor Device According to Third Embodiment)

[0131] like Fig.30 As shown, the method for manufacturing a semiconductor device according to the third embodiment includes a semiconductor substrate providing step S1, a first ion implantation step S2, a second ion implantation step S3, a fourth ion implantation step S5, a fifth ion implantation step S6, a first insulating isolation film forming step S7, a gate dielectric film forming step S8, and a gate electrode forming step S9. The method for manufacturing a semiconductor device according to the third embodiment also includes a sixth ion implantation step S10, a sidewall spacer forming step S11, a seventh ion implantation step S12, an interlayer insulating film forming step S13, a second insulating isolation film forming step S14, a contact plug forming step S15, and a wiring forming step S16. In these aspects, the method for manufacturing a semiconductor device according to the third embodiment is different from the method for manufacturing a semiconductor device according to the first embodiment.

[0132] However, the method for manufacturing a semiconductor device according to the third embodiment is different from the method for manufacturing a semiconductor device according to the first embodiment in that the method for manufacturing a semiconductor device according to the third embodiment does not include a third ion implantation step S4. In the semiconductor device according to the third embodiment, since the positions of both ends of the second region DIF2 in the channel length direction coincide with the positions of both ends of the third region DIF3 in the channel length direction, the second region DIF2 and the third region DIF3 are formed using the same mask by changing the implantation depth in the first ion implantation step S2.

[0133] (Effects of Semiconductor Device According to Third Embodiment)

[0134] In the semiconductor device according to the third embodiment, the second region DIF2 and the third region DIF3 can be formed by ion implantation using the same mask, and the manufacturing process can be simplified.

[0135] Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, but various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor device, comprising: Semiconductor substrate, comprising: A first epitaxial layer, the first epitaxial layer having a first conductivity type and having: a first surface; and a second surface opposite to the first surface; A second epitaxial layer, the second epitaxial layer having the first conductivity type and formed on the second surface, the second epitaxial layer having: a third surface facing the second surface; and a fourth surface opposite to the third surface; and a buried region having a second conductivity type opposite to the first conductivity type and formed to penetrate the first epitaxial layer and the second epitaxial layer; and Gate electrode, Wherein, the second epitaxial layer comprises: a drain region having the second conductivity type and formed on the fourth surface; a source region having the second conductivity type, formed on the fourth surface and spaced apart from the drain region; a drift region having the second conductivity type and formed on the fourth surface such that the drift region surrounds the drain region; a body region having the first conductivity type and formed on the fourth surface such that the body region surrounds the source region; a first region having the first conductivity type and formed at a position closer to the buried region than the drift region in a thickness direction extending from the third surface to the fourth surface; and a second region having the first conductivity type and formed at a position closer to the buried region than the first region in the thickness direction, Wherein, the first region is formed at least below the drain region, The second region has a first end and a second end opposite to the first end in a channel length direction extending from the source region to the drain region, wherein the first end is located between the body region and the drain region in the channel length direction, The second region extends from the first end to the second end, so that the second end at least reaches below the source region. wherein the impurity concentration of the second region is greater than the impurity concentration of the first region, wherein the gate electrode faces the fourth surface between the source region and the drift region, and the gate electrode is insulated, and The impurity concentrations of the body region, the first region, and the second region are greater than the impurity concentration of the second epitaxial layer.

2. The semiconductor device according to claim 1, in, A trench is formed in the semiconductor substrate such that the trench extends from the fourth surface to the first surface, wherein the body region and the buried region are exposed from sidewalls of the trench, and The second region extends from the first end such that the second end reaches the groove.

3. The semiconductor device according to claim 2, in, The first region extends from under the drain region such that the first region reaches the trench.

4. The semiconductor device according to claim 2, in, The first region is formed such that two end positions of the first region in the channel length direction respectively coincide with two end positions of the drift region in the channel length direction.

5. The semiconductor device according to claim 1, in, The second epitaxial layer includes a third region having the first conductivity type, wherein the third region is formed closer to the buried region than the drift region in the thickness direction and farther from the buried region than the first region in the thickness direction, The third region has a third end and a fourth end opposite to the third end in the channel length direction. wherein the third end is located between the body region and the drain region in the channel length direction, wherein the third region extends from the third end toward the fourth end, so that the fourth end at least reaches below the source region, and The impurity concentration of the third region is greater than the impurity concentration of the first region.

6. The semiconductor device according to claim 5, in, A trench is formed in the semiconductor substrate such that the trench extends from the fourth surface toward the first surface, wherein the body region and the buried region are exposed from sidewalls of the trench, and The third region extends so as to reach the groove.

7. The semiconductor device according to claim 5, in, The third region is formed so that positions of both ends of the third region in the channel length direction coincide with positions of both ends of the second region in the channel length direction, respectively.

8. A method for manufacturing a semiconductor device, comprising: (a) providing a semiconductor substrate, the semiconductor substrate comprising: A first epitaxial layer, the first epitaxial layer having a first conductivity type and having: a first surface; and a second surface opposite to the first surface; A second epitaxial layer, the second epitaxial layer having the first conductivity type and having: a third surface formed on the second surface and facing the second surface; and a fourth surface opposite to the third surface; and a buried region having a second conductivity type opposite to the first conductivity type and formed to pass through the first epitaxial layer and the second epitaxial layer; (b) forming a drain region having the second conductivity type on the fourth surface, (c) forming a source region having the second conductivity type and separated from the drain region on the fourth surface, (d) forming a drift region having the second conductivity type on the fourth surface to surround the drain region, (e) forming a body region having the first conductivity type on the fourth surface, (f) forming a first region having the first conductivity type at a position closer to the buried region than the drift region in a thickness direction from the third surface toward the fourth surface; (g) forming a second region having the first conductivity type at a position closer to the buried region than the first region in the thickness direction; and (h) forming a gate electrode, wherein the first region is formed below at least the drain region; The second region has a first end and a second end opposite to the first end in a channel length direction from the source region toward the drain region. wherein the first end is located between the body region and the drain region in the channel length direction, wherein the second region is located from the first end to the second end such that the second end reaches below the source region; wherein the impurity concentration of the second region is greater than the impurity concentration of the first region; and The impurity concentrations of the body region, the first region, and the second region are greater than the impurity concentration of the second epitaxial layer.

9. The method for manufacturing a semiconductor device according to claim 8, in, The drift region and the first region are formed by ion implantation using the same mask.

10. The method for manufacturing a semiconductor device according to claim 8, comprising: (i) forming a third region having the first conductivity type at a position closer to the buried region than the drift region in the thickness direction and farther from the buried region than the first region in the thickness direction, The third region has a third end and a fourth end opposite to the third end in the channel length direction. wherein the third end is located between the body region and the drain region in the channel length direction, The third region extends from the third end toward the fourth end, so that the fourth end at least reaches below the source region. wherein the impurity concentration of the third region is greater than the impurity concentration of the first region, and The second region and the third region are formed by ion implantation using the same mask.

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