Zener diode with adjustable breakdown voltage

Abstract

The present invention relates to a Zener diode with an adjustable breakdown voltage. The present invention relates to a Zener diode, comprising: a Zener diode junction formed in a semiconductor substrate (SUB) and parallel to the surface of the substrate between a cathode region (CD1) and an anode region (AD1), a conductive region (BDC, EDC, ED1, NW) configured to generate a first electric field perpendicular to the Zener diode junction when subjected to an appropriate voltage, and a conductive region (GT1, GTC) configured to generate a second electric field in the plane of the Zener diode junction when subjected to an appropriate voltage.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the application date of November 23, 2015, application number 201510818928.5, and invention name “Zener diode with adjustable breakdown voltage”. Technical Field

[0002] The present invention relates to Zener diodes. Background Art

[0003] Zener diodes are commonly used to regulate voltage in circuits or to supply a stable reference voltage. For this purpose, a Zener diode is connected in reverse parallel with a voltage source. When the voltage supplied by the voltage source reaches the breakdown voltage of the diode, the diode becomes conductive and then maintains the voltage at this value.

[0004] Figure 1 is a cross-section of a conventional Zener diode formed in a substrate formed of a semiconductor material of a first conductivity type (e.g., P type). The Zener diode includes a well NW with a second conductivity type (e.g., N type) doped with a positive electrode region forming the Zener diode. The Zener diode includes a cathode region CD of a first P+ conductivity type highly doped formed in the well NW. Region CD is formed in a region ZD of a second N+ conductivity type highly doped. Regions CD and ZD are isolated from the rest of the well NW by shallow trench isolation STI. The Zener diode includes a second N+ conductivity type highly doped anode connection region ED formed in the well NW and isolated from the cathode region by trench STI. In addition, the substrate SUB includes a first P+ conductivity type highly doped region SP forming a bias region of the substrate SUB. The substrate bias region SP is isolated from regions CD and ZD by shallow trench isolation STI.

[0005] Figure 2 Graph C11 represents the variation of the current through the Zener diode according to the reverse voltage applied between regions CD and ED. Graph C11 illustrates the operation of a conventional reverse biased Zener diode. Between 0 and approximately 2.5 V, the current through the diode remains low (less than 10 V). -12 A). From approximately 2.5V to approximately 5.2V, the current through the diode increases linearly (on a logarithmic scale) to approximately 10 -8 A. This operating region cannot be used to supply reference voltages or to perform voltage regulation due to the so-called "band-to-band" phenomenon. Above approximately 2.5 V, a breakdown phenomenon occurs and the diode becomes highly conductive by the avalanche effect, reaching a maximum voltage BV of approximately 5.5 V, called the "breakdown voltage". The diode maintains this voltage constant regardless of the current strength, assuming that the current is maintained at approximately 10 -8 A to 10 -6A. Zener diodes are often used in this operating region to supply a stable reference voltage or to perform voltage regulation.

[0006] One proposal that has been made consists in making a circuit combining several discrete components to replicate the operation of a Zener diode using a control input to adjust the breakdown voltage of the Zener diode. Thus, the circuit, labeled TL431, operates in a manner similar to a Zener diode, the breakdown voltage of which can be adjusted by the value of a voltage supplied to a control terminal of the circuit. However, this circuit is quite complex and large in size due to the fact that it includes dozens of discrete components, including more than ten transistors. Summary of the invention

[0007] It is therefore desirable to manufacture a Zener diode with an adjustable breakdown voltage. It is also desirable to be able to manufacture such a diode in the form of a discrete component in an integrated circuit by implementing the manufacturing steps normally used to manufacture CMOS transistors.

[0008] Some embodiments relate to a Zener diode, comprising: a Zener diode junction formed in a semiconductor substrate and parallel to the surface of the substrate between a cathode region and an anode region having a first conductivity type, the cathode region being formed by a region having a second conductivity type on the surface of the substrate; a first conductive region configured to generate a first electric field perpendicular to the Zener diode junction when subjected to an appropriate voltage. According to one embodiment, the Zener diode comprises a second conductive region configured to generate a second electric field along the plane of the Zener diode junction when subjected to an appropriate voltage.

[0009] According to one embodiment, the second conductive region includes an embedded gate separated from the Zener diode junction only by a dielectric layer.

[0010] According to one embodiment, the dielectric layer has a thickness between 15 and 25 nm.

[0011] According to one embodiment, the gate isolates the cathode region from the anode connection region.

[0012] According to one embodiment, the gate surrounds the Zener diode junction.

[0013] According to one embodiment, the gate has an octagonal or rectangular shape.

[0014] According to one embodiment, a Zener diode includes a well formed in a semiconductor substrate and having a second conductivity type and forming an anode region, and an anode connection region of the second conductivity type formed in the well on a surface of the substrate and isolated from the cathode region.

[0015] According to one embodiment, the well is isolated from the substrate by shallow trench isolation.

[0016] According to one embodiment, the Zener diode comprises a thin region of a first conductivity type arranged between an anode region and a cathode region.

[0017] Some embodiments may also relate to a circuit comprising a Zener diode as previously defined.

[0018] Some embodiments may also relate to a method for controlling a Zener diode as previously defined, the process comprising the steps of: applying a first voltage to the cathode region; applying a second voltage to the anode region to reverse bias the Zener diode, the difference between the first voltage and the second voltage being greater than or equal to the breakdown voltage of the Zener diode. According to one embodiment, the method comprises the step of applying a third voltage to the second conductive region to generate an electric field along the plane of the Zener diode junction.

[0019] According to one embodiment, the third voltage is applied to the second conductive region through an embedded gate, the embedded gate being separated from the Zener diode junction only by a dielectric layer.

[0020] According to one embodiment, the control method comprises the step of adjusting the third voltage according to a breakdown voltage to be reached by the Zener diode.

[0021] According to one embodiment, the breakdown voltage can be adjusted between 5 and 13 V by causing the third voltage to vary between the first voltage and the second voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Some examples of embodiments of the present invention are described below with reference to, but not limited to, the accompanying drawings, in which:

[0023] Figure 1 (described above) is a cross section of a conventional Zener diode;

[0024] Figure 2 (Description above) A characteristic curve showing the current according to the voltage at the terminals of a conventional Zener diode;

[0025] Figure 3 is a cross section of a Zener diode according to one embodiment;

[0026] Figure 4 yes Figure 3 Detailed partial cross section of a Zener diode;

[0027] Figure 5 According to Figure 3 The voltage-current characteristic curve at the terminals of a Zener diode;

[0028] Figure 6 A curve showing a change in a breakdown voltage of a Zener diode according to a gate voltage;

[0029] Figure 7is a top view of a Zener diode according to one embodiment;

[0030] Figure 8 and 9 is a cross-sectional view and a top view of a Zener diode according to another embodiment;

[0031] Fig.10 According to another embodiment Figure 7 A top view of a diode;

[0032] Fig.11 and 12 is a cross-sectional view and a top view of a Zener diode according to another embodiment;

[0033] Fig.13 According to another embodiment Fig.10 A top view of a Zener diode; and

[0034] Fig.14 is a cross section of a Zener diode according to one embodiment. DETAILED DESCRIPTION

[0035] Figure 3 : represents a Zener diode ZR according to an embodiment. The Zener diode is formed in a well NW formed in a substrate SUB made of a semiconductor material doped with a first conductivity type (e.g., P type). The well NW has a doping of a second conductivity type (N type). The Zener diode ZR includes a cathode region CD1 with a high doping of a first conductivity type (e.g., P+ type) formed in the well NW constituting the anode region. The well NW is isolated from the rest of the substrate SUB by a shallow trench isolation STI1. The Zener diode ZR also includes a high doping region ED1 of a second conductivity type (N+ type) forming a bias region of the well NW and thus forming a connection region of the anode of the diode ZR. In addition, the substrate SUB includes one or more high doping regions SP1 of a first conductivity type (P+ type) forming a bias region of the substrate SUB. The Zener diode ZR also includes a cathode contact pad CDC formed on the region CD1 and an anode contact pad EDC formed on the region ED1. One or more bias contacts SPC of the substrate are formed on the bias region SPP of the substrate SUB.

[0036] According to one embodiment, the Zener diode ZR comprises a vertical embedded gate GT1 formed in the well NW so as to be separated from the cathode region CD1 and in particular from the junction region PN of the diode ZR between the region CD1 and the anode region formed by the well NW only by the gate oxide layer GTD. The gate GT1 is provided to receive a bias voltage GV through a gate contact pad GTC. The voltage GV can be supplied by a circuit CMD which also supplies a cathode voltage CV to the cathode contact pad CDC and an anode voltage to the anode contact pad EDC.

[0037] In order to increase the transition slope between the P+ and N doping of the junction PN forming the Zener diode, and thus obtain a "mutated" junction PN, the region CD1 can be formed on the relatively thin region ZD1 with high doping of the second N+ conductivity type. However, the region ZD1 remains optional and can be provided in the case where it is desired to reduce the range of the breakdown voltage BV that is easily reached by causing a change in the voltage applied to the gate GTC.

[0038] The gate GT1 can be manufactured by etching a hole or trench in the substrate SUB, by forming a dielectric layer GTD on the walls and bottom of the trench (for example, by oxidation), and then by filling the trench with a conductive material such as metal or polysilicon. These manufacturing steps, as well as these steps that enable the formation of different doping regions and trenches STI, are usually implemented to manufacture circuits based on CMOS transistors. The dielectric or gate oxide layer GTD can have a thickness between 15nm and 25nm, for example on the order of 20nm, to obtain a breakdown voltage greater than 5V.

[0039] Figure 4The junction PN of the Zener diode ZR formed between the region CD1 and the well NW and in particular the contact region between the junction PN and the gate GT1 are shown in more detail. When the Zener diode ZR is reverse biased, the cathode contact pad CDC receives a voltage lower than the voltage applied to the bias contact pad EDC of the well NW, for example, a voltage set to 0V. Under these circumstances, an electric field Ez appears in the region of the junction PN of the diode ZR from the well NW toward the region CD1, with a direction perpendicular to the surface of the substrate SUB. If the gate GT1 receives a positive voltage, an electric field Ex also appears in the plane of the junction PN between the cathode CD1 and the anode region formed in the well NW, with a direction toward the gate GT1. The simultaneous appearance of the electric fields Ez and Ex forms a resulting field Er having a direction positioned in an angular sector between the directions of the fields Ez and Ex. It can be seen that the amplitude of the field Er is greater than the field Ez. In addition to the effect of increasing the electric field, there is also a proximity effect because the gate GT1 is in direct contact with the junction PN. As a result, the charges present at the junction PN are subjected to a higher electric field and thus become mobile under the influence of the lower voltage applied to the region CD1, and this mobility produces a breakdown phenomenon by the avalanche effect. Therefore, the gate GT1 acts here as an electrically conductive element to bring the voltage to the vicinity of the junction PN of the Zener diode in order to generate an electric field Ex.

[0040] Figure 5 Curves C12, C13, C14 represent the variation of the current through the Zener diode ZR according to the voltage CV when the voltage CV applied to the cathode region CD1 varies between 0 and -15V, wherein the voltage AV applied to the anode connection region ED1 is set to 0V, for example. The diode ZR is thus reverse biased. Curve C12 is obtained by applying a voltage GV (0V) equal to the anode voltage AV to the gate GT1. Curve C13 is obtained by applying a voltage greater than the anode voltage AV (approximately 3V) to the gate GT1, and curve C14 is obtained by applying a voltage GV (approximately -3V) lower than the anode voltage AV to the gate GT1. Between 0 and approximately 8.5V for curve C12, between 0 and 6.5V for curve C13, and between 0 and approximately 11V for curve C14, the current through the diode ZR increases linearly according to a logarithmic scale while remaining very low (less than 5·10 -8 A). Above these values, a breakdown phenomenon occurs and the diode ZR becomes highly conductive at a breakdown voltage BV2 of approximately 9 V for curve C12, a breakdown voltage BV3 of approximately 7 V for curve C13, and a breakdown voltage BV4 of approximately 11.4 V for curve C14. The diode ZR keeps this voltage BV2, BV3, BV4 constant, regardless of the intensity of the current, provided that the current remains greater than approximately 10 -6A. Comparison of the curves C12 , C13 and C14 shows that the application of a voltage to the gate GT1 makes it possible to cause a change in the breakdown voltage of the diode ZR.

[0041] According to one embodiment, the breakdown voltage of the diode ZR is controlled by adjusting the voltage GV applied to the gate GT1, for example by the circuit CMD. In this way, the Zener diode ZR can be used to generate an adjustable reference voltage source or a voltage regulator with an adjustable set point voltage.

[0042] Figure 6 Curve C15 represents the change of the breakdown voltage BV of the diode ZR according to the voltage GV applied to the gate GT1. Curve C15 shows that the breakdown voltage BV of the diode ZR decreases substantially linearly from approximately 12.7 V to 6.7 V when the gate voltage GT1 increases from -6 V to 3 V, where the anode voltage AV is set to 0 V. It should be noted that by increasing the gate voltage GT1 again, the breakdown voltage can be reduced to 5 V, and by reducing the gate voltage, the breakdown voltage can reach 13 V.

[0043] Figure 7 denoted by a Zener diode ZR according to an embodiment. Figure 7 The gate GT1 isolates the regions CD1 and ZD1 from the bias region ED1. The trench ST1 surrounds the region including the regions CD1 and ZD1, the gate GT1, and the region ED1. One or more regions SP1 for biasing the substrate SUB defined by the trench ST1 may be formed around the diode ZR.

[0044] Figure 8 and 9 denoted by a Zener diode ZR1 according to another embodiment. Figure 8 and 9 , the diode ZR1 comprises a cathode region CD2 having a high doping of a first conductivity type (P+ type), superimposed on a region ZD2 having a high doping of a second conductivity type (N+ type). The regions CD2, ZD2 are formed in a well NW having a doping of the second conductivity type (N type) and formed in the substrate SUB.

[0045] According to one embodiment, the embedded gate GT2 is formed in the region DB2, ZD2 so as to contact the junction PN of the diode ZR1. The region CD2, ZD2 including the gate GT2 is isolated from the rest of the well NW by the shallow trench isolation STI2. The Zener diode ZR1 also includes a highly doped region ED2 of the second conductivity type (N+ type) in the well NW, which forms a region for biasing the well NW and for connecting the anode of the diode ZR1. The well NW is isolated from the rest of the substrate SUB by the shallow trench isolation ST3. In addition, the substrate SUB includes one or more highly doped regions SP1 of the first conductivity type (P+ type) forming the bias region of the substrate SUB. The Zener diode ZR1 also includes a cathode contact pad CDC formed on the region CD2, an anode contact pad EDC formed on the region ED2, and a gate contact pad GTC formed on the gate GT2. One or more bias contacts SPC are formed on the bias region SPP of the substrate SUB.

[0046] exist Fig. 9 On the upper surface, trench isolations STI2 and STI3 isolate three regions, namely, a central region and two side regions including an anode connection region ED2 on either side of the central region. The central region includes a gate GT2 and cathode regions CD2 on either side of the gate.

[0047] Fig.10 According to another embodiment, a Figure 8 The cross-sectional configuration of the Zener diode ZR2. The diode ZR2 includes a cathode region CD3 superimposed on the anode region and surrounding the embedded gate GT3, and the cathode region CD3 is surrounded by the trench isolation STI4. The diode ZR2 also includes an anode connection region ED3 surrounding the trench isolation STI4 and isolated from the substrate SUB by the trench isolation STI5. The cathode region CD3 and the anode connection region ED3 and the trenches STI4 and STI5 have an octagonal shape. The gate GT3 can have a square shape or more generally a rectangular or even octagonal shape.

[0048] Fig.11 and 12 : represents a Zener diode ZR3 comprising a cathode region CD4 with a high doping of a first conductivity type (P+ type) superimposed on a region ZD4 with a high doping of a second conductivity type (N+ type). The regions CD4, ZD4 are formed in the well NW and isolated from the rest of the well NW by an embedded gate GT4 formed in a trench surrounding the regions CD4, ZD4. An anode connection region ED4 is formed in the well NW along the outer edge of the gate GT4. The well NW is isolated from the substrate SUB by a trench isolation STI6 surrounding the gate GT4 and the anode connection region ED4.

[0049] Fig.13 According to another embodiment, a Fig.11 The cross-sectional configuration of the Zener diode ZR4. The diode ZR4 includes a cathode region CD5 superimposed on the anode region and surrounded by an embedded gate GT5, and the gate GT5 is surrounded by an anode connection region ED5. The diode ZR4 also includes a shallow trench isolation STI7 that isolates the anode connection region ED5 and the well NW from the substrate SUB. The cathode region CD5 and the anode connection region ED5, as well as the gate GT5 and the trench STI7 have an octagonal shape.

[0050] It will be appreciated by those skilled in the art that the present invention allows for various alternative embodiments and various applications. In particular, the present invention is not limited to the shapes of the different regions of the Zener diode presented. In particular, regions ZD2 and ZD4 may be omitted, primarily in the case where it is not desired to reduce the range of breakdown voltages that are easily reached by causing a change in the voltage applied to the gates GT2, GT3, GT4, GT5. Other shapes other than the described rectangular and octagonal shapes may be considered for different regions of the Zener diode. Therefore, circular and square shapes and other polygonal shapes may be considered for these regions.

[0051] In addition, in all the embodiments described above, the conductivity type of the doping of the different regions forming the Zener diode can be reversed. Fig.14 A Zener diode ZR5 having the shape of a diode ZR formed in a well PW doped with a first conductivity type (P type), wherein the well PW is formed in a well N0 formed by deeply implanting a dopant of a second conductivity type (N type) in a substrate SUB. As above, the well PW is isolated from the well N0 by a trench isolation STI8. The well N0 can be isolated from the substrate SUB by a shallow trench isolation STI9. The diode ZR5 includes a vertical gate GT6 embedded in the well PW. Fig.14 In the example, the gate GT6 defines a highly doped cathode region CD6 of a second conductivity type (N+ type) superimposed on a highly doped region ZD6 of a first conductivity type (P+ type) on one side with a trench isolation STI8. The gate GT6 defines a highly doped anode connection region ED6 of a first conductivity type (P+ type) on the other side with a trench isolation STI8. Corresponding contact pads CDC and EDC are provided on top of regions CD6 and ED6. The well N0 is biased (grounded) by a highly doped bias region SNC of a second conductivity type (N+ type), and a bias contact pad SNC is provided on top of each bias region. It should be noted that the Zener diode ZR5 is reverse biased by applying a voltage greater than the voltage applied to the contact pad EDC to the cathode contact pad CDC to bias the well PW. Here, region ZD6 can be omitted again for the same reasons as mentioned previously.

[0052] Furthermore, it goes without saying that the various embodiments described above can be combined in different ways while remaining within the framework of the present invention.

Claims

1. An electronic device, comprising: A semiconductor substrate having a first surface; an anode region formed in the substrate, the anode region having a first conductivity type; a cathode region formed in the substrate and extending from the first surface into the substrate, the cathode region having a second conductivity type; a Zener diode junction between the anode region and the cathode region; a gate extending from the first surface into the substrate; as well as A gate dielectric layer is between the Zener diode junction and the gate, and the gate dielectric layer is in abutting contact with side surfaces of the anode region and the cathode region. 2 . The electronic device of claim 1 , wherein the cathode region is over at least a portion of the anode region. The electronic device of claim 1 , wherein the dielectric layer has a thickness between 15 nm and 25 nm.

4. The electronic device of claim 1, wherein the Zener diode junction is aligned substantially parallel to the first surface of the substrate.

5. The electronic device according to claim 1, further comprising: A well is formed in the substrate, the well having the first conductivity type, wherein the anode region is formed in the well, the gate is over at least a portion of the well and the gate dielectric layer abuts a first side surface and a second side surface of the well.

6. The electronic device according to claim 5, further comprising: An anode connection region having the first conductivity type extends from the first surface of the substrate into the well and is separated from the cathode region by the gate.

7. The electronic device according to claim 6, further comprising: A shallow trench isolation at least partially surrounds the cathode region, the anode connection region, the well, and the gate. 8 . The electronic device of claim 7 , wherein the well is isolated from at least a portion of the substrate by the shallow trench isolation.

9. The electronic device according to claim 7, further comprising: A substrate bias region has a higher doping level of the second conductivity type than the substrate, the substrate bias region extending from the first surface into the substrate and separated from at least one of the anode connection region and the cathode region by the shallow trench isolation.

10. The electronic device according to claim 1, further comprising: A thin region of the first conductivity type is located between the anode region and the cathode region, the thin region having a higher doping level of the first conductivity type than the anode region.

11. The electronic device of claim 1, wherein the gate surrounds the Zener diode junction. 12 . The electronic device of claim 11 , wherein the gate has one of an octagonal shape and a rectangular shape.

13. An electronic device comprising: A semiconductor substrate having a first surface; an anode region formed in the substrate, the anode region having a first conductivity type; a cathode region having a second conductivity type formed in the substrate and extending from the first surface into the substrate, the cathode region being over at least a portion of the anode region; a Zener diode junction between the anode region and the cathode region; as well as A gate structure extends from the first surface into the substrate, the gate structure including opposing first and second side surfaces in abutting contact with the Zener diode junction. 14 . The electronic device of claim 13 , the gate structure comprising a gate and a gate dielectric layer, wherein the gate dielectric layer surrounds the gate and abuts the Zener diode junction.

15. The electronic device according to claim 14 further includes a well formed in the substrate, the well having the first conductivity type, wherein the anode region is formed in the well, the gate is above at least a portion of the well and the gate dielectric layer abuts the first side surface and the second side surface of the well.

16. The electronic device according to claim 15, further comprising: a first shallow trench isolation at least partially surrounding the cathode region, the anode region and the gate; a second shallow trench isolation at least partially surrounding the well; as well as An anode connection region extends from the first surface of the substrate into the well and is separated from the cathode region by the first shallow trench isolation, wherein the anode connection region is located between the first shallow trench isolation and the second shallow trench isolation.

17. A method for manufacturing an electronic device, comprising: forming an anode region in a semiconductor substrate, the anode region having a first conductivity type; forming a cathode region in the substrate, the cathode region having a second conductivity type and extending from the first surface into the substrate; forming a gate extending from the first surface into the substrate; as well as A gate dielectric layer is formed between the gate and a Zener diode junction formed between the anode region and the cathode region, and the gate dielectric layer is formed in abutting contact with side surfaces of the anode region and the cathode region.

18. The method according to claim 17, further comprising: A well having the first conductivity type is formed in the substrate, wherein forming the anode region includes forming the anode region in the well, and forming the gate includes forming the gate over at least a portion of the well.

19. The method according to claim 18, further comprising: A shallow trench isolation is formed at least partially surrounding the cathode region, the anode region, the well, and the gate.

20. The method of claim 17, further comprising: A thin region having the first conductivity type is formed between the anode region and the cathode region, the thin region having a higher doping level of the first conductivity type than the anode region.

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