Interleaved and tiled stack micro device integration and driving

Abstract

This application relates to staggered and tiled stack micro device integration and driving. Structures and methods for integrating micro devices into a system or receiver substrate are disclosed. The integration of micro devices is facilitated by adding a staging pad to a micro device before or after transfer. A stage is created after the first micro device is transferred to the substrate for micro device transfer after the first (or the second) micro device transfer. The stage improves the surface profile of the substrate so that the next micro device can be transferred without the first micro device on the substrate being damaged or disturbed by the surface of the donor or transfer head. Some embodiments further relate to assembling display devices and more particularly to stacking tiles to a backplane to form the assembled display device.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 809,163, filed February 22, 2019, and U.S. Provisional Patent Application No. 62 / 823,350, filed March 25, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to integrating microdevices into a system or receiver substrate, and more specifically, to creating stages to improve the surface profile of the receiver substrate. Some embodiments further relate to tiled display devices, and more specifically, to stacking tiles onto a backplane to form a tiled display device. Background Technology

[0004] Many microdevices (including light-emitting diodes (LEDs), organic LEDs, sensors, solid-state devices, integrated circuits, microelectromechanical systems (MEMS), and other electronic components) are typically fabricated in batches, usually on planar substrates. To form an operating system, microdevices from at least one donor substrate need to be transferred to a receiver substrate. Summary of the Invention

[0005] According to one embodiment, a method for integrating microdevices may be provided. The method may include: providing one or more microdevices on a donor substrate; integrating a first set of microdevices from the donor substrate into a system substrate; providing one or more hierarchical pads to a second set of devices on the donor substrate; and integrating the second set of microdevices into the system substrate.

[0006] According to another embodiment, a method for stacking modular structure layers onto a substrate may be provided. Each modular structure layer includes a plurality of microdevices. The method may include: releasing a first modular structure layer on the substrate; providing a second modular structure layer on the substrate and aligning it with the first modular structure layer; and bonding the first modular structure layer and the second modular structure layer on the substrate, wherein the first modular structure and the second modular structure are physically separated from each other.

[0007] According to one embodiment, a display device may be provided. The display device may include a plurality of tile structures stacked on top of each other, each of the tile structures comprising: a substrate; an array of microdevices disposed on the substrate; a top electrode disposed on a first surface of each microdevice; and a bottom electrode disposed on a surface opposite to the first surface of the microdevice; and a backplate coupled to the plurality of tile structures.

[0008] According to another embodiment, a solid-state array device may be provided. The solid-state array may include one or more pixels, each pixel having two or more microdevices, and at least one of the two microdevices is coupled to a pixel circuit, and each microdevice is coupled to a bias voltage via a corresponding switch. Attached Figure Description

[0009] The foregoing and other advantages of the present invention will become apparent from the following detailed description and with reference to the drawings.

[0010] Figure 1A This demonstrates a process for integrating multiple microdevices into a system substrate according to an embodiment of the present invention.

[0011] Figure 1B Examples of processing steps for integrating multiple devices into a substrate (temporary or system substrate) according to embodiments of the present invention are shown.

[0012] Figure 1C This illustrates another example of a processing step for integrating multiple devices into a substrate (temporary or system substrate) according to an embodiment of the invention.

[0013] Figure 2A A system substrate with an integrated first microdevice is shown according to an embodiment of the present invention.

[0014] Figure 2B-1 A system substrate with an integrated microdevice and a stage pad for realizing the integration of a second microdevice is shown according to an embodiment of the present invention.

[0015] Figure 2B-2 A donor substrate with an integrated microdevice and a stage pad for realizing the integration of a second microdevice is shown according to an embodiment of the present invention.

[0016] Figure 2C This demonstrates the integration of at least one other microdevice with a stage on a receiver substrate according to an embodiment of the invention.

[0017] Figures 3A to 3C A system (or temporary) substrate according to an embodiment of the invention is shown, wherein a microdevice different from a first microdevice is transferred to a different layer than the first microdevice.

[0018] Figure 4 A stacked microdevice with a pad is shown according to an embodiment of the present invention, while sharing at least one electrode and a pad.

[0019] Figure 5 A top view of a stacked microdevice according to an embodiment of the present invention is shown.

[0020] Figure 6This invention illustrates a stacked microdevice with pads according to an embodiment of the invention, and individual electrodes and pads for each device.

[0021] Figure 7 A stacked microdevice with pads on a system substrate is shown according to an embodiment of the present invention.

[0022] Figures 8A to 8E Different arrangements of microdevices and stages are shown according to embodiments of the present invention.

[0023] Figures 9A to 9B An exemplary pixel structure with shared electrodes between different microdevices is shown according to an embodiment of the present invention.

[0024] Figures 10A to 10B An exemplary pixel structure with a shared electrode between a microdevice and a switch, according to an embodiment of the present invention, is shown.

[0025] Figures 10C to 10D Examples of switching operations during different operating cycles according to embodiments of the present invention are shown.

[0026] Figure 10E Demonstrating embodiments similar to those according to the present invention Figure 10A and 10B Another embodiment of the general execution.

[0027] Figures 11A to 11B An exemplary pixel structure is shown in an embodiment of the invention in which more than two microdevices share the same contact / electrode.

[0028] Figures 12A to 12B An exemplary pixel structure is shown in an embodiment of the invention in which more than two microdevices share the same contact / electrode.

[0029] Figures 13A to 13B An exemplary pixel structure according to an embodiment of the present invention is shown.

[0030] Figures 14A to 14B An exemplary pixel structure according to an embodiment of the present invention is shown.

[0031] Figure 15A A pixel diagram showing a shared driving / sensing element and a separate storage element with different microdevices according to an embodiment of the present invention.

[0032] Figure 15B The switching configurations during different operating cycles according to embodiments of the present invention are shown.

[0033] Figure 16A Another pixel block diagram showing a shared driving / sensing element and a separate storage element with different microdevices according to an embodiment of the present invention is shown.

[0034] Figure 16B The switching configurations during different operating cycles according to embodiments of the present invention are shown.

[0035] Figure 17 A cross-section of a monochromatic patchwork structure with a top metallized structure is shown according to an embodiment of the present invention.

[0036] Figure 18 A stacked patch structure incorporated into a system (or temporary) substrate is shown according to an embodiment of the present invention.

[0037] Figure 19A A cross-section of the first piecework layer structure being transferred to a substrate according to an embodiment of the present invention is shown.

[0038] Figure 19B A cross-section of a patterned first and second tile layer structure according to an embodiment of the present invention is shown.

[0039] Figure 19C A cross-section of the first and second panels bonded to a system substrate according to an embodiment of the present invention is shown.

[0040] Figure 19D Cross-sections of patterned second and third tile layer structures according to embodiments of the present invention are shown.

[0041] Figure 19E A cross-section of a third-layer structure incorporated into a system substrate according to an embodiment of the present invention is shown.

[0042] Figure 20A The diagram illustrates a cross-section of a first non-metallized tile layer structure transferred to a substrate and through a via formed by the tiles, according to an embodiment of the invention.

[0043] Figure 20B A cross-section of a patterned first and second tile layer structure according to an embodiment of the present invention is shown.

[0044] Figure 20C A cross-section of the first and second panels bonded to a system substrate according to an embodiment of the present invention is shown.

[0045] Figure 20D Cross-sections of patterned second and third tile layer structures according to embodiments of the present invention are shown.

[0046] Figure 20E A cross-section of a third-layer structure incorporated into a system substrate according to an embodiment of the present invention is shown.

[0047] Figures 21A to 21CA cross-section of a colored tile having a bonding pad formed on top of a stacked layer, according to an embodiment of the invention, is shown.

[0048] Figure 22 Another cross-section of a full-color patchwork incorporated into a system (or temporary) substrate according to an embodiment of the invention is shown.

[0049] Figures 23A to 23N A cross-sectional view showing the processing steps of stacking pieces onto a back panel according to an embodiment of the present invention.

[0050] Figure 24 Demonstrating embodiments according to the present invention Figure 23N The image shows a top view of the assembled stacked displays.

[0051] The same reference numerals used in different diagrams indicate similar or identical elements.

[0052] While various modifications and alternatives are permissible with respect to the invention, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the invention is not intended to be limited to the specific forms disclosed. Rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. Detailed Implementation

[0053] In this description, the terms "device" and "microdevice" are used interchangeably. However, those skilled in the art will understand that the embodiments described herein are independent of device size.

[0054] In this description, the terms "system substrate," "receiver substrate," and "backplane" are used interchangeably. However, those skilled in the art will understand that the embodiments described herein are independent of substrate type.

[0055] According to one embodiment, one or more stages may be created after the first microdevice is transferred to a system (temporary) substrate for subsequent microdevice transfers. The stages improve the surface profile of the system (temporary) substrate, allowing the transfer of the next microdevice without damage or interference to the surface of the donor or transfer head.

[0056] According to another embodiment, the stage may be a planarization layer formed on the substrate after the first microdevice is transferred. In one case, the stage is a pillar formed on the substrate. In another case, the stage is a pillar formed on the surface of the microdevice.

[0057] According to one embodiment, the level can be a combination of the above methods.

[0058] According to another embodiment, the stage is conductive and can connect a microdevice to a signal. In one case, a via can be made through the stage to couple the microdevice to the signal. In another case, a pad can be formed in the via for connection.

[0059] According to one embodiment, the first microdevice may be part of a stage.

[0060] According to another embodiment, the conductive layer can connect a common electrode to first and second (or other stacked) microdevices. In one case, the conductive layer is part of a stage.

[0061] According to one embodiment, the second microdevice may slightly overlap with, but not completely cover, the first device. After depositing and etching the second electrode, a bonding layer may be added to the electrode, and then the second device is integrated. This process can be repeated for all further device integration.

[0062] In one embodiment, a reflective layer may be added to an individual device or to an entire group of devices for each pixel in these embodiments. Conductive electrodes may also be used as a reflective layer.

[0063] In another embodiment, the top electrode may have two parts: a reflective portion on the vertical side and a transparent electrode on the top side.

[0064] In one embodiment, an electrode is connected to two different microdevice contacts. Here, a switch is used to couple the electrode to different signals depending on the function of the different microdevices.

[0065] In one case, the hierarchical pad profile in all the structures mentioned herein may be above or below the system substrate surface. In another case, the hierarchical pad profile may be made of several different layers. In one embodiment, the hierarchical pad may be above the system substrate surface to provide more selectivity.

[0066] In one embodiment, the graded pad is conductive and creates an electrical connection between the system substrate and the microdevice.

[0067] In another embodiment, one or more planarization layers may be formed flush with the surface of the system substrate. In one case, openings through the planarization layer may be provided to create contact between the microdevice and the system substrate. In another case, the hierarchical pad and the planarization layer may be identical. In yet another case, the hierarchical pad may be formed separately.

[0068] In one scenario, a microdevice may have more than one connection on each side.

[0069] In one embodiment, the backsheet may be formed on top of, on bottom of, or between the planarization layer.

[0070] In another embodiment, a buffer layer or release layer may be formed on the system substrate prior to the microdevice. The buffer layer and the release layer may be the same or different layers.

[0071] In another case, the bonding layer can be added to the electrodes and microdevices.

[0072] In one embodiment, a reflective layer may be added to an individual device. In another case, a conductive electrode may also be used as a reflective layer. In this case, the top electrode may have two parts: a reflective portion on the vertical side and a transparent electrode on the top side.

[0073] In another embodiment, when the devices share electrodes, the devices can be driven by a combination of methods.

[0074] In one embodiment, a pixel structure with shared electrodes between different microdevices can be provided.

[0075] In another embodiment, a programmable switch may be provided to change the pixel configuration.

[0076] In one embodiment, time-based multiplexing can be performed. Here, the driver is shared among the devices and can be allocated to each device at a given time during the frame time.

[0077] Various embodiments of the present invention’s structure and process will be described in detail below.

[0078] refer to Figure 1A This provides a block diagram illustrating examples of transferring and integrating multiple microdevices into a system substrate. In one embodiment, one or more microdevices may be fabricated on a donor substrate. One or more microdevices may be transferred and integrated into a system substrate or a temporary substrate. Microdevices may be transferred from different donor substrates. Block diagram 100 may include one or more donor substrates (104, 106) and one or more microdevices fabricated thereon. Multiple donor substrates may be present. Transfer mechanism 108 may be applied to transfer one or more microdevices from one or more donor substrates to a landing area on system substrate 110.

[0079] Figure 1BThis describes an example method for integrating multiple devices into a system substrate. In a first step 110, at least one microdevice may be transferred into the system substrate. In step 120, after transferring the first microdevice, a stage for at least one second microdevice is formed on the system substrate, wherein the top of the second microdevice is higher than the top of the first microdevice. The stage may also have adhesive properties to facilitate the transfer of the microdevice. In another case, an additional bonding layer may be formed on top of the stage. Further, in step 114, at least one second microdevice is transferred onto the stage, and in step 116, the substrate surface is planarized. In some cases, the planarization layer may be removed, and a post-processing step may be performed in step 118. The post-processing may include electrode deposition, forming vias / openings for access to the microdevice, optical layer deposition, etc.

[0080] Figure 1C This describes an example method for processing steps to integrate multiple devices into a system substrate. In a first step 110-1, at least one microdevice may be transferred into the system substrate. In step 120-1, after the transfer of the first microdevice, a stage for at least one second microdevice is formed on the system substrate, wherein the stage is at or above a distance from the substrate surface, and the second microdevice will land on top of the first microdevice. The stage may also have adhesive properties to facilitate the transfer of the microdevice. In another case, an additional bonding layer may be formed on top of the stage. Further, in step 114-1, at least one second microdevice is transferred onto the stage, and in step 116-1, the substrate surface is planarized. In some cases, the planarization layer may be removed, and a post-processing step may be performed in step 118-1. The post-processing may include electrode deposition, forming vias / openings for access to the microdevice, optical layer deposition, etc.

[0081] Figure 2A A system substrate with a first integrated microdevice is shown according to an embodiment of the present invention. Here, the system or temporary substrate 200 may have landing regions (or landing surfaces) (202, 206) formed on the surface of the system substrate 200. Pads may be present as part of the landing regions (202, 206) of the microdevice. The pads may be used only to assist transfer (e.g., bonding or adhesive layers) or to couple the microdevice to a signal. The first microdevice 204 is transferred from the donor substrate and integrated into a corresponding landing region 202 on the system substrate 200.

[0082] In one embodiment, a stage may be formed on the surface of the system substrate, wherein a second microdevice (landing area) is transferred to achieve integration of the second microdevice and improve the surface profile of the receiver substrate. The stage may be on top of a pad or directly on another surface. The height of the stage is equal to or greater than the combined height of the first microdevice plus the first landing area minus the height of the landing area of ​​the second microdevice.

[0083] In one scenario, the grading pads can be deposited and etched onto the substrate. In another scenario, the grading pads can be transferred, printed, or deposited onto the substrate.

[0084] Figure 2B-1 A system substrate with a stage for integrating a first microdevice and for integrating a second microdevice, according to an embodiment of the invention, is shown. Here, a stage 207 may be provided to facilitate the integration of the second microdevice. Stage 207 may be formed on the top surface of a corresponding landing region 206, where the second microdevice will be transferred. Stage 207 serves to prepare the surface of the system substrate for the integration of the second microdevice. Here, after the first microdevice 204 is integrated into the system substrate, the position of the second (or more) microdevices can be raised by adding stage / level pads to facilitate the integration of the second and other microdevices. This process can continue for the integration of several other microdevice families. Stage 207 may be on top of the pads or directly on another surface. The height of stage 250 is equal to or greater than the combined height 252 of the first microdevice 204 plus the first landing region 202 minus the height of the landing region 206 of the second microdevice 208.

[0085] In one embodiment, a stage may be formed on a temporary substrate before the second microdevice is transferred to the system substrate.

[0086] Figure 2B-2 A donor substrate with integrated microdevices and graded pads for integrating second microdevices is shown according to an embodiment of the invention. Here, the donor substrate 100 may have grades 207 formed on microdevice 208 before being transferred to the system substrate. In one case, one or more graded pads may be used for each microdevice. In another case, graded pads may be added only to the device region to be integrated next.

[0087] In one embodiment, a microdevice donor substrate having at least one stage microdevice may be prepared for integration into a system substrate containing at least one other microdevice.

[0088] Figure 2C This illustrates the integration of at least one additional microdevice with a stage on a receiver substrate according to an embodiment of the invention. Here, the second microdevice 208 and stage 207 on the donor substrate can be transferred to a corresponding landing region 206 on a system substrate 200 containing at least one additional microdevice. Stage 207 is conductive and creates an electrical connection between the system substrate 200 and the second microdevice 208. The stage can be transferred to the system substrate by any of the methods described in this invention or other methods, or it can be deposited or etched.

[0089] If more than two devices are integrated into the system substrate, a second hierarchical pad can be moved to the regions of the second and third devices. Then, after integrating the second device, another hierarchical pad is moved to the location where the third device can be integrated. This process can also be followed for more than three devices.

[0090] In one embodiment, the grading pad may be raised above the system substrate surface to provide greater selectivity during transfer. After all devices have been transferred, a planarization layer can be used to flatten the surface. If a common electrode is required, openings need to be created in the planarization layer to deposit the common electrode.

[0091] In one case, the grading pad and the planarization layer can be the same. In another case, the grading pad can be formed separately.

[0092] Figures 3A to 3C A system (or temporary) substrate according to an embodiment of the invention is shown, wherein a microdevice different from a first microdevice is transferred to a different layer than the first microdevice. Reference Figures 3A to 3C It can provide an interlaced structure to integrate microdevices into the system substrate. Figure 3A Demonstrates a system (or temporary) substrate in which a second microdevice, distinct from the first microdevice, is transferred to a layer different from the first microdevice. The system substrate comprises the above-described ( Figure 2B-1 and 2C The integration of the first microdevice 304 and the second microdevice 308 is described in the following section. The first microdevice 304 is transferred to a corresponding landing region 302 on the system substrate. The second microdevice 308 can be transferred to a different layer than the first microdevice 304. After integrating the first microdevice 304, the surface of the system substrate is flush with the planarization layer 305. An opening 320 can then be formed through the planarization layer 305 to create a connection between the second microdevice 308 and the system substrate 300. Electrodes 307 can be provided to the second microdevice 308 to establish a connection with the system substrate 300.

[0093] Figure 3B A system (or temporary) substrate 300 is shown, in which a second microdevice, distinct from the first microdevice 304, is transferred to a different layer than the first microdevice 304. After integrating the first microdevice 304, the surface of the system substrate is flush with a planarization layer 305. An opening 320 can then be formed through the planarization layer 305 to create a connection between the second microdevice 308 and the system substrate 300. An electrode 307 can be provided to the second microdevice 308 to establish a connection with the system substrate 300; the electrode 307 can also be a common electrode for the first microdevice.

[0094] Figure 3CThe system (or temporary) substrate shows two microdevices (304, 308) sharing a common electrode 307. A planarization layer 305 may extend to the surface of the second microdevice 308. Another electrode 312 of the second microdevice 308 may be present through a second opening in the planarization layer 305.

[0095] Figure 4 A stacked microdevice with a graded pad is shown according to an embodiment of the invention, sharing at least one electrode and pad. A temporary substrate / cassette substrate 300 may be provided. A buffer layer / release layer 316 may be deposited on the cassette substrate 300 to facilitate microdevice release. The buffer layer 316 may be formed prior to the microdevice. The release layer may be a separate layer formed on top of the substrate. The release layer may be the same as the buffer layer. Two microdevices 304 and 308 may be provided. The two microdevices may share at least one common electrode 307 and a common graded pad 312. A separate stage 314 may be provided for the first microdevice 304 on the landing region 302, and a separate stage 310 may be provided for the second microdevice 308.

[0096] Figure 5 Demonstrating embodiments according to the present invention Figure 4 The image shows a top view of the stacked microdevices. Here, microdevice 304 has a shared hierarchical pad 312. A planarization layer 305 can be deposited to cover the microdevice and the hierarchical pad. A buffer / release layer 316 can be deposited on the cartridge substrate to facilitate microdevice release. A separate hierarchical pad 314 can be provided for the first microdevice 304.

[0097] Figure 6 A stacked microdevice with pads is shown, each pad having a separate electrode and pad for each device. A cartridge substrate 300 is provided here. A buffer / release layer 316 may be deposited on the cartridge substrate 300 to facilitate microdevice release. Two microdevices 304 and 308 may be provided here. The two microdevices may be stacked together with separate electrodes and hierarchical pads. Here, the first microdevice 304 may have electrodes 302 and stages (314 and 312-B). The second microdevice 308 may have another electrode 307 and stages (310 and 312-A).

[0098] Figure 7A stacked microdevice with pads on a system substrate is shown according to an embodiment of the invention. Here, a stack of multiple microdevices with hierarchical pads on the system substrate may be provided. For example, three microdevices 702, 704, and 706 are provided here. A first microdevice 702 may be integrated into a system substrate 700. In one case, a hierarchical pad may be present for integration of the first microdevice 702 into the system substrate. In another case, the first microdevice 702 may be directly integrated into the system substrate. A hierarchical pad 704-2 may be provided for integration of a second microdevice (e.g., 704) to facilitate integration of the second microdevice 704 into the system substrate. The hierarchical pad 704-2 prepares the surface of the system substrate for integration of the second microdevice 704.

[0099] In one embodiment, after the first microdevice 702 is integrated into the system substrate, the integration location of the second (or subsequent) microdevices can be improved by adding hierarchical pads that facilitate the integration of second and other microdevices. This process can continue for the integration of several other families of microdevices. For example, a third microdevice 706 can be integrated into the system substrate using raised hierarchical pads 706-2.

[0100] In one embodiment, the hierarchical pad is conductive for connecting microdevices to signals. In another embodiment, a planarization layer 705 may be formed on and above the microdevices and the hierarchical pad. Vias (712, 714, 716) may be formed through the planarization layer 705 to provide electrodes (720, 724, 726) to each microdevice for connecting the microdevice to signals. In one case, the microdevice may have more than one connection on each side. In this case, each microdevice may require more than one via. The hierarchical layer may be the same as the planarization layer (the planarization layer may be deposited after each device).

[0101] In another embodiment, the backsheet may be formed on top of the planarization layer. In one case, the backsheet may be at the bottom or between the planarization layers.

[0102] In one embodiment, a buffer layer may be formed prior to the formation or transfer of the microdevice. In another embodiment, a release layer may be formed on top of the substrate. The release layer and the buffer layer may be the same or different layers.

[0103] Figures 8A to 8E Different arrangements of microdevices and levels are shown according to embodiments of the present invention. Here, a system (or temporary) substrate may be provided, wherein microdevices different from the first microdevice are transferred to different levels in different arrangements than the first microdevice.

[0104] refer to Figure 8AHere, the microdevices overlap and are connected via a common electrode. In one case, the microdevices (802, 804, and 806) can overlap (a stage can be used on the other side of the support device). Overlapping can be used to connect the common electrode 820. In one case, the common electrode 820 can be connected to both the bottom and top sides of the device. Connecting the microdevices is achieved by stacking them one on top of the other. Each microdevice may also have one or more other connections. A first microdevice 802 can be transferred into a substrate 800. A second microdevice 804, different from the first microdevice 802, can be transferred to the substrate at a different level than the first microdevice. After transferring the first microdevice, a planarization layer 805 can be formed on the substrate. The stage can be the planarization layer 805. The stage is conductive and can connect the microdevice to a signal. Furthermore, vias / openings are made through the stage to couple the microdevice to a signal. Electrodes 814 for the first microdevice can be provided through the openings. A common connection 810 can be provided between the first microdevice 802 and the second microdevice 804. This process can be continued for the integration of third and more device families. After integrating the second microdevice, another stage is transferred. The third microdevice 806 can be transferred to the substrate. The second and third microdevices can share a connection 812. A common electrode 820 can be provided for all transferred microdevices.

[0105] Figure 8B Demonstrating embodiments according to the present invention Figure 8A A top view. Here, the microdevices overlap and are connected via a common electrode. In one case, the microdevices (802, 804, and 806) may overlap (a stage can be used to support the other side of the device). Overlapping can be used to connect the common electrode 820. In one case, the common electrode 820 may be connected to both the bottom and top sides of the device. Connecting the microdevices is achieved by stacking them one on top of the other. Each microdevice may also have one or more other connections; for example, the first microdevice 802 may have an electrode / contact 822-1, the second microdevice may have an electrode / contact 822-2, and the third microdevice 806 may have an electrode / contact 822-3.

[0106] Figure 8C Different arrangements of microdevices and stages are illustrated according to embodiments of the present invention. Microdevices 802, 804, and 806 may be provided here. Each microdevice may have corresponding electrodes and contacts to establish a connection with the system substrate. For example, microdevice 806 may have individual electrodes 822 and contacts 828-3. Furthermore, a common electrode 820 may be formed on top to provide a connection to the microdevice.

[0107] Figure 8DDifferent arrangements of placing microdevices and stages according to embodiments of the present invention are illustrated. Here, three microdevices 802, 804, and 806 may be provided. The microdevices may have a common connection. A common connection 810-1 between the first microdevice 802 and the second microdevice 804 and a common connection 810-2 between the second microdevice 804 and the third microdevice 806 may exist. In one case, each microdevice may have a corresponding electrode to establish a connection with the system substrate 800. In another case, a common electrode 820-1 may exist between the microdevices. Furthermore, a planarization layer 805 may be formed on the substrate after the first microdevice is transferred. The stage may be the planarization layer 805. The stage is conductive and can connect the microdevices to signals.

[0108] Figure 8E Demonstrating embodiments according to the present invention Figure 8D A top view. Here, the microdevices are connected via a common electrode. In one case, the common electrode 820 may be connected to both the bottom and top sides of the device. The connection between the microdevices is achieved by stacking them one on top of the other. Each microdevice may also have one or more other connections; for example, the first microdevice 802 may have electrodes 822-3 and contacts 822-4.

[0109] According to one embodiment, a solid-state array device may be provided. The solid-state array device may include one or more pixel circuits, each pixel circuit having two or more microdevices, at least one of the two microdevices being coupled to a pixel circuit, and each microdevice being coupled to a bias voltage via a switch.

[0110] According to another embodiment, one of the microdevices is decoupled from the shared pixel circuitry via a switch and coupled to a bias voltage that turns off the microdevice.

[0111] Figure 9 shows a pixel structure with shared electrodes among different microdevices. Figures 9A to 9B A driving scheme for a microdevice according to an embodiment of the present invention is illustrated. Here, the embodiment demonstrates a combined driving method for devices having shared electrodes. Three microdevices 912, 916, and 920 may have corresponding pixel circuits 910, 914, and 918. In the case of devices sharing electrodes, a combined method can be used to drive the devices. Figures 9A to 9B An example of this driver scheme is shown. In

[0112] Figure 9A Voltage source V B It can be applied to each microdevice. I1 defines the driving force of the first device 912, I1+I2 defines the driving force of the second device 916, and I1+I2+I3 defines the driving force of the third device 920. This daisy chain can also be extended to more devices. Figure 9BAn alternative arrangement of microdevices 912, 916, and 920 is shown, where I3 defines the driving force of the third device 920, I2+I3 defines the driving force of the second device 916, and I1+I2+I3 defines the driving force of the first device 912. This daisy chain can also be extended to more devices. In one case, each of the voltage sources can be replaced by a current source.

[0113] Figures 10A to 10E A time-multiplexing driver scheme according to an embodiment of the present invention is illustrated. In one case, time multiplexing can be provided between devices. Here, the driver is shared between devices and can be allocated to each device at a given time during the frame time.

[0114] Figure 10A and 10B Demonstrates exemplary pixel structures that use shared electrodes between different microdevices and switches to change pixel configurations. (Reference) Figure 10A and 10B The three microdevices 1012, 1016, and 1020 may have corresponding pixel circuits 1010, 1014, and 1018. Switch configurations 1022, 1032, 1034, 1042, and 1044 may be provided to each device to connect the device to pixel circuits 1010, 1014, and 1018 or bias voltages VB1, VB2, and VB3. For example, a switch 1022 is provided to device 1012 to provide a voltage source VB2 coupled to switches 1032 and 1034 to device 1016, and a voltage source VB3 coupled to switches 1042 and 1044 can be provided to device 1020.

[0115] In another embodiment, pixel circuits 1010, 1014 and 1018 may be a single pixel circuit and shared among devices 1012, 1016 and 1020, and may be allocated to each device 1012, 1016 and 1020 at a given time during the frame time.

[0116] Figure 10C Examples of switching operations during different operating cycles are shown. Each device is connected to the pixel circuitry and is in an operating mode for at least a subframe of the frame time. During the operating mode, the switch connecting the device to the pixel circuitry is turned on, and the switch biasing the other side of the device to a bias voltage is turned off. During other times in the frame, the device is not connected to the pixel circuitry and is inoperable. For the inoperable mode, the device may be disconnected from the pixel circuitry and connected to the bias voltage on both sides, or at least one side may float. The bias voltage is set to ensure the device is turned off.

[0117] refer to Figure 10CDuring the first subframe, switches 1022, 1034, and 1044 are turned on while other switches 1032 and 1042 are turned off. Therefore, device 1012 is coupled to pixel circuit 1010, and other devices 1016 and 1020 are decoupled from pixel circuits 1014 and 1018. Thus, device 1012 is operable and controlled by pixel circuit 1010, while other devices 1016 and 1020 are inoperable.

[0118] refer to Figure 10C During the second subframe, switches 1032 and 1044 are turned on while other switches 1022, 1034, and 1042 are turned off. Therefore, device 1016 is coupled to pixel circuit 1014, and other devices 1012 and 1020 are decoupled from pixel circuits 1010 and 1018. Thus, device 1016 is operable and controlled by pixel circuit 1014, while other devices 1012 and 1020 are inoperable.

[0119] refer to Figure 10C During the third subframe, switches 1042 and 1034 are turned on while other switches 1022, 1044, and 1032 are turned off. Therefore, device 1020 is coupled to pixel circuit 1018, and other devices 1012 and 1016 are decoupled from pixel circuits 1010 and 1014. Thus, device 1020 is operable and controlled by pixel circuit 1018, while other devices 1012 and 1016 are inoperable.

[0120] refer to Figure 10D The on-time of each device is extended, and at least two devices are operable during one subframe. During the first and third subframes, devices 1012 and 1020 are operable and controlled by pixel circuits 1010 and 1018, while device 1016 is inoperable. During the second and fourth subframes, device 1016 is coupled to 1014, and the other devices 1012 and 1020 are inoperable. One can combine the first and third subframes and combine the second and fourth subframes.

[0121] Figure 10E The display is similar to Figure 10A and 10B Another embodiment of the general implementation. However, the two pixel circuits 1010, 1014 are connected to the same point shared between the two devices 1012 and 1016. Here, one can merge the two circuits 1010, 1014 and eliminate switches 1022, 1032. The operation of this pixel and device arrangement can be similar to Figure 10C and 10D The operation.

[0122] Figures 11A to 11B Other embodiments of the invention, in which more than two microdevices share the same contact / electrode, are shown. References Figure 11A and11B The three microdevices 1112, 1116, and 1120 may have corresponding pixel circuits 1110, 1118, and 1114. Switch configurations 1142, 1144, 1132, and 1122 may be provided to connect devices 1112, 1116, and 1120 to pixel circuits 1110, 1118, and 1114 or bias voltages VB3, VB2, VB4, and VB5. For example, switch 1142 is provided to device 1120 and pixel circuit 1118, coupling voltage VB3 to switch 1144; switch 1132 is provided to device 1116 and pixel circuit 1114, coupling voltage source VB2 to switch 1134; and switch 1122 is provided to device 1112 and pixel circuit 1110. Here, the two pixel circuits 1118 and 1114 are connected to the same point shared between the two devices 1120 and 1116.

[0123] In some embodiments, the pixel circuit may be a single pixel circuit shared among devices and may be allocated to each device at a given time during the frame time.

[0124] refer to Figure 12A and 12B A pixel structure shared across different microdevices can be provided. In these embodiments, three microdevices 1212, 1216, and 1220 share a common pixel 1210. Switch configurations 1222, 1232, 1234, 1242, and 1244 can be provided to connect devices 1212, 1216, and 1220 to the common pixel circuit 1210 or bias voltages VB3 and VB2. Here, the common pixel circuit 1210 can be allocated to each microdevice at a given time during the frame time.

[0125] refer to Figure 13A and 13B This allows for a shared pixel structure across different microdevices. In these embodiments, three microdevices 1312, 1316, and 1320 may share a common pixel circuit 1310. Switch configurations 1322, 1332, and 1342 may be provided to connect devices 1312, 1316, and 1320 to the common pixel circuit 1310 and bias voltages VB3, VB2, and VB1. Here, the common pixel circuit 1310 may be allocated to each microdevice at a given time during the frame time.

[0126] refer to Figure 14A and 14BA pixel structure can be provided that is shared across different microdevices. In these embodiments, three microdevices 1412, 1416, and 1420 share a common pixel circuit 1410. Switch configurations 1422, 1432, and 1442 can be provided between the common pixel circuit 1410 and the devices 1412, 1416, and 1420 connected to bias voltages VB3, VB2, and VB1.

[0127] refer to Figure 15A It can provide pixel maps with shared drives and individual storage elements for different microdevices. (Reference) Figure 15A The three storage elements 1510-B1, 1510-B2, and 1510-B3 may have a common pixel element 1510-A. Switch configurations 1550, 1560, and 1570 may be provided to each storage element to connect to the common pixel element 1510-A or to a common bias voltage VBC via another switch 1580. Another switch configuration 1572, 1574, 1562, 1564, 1552, and 1554 may be provided to connect storage elements 1510-B1, 1510-B2, and 1510-B3 to individual bias voltages VB4, VB5, and VB6. The common pixel drive element 1510-A may be connected to microdevices 1512, 1516, and 1520, which are connected to corresponding bias voltages VB1, VB2, and VB3.

[0128] refer to Figure 15B This allows for switching configurations during different operating cycles. Each storage element is connected to a common pixel driver and is in operating mode for at least a subframe of the frame time. During operating mode, a switch connecting the storage element to the pixel driver element is turned on, and a switch biasing the other side of the storage element to a bias voltage is turned on. During other times in the frame, the storage element is not connected to the pixel driver element and is inoperable. For inoperable mode, the storage element can be disconnected from the pixel driver element and connected to the bias voltage on both sides, or at least one side can float. The bias voltage is set to ensure the storage element is turned off.

[0129] exist Figure 15B During the first subframe, switches 1570, 1560, 1550, 1574, 1564, 1580, and 1554 are turned on, while switches 1572, 1562, and 1552 are turned off. Therefore, all storage elements 1510-B1, 1510-B2, and 1510-B3 are operable. Figure 15BDuring the second subframe, switches 1580, 1560, 1550, 1574, 1562, 1564, 1552, and 1554 are turned off, while switches 1570 and 1572 are turned on. Therefore, only the first storage element 1510-B1 is operational and coupled to the pixel driver element, while the other storage elements 1510-B2 and 1510-B3 are decoupled from the pixel driver element and are inoperable.

[0130] exist Figure 15B During the third subframe, switches 1580, 1570, 1550, 1574, 1572, 1564, 1552, and 1554 are turned off, while switches 1560 and 1562 are turned on. Therefore, only the second storage element 1510-B2 is operational and coupled to the pixel driver element 1510-A, while the other storage elements 1510-B1 and 1510-B3 are decoupled from the pixel driver element and are inoperable.

[0131] exist Figure 15B During the fourth subframe, switches 1580, 1570, 1560, 1574, 1572, 1564, 1562, and 1554 are turned off, while switches 1550 and 1552 are turned on. Therefore, only the third storage element 1510-B3 is operational and coupled to the pixel driver element 1510-A, while the other storage elements 1510-B1 and 1510-B2 are decoupled from the pixel driver element and are inoperable.

[0132] Subframes 2 to 4 can be repeated during different operation cycles. Figure 15B This allows different switches to be turned on in each subframe, and thus the storage element is in operation during each subframe.

[0133] refer to Figure 16A It can provide pixel maps of shared drives and individual storage elements with different microdevices. (Reference) Figure 16A The three storage elements 1610-B1, 1610-B2, and 1610-B3 may have a common pixel element 1610-A. A switch configuration 1680 may be provided to connect each storage element 1610-B1, 1610-B2, and 1610-B3 to the common pixel element 1610-A or a common bias voltage VBC. The storage elements may include capacitors. Another switch configuration 1672, 1674, 1662, 1664, 1652, and 1654 may be provided to connect the storage elements 1610-B1, 1610-B2, and 1610-B3 to individual bias voltages VB4, VB5, and VB6. The common pixel drive element 1610-A may be connected to microdevices 1612, 1616, and 1620, which are connected to corresponding bias voltages VB1, VB2, and VB3.

[0134] exist Figure 16B During the first subframe, switches 1680, 1674, 1664, and 1654 are turned on, while switches 1672, 1662, and 1652 are turned off. Therefore, all storage elements 1610-B1, 1610-B2, and 1610-B3 are operational. Figure 16B During the second subframe, switches 1680, 1674, 1664, 1654, 1662, and 1652 are turned off, while switch 1672 is turned on. Therefore, only the first storage element 1610-B1 is operational and coupled to the pixel driver element, while the other storage elements 1610-B2 and 1610-B3 are decoupled from the pixel driver element and inoperable.

[0135] exist Figure 16B During the third subframe, switches 1680, 1674, 1664, 1654, 1672, and 1652 are turned off, while switch 1662 is turned on. Therefore, only the second storage element 1610-B2 is operational and coupled to the pixel driver element 1610-A, while the other storage elements 1610-B1 and 1610-B3 are decoupled from the pixel driver element and are inoperable.

[0136] exist Figure 16B During the fourth subframe, switches 1680, 1674, 1664, 1654, 1672, and 1662 are turned off, while switch 1652 is turned on. Therefore, only the third storage element 1610-B3 is operational and coupled to the pixel driver element 1610-A, while the other storage elements 1610-B1 and 1610-B2 are decoupled from the pixel driver element and are inoperable.

[0137] Subframes 2 to 4 can be repeated during different operation cycles. Figure 16B This allows different switches and therefore storage elements to be in operation in each subframe.

[0138] Module stacking for optoelectronic systems

[0139] Some embodiments of the present invention relate to modular display devices, and more specifically, to stacking modules onto a back panel to form a modular display device.

[0140] Here, different colored micro-LEDs are used to explain the invention. However, different microdevices can be used instead of colored micro-LEDs.

[0141] According to one embodiment, a method is provided for stacking a mosaic structure layer onto a substrate, each mosaic structure layer including a plurality of microdevices, the method comprising: releasing a first mosaic structure layer on the substrate; providing a second mosaic structure layer on the substrate and aligning it with the first mosaic structure layer; and bonding the first mosaic structure layer and the second mosaic structure layer on the substrate, wherein the first mosaic structure and the second mosaic structure are physically separated from each other.

[0142] In one embodiment, the modular structure may include one or more microdevices transferred onto a carrier substrate.

[0143] In another embodiment, a buffer layer may be formed on the carrier substrate before the microdevice is transferred to the substrate. The buffer layer may be a release layer, a support substrate, or a backplane layer.

[0144] In another embodiment, the microdevice is planarized. The planarization layer is patterned or etched back to establish connections to the microdevice.

[0145] In another embodiment, the first patchwork structure layer is released from the carrier substrate. Additional processing steps may be performed after the transfer of the first patchwork structure layer. For example, traces or bumps may be formed.

[0146] In another embodiment, the second tile structure layer is aligned with the first tile structure layer by alignment marks or by other structures in the first and second tile structure layers.

[0147] Then, in one embodiment, the second piece structure layer is bonded to the first piece structure layer by means of an adhesive layer or bonding pad.

[0148] In another embodiment, through-holes may be formed through the modular structure layers to connect the modular structure layers together or to provide connections for connecting different layers to a back panel.

[0149] In one embodiment, a system substrate is bonded at the top of the modular structure. In another embodiment, the substrate may be bonded at the bottom side of the modular structure.

[0150] In another embodiment, the backplate and substrate can be fabricated separately from the modules and then bonded together. In yet another embodiment, the backplate between the modules is flexible.

[0151] To improve the surface profile, in one embodiment, a patterned planarization layer is patterned in certain areas to provide recesses for incorporating microdevices from other tile layer structures.

[0152] In another embodiment, the driving circuitry may be formed on the substrate prior to the stacked tile layers. Vias / apertures may be used to connect the tiles to the driving circuitry. The driving circuitry may be pixel circuitry. A planarization and protective layer may be formed after the driving circuitry to prepare the surface for integration into the stacked tile structure. The driving circuitry may also be a tile structure transferred to the substrate.

[0153] In one embodiment, a common electrode connecting one terminal of the device may exist between each module. The common electrode may be located at multiple modules or at the final common metallization layer.

[0154] In one scenario, a bonding layer can be formed between the modular layers to enable the integration of microdevices. The bonding layer can be an adhesive or a bonding pad. The adhesive can be various materials, such as SU8, polyamide, UV-cured, or thermosetting epoxy. The bonding pad can be Au / In or Au / Au, or other materials compatible with compression, thermocompression, eutectic bonding, and other bonding methods.

[0155] Each tile structure can be tested before stacking, and the stacked tile structures can meet a certain threshold in terms of performance and yield.

[0156] Figure 17 An embodiment of a monochromatic tile structure with top metallization is shown. To fabricate the tile structure, one or more microdevices 1708 are transferred onto a carrier substrate 1702. These microdevices may have the same color. The color may be one of red, green, or blue. A buffer layer may be formed on the substrate 1702 before transferring the microdevices. The buffer layer may be a release layer, a support substrate, or a backplane layer. It may also contain some optical layers. One of the microdevices may have a contact pad or ohmic contact 1710 above the surface of the microdevice. The microdevice 1708 is planarized. Other processing steps may be performed after the planarization layer. For example, the planarization layer 1706 is patterned or etched back to establish connections to the microdevice 1708. In another case, the planarization layer 1706 is etched back to expose the top of the microdevice 1708. An opening / via may be formed through the planarization layer 1706 to provide a metallization layer 1704 for traces and bridges. One of the traces may be a common electrode.

[0157] Figure 18 This demonstrates a stacked mosaic of components bonded to a system (or temporary) substrate. Here, a mosaic structure layer is fabricated, in which microdevices are transferred into a carrier substrate. The mosaic structure layer may be covered by a planarization layer and other metallization layers. Other layers, such as a support substrate layer or a release layer, may be used. A first mosaic structure layer is bonded to the substrate by applying an adhesive layer or bonding pad between the mosaic and the substrate. The first mosaic structure layer is then released from the carrier substrate. Additional processing steps may be performed after the transfer of the first mosaic structure layer. For example, traces or bumps may be formed. The second mosaic structure layer is then aligned with the first mosaic structure layer by alignment marks or other structures in the first and second mosaic structure layers. The second mosaic structure layer is then bonded to the first mosaic structure layer by an adhesive layer or bonding pad. The stacking process can continue to add more functional microdevice mosaic structure layers to the substrate. Through-holes may be formed through the mosaic structure layers to connect the mosaic structure layers together or to provide connections for different layers to a backplane.

[0158] Substrate 1802 may be one of a stacked substrate, a system substrate, a temporary substrate, or a backplane. Here, a first patchwork layer structure having microdevices (e.g., 1820, 1808-1) is released from a carrier substrate to substrate 1802. Additional processing steps may be performed after the transfer of the first patchwork layer. For example, traces or bumps may be formed. Then, a second patchwork layer structure having microdevices (e.g., 1810-2) is released from another carrier substrate and aligned with the first patchwork layer structure by alignment marks (1810, 1810-2) or by other structures in the first and second patchwork layers. The second patchwork layer is then bonded to the first patchwork layer by an adhesive layer or bonding pad. Furthermore, a third mosaic layer structure having microdevices (e.g., 1808-3) is released from other carrier substrates and aligned with the first and second mosaic layer structures via alignment marks (1810, 1810-2, and 1810-3) or via other structures in the first, second, or third mosaic layer structures. The third mosaic layer is then bonded to the first and second mosaic layer structures via adhesive layers or bonding pads. The stacking process can continue to add more functional microdevice mosaics to the substrate. Through-holes can be formed through the mosaics to connect them together. In one embodiment, the first and second microdevice mosaics and subsequent mosaics are physically separated from each other.

[0159] Here, the substrate is bonded at the top of the modular structure. In one case, the substrate may be bonded at the bottom side of the modular structure.

[0160] In one embodiment, the backplate and substrate may be fabricated separately from the modules and then joined together. In another embodiment, the backplate between the modules is flexible.

[0161] Figure 19A This diagram shows a cross-section of the transfer of a first mosaic layer structure to a system substrate. Here, the first mosaic layer structure is bonded to a system (or temporary) substrate 1902. The first mosaic structure layer is released from the carrier substrate. The first mosaic structure layer is fabricated in which the microdevice is transferred into the carrier substrate. The transferred mosaic structure layer may be covered by a planarization layer 1912 and other metallization layers 1904. The first mosaic structure layer is bonded to the system substrate 1902 by applying an adhesive layer or bonding pad between the mosaic and the substrate. Traces or bumps may also be formed. Alignment marks 1910 may be provided in the mosaic structure to align subsequent mosaics with the first mosaic structure.

[0162] Figure 19B Cross-sections of a first and second patch layer structure on a patterned system substrate are shown. The first patch layer structure is patternable. A planarization layer 1916 surrounding the microdevice 1908 is patterned or etched back to remove excess material on or around the microdevice to facilitate the bonding process.

[0163] A second patchwork layer structure 1920 may be provided on the carrier substrate 1922. A buffer layer may be formed on the substrate 1922 before the microdevice 1924 is transferred to the substrate 1922. The buffer layer may be a release layer, a support substrate, or a backplane layer. It may also contain some optical layers. Each of the microdevices may have contact pads or ohmic contacts 1926 above the surface of the microdevice. The microdevice 1924 is planarized. A patterned or etch-back planarization layer 1916-2 is used to establish connections to the microdevice 1924. Openings / vias may be formed through the planarization layer 1916-2 to provide metallization for traces and bridges.

[0164] To improve the surface profile, in one embodiment, a planarization layer is patterned in certain areas to provide recesses 1918 for incorporating microdevices from other tile layer structures. Alignment marks 1910-2 may be provided in the second tile layer structure for alignment with the first tile layer structure.

[0165] Figure 19C This diagram shows a cross-section of the bonding between the second and first mosaic modules on system substrate 1902. Here, the second mosaic module layer is aligned with the first mosaic module layer using alignment marks (1910, 1910-2) or other structures within the first and second mosaic module structures. The second mosaic module is then bonded to the first mosaic module using an adhesive or bonding pad. The stacking process can continue to add more functional microdevice modules to the substrate. In one case, through-holes can be formed through the mosaic modules to connect them together.

[0166] In one embodiment, a common electrode connecting one terminal of the device may exist between each tile. The common electrode may be located at multiple tiles or at the final common metallization layer. Optical structures may be formed on top of each microdevice at different tiles to allow better coupling of light to the outside or from the outside world to the device. In one case, the optical structure may be a through-hole with metal surrounding the area above the microdevice to confine light.

[0167] Figure 19D The cross-sections of the patterned second and third panel layers are shown. The first and second panel layers can be patterned together to remove excess material on and around the microdevice to facilitate the bonding process.

[0168] A third mosaic layer structure 1930 may be provided on the carrier substrate. Each of the microdevices may have a contact pad or ohmic contact above the surface of the microdevice. The microdevice is planarized. A patterned or etch-back planarization layer 1916-3 is used to establish a connection to the microdevice 1924. Excess planarization layer around the microdevice may be removed. Alignment marks 1910-3 may be provided in the third mosaic layer structure for alignment with the combined first and second mosaic layer structures.

[0169] Figure 19E This diagram shows a cross-section of the third-layer structure bonded to the system substrate. Here, the first and second modular layers are aligned with the third modular layer using alignment marks (1910, 1910-2, 1910-3) or other structures within the modular structure. The third module is then bonded to the second and first modules using adhesives or bonding pads. The stacking process can continue to add more functional microdevice modules to the substrate. Through-holes can be formed through the modules to connect them together.

[0170] In one embodiment, the driving circuitry may be formed on the substrate prior to stacking the tile layers. Vias / apertures may be used to connect the tiles to the driving circuitry. The driving circuitry may be pixel circuitry. A planarization and protective layer may be formed after the driving circuitry to prepare the surface for integration into the stacked tile structure. The driving circuitry may also be a tile structure transferred to the substrate.

[0171] Figure 20A This diagram illustrates a cross-section of a first, non-metallized mosaic layer structure being transferred to a substrate, vias formed through the mosaic, and a backplate mounted to the top of the layer via the vias. Here, the first mosaic layer structure is bonded to a system (or temporary) substrate 2002. The first mosaic structure layer is released from the carrier substrate. The mosaic structure layer is fabricated, in which microdevices are transferred into the carrier substrate. The transferred mosaic structure layer may be covered by a planarization layer 2012. In this case, vias may also be formed through the mosaic, and the backplate 2002 may be mounted to the top of the layer via the vias. The first mosaic structure layer is bonded to the system substrate by applying an adhesive layer or bonding pad between the mosaic and the substrate. Traces or bumps may also be formed. Alignment marks 2010 may be provided in the mosaic structure for alignment with subsequent mosaics.

[0172] Figure 20B Cross-sections of a first and second patch layer structure on a patterned system substrate are shown. The first patch layer structure is patternable. A planarization layer 2012 around the microdevice is patterned or etched back to remove excess material on or around the microdevice to facilitate the bonding process.

[0173] A second modular layer structure 2020 may be provided on the carrier substrate 2022. A buffer layer may be formed on the substrate 2022 before the microdevice 2024 is transferred to the substrate 2022. The buffer layer may be a release layer, a support substrate, or a backplane layer. It may also include some optical layers. One of the microdevices may have contact pads or ohmic contacts above the surface of the microdevice. The microdevice 2024 is planarized. In one embodiment, a planarization layer is patterned in some areas to provide recesses 2018 to accommodate microdevices from other modular layer structures. Alignment marks 2010-2 may be provided in the second modular layer structure for alignment with the first modular layer structure.

[0174] Figure 20CThis image shows a cross-section of the bonding between the second and first mosaic modules on system substrate 2002. Here, the second mosaic module layer is aligned with the first mosaic module layer using alignment marks (2010, 2010-2) or other structures within the first and second mosaic module structures. The second mosaic module is then bonded to the first mosaic module using an adhesive or bonding pad. The stacking process can continue to add more functional microdevice modules to the substrate. In one case, through-holes can be formed through the mosaic modules to connect them together.

[0175] In one embodiment, a common electrode connecting one terminal of the device may exist between each tile. The common electrode may be located at multiple tiles or at the final common metallization layer. Optical structures may be formed on top of each microdevice at different tiles to allow better coupling of light to the outside or from the outside world to the device. In one case, the optical structure may be a through-hole with metal surrounding the area above the microdevice to confine light.

[0176] Figure 20D The cross-sections of the patterned second and third panel layers are shown. The first and second panel layers can be patterned together to remove excess material on and around the microdevice to facilitate the bonding process.

[0177] A third modular layer structure 2030 may be provided on the carrier substrate. Each of the microdevices may have a contact pad or ohmic contact above the surface of the microdevice. The microdevice is planarized. Excess planarization layer around the microdevice may be removed. Alignment marks 2010-3 may be provided in the third modular layer structure for alignment with the combined first and second modular layer structures.

[0178] Figure 20E This diagram shows a cross-section of the third-layer structure bonded to a system or temporary (carrier) substrate. Here, the first and second modular layer structures are aligned with the third modular layer using alignment marks (2010, 2010-2, 2010-3) or other structures within the modular structure. The third module is then bonded to the second and first modules using adhesives or bonding pads. The stacking process can continue to add more functional microdevice modules to the substrate. Through-holes can be formed through the modules to connect them together.

[0179] In another embodiment, the driving circuitry may be formed on the substrate prior to the stacked tile layers. Vias / apertures may be used to connect the tiles to the driving circuitry. The driving circuitry may be pixel circuitry. A planarization and protective layer may be formed after the driving circuitry to prepare the surface for integration into the stacked tile structure. The driving circuitry may also be a tile structure transferred to the substrate.

[0180] Each tile structure can be tested before stacking and the stacked tile structures can meet a certain threshold in terms of performance and yield.

[0181] Figure 21A A cross-section of a colored mosaic with bonding pads 2120 formed on top of a stacked layer is shown. Here, substrate 2102 may be located on the bottom side. Bonding layers (2106-1, 2006-2) may be formed between mosaic layers 2112 to enable microdevice integration. Substrate 2102 may be one of a stacked substrate, a system substrate, a temporary substrate, or a backplane. Here, the mosaic structure is a full-color mosaic containing multiple microdevices (e.g., R, G, B shown in FIG. 19). Microdevices may be bonded to the substrate in different mosaic layers 2112. A common electrode 2104 connecting one terminal of the device may be present between each mosaic. The common electrode may be at multiple mosaics or at the last common metallization layer. Optical structures 2122 may be formed on top of each microdevice at different mosaics to allow better coupling of light to the outside or from the outside world to the device. In one case, the optical structure may be a via with metal surrounding an area above the microdevice to confine light.

[0182] A bonding layer 2106-1 may be formed on the surface in which a second microdevice assembly (e.g., G) will be bonded. The bonding layer may be an adhesive or a bonding pad. The adhesive may be a variety of materials, such as SU8, polyamide, UV or thermosetting epoxy resin. The bonding pad may be Au / In or Au / Au or other materials compatible with compression, thermocompression, eutectic and bonding methods.

[0183] In one embodiment, the back panel may be formed on top of, on bottom of, or between the tile layers.

[0184] In one embodiment, one or more planarization layers may be formed to smooth the substrate surface. In one case, openings through the planarization layer may be provided to create contact between the microdevice and the substrate. In another case, the bonding layer and the planarization layer may be the same. In yet another case, the bonding layer may be formed separately.

[0185] Figure 21B The display shows that through-holes can be formed through the tiles to connect them together, and back panels can be mounted to the top of the stacked layers through the through-holes.

[0186] Figure 21C The driving circuit 2120 can be formed on the substrate before stacking the tile layers. Here, via openings can be used to connect the tiles to the driving circuit. The driving circuit can be a pixel circuit. A planarization and protective layer can be formed after the driving circuit to prepare the surface for integration into the stacked tile structure. The driving circuit can also be a tile structure transferred to the substrate.

[0187] Figure 22Another cross-section is shown of a full-color patch bonded to a system (or temporary) substrate. In one embodiment, contact pads (2212-1, 2212-2) or ohmic contacts may be formed on opposite sides of the microdevice between the patch layers. Here, the microdevice has bonding pads on both the top and bottom surfaces of the device. Metallization on the contact pads can be provided by providing openings in a planarization layer between the patch layers.

[0188] Figure 23A A cross-sectional view of a monochrome patchwork structure according to an embodiment of the present invention is shown. Here, the carrier substrate 2302 has one or more microdevices 2304. These microdevices 2304 can be fabricated directly on the carrier substrate or transferred from a growth substrate to the carrier substrate. The microdevices can be of the same type. In one example, the microdevices are microLEDs and can be of the same color. The color can be one of red, green, or blue. A buffer layer 2306 can be formed on the substrate 2302 before the microdevices 2304-1 are transferred to the carrier substrate 2302. The buffer layer can be a release layer, a support substrate, or a backing layer. It may also contain some optical layers.

[0189] Figure 23B A cross-sectional view of a monochrome patch structure having a planarization layer and a top electrode according to an embodiment of the present invention is shown. Here, a planarization layer 2308-1 is formed around the microdevice. Other processing steps may be performed after the planarization layer 2308-1 is formed. For example, the planarization layer 2308-1 may be patterned or etched back to establish a connection to the microdevice 2304-1. Each of the microdevices may have an electrode 2310-1 above the top surface of the microdevice 2304-1.

[0190] Figure 23C A cross-sectional view of a first monochromatic patch structure incorporated into a system (or temporary) substrate according to an embodiment of the present invention is shown. The substrate 2312 may be one of a stacked substrate, a system substrate, a temporary substrate, or a backplane. Here, the first patch layer structure having a microdevice (e.g., 2304-1) (as shown in the image) Figure 23A and 23B (As shown in the diagram) The first modular structure is released from the carrier substrate and bonded or transferred to substrate 2312. Substrate 2312 may be a temporary substrate. The first modular structure is bonded to the temporary substrate 2312 by applying an adhesive layer or bonding layer 2314 between the microdevice 2304-1 and the temporary substrate 2312. The carrier substrate can then be removed after bonding with the temporary substrate. In one case, the buffer layer can also be removed.

[0191] Figure 23DA cross-sectional view is shown of a first monochromatic patch structure incorporated into a system (or temporary) substrate having a bottom connection, according to an embodiment of the invention. Connections can be provided to the microdevice on a surface opposite to the microdevice. Here, after removing the buffer layer, a bottom electrode 2316-1 can be formed on a surface opposite the first surface of the microdevice 2304-1 to extend the connection of the microdevice when the microdevice is present on the bottom side.

[0192] The stacking process can continue to be used to add more functional microdevice mosaic structure layers to the temporary substrate. In one embodiment, the first microdevice mosaic, the second microdevice mosaic, and subsequent mosaics are physically separated from each other.

[0193] In one embodiment, a temporary substrate is attached to the top of the modular structure. In another embodiment, a temporary substrate may be attached to the bottom side of the modular structure.

[0194] Figure 23E A cross-sectional view of a second monochromatic patch structure bonded to a temporary substrate according to an embodiment of the present invention is shown. Here, the second patch layer structure having a microdevice (e.g., 2304-2), a second planarization layer 2308-2, a top electrode 2310-2, and a bottom electrode 2316-2 can be formed separately on another carrier substrate. The microdevice 2304-2 can be released from the other carrier substrate and aligned with the first patch layer structure. The second patch structure layer is then bonded to the first patch structure layer by means of an adhesive layer or bonding pad 2314-2. Each of the second microdevices 2304-2 may have a top electrode 2310-2 above the top surface of the microdevice and a bottom electrode 2316-2 on a surface opposite to the first surface of the microdevice 2304-2 to extend the connection of the microdevice 2304-2 when the microdevice is present on the bottom side.

[0195] Figure 23F A cross-sectional view of a through-hole formed through a modular structure according to an embodiment of the invention is shown. Here, through-holes 2324 may be formed through the modular structure layers to connect the modular structure layers together or to provide connections to different layers to a temporary substrate 2312.

[0196] Figure 23G A cross-sectional view of the through-holes connected to pads and electrodes according to an embodiment of the present invention is shown. Here, the through-holes 2324 corresponding to the top electrodes (2310-1, 2310-2) can be filled with a conductive material, and some can be connected together to form a common electrode 2330. The common electrode between each panel connects one terminal of the device together. The common electrode may be at multiple panels or at the final common metallization layer. Pads 2332 may be formed on portions of the bottom electrodes (2316-1, 2316-2) for bonding, or some may be connected together to form a common pad.

[0197] Figure 23H A cross-sectional view showing the bonding between a temporary substrate and a backplane according to an embodiment of the present invention is shown. In one embodiment, the backplane and temporary substrate may be fabricated separately from the mosaic and then bonded together. In another embodiment, the backplane between the mosaic structures is flexible. The backplane 2340 may include driving circuitry 2334. The driving circuitry may include pixel circuitry and electrodes. The driving circuitry may include a common electrode or patterned electrode for each microdevice. The backplane 2340 may have pads corresponding to pads 2332 of the stacked microdevices. Microdevices may be bonded or attached to the backplane 2340 via pads 2336 or other adhesive layers.

[0198] Figure 23I A cross-sectional view of an optical layer on a temporary substrate according to an embodiment of the present invention is shown. Here, an optical layer 2342 may be provided on the temporary substrate 2312 prior to the stacked mosaic layer structure. The optical layer 2342 may limit the light output or input light of the microdevice. Furthermore, the optical layer 2342 may also reduce viewing angle effects because light from different layers will be combined and emitted through the optical layer 2342.

[0199] Figure 23J A cross-sectional view is shown of an optical layer bonded to a temporary substrate on a backplane according to an embodiment of the invention. Here, an optical layer 2342 may be provided on the temporary substrate 2312 prior to stacking the microdevice layers. In one case, the optical layer may be formed on top of each microdevice at different tile locations to allow for better optical coupling. The optical layer may limit the light output or input light of the microdevice. It may also reduce viewing angle effects because light from different layers will be combined and ejected through the optical layer 2342. The temporary substrate and the backplane may then be bonded together. The backplane 2340 may include driving circuitry 2334. The driving circuitry may include pixel circuitry and electrodes. The driving circuitry may include a common electrode or patterned electrode for each microdevice. The backplane 2340 may have pads corresponding to the pads 2332 of the stacked microdevices. Microdevices may be bonded or attached to the backplane 2340 via pads 2336 or other adhesive layers.

[0200] Figure 23K A cross-sectional view of a patterned stacked tile layer structure on a temporary substrate according to an embodiment of the present invention is shown. Here, the stacked tile layer structure can be patterned to create isolation regions containing multiple microdevices. Isolation regions or islands may represent pixel regions. Patterning may occur at the temporary substrate or after bonding to a backplane.

[0201] Figure 23L A cross-sectional view of a reflective layer formed around an island according to an embodiment of the present invention is shown. Here, a reflective layer 2346 may be formed around the island to further reduce viewing angle effects by guiding light from different layers to a single surface.

[0202] Figure 23M A cross-sectional view of a patterned stacked tile layer structure on a backplane according to an embodiment of the present invention is shown. Here, the stacked tile layer structure can be patterned to create isolation regions containing multiple microdevices after bonding to the backplane. Isolation regions or islands may represent pixel regions. Patterning occurs after a temporary substrate is bonded to the backplane.

[0203] Figure 23N A cross-sectional view illustrating the removal of a temporary substrate according to an embodiment of the invention is shown. Here, the temporary substrate can be removed after bonding with the backplate. The spaces between pixels can be filled with a filler. The filler can be a black matrix. In one case, the filler can be placed between the pixels before being transferred to the temporary substrate.

[0204] Figure 24 Demonstrating embodiments according to the present invention Figure 23N The diagram shows a schematic top view of a modular stacked display. Here, in the top view of the modular stacked display, the stacked layer structure is patterned into isolated areas containing islands of multiple microdevices. Some randomly positioned islands can be formed to reduce visual artifacts when fewer different tiles are combined in a single backplane. Each island may include a common pad 2402, a common electrode 2412, a via 2410, a microdevice pad 2404, a planarization layer 2306, and a reflector layer 2408 surrounding the island to further reduce viewing angle effects by guiding light from different layers to a single surface.

[0205] According to one embodiment, a method for integrating microdevices may be provided. The method may include: providing one or more microdevices on a donor substrate; integrating a first set of microdevices from the donor substrate into a system substrate; providing one or more hierarchical pads to a second set of devices on the donor substrate; and integrating the second set of microdevices into the system substrate.

[0206] According to another embodiment, one or more hierarchical pads are one of a conductive layer, a planarization layer, or pillars formed on the surface of a substrate or microdevice, and one or more hierarchical pads create a connection between the microdevice and the system substrate.

[0207] According to one embodiment, the method may further include providing one or more planarization layers above the integrated microdevice to a system substrate, wherein openings are created in the planarization layers to couple the microdevice to a signal.

[0208] According to another embodiment, the method may further include depositing an electrode over a microdevice through an opening in a planarization layer, adding a bonding layer to the electrode, and providing a reflective layer to each microdevice.

[0209] According to some embodiments, the first microdevice and the second microdevice overlap and are connected by a common electrode.

[0210] According to one embodiment, a solid-state array device includes one or more pixels, each pixel having two or more microdevices, at least one of the two microdevices being coupled to pixel circuitry, and each microdevice being coupled to a bias voltage via a corresponding switch.

[0211] According to another embodiment, the pixel circuit is one of a pixel circuit corresponding to each microdevice and a shared pixel circuit between microdevices, wherein the shared pixel circuit is allocated to each microdevice at a given time during the frame time.

[0212] According to some embodiments, one of the microdevices is switched on during an operating mode by being coupled to a shared pixel circuit and decoupled from a bias voltage, and another of the microdevices is switched off during a non-operating mode by being decoupled from the shared pixel circuit and coupled to a bias voltage.

[0213] According to one embodiment, the on-time of each microdevice is extended, and at least two microdevices are operable during a subframe of the frame time. Each microdevice has a corresponding storage element coupled to a shared pixel circuit via a corresponding switch, wherein the storage element includes a capacitor.

[0214] According to another embodiment, a method is provided for stacking modular structure layers onto a substrate. Each modular structure layer includes a plurality of microdevices. The method may include: releasing a first modular structure layer on the substrate; providing a second modular structure layer on the substrate and aligning it with the first modular structure layer; and bonding the first and second modular structure layers on the substrate, wherein the first and second modular structures are physically separated from each other.

[0215] According to another embodiment, the second modular structure layer is aligned with the first modular structure layer by alignment marks, and the second modular structure layer is bonded to the first modular structure layer by an adhesive layer or bonding pad, wherein the bonding pad is formed on either side of the microdevice between the modular structure layers, and the first and second modular structure layers are covered by a planarization layer and a metallization layer.

[0216] According to another embodiment, the method may further include: providing vias through the planarization layer to connect the first and second modular structure layers together or providing connections to connect different modular structure layers to a substrate; providing vias through the first and second modular structure layers to couple the modular layers to control and bias signals, wherein the substrate is one of a temporary substrate, a system substrate, or a backplane and is adhered to the bottom surface, top surface, or between the modular layer structures. The microdevices may have the same or different colors.

[0217] According to one embodiment, the method may further include: providing driving circuitry on a substrate prior to stacking the tiled structure; testing each tiled structure layer prior to stacking; providing bonding layers between the tiled structure layers to enable integration of microdevices; providing a common electrode between each tiled structure layer to connect a terminal of the microdevice together; and forming an optical structure on each microdevice at different tiled structure layers.

[0218] According to another embodiment, the bonding layer is one of an adhesive or a bonding pad, wherein the adhesive is one of SU8, polyamide, UV-cured, or thermosetting epoxy resin. The bonding pad is one of Au / In, Au / Au, or other materials compatible with compression, thermocompression, and eutectic bonding methods and is formed on either side of the microdevice between the modular structural layers. The second modular structural layer has recesses in a planarization layer to receive microdevices from the first modular layer structure, wherein excess planarization layer around the microdevices in the first layer structure is removed to facilitate bonding.

[0219] According to one embodiment, a display device may be provided. The display device may include: a plurality of modular structures stacked on top of each other, each of the modular structures including a substrate, an array of microdevices disposed on the substrate, a top electrode disposed on a first surface of each microdevice, and a bottom electrode disposed on a surface opposite to the first surface of the microdevice; and a backplate coupled to the plurality of modular structures.

[0220] According to one embodiment, multiple modular structures are transferred to a temporary substrate before being bonded to a backplane, and the multiple modular structures are bonded to each other through an intervening bonding layer.

[0221] According to another embodiment, a planarization layer is formed between the array of microdevices in each modular structure and provides openings for top and bottom electrodes to establish connections with the microdevices. A common electrode is provided between each modular structure to connect the microdevices together.

[0222] According to some embodiments, the bottom electrode includes bonding pads for attaching the microdevice to a backplane. The backplane includes drive circuitry and contact pads corresponding to the bonding pads of the microdevice. An optical layer is provided on the temporary substrate before the mosaic structure is stacked onto the temporary substrate, wherein the stacked mosaic structure is patterned to create islands at the temporary substrate or after attachment to the backplane.

[0223] According to another embodiment, a reflective layer is provided around the island to reduce viewing angle effects by guiding light from different tile structures to a single surface.

[0224] According to another embodiment, a temporary substrate is removed after bonding with a backplane, and the space between the microdevices is filled with a filler material before or after bonding with the backplane.

[0225] In summary, this invention discloses structures and methods for integrating microdevices into a system or receiver substrate. Microdevice integration is facilitated by adding hierarchical pads to the microdevices before or after transfer. A stage is created after the first microdevice is transferred to the substrate for subsequent microdevice transfers following the first (or second) microdevice transfer. The stage improves the surface profile of the substrate, allowing the transfer of the next microdevice without damage or interference to the surface of the first microdevice on the substrate from the donor or transfer head. Some embodiments further relate to tiled display devices, and more specifically, to stacking tiles onto a backplane to form a tiled display device.

[0226] Although specific embodiments and applications of the invention have been described and illustrated, it should be understood that the invention is not limited to the precise constructions and compositions disclosed herein, and various modifications, alterations and variations will be apparent from the foregoing description without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A solid-state array device comprising one or more pixels; Each pixel has at least two microdevices directly connected to a shared pixel circuit, and each microdevice is coupled to a bias voltage via a corresponding switch for a bias voltage, and the pixel has at least two storage elements. Each microdevice is provided to its corresponding storage element via the shared pixel circuitry; Each storage element is connected to a switch configuration that is connected to the shared pixel circuitry, or the switch configuration is connected to another common bias voltage via another switch. and Another switch configuration is used to connect each storage element to a corresponding individual bias voltage.

2. The solid-state array device of claim 1, wherein the shared pixel circuitry is allocated to each microdevice at a given time during the frame time.

3. The solid-state array device of claim 1, wherein one of the microdevices coupled to the shared pixel circuit is decoupled from the bias voltage to turn on the microdevice during an operation mode.

4. The solid-state array device of claim 1, wherein one of the microdevices is decoupled from the shared pixel circuitry and coupled to the bias voltage to shut down the microdevice during non-operational modes.

5. The solid-state array device of claim 1, wherein the on-time of each microdevice for a frame is extended such that the two microdevices are operable during a subframe of a frame time.

6. The solid-state array device of claim 1, wherein the storage element comprises a capacitor.

7. The solid-state array device of claim 1, wherein each storage element is connected to the corresponding individual bias voltage via a corresponding individual switch in the other switch configuration.

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