Wiring structure and manufacturing method

Abstract

This disclosure relates to a wiring structure and a method for manufacturing the wiring structure. The wiring structure includes a conductive structure, a surface structure, and at least one through-hole. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is adjacent to the top surface of the conductive structure. The through-hole extends through the surface structure and into at least a portion of the conductive structure.

Description

Technical Field

[0001] This disclosure relates to a wiring structure and a manufacturing method, and to a wiring structure comprising at least two conductive structures attached or bonded together by an intermediate layer, and a method for manufacturing said wiring structure. Background Technology

[0002] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips are integrated with an increasing number of electronic components to achieve improved electrical performance and additional functionality. Therefore, semiconductor chips have more input / output (I / O) connections. To manufacture semiconductor packages containing semiconductor chips with an increased number of I / O connections, the size of the circuit layers in the semiconductor substrate that carries the semiconductor chip may increase accordingly. Consequently, the thickness and warpage of the semiconductor substrate may increase, and the yield of the semiconductor substrate may decrease. Summary of the Invention

[0003] In some embodiments, a wiring structure includes: (a) a conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (b) a surface structure adjacent to the top surface of the conductive structure; and (c) at least one through-hole extending through the surface structure and into at least a portion of the conductive structure.

[0004] In some embodiments, a wiring structure includes: (a) a low-density stack structure including at least one dielectric layer and at least one low-density circuit layer in contact with the dielectric layer; (b) a high-density stack structure disposed on the low-density stack structure, wherein the high-density stack structure includes at least one dielectric layer and at least one high-density circuit layer in contact with the dielectric layer of the high-density stack structure; (c) a surface structure disposed on a top surface of the high-density stack structure; and (d) at least one upper through-hole extending through the surface structure and the high-density stack structure and terminating on the low-density circuit layer of the low-density stack structure.

[0005] In some embodiments, a method for manufacturing a wiring structure includes: (a) providing a lower conductive structure comprising at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (b) providing an upper conductive structure comprising at least one dielectric layer and at least one circuit layer in contact with the dielectric layer of the upper conductive structure; (c) attaching the upper conductive structure to the lower conductive structure; (d) forming a surface structure on a top surface of the upper conductive structure; and (e) forming at least one upper through-hole extending through the surface structure and into at least a portion of the upper conductive structure. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of some embodiments of this disclosure can be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This shows a cross-sectional view of a wiring structure according to some embodiments of the present disclosure.

[0008] Figure 2 show Figure 1 A magnified view of section "A" in the image.

[0009] Figure 3 show Figure 1 A partially enlarged top view of the upper conductive structure.

[0010] Figure 4 This shows a cross-sectional view of the upper through-hole according to some embodiments of the present disclosure.

[0011] Figure 5 show Figure 4 A three-dimensional view of the upper part of the guide hole.

[0012] Figure 6 This shows a cross-sectional view of the upper through-hole according to some embodiments of the present disclosure.

[0013] Figure 7 This shows a cross-sectional view of the upper through-hole according to some embodiments of the present disclosure.

[0014] Figure 8 This shows a cross-sectional view of a wiring structure according to some embodiments of the present disclosure.

[0015] Figure 9 This shows a cross-sectional view of a wiring structure according to some embodiments of the present disclosure.

[0016] Figure 10 This shows a cross-sectional view of a wiring structure according to some embodiments of the present disclosure.

[0017] Figure 10A A top view showing an example of a reference mark of an upper conductive structure according to some embodiments of the present disclosure.

[0018] Figure 10B A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of the present disclosure.

[0019] Figure 10C show Figure 10A The reference mark of the upper conductive structure and Figure 10BA top view of a composite image of the reference marks on the lower conductive structure.

[0020] Figure 10D A top view showing an example of a reference mark of an upper conductive structure according to some embodiments of the present disclosure.

[0021] Figure 10E A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of the present disclosure.

[0022] Figure 10F Reference marks showing the upper conductive structure of 10D and Figure 10E A top view of a composite image of the reference marks on the lower conductive structure.

[0023] Figure 10G A top view showing an example of a reference mark of an upper conductive structure according to some embodiments of the present disclosure.

[0024] Figure 10H A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of the present disclosure.

[0025] Figure 10I show Figure 10G The reference mark of the upper conductive structure and Figure 10H A top view of a composite image of the reference marks on the lower conductive structure.

[0026] Figure 11 A cross-sectional view showing the bonding between the package structure and the substrate.

[0027] Figure 12 This shows a cross-sectional view of a wiring structure according to some embodiments of the present disclosure.

[0028] Figure 13 show Figure 12 A magnified view of section "B" in the image.

[0029] Figure 14 A cross-sectional view showing the bonding between the package structure and the substrate.

[0030] Figure 15 This shows a cross-sectional view of a wiring structure according to some embodiments of the present disclosure.

[0031] Figure 16 This shows a cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0032] Figure 17 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0033] Figure 18This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0034] Figure 19 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0035] Figure 20 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0036] Figure 21 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0037] Figure 22 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0038] Figure 23 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0039] Figure 24 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0040] Figure 25 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0041] Figure 26 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0042] Figure 27 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0043] Figure 28 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0044] Figure 29 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0045] Figure 30 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0046] Figure 31This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0047] Figure 32 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0048] Figure 33 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0049] Figure 34 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0050] Figure 35 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0051] Figure 36 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0052] Figure 37 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0053] Figure 38 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0054] Figure 39 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0055] Figure 40 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0056] Figure 41 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0057] Figure 42 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0058] Figure 43 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0059] Figure 44This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0060] Figure 45 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0061] Figure 46 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0062] Figure 47 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0063] Figure 48 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0064] Figure 49 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0065] Figure 50 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0066] Figure 51 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0067] Figure 52 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0068] Figure 53 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0069] Figure 54 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0070] Figure 55 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0071] Figure 56 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0072] Figure 57This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0073] Figure 58 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0074] Figure 59 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0075] Figure 60 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0076] Figure 61 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0077] Figure 62 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0078] Figure 63 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0079] Figure 64 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0080] Figure 65 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0081] Figure 66 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0082] Figure 67 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. Detailed Implementation

[0083] Throughout the drawings and detailed description, common reference numerals are used to indicate the same or similar components. Embodiments of this disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0084] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0085] To meet specifications for increased I / O counts, the number of dielectric layers on the substrate should be increased. In some comparative embodiments, the manufacturing process of the core substrate may include the following stages. First, a core is provided, having two copper foils disposed on both sides. Subsequently, multiple dielectric layers and multiple circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in a corresponding dielectric layer. Therefore, the core substrate may contain multiple stacked dielectric layers and multiple circuit layers embedded in the dielectric layers on both sides of the core. Since the line width / line space (L / S) of the circuit layers in such a core substrate can be greater than or equal to 10 micrometers (μm) / 10 μm, the number of dielectric layers in such a core substrate is relatively large. Although the manufacturing cost of such a core substrate is low, the manufacturing yield of the circuit layers and dielectric layers in such a core substrate is also low, thus the yield of such a core substrate is low. In addition, each dielectric layer is relatively thick, and therefore, this core substrate is relatively thick. In some comparative embodiments, if the package has 10,000 I / Os, then the core substrate may contain twelve circuit and dielectric layers. The manufacturing yield of one layer (containing one circuit and one dielectric layer) of such a core substrate can be 90%. Therefore, the yield of this core substrate can be (0.9). 12 =28.24%. Furthermore, the warpage of the twelve circuit and dielectric layers can accumulate, and therefore the top layers can exhibit severe warpage. Consequently, the yield of this core substrate can be further reduced.

[0086] To address the aforementioned issues, in some comparative embodiments, a coreless substrate is provided. The coreless substrate may comprise multiple dielectric layers and multiple fan-out circuit layers. In some embodiments, the fabrication process of the coreless substrate may include the following stages: First, a carrier is provided. Subsequently, multiple dielectric layers and multiple fan-out circuit layers are formed or stacked on the surface of the carrier. One fan-out circuit layer may be embedded in a corresponding dielectric layer. Subsequently, the carrier is removed. Thus, the coreless substrate may comprise multiple stacked dielectric layers and multiple fan-out circuit layers embedded within the dielectric layers. Since the linewidth / spacing (L / S) of the fan-out circuit layers in this coreless substrate can be less than or equal to 2 μm / 2 μm, the number of dielectric layers in this coreless substrate can be reduced. Furthermore, the fabrication yield of the fan-out circuit layers and dielectric layers in such a coreless substrate is high. For example, the fabrication yield of one layer (comprising one fan-out circuit layer and one dielectric layer) in this coreless substrate can be 99%. However, the fabrication cost of such a coreless substrate is relatively high.

[0087] At least some embodiments of this disclosure provide wiring structures with an advantageous trade-off between yield and manufacturing cost. In some embodiments, the wiring structure includes an upper conductive structure and a lower conductive structure bonded to the upper conductive structure via an intermediate layer. At least some embodiments of this disclosure further provide techniques for manufacturing the wiring structures.

[0088] Figure 1 A cross-sectional view of wiring structure 1 according to some embodiments of the present disclosure is shown. Figure 2 show Figure 1 A partially enlarged view of area "A" in the diagram. The wiring structure 1 includes an upper conductive structure 2, a surface structure 16, and at least one upper through via 14. In some embodiments, the wiring structure 1 further includes an outer circuit layer 28, an intermediate layer 12, and a lower conductive structure 3.

[0089] The upper conductive structure 2 includes at least one dielectric layer (including, for example, two first dielectric layers 20 and one second dielectric layer 26) and at least one circuit layer (including, for example, three circuit layers 24 formed of metal, metal alloy or other conductive material) in contact with the dielectric layer (e.g., the first dielectric layer 20 and the second dielectric layer 26). In some embodiments, the upper conductive structure 2 may resemble a coreless substrate and may be of wafer type, panel type or strip type. The upper conductive structure 2 may also be referred to as a "stacked structure" or a "high-density conductive structure" or a "high-density stacked structure". The circuit layers of the upper conductive structure 2 (including, for example, three circuit layers 24) may also be referred to as "high-density circuit layers". In some embodiments, the density of circuit lines (including, for example, traces or pads) in the high-density circuit layer is greater than the density of circuit lines in the low-density circuit layer. That is, the count of circuit lines (including, for example, traces or pads) per unit area of ​​the high-density circuit layer is greater than the count of circuit lines per unit area of ​​the low-density circuit layer, for example, about 1.2 times or more, about 1.5 times or more, or about 2 times or more. Alternatively or in combination, the linewidth / spacing (L / S) of the high-density circuit layer is smaller than that of the low-density circuit layer, for example, about 90% or less, about 50% or less, or about 20% or less. Furthermore, a conductive structure containing a high-density circuit layer may be designated as a "high-density conductive structure," and a conductive structure containing a low-density circuit layer may be designated as a "low-density conductive structure."

[0090] The upper conductive structure 2 has a top surface 21 and a bottom surface 22 opposite to the top surface 21, and defines at least one single continuous through-hole 23. For example... Figure 1 As shown, the upper conductive structure 2 includes multiple dielectric layers (e.g., two first dielectric layers 20 and a second dielectric layer 26), multiple circuit layers (e.g., three circuit layers 24), and at least one inner via 25. The dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) are stacked on top of each other. For example, the second dielectric layer 26 is disposed on the first dielectric layer 20, and therefore, the second dielectric layer 26 is the topmost dielectric layer. In some embodiments, the material of the dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) is transparent and can be seen or detected by the human eye or a machine. That is, a mark adjacent to the bottom surface 22 of the upper conductive structure 2 can be identified or detected by the human eye or a machine from the top surface 21 of the upper conductive structure 2. In some embodiments, the transparent material of the dielectric layers has a transmittance of at least about 60%, at least about 70%, or at least about 80% for wavelengths in the visible range (or other relevant wavelengths used to detect the mark).

[0091] Furthermore, each first dielectric layer 20 has a top surface 201 and a bottom surface 202 opposite to the top surface 201, and defines a via 203 having an inner surface 2031. The second dielectric layer 26 has a top surface 261 and a bottom surface 262 opposite to the top surface 261, and defines a via 263 having an inner surface 2631. The bottom surface 262 of the second dielectric layer 26 is disposed adjacent to and in contact with the top surface 201 of the first dielectric layer 20. Therefore, the top surface 21 of the upper conductive structure 2 is the top surface 261 of the second dielectric layer 26, and the bottom surface 22 of the upper conductive structure 2 is the bottom surface 202 of the bottommost first dielectric layer 20.

[0092] like Figure 1 As shown, each via 203 of the first dielectric layer 20 tapers downwards in the direction from the top surface 21 of the upper conductive structure 2 toward the bottom surface 22; that is, the size of the top portion of the via 203 is larger than the size of the bottom portion of the via 203. The via 263 of the second dielectric layer 26 also tapers downwards; that is, the size of the top portion of the via 263 is larger than the size of the bottom portion of the via 263. Furthermore, the via 263 of the second dielectric layer 26 is aligned with and communicates with the via 203 of the first dielectric layer 20. The bottom portion of the via 263 of the second dielectric layer 26 is adjacent to or connected to the top portion of the via 203 of the first dielectric layer 20 beneath the second dielectric layer 26. The size of the bottom portion of the via 263 of the second dielectric layer 26 is substantially equal to the size of the top portion of the via 203 of the first dielectric layer 20 beneath the second dielectric layer 26. Therefore, the inner surface 2631 of the via 263 of the second dielectric layer 26 is coplanar or aligned with the inner surface 2031 of the via 203 of the first dielectric layer 20. Note that the aforementioned "coplanar" surfaces do not need to be flat. In some embodiments, the inner surfaces 2631 of the via 263 of the second dielectric layer 26 and the inner surfaces 2031 of the via 203 of the first dielectric layer 20 may be curved surfaces and are portions of the inner surfaces 231 of a single continuous via 23 for accommodating the upper through-hole 14. The vias 263 of the second dielectric layer 26 and the vias 203 of the first dielectric layer 20 are configured together to form or define a portion of a single via 23. Figure 1 As shown, the cross-sectional views of one side of the inner surface 2631 of the via 263 in the second dielectric layer 26 and the inner surface 2031 of the via 203 in the first dielectric layer 20 are substantially straight line segments. That is, the cross-sectional views of one side of the inner surface 2631 of the via 263 in the second dielectric layer 26 and the inner surface 2031 of the via 203 in the first dielectric layer 20 can extend along the same substantially straight line. A single via 23 extends through the upper conductive structure 2; that is, a single via 23 extends from the top surface 21 of the upper conductive structure 2 to the bottom surface 22 of the upper conductive structure 2. The single via 23 gradually narrows downwards.

[0093] The circuit layer 24 may be a fan-out circuit layer or a redistribution layer (RDL), and the L / S ratio of the circuit layer 24 may be less than or equal to about 2 μm / about 2 μm, or less than or equal to about 1.8 μm / about 1.8 μm. Each circuit layer 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. In some embodiments, the circuit layer 24 is embedded in a corresponding first dielectric layer 20, and the top surface 241 of the circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. In some embodiments, each circuit layer 24 may include a seed layer 243 and a conductive material 244 (e.g., a metallic material) disposed on the seed layer 243. Figure 1 As shown, the bottommost circuit layer 24 is disposed on the bottom surface 22 of the upper conductive structure 2 (e.g., the bottom surface 202 of the bottommost first dielectric layer 20) and protrudes from it.

[0094] The upper conductive structure 2 includes a plurality of internal vias 25. Some internal vias 25 are disposed between two adjacent circuit layers 24 to electrically connect the two circuit layers 24. Some internal vias 25 are disposed between the topmost circuit layer 24 and the outer circuit layer 28 to electrically connect the topmost circuit layer 24 and the outer circuit layer 28. In some embodiments, each internal via 25 may include a seed layer 251 and a conductive material 252 (e.g., a metallic material) disposed on the seed layer 251. In some embodiments, each internal via 25 and the corresponding circuit layer 24 may be integrally formed as a monolithic or one-piece structure. Each internal via 25 gradually narrows upward along the direction from the bottom surface 22 of the upper conductive structure 2 toward the top surface 21. That is, the size (e.g., width) of the top portion of the internal via 25 is smaller than the size (e.g., width) of the bottom portion of the internal via 25 closer to the bottom surface 22. In some embodiments, the maximum width of the internal guide hole 25 (e.g., at the bottom portion) may be less than or equal to about 25 μm, such as about 25 μm, about 20 μm, about 15 μm or about 10 μm.

[0095] The lower conductive structure 3 includes at least one dielectric layer (including, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) and at least one circuit layer (including, for example, a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a') contacting the dielectric layer (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower circuit layers 36a), which is formed of metal, metal alloy, or other conductive material. In some embodiments, the lower conductive structure 3 may be similar to a core substrate further including a core portion 37, and may be wafer type, panel type, or strip type. The lower conductive structure 3 may also be referred to as a "lower stacked structure," a "low-density conductive structure," or a "low-density stacked structure." The circuit layer of the lower conductive structure 3 (including, for example, a first upper circuit layer 34; two second upper circuit layers 38, 38'; a first lower circuit layer 34a; and two second lower circuit layers 38a, 38a') can also be referred to as a "low-density circuit layer". For example... Figure 1 As shown, the lower conductive structure 3 has a top surface 31 and a bottom surface 32 opposite to the top surface 31. The lower conductive structure 3 includes multiple dielectric layers (e.g., a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a and a second lower dielectric layer 36a), multiple circuit layers (e.g., a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a and two second lower circuit layers 38a, 38a'), and at least one internal via (including, for example, multiple upper interconnect vias 35 and multiple lower interconnect vias 35a).

[0096] The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371, and defines a plurality of first through-holes 373 extending through the core portion 37. Interconnect vias 39 are disposed or formed in each of the first through-holes 373 for vertical connection. In some embodiments, the interconnect vias 39 comprise a base metal layer 391 and an insulating material 392. The base metal layer 391 is disposed or formed on the sidewalls of the first through-holes 373 and defines a central through-hole. The insulating material 392 fills the central through-hole defined by the base metal layer 391. In some embodiments, the insulating material may be omitted from the interconnect vias 39, and they may comprise a monolithic metal material filling the first through-holes 373.

[0097] A first upper dielectric layer 30 is disposed on the top surface 371 of the core portion 37, and has a top surface 301 and a bottom surface 302 opposite to the top surface 301. Therefore, the bottom surface 302 of the first upper dielectric layer 30 contacts the top surface 371 of the core portion 37. A second upper dielectric layer 36 is stacked or disposed on the first upper dielectric layer 30, and has a top surface 361 and a bottom surface 362 opposite to the top surface 361. Therefore, the bottom surface 362 of the second upper dielectric layer 36 contacts the top surface 301 of the first upper dielectric layer 30, and the second upper dielectric layer 36 is the topmost dielectric layer. Additionally, a first lower dielectric layer 30a is disposed on the bottom surface 372 of the core portion 37, and has a top surface 301a and a bottom surface 302a opposite to the top surface 301a. Therefore, the top surface 301a of the first lower dielectric layer 30a contacts the bottom surface 372 of the core portion 37. A second lower dielectric layer 36a is stacked or disposed on the first lower dielectric layer 30a. The second lower dielectric layer 36a has a top surface 361a and a bottom surface 362a opposite to the top surface 361a, and defines a through-hole with an inner surface. Therefore, the top surface 361a of the second lower dielectric layer 36a contacts the bottom surface 302a of the first lower dielectric layer 30a, and the second lower dielectric layer 36a is the bottommost dielectric layer. Figure 1 As shown, the top surface 31 of the lower conductive structure 3 is the top surface 361 of the second upper dielectric layer 36, and the bottom surface 32 of the lower conductive structure 3 is the bottom surface 362a of the second lower dielectric layer 36a.

[0098] The thickness of each dielectric layer of the upper conductive structure 2 (e.g., the first dielectric layer 20 and the second dielectric layer 26) is less than or equal to about 40%, less than or equal to about 35%, or less than or equal to about 30% of the thickness of each dielectric layer of the lower conductive structure 3 (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a). For example, the thickness of each dielectric layer of the upper conductive structure 2 (e.g., the first dielectric layer 20 and the second dielectric layer 26) may be less than or equal to about 7 μm, and the thickness of each dielectric layer of the lower conductive structure 3 (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a) may be about 40 μm.

[0099] The L / S ratio of the first upper circuit layer 34 can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first upper circuit layer 34 can be greater than or equal to about five times the L / S ratio of the circuit layer 24 of the upper conductive structure 2. The first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In some embodiments, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37 and is covered by the first upper dielectric layer 30. The bottom surface 342 of the first upper circuit layer 34 contacts the top surface 371 of the core portion 37. In some embodiments, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be formed of copper foil (e.g., may constitute part of copper foil). The second metal layer 344 is disposed on the first metal layer 343 and may be an electroplated copper layer. A third metal layer 345 is disposed on the second metal layer 344, and may be another electroplated copper layer. In some embodiments, the third metal layer 345 may be omitted.

[0100] The L / S ratio of the second upper circuit layer 38 can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second upper circuit layer 38 can be substantially equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the circuit layer 24 of the upper conductive structure 2. The second upper circuit layer 38 has a top surface 381 and a bottom surface 382 opposite to the top surface 381. In some embodiments, the second upper circuit layer 38 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 and is covered by the second upper dielectric layer 36. The bottom surface 382 of the second upper circuit layer 38 can contact the top surface 301 of the first upper dielectric layer 30. In some embodiments, the second upper circuit layer 38 is electrically connected to the first upper circuit layer 34 through an upper interconnect via 35. That is, the upper interconnect via 35 is disposed between the second upper circuit layer 38 and the first upper circuit layer 34 to electrically connect the second upper circuit layer 38 and the first upper circuit layer 34. In some embodiments, the second upper circuit layer 38 and the upper interconnect via 35 are integrally formed as a single-piece structure. Each upper interconnect via 35 gradually narrows downwards from the top surface 31 of the lower conductive structure 3 toward the bottom surface 32.

[0101] Additionally, in some embodiments, the second upper circuit layer 38' is disposed on and protrudes from the top surface 361 of the second upper dielectric layer 36. In some embodiments, the second upper circuit layer 38 is electrically connected to the second upper circuit layer 38' via an upper interconnect via 35. That is, the upper interconnect via 35 is disposed between the second upper circuit layers 38 and 38' to electrically connect the second upper circuit layers 38 and 38'. In some embodiments, the second upper circuit layer 38' and the upper interconnect via 35 are integrally formed as a single-piece structure. In some embodiments, the second upper circuit layer 38' is the topmost circuit layer of the lower conductive structure 3.

[0102] The L / S ratio of the first lower circuit layer 34a can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first lower circuit layer 34a can be greater than or equal to about five times the L / S ratio of the circuit layer 24 of the upper conductive structure 2. The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In some embodiments, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37 and is covered by a first lower dielectric layer 30a. The top surface 341a of the first lower circuit layer 34a contacts the bottom surface 372 of the core portion 37. In some embodiments, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be formed of copper foil. A second metal layer 344a is disposed on the first metal layer 343a, and may be an electroplated copper layer. A third metal layer 345a is disposed on the second metal layer 344a, and may be another electroplated copper layer. In some embodiments, the third metal layer 345a may be omitted.

[0103] The L / S ratio of the second lower circuit layer 38a can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second lower circuit layer 38a can be substantially equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the circuit layer 24 of the upper conductive structure 2. The second lower circuit layer 38a has a top surface 381a and a bottom surface 382a opposite to the top surface 381a. In some embodiments, the second lower circuit layer 38a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a and is covered by the second lower dielectric layer 36a. The top surface 381a of the second lower circuit layer 38a contacts the bottom surface 302a of the first lower dielectric layer 30a. In some embodiments, the second lower circuit layer 38a is electrically connected to the first lower circuit layer 34a through a lower interconnect via 35a. That is, the lower interconnect via 35a is disposed between the second lower circuit layer 38a and the first lower circuit layer 34a for electrically connecting the second lower circuit layer 38a and the first lower circuit layer 34a. In some embodiments, the second lower circuit layer 38a and the lower interconnect via 35a are integrally formed or a single-piece structure. The lower interconnect via 35a gradually narrows upward along the direction from the bottom surface 32 of the lower conductive structure 3 toward the top surface 31.

[0104] In some embodiments, a second lower circuit layer 38a' is disposed on and protrudes from the bottom surface 362a of the second lower dielectric layer 36a. In some embodiments, the second lower circuit layer 38a' is electrically connected to the second lower circuit layer 38a through a lower interconnect via 35a. That is, the lower interconnect via 35a is disposed between the second lower circuit layers 38a and 38a' to electrically connect the second lower circuit layers 38a and 38a'. In some embodiments, the second lower circuit layer 38a' and the lower interconnect via 35a are integrally formed as a single-piece structure. In some embodiments, the second lower circuit layer 38a' is the bottommost low-density circuit layer of the lower conductive structure 3.

[0105] In some embodiments, each interconnect via 39 is electrically connected to the first upper circuit layer 34 and the first lower circuit layer 34a. The base metal layer 391 of the interconnect via 39, the second metal layer 344 of the first upper circuit layer 34, and the second metal layer 344a of the first lower circuit layer 34a can be integrally formed as a single-piece structure.

[0106] An intermediate layer 12 is inserted or disposed between the upper conductive structure 2 and the lower conductive structure 3 to bond the upper conductive structure 2 and the lower conductive structure 3 together. That is, the intermediate layer 12 adheres to the bottom surface 22 of the upper conductive structure 2 and the top surface 31 of the lower conductive structure 3. In some embodiments, the intermediate layer 12 may be an adhesive layer cured from an adhesive material (e.g., a cured adhesive material, such as an adhesive polymer). The intermediate layer 12 has a top surface 121 and a bottom surface 122 opposite to the top surface 121, and defines at least one first through-hole 123 having an inner surface 1231. The top surface 121 of the intermediate layer 12 contacts the bottom surface 22 of the upper conductive structure 2 (that is, the bottom surface 22 of the upper conductive structure 2 is attached to the top surface 121 of the intermediate layer 12), and the bottom surface 122 of the intermediate layer 12 contacts the top surface 31 of the lower conductive structure 3. Therefore, the bottom first circuit layer 24 of the upper conductive structure 2 and the top circuit layer (e.g., the second upper circuit layer 38') of the lower conductive structure 3 are embedded in the intermediate layer 12. In some embodiments, the bonding force between two adjacent dielectric layers of the upper conductive structure 2 (e.g., two adjacent first dielectric layers 20) is greater than the bonding force between the dielectric layer of the upper conductive structure 2 (e.g., the bottom first dielectric layer 20) and the intermediate layer 12. The surface roughness of the boundary between two adjacent dielectric layers of the upper conductive structure 2 (e.g., two adjacent first dielectric layers 20) is greater than the surface roughness of the boundary between the dielectric layer of the upper conductive structure 2 (e.g., the bottom first dielectric layer 20) and the intermediate layer 12, for example, in terms of root mean squared surface roughness, about 1.1 times or more, about 1.3 times or more, or about 1.5 times or more.

[0107] In some embodiments, the material of the intermediate layer 12 is transparent and can be seen through by the human eye or a machine. That is, the markings adjacent to the top surface 31 of the lower conductive structure 3 can be identified or detected by the human eye or a machine from the top surface 21 of the upper conductive structure 2.

[0108] The first via 123 extends through the intermediate layer 12. In some embodiments, the first via 123 of the intermediate layer 12 extends through the bottommost first circuit layer 24 of the upper conductive structure 2 and terminates at or above the topmost circuit layer of the lower conductive structure 3 (e.g., the second upper circuit layer 38'). That is, the first via 123 of the intermediate layer 12 does not extend through the topmost circuit layer of the lower conductive structure 3 (e.g., the second upper circuit layer 38'). The first via 123 of the intermediate layer 12 may expose a portion of the topmost circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'). Figure 1As shown, the first via 123 of the intermediate layer 12 gradually narrows downwards from the top surface 121 of the intermediate layer 12 towards the bottom surface 122; that is, the size of the top portion of the first via 123 is larger than the size of the bottom portion of the first via 123. Furthermore, the first via 123 of the intermediate layer 12 is aligned with and communicates with the via 203 of the first dielectric layer 20 and the via 263 of the second dielectric layer 26. The bottom portion of the via 203 of the bottommost first dielectric layer 20 is adjacent to or connected to the top portion of the first via 123 of the intermediate layer 12. The size of the bottom portion of the via 203 of the bottommost first dielectric layer 20 is substantially equal to the top portion of the first via 123 of the intermediate layer 12. Therefore, the inner surface 1231 of the first via 123 of the intermediate layer 12 is coplanar or aligned with the inner surface 2031 of the via 203 of the first dielectric layer 20 and the inner surface 2631 of the via 263 of the second dielectric layer 26. In some embodiments, the inner surface 1231 of the first via 123 of the intermediate layer 12 is a curved surface and is a portion of the inner surface 231 of a single continuous via 23 for accommodating the upper through-hole 14. The first via 123 of the intermediate layer 12, the via 203 of the first dielectric layer 20, and the via 263 of the second dielectric layer 26 are configured together to define or form a single via 23. Therefore, the single via 23 includes the first via 123 of the intermediate layer 12, the via 203 of the first dielectric layer 20, and the via 263 of the second dielectric layer 26.

[0109] like Figure 1 As shown, the cross-sectional views of one side of the inner surface 2031 of the first via 123 of the intermediate layer 12, the via 203 of the first dielectric layer 20, and the inner surface 2631 of the via 263 of the second dielectric layer 26 are substantially straight line segments. That is, the cross-sectional views of one side of the inner surface 1231 of the first via 123 of the intermediate layer 12, the inner surface 2031 of the via 203 of the first dielectric layer 20, and the inner surface 2631 of the via 263 of the second dielectric layer 26 can extend along the same substantially straight line. A single via 23 extends through the upper conductive structure 2 and the intermediate layer 12; that is, a single via 23 extends from the top surface 21 of the upper conductive structure 2 to the bottom portion of the intermediate layer 12 to expose a portion of the topmost circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'). The single via 23 gradually narrows downwards. The maximum width of a single through-hole 23 (e.g., the diameter at the top portion) may be less than or equal to about 20 μm, such as about 20 μm, about 15 μm, or about 10 μm.

[0110] Surface structure 16 is adjacent to the top surface 21 of the upper conductive structure 2. For example... Figure 2As shown, surface structure 16 is disposed on the top surface 261 of the second dielectric layer 26 and defines a via 163 having an inner surface 1631. The via 163 of surface structure 16 is aligned with and communicates with via 23. The via 163 is formed by lithography (e.g., exposure and development) rather than drilling. Therefore, the width (e.g., diameter) of the via 163 can be reduced to less than or equal to about 20 μm, for example, about 20 μm, about 15 μm, or about 10 μm. In addition, the inner surface 1631 can be substantially perpendicular to the top surface 21 of the conductive structure 2. The material of surface structure 16 includes a metal, such as copper. Surface structure 16 includes a first portion 161 and a second portion 162. The first portion 161 is adjacent to the via 163, and the second portion 162 is farther away from the via 163. In some embodiments, the second portion 162 surrounds the through hole 163, and the first portion 161 surrounds the through hole 163 and is disposed between the second portion 162 and the through hole 163.

[0111] During the manufacturing process, a single through-hole 23 is formed by laser drilling, wherein the surface structure 16 acts as a mask (or sacrificial layer). Laser beam 9 ( Figure 52 The power of the laser beam 9 is set to low (e.g., approximately 800 kW), which allows it to penetrate the second dielectric layer 26 and the first dielectric layer 20, but not the metal portion of the surface structure 16. In some embodiments, the power of the laser beam 9 is consistent throughout the drilling process. That is, the power of the laser beam 9 does not change throughout the drilling process. The width (e.g., diameter) of the via 23 is the width (e.g., diameter) of the via 163, not the width (e.g., diameter) of the laser beam 9. Figure 52 The laser beam 9 (determined by) Figure 52 The first portion 161 of the removable surface structure 16 has a thickness of approximately 1 μm; therefore, the thickness of the first portion 161 is less than the thickness of the second portion 162. The first portion 161 has a non-consistent or varying thickness, while the second portion 162 has a substantially consistent thickness. The top surface of the first portion 161 is an inclined surface, wherein the thickness of the first portion 161 gradually narrows along the direction toward the through-hole 163, and the surface roughness of the top surface of the first portion 161 is greater than the surface roughness of the top surface of the second portion 162, for example, in terms of root mean square surface roughness, approximately 1.1 times or greater, approximately 1.3 times or greater, or approximately 1.5 times or greater. After the laser drilling process, the angle of inclination between the inner surface 231 of the through-hole 23 and the top surface 21 of the conductive structure 2 is greater than approximately 90 degrees, for example, approximately 93 degrees or greater, approximately 95 degrees or greater, or approximately 98 degrees or greater.

[0112] like Figure 1As shown, it further includes at least one surface trace 17, which is adjacent to the top surface 21 of the upper conductive structure 2 and electrically connected to the surface structure 16. In some embodiments, the surface trace 17 and the surface structure 16 are disposed on the top surface 261 of the second dielectric layer 26 and are formed simultaneously.

[0113] An upper through-hole 14 is formed or disposed in a single through-hole 23 and is made of metal, metal alloy, or other conductive material. Therefore, the upper through-hole 14 extends through at least a portion of the upper conductive structure 2 and the intermediate layer 12, and is electrically connected to the topmost circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'). Figure 1 As shown, the upper through-hole 14 extends through and contacts the bottommost first circuit layer 24 of the upper conductive structure 2, and terminates at or on a portion of the topmost circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'), and contacts that portion. The upper through-hole 14 extends from the top surface 21 of the upper conductive structure 2 to the bottom surface 122 of the intermediate layer 12. Therefore, the upper through-hole 14 extends to contact a portion of the lower conductive structure 3, but does not extend through the lower conductive structure 3. Furthermore, the upper through-hole 14 gradually narrows downwards; that is, the size of the top portion of the upper through-hole 14 is larger than the size of the bottom portion. Therefore, the narrowing direction of the internal through-hole 25 of the upper conductive structure 2 is different from the narrowing direction of the upper through-hole 14. In some embodiments, the upper through-hole 14 is an integral or one-piece structure with a homogeneous material composition, and the surrounding surface of the upper through-hole 14 is a substantially continuous surface without boundaries. The width (e.g., diameter) of the upper through-hole 14 is less than or equal to about 20 μm, for example, about 20 μm, about 15 μm, or about 10 μm. The surface structure 16 includes a first portion 161 and a second portion 162. The first portion 161 of the surface structure 16 is adjacent to the upper through-hole 14, and the first portion 161 of the surface structure 16 is disposed between the second portion 162 of the surface structure 16 and the upper through-hole 14.

[0114] like Figure 1 As shown, the upper conductive structure 2 includes a high-density region 41 and a low-density region 47. In some embodiments, the density of circuit lines (including traces or pads) in the high-density region 41 is greater than the density of circuit lines in the low-density region 47. That is, the count of circuit lines (including traces or pads) per unit area in the high-density region 41 is greater than the count of circuit lines per unit area in the low-density region 47. Alternatively or in combination, the L / S ratio of the circuit layers in the high-density region 41 is less than the L / S ratio of the circuit layers in the low-density region 47. In addition, an upper through-hole 14 is provided in the low-density region 47 of the high-density conductive structure (e.g., the upper conductive structure 2). In some embodiments, the high-density region 41 may be a chip bonding region.

[0115] Additionally, an external circuit layer 28 (e.g., a top low-density circuit layer) is disposed on and protrudes from the top surface 21 of the upper conductive structure 2 (e.g., the top surface 261 of the second dielectric layer 26). Figure 1 As shown, the external circuit layer 28 includes a pad portion 281 and at least one surface trace 282. The pad portion 281 is disposed on the surface structure 16 and the upper through-hole 14. In some embodiments, the pad portion 281 and the upper through-hole 14 are integrally formed and simultaneously, and the pad portion 281 and the upper through-hole 14 may be an integral or single-piece structure. The trace portion 282 is electrically connected to the pad portion 281 and is adjacent to the top surface 21 of the upper conductive structure 2. Figure 1 As shown, trace portion 282 is disposed on surface trace 17 and conforms to surface trace 17. The L / S of outer circuit layer 28 may be greater than or equal to the L / S of circuit layer 24. In some embodiments, the L / S of outer circuit layer 28 may be substantially equal to the L / S of second lower circuit layer 38a'. Figure 1 As illustrated in the embodiments, there are no horizontally connected or extended circuit layers in the second dielectric layer 26.

[0116] like Figure 1As shown in the embodiments illustrated, wiring structure 1 is a combination of upper conductive structure 2 and lower conductive structure 3, wherein the circuit layer 24 of upper conductive structure 2 has fine pitch, high yield, and low thickness; and the circuit layers of lower conductive structure 3 (e.g., first upper circuit layer 34, second upper circuit layers 38, 38', first lower circuit layer 34a, and second lower circuit layers 38a, 38a') have low manufacturing cost. Therefore, wiring structure 1 offers a favorable trade-off between yield and manufacturing cost, and wiring structure 1 has a relatively low thickness. In some embodiments, if the package has 10,000 I / Os, then wiring structure 1 comprises three circuit layers 24 of upper conductive structure 2 and six circuit layers of lower conductive structure 3 (e.g., first upper circuit layer 34, second upper circuit layers 38, 38', first lower circuit layer 34a, and second lower circuit layers 38a, 38a'). The manufacturing yield of one layer of the circuit layer 24 of the upper conductive structure 2 can be 99%, and the manufacturing yield of one layer of the circuit layer of the lower conductive structure 3 (e.g., the first upper circuit layer 34, the second upper circuit layers 38, 38', the first lower circuit layer 34a, and the second lower circuit layers 38a, 38a') can be 90%. Therefore, the yield of the wiring structure 1 can be improved. Furthermore, the warpage of the upper conductive structure 2 and the warpage of the lower conductive structure 3 are separate and do not affect each other. In some embodiments, the warpage shape of the upper conductive structure 2 may be different from the warpage shape of the lower conductive structure 3. For example, the warpage shape of the upper conductive structure 2 may be convex, and the warpage shape of the lower conductive structure 3 may be concave. In some embodiments, the warpage shape of the upper conductive structure 2 may be the same as the warpage shape of the lower conductive structure 3; however, the warpage of the lower conductive structure 3 does not accumulate on the warpage of the upper conductive structure 2. Therefore, the yield of the wiring structure 1 can be further improved.

[0117] Furthermore, during the manufacturing process, the lower conductive structure 3 and the upper conductive structure 2 can be tested separately before being joined together. Therefore, known good lower conductive structures 3 and known good upper conductive structures 2 can be selectively joined together. Defective (or unqualified) lower conductive structures 3 and defective (or unqualified) upper conductive structures 2 can be discarded. Therefore, the yield of the wiring structure 1 can be further improved.

[0118] Figure 3 show Figure 1A partially enlarged top view of the upper conductive structure 2. The upper through-holes 14 are arranged in multiple rows (including, for example, a first row 18a, a second row 18b, and a third row 18c) to form multiple via walls (or fence structures) with signal isolation functionality. In the illustrated embodiment, the width (e.g., diameter) of the upper through-hole 14 may be greater than the width (e.g., diameter) of the through-hole 163, but not the width (e.g., diameter) of the laser beam 9. Figure 52 The width (e.g., diameter) of the upper through-hole 14 can be reduced to a minimum. If the distance d between the first row 18a and the second row 18b is fixed, then the third row 18c and the two trace portions 282 can be disposed between the first row 18a and the second row 18b. In a comparative embodiment, the width (e.g., diameter) of the upper through-hole 14 is relatively large. Therefore, when the distance d between the first row 18a and the second row 18b is fixed, there is space between the first row 18a and the second row 18b to accommodate the two trace portions 282, but the third row 18c is not further disposed between the first row 18a and the second row 18b.

[0119] Figure 4 This shows a cross-sectional view of the upper through-hole 14a according to some embodiments of the present disclosure. Figure 5 show Figure 4A perspective view of the upper through-hole 14a. The circuit layer 24 of the upper conductive structure 2 includes a first circuit layer 24a, a second circuit layer 24b, and a third circuit layer 24c. The third circuit layer 24c is disposed below the through-hole 163 of the surface structure 16, the second circuit layer 24b is disposed below the third circuit layer 24c, and the first circuit layer 24a is disposed below the second circuit layer 24b. The first circuit layer 24a defines the through-hole 246a, the second circuit layer 24b defines the through-hole 246b, and the third circuit layer 24c defines the through-hole 246c. The through-hole 163 of the surface structure 16, the through-hole 246c of the third circuit layer 24c, the through-hole 246b of the second circuit layer 24b, and the through-hole 246a of the first circuit layer 24a are aligned with each other. It should be noted that the vias 246c of the third circuit layer 24c, 246b of the second circuit layer 24b, and 246a of the first circuit layer 24a are formed by photolithography (e.g., exposure and development) rather than drilling. Therefore, the inner surfaces of the vias 246a, 246b, and 246c are substantially perpendicular to the top surface 21 of the upper conductive structure 2. In some embodiments, the width (e.g., diameter) of the via 246c of the third circuit layer 24c is smaller than the width (e.g., diameter) of the via 163, the width (e.g., diameter) of the via 246b of the second circuit layer 24b is smaller than the width (e.g., diameter) of the via 246c of the third circuit layer 24c, and the width (e.g., diameter) of the via 246a of the first circuit layer 24a is smaller than the width (diameter) of the via 246b of the second circuit layer 24b.

[0120] like Figure 4 As shown, the inner surface 231a of the through-hole 23a further includes the inner surfaces of the through-holes 246a, 246b, and 246c. Therefore, the inner surface 231a of the through-hole 23a may not be a substantially smooth or continuous surface. An upper through-hole 14a is disposed in the through-hole 23a to extend through and contact the circuit layer 24 (e.g., the first circuit layer 24a, the second circuit layer 24b, and the third circuit layer 24c) of the upper conductive structure 2. It should be noted that the size and shape of the bottom portion of the upper through-hole 14a can be defined by the through-hole 246c of the third circuit layer 24c, the through-hole 246b of the second circuit layer 24b, and the through-hole 246a of the first circuit layer 24a.

[0121] Figure 6 This shows a cross-sectional view of the upper through-hole 14b according to some embodiments of the present disclosure. The upper through-hole 14b is similar to... Figure 4The upper through-hole 14a shown differs in that the through-hole 163 of surface structure 16, the through-hole 246c of the third circuit layer 24c, the through-hole 246b of the second circuit layer 24b, and the through-hole 246a of the first circuit layer 24a are not aligned or offset from each other. Therefore, the inner surface 231b of the through-hole 23b may not be substantially smooth or continuous. The upper through-hole 14b is provided in the through-hole 23b to extend through and contact the circuit layers 24 of the upper conductive structure 2 (e.g., the first circuit layer 24a, the second circuit layer 24b, and the third circuit layer 24c). Additionally, as... Figure 6 As shown, a portion 205 of the bottom first dielectric layer 20 can extend into the space between the surrounding surface of the upper through-hole 14b and the inner surface of the through-hole 246b of the second circuit layer 24b.

[0122] Figure 7 This shows a cross-sectional view of the upper through-hole 14c according to some embodiments of the present disclosure. The upper through-hole 14c is similar to... Figure 4 The upper through-hole 14a shown differs from the through-hole 23c in shape. (As shown) Figure 7 As shown, the inner surface 2031 of the via 203 of the first dielectric layer 20 and the inner surface 2631 of the via 263 of the second dielectric layer 26 are curved surfaces. Therefore, the upper through-hole 14c in the via 23c has a gourd shape. In some embodiments, the upper through-hole 14c includes a plurality of segments 141 disposed between the circuit layers 24 (e.g., the first circuit layer 24a, the second circuit layer 24b, and the third circuit layer 24c) of the upper conductive structure 2. Each segment 141 includes a top portion 1411, a middle portion 1412, and a bottom portion 1413. The width W2 of the middle portion 1412 is greater than the width W1 of the top portion 1411, and the width W2 of the middle portion 1421 is greater than the width W3 of the bottom portion 1423. That is, from a cross-sectional view, the sidewalls of each segment 141 are curved (e.g., convex).

[0123] Figure 8 A cross-sectional view of a wiring structure 1a according to some embodiments of the present disclosure is shown. The wiring structure 1a is similar to... Figure 1 The wiring structure 1 shown is different in that the trace portion 282 is omitted. Figure 1 Therefore, the external circuit layer 28a may include surface traces 17 and pad portions 281.

[0124] Figure 9 A cross-sectional view of a wiring structure 1b according to some embodiments of the present disclosure is shown. The wiring structure 1b is similar to... Figure 1 The wiring structure 1 shown is different in that the surface trace 17 is omitted. Figure 1Therefore, the trace portion 282 of the outer circuit layer 28 can be directly disposed on the top surface 21 of the upper conductive structure 2.

[0125] Figure 10 A cross-sectional view of a wiring structure 1c according to some embodiments of the present disclosure is shown. The wiring structure 1c is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2c and the lower conductive structure 3c. For example... Figure 10 As shown, both the upper conductive structure 2c and the lower conductive structure 3c are strip structures. Therefore, the wiring structure 1c is a strip structure. In some embodiments, the lower conductive structure 3c may be a panel structure carrying multiple strip upper conductive structures 2c. Therefore, the wiring structure 1c is a panel structure. From a top view, the length of the upper conductive structure 2c (e.g., about 240 mm) is greater than the width of the upper conductive structure 2c (e.g., about 95 mm). Additionally, from a top view, the length of the lower conductive structure 3c is greater than the width of the lower conductive structure 3c. Furthermore, the lateral peripheral surface 27 of the upper conductive structure 2c is not coplanar with the lateral peripheral surface 33 of the lower conductive structure 3c (e.g., it is recessed inward or otherwise offset from it). In some embodiments, during the manufacturing process, both the lower conductive structure 3c and the upper conductive structure 2c may be known good strip structures. Alternatively, the upper conductive structure 2c may be a known good strip structure, and the lower conductive structure 3c may be a known good panel structure. Therefore, the yield of wiring structure 1c can be further improved.

[0126] like Figure 10 As shown, the upper conductive structure 2c includes at least one fiducial mark 43 at its corner, and the lower conductive structure 3c includes at least one fiducial mark 45 at its corner. During the manufacturing process, the fiducial mark 43 of the upper conductive structure 2c is aligned with the fiducial mark 45 of the lower conductive structure 3c to ensure the relative positions of the upper conductive structure 2c and the lower conductive structure 3c. In one embodiment, the fiducial mark 43 of the upper conductive structure 2c is disposed on and protrudes from the bottom surface 22 of the upper conductive structure 2c (e.g., the bottom surface 202 of the bottommost first dielectric layer 20). The fiducial mark 43 and the bottommost circuit layer 24 may be on the same layer or partially on the same layer, and may be formed simultaneously. In addition, the fiducial mark 45 of the lower conductive structure 3c is disposed on and protrudes from the top surface 31 of the lower conductive structure 3c (e.g., the top surface 361 of the second upper dielectric layer 36). The reference mark 45 and the second upper circuit layer 38' can be on the same layer or partially on the same layer, and can be formed simultaneously.

[0127] Figure 10AA top view showing an example of a reference mark 43a of the upper conductive structure 2c according to some embodiments of the present disclosure. The reference mark 43a of the upper conductive structure 2c has a continuous cross shape.

[0128] Figure 10B A top view showing an example of a reference mark 45a of the lower conductive structure 3c according to some embodiments of the present disclosure. The reference mark 45a of the lower conductive structure 3c comprises four square segments at the four corners.

[0129] Figure 10C show Figure 10A The reference mark 43a and the upper conductive structure 2c Figure 10B The combined image is a top view of the reference mark 45a of the lower conductive structure 3c. When the upper conductive structure 2c is precisely aligned with the lower conductive structure 3c, the combined image shows the complete reference mark 43a and the complete reference mark 45a, as shown. Figure 10C As shown in the diagram. That is to say, from the top view, reference mark 43a does not cover or overlap reference mark 45a.

[0130] Figure 10D A top view showing an example of a reference mark 43b of the upper conductive structure 2c according to some embodiments of the present disclosure. The reference mark 43b of the upper conductive structure 2c is a continuously inverted "L" shape.

[0131] Figure 10E A top view showing an example of a reference mark 45b of a lower conductive structure 3c according to some embodiments of the present disclosure. The reference mark 45b of the lower conductive structure 3c has a continuously inverted "L" shape that is substantially the same as the reference mark 43b of the upper conductive structure 2c.

[0132] Figure 10F Reference mark 43b shows the upper conductive structure 2c of 10D and Figure 10E The combined image is a top view of the reference mark 45b of the lower conductive structure 3c. When the upper conductive structure 2c is precisely aligned with the lower conductive structure 3c, the combined image only shows the reference mark 43b of the upper conductive structure 2c, as shown. Figure 10F As shown. That is to say, from the top view, datum mark 43b completely covers or overlaps datum mark 45b.

[0133] Figure 10G A top view showing an example of a reference mark 43c of the upper conductive structure 2c according to some embodiments of the present disclosure. The reference mark 43c of the upper conductive structure 2c has a continuous circular shape.

[0134] Figure 10HA top view showing an example of a reference mark 45c of a lower conductive structure 3c according to some embodiments of the present disclosure. The reference mark 45c of the lower conductive structure 3c has a continuous circular shape that is larger than that of the reference mark 43c of the upper conductive structure 2c.

[0135] Figure 10I show Figure 10G The upper conductive structure 2c reference mark 43c and Figure 10H A top view of the combined image of the reference mark 45c of the lower conductive structure 3c. When the upper conductive structure 2c is precisely aligned with the lower conductive structure 3c, the combined image shows two concentric circles, as... Figure 10I As shown in the diagram. That is, the reference mark 43c is located at the center of the reference mark 45c.

[0136] Figure 11 A cross-sectional view showing the bonding of a package structure 4 to a substrate 46 according to some embodiments is shown. The package structure 4 includes a wiring structure 1d, a semiconductor chip 42, a plurality of first connection elements 44, and a plurality of second connection elements 48. Figure 11 The wiring structure 1d is similar to Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2d and the lower conductive structure 3d. Both the upper conductive structure 2d and the lower conductive structure 3d are dies and can be individually divided simultaneously. Therefore, wiring structure 1d is a unitary structure. That is, the lateral peripheral surface 27d of the upper conductive structure 2d, the lateral peripheral surface 33d of the lower conductive structure 3d, and the lateral peripheral surface of the intermediate layer 12 are substantially coplanar with each other. The semiconductor chip 42 is electrically connected and bonded to the outer circuit layer 28 of the upper conductive structure 2d via a first connecting element 44 (e.g., solder bumps or other conductive bumps). The second lower circuit layer 38a' of the lower conductive structure 3d is electrically connected and bonded to the substrate 46 (e.g., a motherboard, such as a printed circuit board, PCB) via a second connecting element 48 (e.g., solder bumps or other conductive bumps).

[0137] Figure 12 A cross-sectional view of a wiring structure 1e according to some embodiments of the present disclosure is shown. The wiring structure 1e is similar to... Figure 1The wiring structure 1 shown differs in the structure of the upper conductive structure 2e and the lower conductive structure 3e. In the upper conductive structure 2e, the second dielectric layer 26 is replaced by the topmost first dielectric layer 20. Additionally, the upper conductive structure 2e may further include a topmost circuit layer 24'. The topmost circuit layer 24' may omit the seed layer and can be electrically connected to the lower circuit layer 24 via an internal via 25. The top surface of the topmost circuit layer 24' may be substantially coplanar with the top surface 21 of the upper conductive structure 2e (e.g., the top surface 201 of the topmost first dielectric layer 20). Therefore, the top surface of the topmost circuit layer 24' can be exposed from the top surface 21 of the upper conductive structure 2e (i.e., the top surface 201 of the topmost first dielectric layer 20). The topmost circuit layer 24' includes a pad portion 245 that acts as a mask (or sacrificial layer) during the laser drilling process. Furthermore, the bottommost first dielectric layer 20 may cover the bottommost circuit layer 24. Therefore, the entire bottom surface 22 of the upper conductive structure 2e (e.g., the bottom surface 202 of the bottommost first dielectric layer 20) is substantially flat.

[0138] In the lower conductive structure 3e, the second upper dielectric layer 36 and the second upper circuit layers 38, 38' are omitted. Therefore, the top surface 31 of the lower conductive structure 3e is the top surface 301 of the first upper dielectric layer 30, which is substantially flat. In addition, it further includes two additional second lower dielectric layers 36a and two additional second lower circuit layers 38a'.

[0139] Intermediate layer 12 is adhered to the bottom surface 22 of upper conductive structure 2e and the top surface 31 of lower conductive structure 3e. Therefore, the entire top surface 121 and the entire bottom surface 122 of intermediate layer 12 are substantially flat. Intermediate layer 12 does not contain or contact horizontally extending or connected circuit layers. That is, no horizontally extending or connected circuit layers are disposed or embedded in intermediate layer 12. Upper through-hole 14 extends through upper conductive structure 2e and intermediate layer 12.

[0140] Figure 13 show Figure 12 A magnified view of section "B" in the image. Pad portion 245 is similar. Figure 1 and Figure 2The surface structure 16. A pad portion 245 is embedded in the topmost first dielectric layer 20 and exposed from the top surface 21 of the upper conductive structure 2. The pad portion 245 defines a via 2453 aligned with and connected to a via 23. The via 2453 is formed by photolithography (e.g., exposure and development) rather than drilling. The pad portion 245 includes a first portion 2451 and a second portion 2452. The first portion 2451 is adjacent to the via 2453, and the second portion 2452 is further away from the via 2453. In some embodiments, the second portion 2452 surrounds the via 2453, and the first portion 2451 surrounds the via 2453 and is disposed between the second portion 2452 and the via 2453. The thickness of the first portion 2451 is less than the thickness of the second portion 2452. The first portion 2451 has a non-uniform or different thickness, and the second portion 2452 has a substantially uniform thickness. The top surface of the first part 2451 is an inclined surface, wherein the thickness of the first part 2451 gradually narrows along the direction toward the through hole 2453, and the surface roughness of the top surface of the first part 2451 is greater than the surface roughness of the second part 2452, for example, in terms of root mean square surface roughness, about 1.1 times or more, about 1.3 times or more, or about 1.5 times or more.

[0141] Figure 14 A cross-sectional view showing the bonding of a package structure 4a to a substrate 46 according to some embodiments is shown. The package structure 4a includes a wiring structure 1f, a semiconductor chip 42, a plurality of first connection elements 44, and a plurality of second connection elements 48. The wiring structure 1f is similar to Figure 12 The wiring structure 1e shown differs in the structure of the upper conductive structure 2f and the lower conductive structure 3f. Both the upper conductive structure 2f and the lower conductive structure 3f are grains and can be individually divided. Therefore, the wiring structure 1f is a unit cell structure. That is, the lateral peripheral surface 27f of the upper conductive structure 2f, the lateral peripheral surface 33f of the lower conductive structure 3f, and the lateral peripheral surface of the intermediate layer 12 are substantially coplanar with each other.

[0142] Semiconductor chip 42 is electrically connected and bonded to the topmost circuit layer 24' of the upper conductive structure 2f via a first connecting element 44 (e.g., solder bump or other conductive bump). The bottommost second lower circuit layer 38a' of the lower conductive structure 3f is electrically connected and bonded to the substrate 46 (e.g., motherboard, such as PCB) via a second connecting element 48 (e.g., solder bump or other conductive bump).

[0143] Figure 15 A cross-sectional view of a wiring structure 1g according to some embodiments of the present disclosure is shown. The wiring structure 1g is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2g and the lower conductive structure 3g. Furthermore, it further includes at least one lower through-hole 15.

[0144] like Figure 15 As shown, the lower conductive structure 3g defines a single via 40 having an inner surface 401. The core portion 37 defines a plurality of second vias 374 extending through the core portion 37. Each second via 374 has an inner surface 3741. A first upper dielectric layer 30 defines a via 303 having an inner surface 3031. A second upper dielectric layer 36 defines a via 363 having an inner surface 3631. A first lower dielectric layer 30a defines a via 303a having an inner surface 3031a. A second lower dielectric layer 36a defines a via 363a having an inner surface 3631a. The vias 363, 303, 374, 303a, and 363a are collectively configured to define or form a portion of the single via 40 for receiving the lower via 15. Figure 15 As shown, the cross-sectional views of one side of the inner surface 3631 of through hole 363, the inner surface 3031 of through hole 303, the inner surface 3741 of the second through hole 374, the inner surface 3031a of through hole 303a, and the inner surface 3631a of through hole 363a are substantially straight line segments. That is, the cross-sectional views of one side of the inner surface 3631 of through hole 363, the inner surface 3031 of through hole 303, the inner surface 3741 of the second through hole 374, the inner surface 3031a of through hole 303a, and the inner surface 3631a of through hole 363a can extend along the same substantially straight line. A single through hole 40 extends through the lower conductive structure 3g; that is, a single through hole 40 extends from the bottom surface 32 of the lower conductive structure 3g to the top surface 31 of the lower conductive structure 3g. The single through hole 40 gradually narrows upwards.

[0145] Furthermore, the thickness of the bottommost first circuit layer 24a of the upper conductive structure 2g is greater than the thickness of the second circuit layer 24b, for example, about 1.1 times or more, about 1.3 times or more, or about 1.5 times or more. For example, the thickness of the first circuit layer 24a may be about 4 μm, and the thickness of the second circuit layer 24b may be about 3 μm. This is because the first circuit layer 24a can be used to block the laser beam during the manufacturing process. The bottommost circuit layer 24a (e.g., the first circuit layer 24a) is disposed on and protrudes from the bottom surface 22 of the upper conductive structure 2g (e.g., the bottom surface 202 of the bottommost first dielectric layer 20).

[0146] A lower through-hole 15 is formed or disposed in a single through-hole 40. Therefore, the lower through-hole 15 extends through at least a portion of the lower conductive structure 3g and the intermediate layer 12, and is electrically connected to the circuit layer of the upper conductive structure 2g (e.g., the bottom surface of the first circuit layer 24a). Figure 15As shown, the lower through-hole 15 extends through and contacts the topmost circuit layer (e.g., the second upper circuit layer 38') of the lower conductive structure 3g, and terminates at or on a portion of the bottommost circuit layer (e.g., the bottom surface of the first circuit layer 24a) of the upper conductive structure 2g, and contacts that portion. The lower through-hole 15 extends from the bottom surface 32 of the lower conductive structure 3g to the top portion of the intermediate layer 12. Therefore, the lower through-hole 15 extends to contact a portion of the upper conductive structure 2g, and the lower through-hole 15 does not extend through the upper conductive structure 2g. The length of the lower through-hole 15 is greater than the thickness of the low-density conductive structure (e.g., the lower conductive structure 3g). In addition, the lower through-hole 15 gradually narrows upward, that is, the size of the top portion of the lower through-hole 15 is smaller than the size of the bottom portion of the lower through-hole 15. Therefore, the narrowing direction of the internal through-hole 25 of the upper conductive structure 2g is the same as the narrowing direction of the lower through-hole 15. In some embodiments, the lower through-hole 15 is an integral or single-piece structure with a homogeneous material composition, and the surrounding surface 153 of the lower through-hole 15 is a substantially continuous surface without boundaries. The lower through-hole 15 and the second lower circuit layer 38a' can be integrally formed as an integral or single-piece structure. The size of the top portion of the lower through-hole 15 can be substantially equal to the size of the bottom portion of the upper through-hole 14, and the narrowing direction of the lower through-hole 15 can be different from the narrowing direction of the upper through-hole 14.

[0147] Figure 16 This diagram shows a cross-sectional view of a package structure 4b according to some embodiments of the present disclosure. The package structure 4b includes a wiring structure 1h, a semiconductor chip 42, a plurality of first connection elements 44, and at least one passive component 49. Figure 16 The wiring structure 1h is similar to Figure 11The wiring structure 1d shown differs in the structure of the upper conductive structure 2h and the lower conductive structure 3h. In the upper conductive structure 2h, an upper through-hole 14h may be disposed below the semiconductor chip 42, and one of the circuit layers (e.g., the second circuit layer 24b) may include one or more traces (e.g., high-density traces) and a ground plane 245 for grounding. In some embodiments, the plurality of upper through-holes 14h may be configured to be parallel to each other or laterally adjacent to each other to form a first via wall (or fence structure). In addition, a plurality of internal vias 25h may be stacked on top of each other to form a columnar structure, and the plurality of columnar structures may be configured to be parallel to each other or laterally adjacent to each other to form a second via wall (or fence structure). The upper conductive structure 2h can provide signal transmission between semiconductor chips 42, between semiconductor chips 42 and passive components 49, and / or between passive components 49. Such transmitted signals may not include electrical signals. For example, the upper conductive structure 2h provides excellent stability for the transmission of radio frequency (RF) signals and high-speed digital signals. The high-speed digital signal and the RF / analog modulation signal can be arranged on the same layer or different layers. To prevent interference from the high-speed digital signal to the RF / analog modulation signal, two layouts can be designed for two scenarios. In the first scenario where the high-speed digital signal and the RF / analog modulation signal are arranged on the same layer, the first or second via wall can achieve signal isolation. That is, the first or second via wall can be positioned between the high-speed digital signal and the RF / analog modulation signal. In the second scenario where the high-speed digital signal and the RF / analog modulation signal are arranged on different layers, the ground plane 245 can achieve signal isolation. That is, the ground plane 245 can be positioned between the high-speed digital signal and the RF / analog modulation signal.

[0148] In the lower conductive structure 3h, the second upper circuit layer 38', the second upper dielectric layer 36, the second lower circuit layer 38a', and the second lower dielectric layer 36a are omitted. Additionally, the lower through-hole 15h may be disposed below the internal through-hole 25h, and one of the circuit layers (e.g., the second upper circuit layer 38) may include one or more traces (e.g., low-density traces) and a ground plane 385 for grounding. The lower conductive structure 3h provides power signal transmission between semiconductor chips 42, between semiconductor chips 42 and passive components 49, and / or between passive components 49. It should be noted that the circuit layers (e.g., upper circuit layers 34, 38 and lower circuit layers 34a, 38a) have low DC impedance and low parasitic capacitance. Furthermore, the ground plane 385 provides signal isolation between the lower conductive structure 3h and the upper conductive structure 2h.

[0149] The common ground of the wiring structure 1h can be achieved through two paths. The first path is a combination of ground plane 245, ground plane 385, upper through-hole 14h, upper interconnect via 35h, interconnect via 39h, and lower interconnect via 35a'. The second path is a combination of ground plane 245, ground plane 385, stack internal via 25h, and lower through-hole 15h. Furthermore, the first via wall may further include upper interconnect via 35h, interconnect via 39h, and lower interconnect via 35a' below the upper through-hole 14h to form an extended first via wall. The second via wall may further include lower through-hole 15h below the stack internal via 25h to form an extended second via wall. The extended first and extended second via walls can prevent signal leakage when they are positioned adjacent to the lateral surrounding surface of the wiring structure 1h.

[0150] Figures 17 to 53 Methods for manufacturing wiring structures according to some embodiments of the present disclosure are shown. In some embodiments, the method is used to manufacture... Figure 1 The wiring structure 1 and / or shown Figure 11 The encapsulation structure shown is 4.

[0151] refer to Figures 17 to 36 The lower conductive structure 3 is provided. The lower conductive structure 3 is manufactured as follows. (See reference...) Figure 17 A core portion 37 is provided, having a top copper foil 50 and a bottom copper foil 52. The core portion 37 can be of wafer type, panel type, or strip type. The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371. The top copper foil 50 is disposed on the top surface 371 of the core portion 37, and the bottom copper foil 52 is disposed on the bottom surface 372 of the core portion 37.

[0152] refer to Figure 18 Multiple first through holes 373 are formed by drilling techniques (such as laser drilling or mechanical drilling) or other suitable techniques to extend through the core portion 37, the top copper foil 50 and the bottom copper foil 52.

[0153] refer to Figure 19 A second metal layer 54 is formed or disposed on the sidewalls of the top copper foil 50, the bottom copper foil 52, and the first through hole 373 by electroplating or other suitable techniques. A portion of the second metal layer 54 on the sidewall of each first through hole 373 defines a central through hole.

[0154] refer to Figure 20 An insulating material 392 is provided to fill the central through-hole defined by the second metal layer 54.

[0155] refer to Figure 21The top third metal layer 56 and the bottom third metal layer 56 are formed or disposed on the second metal layer 54 by electroplating or other suitable techniques. The third metal layer 56 covers the insulating material 392.

[0156] refer to Figure 22 A top photoresist layer 57 is formed or disposed on the top third metal layer 56, and a bottom photoresist layer 57a is formed or disposed on the bottom third metal layer 56. Subsequently, the photoresist layers 57 and 57a are patterned by exposure and development.

[0157] refer to Figure 23 The portions of the top copper foil 50, second metal layer 54, and top third metal layer 56 not covered by the top photoresist layer 57 are removed using etching or other suitable techniques. The portions of the top copper foil 50, second metal layer 54, and top third metal layer 56 covered by the top photoresist layer 57 are retained to form the first upper circuit layer 34. Simultaneously, the portions of the bottom copper foil 52, second metal layer 54, and bottom third metal layer 56 not covered by the bottom photoresist layer 57a are removed using etching or other suitable techniques. The portions of the bottom copper foil 52, second metal layer 54, and bottom third metal layer 56 covered by the bottom photoresist layer 57a are retained to form the first lower circuit layer 34a. Meanwhile, the portions of the second metal layer 54 and insulating material 392 disposed in the first via 373 form interconnect vias 39. Figure 23 As shown, the first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In some embodiments, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37. The bottom surface 342 of the first upper circuit layer 34 contacts the top surface 371 of the core portion 37. In some embodiments, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be formed from a portion of the top copper foil 50. The second metal layer 344 is disposed on the first metal layer 343 and may be an electroplated copper layer formed from the second metal layer 54. The third metal layer 345 is disposed on the second metal layer 344 and may be another electroplated copper layer formed from the top third metal layer 56.

[0158] The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In some embodiments, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37. The top surface 341a of the first lower circuit layer 34a contacts the bottom surface 372 of the core portion 37. In some embodiments, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a, and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be formed from a portion of the bottom copper foil 52. The second metal layer 344a is disposed on the first metal layer 343a and may be an electroplated copper layer formed from the second metal layer 54. The third metal layer 345a is disposed on the second metal layer 344a and may be another electroplated copper layer formed from the bottom third metal layer 56. The interconnect via 39 includes a base metal layer 391 formed from the second metal layer 54 and an insulating material 392. In some embodiments, the interconnect via 39 may comprise a monolithic metal material filling the first via 373. The interconnect via 39 electrically connects the first upper circuit layer 34 and the first lower circuit layer 34a.

[0159] refer to Figure 24 The top photoresist layer 57 and the bottom photoresist layer 57a are removed by stripping techniques or other suitable techniques.

[0160] refer to Figure 25 A first upper dielectric layer 30 is formed or disposed on the top surface 371 of the core portion 37 using lamination technology or other suitable techniques, to cover the top surface 371 of the core portion 37 and the first upper circuit layer 34. Simultaneously, a first lower dielectric layer 30a is formed or disposed on the bottom surface 372 of the core portion 37 using lamination technology or other suitable techniques, to cover the bottom surface 372 of the core portion 37 and the first lower circuit layer 34a.

[0161] refer to Figure 26 At least one via 303 is formed by drilling or other suitable techniques to extend through the first upper dielectric layer 30 to expose a portion of the first upper circuit layer 34. Simultaneously, at least one via 303a is formed by drilling or other suitable techniques to extend through the first lower dielectric layer 30a to expose a portion of the first lower circuit layer 34a.

[0162] refer to Figure 27 A top metal layer 58 is formed on the first upper dielectric layer 30 and in the via 303 using electroplating or other suitable techniques to form an upper interconnect via 35. Simultaneously, a bottom metal layer 60 is formed on the first lower dielectric layer 30a and in the via 303a using electroplating or other suitable techniques to form a lower interconnect via 35a. Figure 27As shown, the upper interconnecting via 35 gradually narrows downwards, and the lower interconnecting via 35a gradually narrows upwards.

[0163] refer to Figure 28 A top photoresist layer 59 is formed or disposed on a top metal layer 58, and a bottom photoresist layer 59a is formed or disposed on a bottom metal layer 60. Subsequently, the photoresist layers 59 and 59a are patterned by exposure and development.

[0164] refer to Figure 29 The portion of the top metal layer 58 not covered by the top photoresist layer 59 is removed using etching or other suitable techniques. The portion of the top metal layer 58 covered by the top photoresist layer 59 is retained to form the second upper circuit layer 38. Simultaneously, the portion of the bottom metal layer 60 not covered by the bottom photoresist layer 59a is removed using etching or other suitable techniques. The portion of the bottom metal layer 60 covered by the bottom photoresist layer 59a is retained to form the second lower circuit layer 38a.

[0165] refer to Figure 30 The top photoresist layer 59 and the bottom photoresist layer 59a are removed by stripping techniques or other suitable techniques.

[0166] refer to Figure 31 A second upper dielectric layer 36 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 using lamination technology or other suitable techniques, to cover the top surface 301 of the first upper dielectric layer 30 and the second upper circuit layer 38. Simultaneously, a second lower dielectric layer 36a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a using lamination technology or other suitable techniques, to cover the bottom surface 302a of the first lower dielectric layer 30a and the second lower circuit layer 38a.

[0167] refer to Figure 32 At least one via 363 is formed by drilling or other suitable techniques to extend through the second upper dielectric layer 36 to expose a portion of the second upper circuit layer 38. Simultaneously, at least one via 363a is formed by drilling or other suitable techniques to extend through the second lower dielectric layer 36a to expose a portion of the second lower circuit layer 38a.

[0168] refer to Figure 33 A top metal layer 62 is formed on the second upper dielectric layer 36 and in the via 363 by electroplating or other suitable techniques to form an upper interconnect via 35. Simultaneously, a bottom metal layer 64 is formed on the second lower dielectric layer 36a and in the via 363a by electroplating or other suitable techniques to form a lower interconnect via 35a.

[0169] refer to Figure 34A top photoresist layer 63 is formed or disposed on a top metal layer 62, and a bottom photoresist layer 63a is formed or disposed on a bottom metal layer 64. Subsequently, the photoresist layers 63 and 63a are patterned by exposure and development.

[0170] refer to Figure 35 The portion of the top metal layer 62 not covered by the top photoresist layer 63 is removed using etching or other suitable techniques. The portion of the top metal layer 62 covered by the top photoresist layer 63 is retained to form the second upper circuit layer 38'. Simultaneously, the portion of the bottom metal layer 64 not covered by the bottom photoresist layer 63a is removed using etching or other suitable techniques. The portion of the bottom metal layer 64 covered by the bottom photoresist layer 63a is retained to form the second lower circuit layer 38a'.

[0171] refer to Figure 36 The top photoresist layer 63 and the bottom photoresist layer 63a are removed using a stripping technique or other suitable technique. Simultaneously, the lower conductive structure 3 is formed, and dielectric layers (including a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) are cured. At least one of the circuit layers (including, for example, a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a') is in contact with at least one of the dielectric layers (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a). Subsequently, the electrical characteristics (e.g., open circuit / short circuit) of the lower conductive structure 3 are tested.

[0172] refer to Figures 37 to 47 Provides an upper conductive structure 2. The upper conductive structure 2 is manufactured as follows. (Refer to...) Figure 37 A carrier 65 is provided. The carrier 65 can be a glass carrier and can be of wafer type, panel type or strip type.

[0173] refer to Figure 38 A release layer 66 is coated on the bottom surface of the carrier 65.

[0174] refer to Figure 39 A conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 by physical vapor deposition (PVD) or other suitable techniques.

[0175] refer to Figure 40 A second dielectric layer 26 is formed on the conductive layer 67 by coating technology or other suitable technology.

[0176] refer to Figure 41At least one via 264 is formed by exposure and development techniques or other suitable techniques to extend through the second dielectric layer 26 to expose a portion of the conductive layer 67.

[0177] refer to Figure 42 A seed layer 68 is formed on the bottom surface 262 of the second dielectric layer 26 and in the via 264 using PVD technology or other suitable techniques.

[0178] refer to Figure 43 A photoresist layer 69 is formed on the seed layer 68. Subsequently, the photoresist layer 69 is patterned using exposure and development techniques or other suitable techniques to expose portions of the seed layer 68. The photoresist layer 69 defines a plurality of openings 691. At least one opening 691 of the photoresist layer 69 corresponds to and is aligned with a via 264 of the second dielectric layer 26.

[0179] refer to Figure 44 Conductive material 70 (e.g., metallic material) is applied to the opening 691 of the photoresist layer 69 and the seed layer 68 by electroplating or other suitable techniques.

[0180] refer to Figure 45 The photoresist layer 69 is removed by stripping or other suitable techniques.

[0181] refer to Figure 46 The portion of the seed layer 68 not covered by the conductive material 70 is removed by etching or other suitable techniques. Simultaneously, a circuit layer 24 and at least one internal via 25 are formed. The circuit layer 24 may be a fan-out circuit layer or an RDL, and the L / S ratio of the circuit layer 24 may be less than or equal to about 2 μm / about 2 μm, or less than or equal to about 1.8 μm / about 1.8 μm. The circuit layer 24 is disposed on the bottom surface 262 of the second dielectric layer 26. In some embodiments, the circuit layer 24 may include a seed layer 243 formed by the seed layer 68 and a conductive material 244 (e.g., a metal material) disposed on the seed layer 243 and formed by the conductive material 70. The internal via 25 is disposed in the via 264 of the second dielectric layer 26. In some embodiments, the internal via 25 may include a seed layer 251 and a conductive material 252 (e.g., a metal material) disposed on the seed layer 251. The internal via 25 gradually narrows upwards.

[0182] refer to Figure 47 By repeating Figures 40 to 46In this stage, multiple first dielectric layers 20 and multiple circuit layers 24 are formed. In some embodiments, each circuit layer 24 is embedded in a corresponding first dielectric layer 20, and the top surface 241 of the circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. At this time, an upper conductive structure 2 is formed, and dielectric layers (including first dielectric layer 20 and second dielectric layer 26) are cured. At least one of the circuit layers (including, for example, three circuit layers 24) is in contact with at least one of the dielectric layers (e.g., first dielectric layer 20 and second dielectric layer 26). Subsequently, the electrical characteristics (e.g., open circuit / short circuit) of the upper conductive structure 2 are tested.

[0183] refer to Figure 48 An adhesive layer 12 is formed or applied to the top surface 31 of the lower conductive structure 3.

[0184] refer to Figure 49 An upper conductive structure 2 is attached to a lower conductive structure 3 via an adhesive layer 12. In some embodiments, a known good upper conductive structure 2 is attached to a known good lower conductive structure 3. Subsequently, the adhesive layer 12 is cured to form an intermediate layer 12. In some embodiments, the upper conductive structure 2 may be pressed onto the lower conductive structure 3. Therefore, the thickness of the intermediate layer 12 is determined by the gap between the upper conductive structure 2 and the lower conductive structure 3. The top surface 121 of the intermediate layer 12 contacts the bottom surface 22 of the upper conductive structure 2 (that is, the bottom surface 22 of the upper conductive structure 2 is attached to the top surface 121 of the intermediate layer 12), and the bottom surface 122 of the intermediate layer 12 contacts the top surface 31 of the lower conductive structure 3. Therefore, the bottommost first circuit layer 24 of the upper conductive structure 2 (e.g., first circuit layer 24a) and the second upper circuit layer 38' of the lower conductive structure 3 are embedded in the intermediate layer 12. In some embodiments, the bonding force between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2 is greater than the bonding force between the dielectric layer of the upper conductive structure 2 (e.g., the bottom first dielectric layer 20) and the intermediate layer 12. The surface roughness of the boundary between the two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2 is greater than the surface roughness of the boundary between the dielectric layer of the upper conductive structure 2 (e.g., the bottom first dielectric layer 20) and the intermediate layer 12.

[0185] refer to Figure 50 and Figure 51 ,in Figure 51This is a perspective view of the surface trace 17 and surface structure 16. The carrier 65, release layer 66, and conductive layer 67 are removed to expose a portion of the internal via 25. Subsequently, at least one surface trace 17 and surface structure 16 are formed on the top surface 21 of the upper conductive structure 2. The surface trace 17 and surface structure 16 are formed as follows: A metal layer is formed on the entire top surface 21 of the upper conductive structure 2. The metal layer is then patterned by photolithography (e.g., exposure and development) to form the surface trace 17, surface structure 16, and via 163 in the surface structure 16. The surface trace 17 is electrically connected to the surface structure 16 and can be integrally formed with the surface structure 16 as a monolithic or single-piece structure. The via 163 of the surface structure 16 is formed by photolithography rather than drilling, and the width (e.g., diameter) of the via 163 can be reduced to less than or equal to about 20 μm, for example, about 20 μm, about 15 μm, or about 10 μm. In addition, the inner surface of the through hole 163 may be substantially perpendicular to the top surface 21 of the conductive structure 2.

[0186] refer to Figure 52 and Figure 53 A laser beam 9 is applied to the top surface 21 of the surface structure 16 and the upper conductive structure 2. The laser beam 9 can be a carbon dioxide (CO2) laser or an ultraviolet (UV) laser. A first portion 91 of the laser beam 9 is blocked by the solid portion of the surface structure 16, and a second portion 92 of the laser beam 9 passes through a via 163 in the surface structure 16 to form a via 23 in the upper conductive structure 2 and the intermediate layer 12 to expose the circuit layer of the lower conductive structure 3 (e.g., a second upper circuit layer 38'). That is, a single via 23 is formed by laser drilling, wherein the surface structure 16 acts as a mask (or sacrificial layer). The power of the laser beam 9 is set to low (e.g., about 800 kW), which can penetrate the second dielectric layer 26 and the first dielectric layer 20, but does not penetrate the metal portion of the surface structure 16. In some embodiments, the power of the laser beam 9 is consistent throughout the drilling process. That is, the power of the laser beam 9 does not change throughout the drilling process. The width (e.g., diameter) of the through-hole 23 is determined by the width (e.g., diameter) of the through-hole 163, rather than the width (e.g., diameter) of the laser beam 9. The laser beam 9 can remove approximately 1 μm of thickness from a portion (e.g., the first portion 161) of the surface structure 16. Therefore, after the laser drilling process, as... Figure 2As shown, a portion of surface structure 16 (e.g., a portion of the first portion 161) is removed by a laser beam; therefore, the thickness of the first portion 161 is less than the thickness of the second portion 162. The first portion 161 has a non-uniform or different thickness, while the second portion 162 has a substantially uniform thickness. The top surface of the first portion 161 is an inclined surface, wherein the thickness of the first portion 161 gradually narrows along the direction toward the via 163, and the surface roughness of the top surface of the first portion 161 is greater than the surface roughness of the second portion 162, for example, in terms of root mean square surface roughness, about 1.1 times or more, about 1.3 times or more, or about 1.5 times or more. In addition, the angle of inclination between the inner surface 231 of the via 23 and the top surface 21 of the conductive structure 2 is greater than about 90 degrees, for example, about 93 degrees or more, about 95 degrees or more, or about 98 degrees or more.

[0187] The via 23 may include via 263 of the second dielectric layer 26, a plurality of vias 203 of the first dielectric layer 20, and via 123 of the intermediate layer 12. In some embodiments, the via 23 extends through the bottommost first circuit layer 24 of the upper conductive structure 2 and terminates at or above the topmost circuit layer of the lower conductive structure 3 (e.g., the second upper circuit layer 38'). That is, the via 23 does not extend through the topmost circuit layer of the lower conductive structure 3 (e.g., the second upper circuit layer 38'). Figure 53 As shown, the via 23 gradually narrows downwards; that is, the size of the top portion of the via 23 is larger than the size of the bottom portion. Furthermore, the inner surface 1231 of the via 123 in the intermediate layer 12 is coplanar or aligned with the inner surface 2031 of the via 203 in the first dielectric layer 20 and the inner surface 2631 of the via 263 in the second dielectric layer 26. Therefore, the cross-sectional views of one side of the via 123 in the intermediate layer 12, the inner surface 2031 of the via 203 in the first dielectric layer 20, and the inner surface 2631 of the via 263 in the second dielectric layer 26 are substantially straight line segments. In other words, the cross-sectional views of one side of the inner surface 1231 of the via 123 in the intermediate layer 12, the inner surface 2031 of the via 203 in the first dielectric layer 20, and the inner surface 2631 of the via 263 in the second dielectric layer 26 can extend along the same substantially straight line. In other words, the inner surface of a single through-hole 23 can be substantially smooth or continuous. The maximum width of a single through-hole 23 (e.g., at the top portion) can be less than or equal to about 20 μm, such as about 20 μm, about 15 μm, or about 10 μm.

[0188] Subsequently, a metal layer is formed on the surface trace 17 and surface structure 16 by electroplating or other suitable techniques to form at least one upper through-hole 14 in the via 23, and an external circuit layer 28 (including a pad portion 281 and at least one surface trace 282) is formed to obtain Figure 1Wiring structure 1.

[0189] Since the upper conductive structure 2 and the lower conductive structure 3 are manufactured separately, the warpage of the upper conductive structure 2 is separate from the warpage of the lower conductive structure 3 and does not affect each other. In some embodiments, the warpage shape of the upper conductive structure 2 may be different from the warpage shape of the lower conductive structure 3. For example, the warpage shape of the upper conductive structure 2 may be convex, and the warpage shape of the lower conductive structure 3 may be concave. In some embodiments, the warpage shape of the upper conductive structure 2 may be the same as the warpage shape of the lower conductive structure 3; however, the warpage of the lower conductive structure 3 does not accumulate on the warpage of the upper conductive structure 2. Therefore, the yield of the wiring structure 1 can be improved. In addition, the lower conductive structure 3 and the upper conductive structure 2 can be tested separately before being joined together. Therefore, known good lower conductive structures 3 and known good upper conductive structures 2 can be selectively joined together. Defective (or unqualified) lower conductive structures 3 and defective (or unqualified) upper conductive structures 2 can be discarded. Therefore, the yield of the wiring structure 1 can be further improved.

[0190] In some embodiments, semiconductor chip 42 ( Figure 11 The upper conductive structure 2 is electrically connected and bonded to the outer circuit layer 28 of the upper conductive structure 2 via multiple first connecting elements 44 (e.g., solder bumps or other conductive bumps). Subsequently, the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3 are simultaneously separated to form... Figure 11 The package structure 4 shown is a wiring structure 1d and a semiconductor chip 42. Figure 11 The wiring structure 1d comprises a separate upper conductive structure 2d and a separate lower conductive structure 3d. That is, the lateral peripheral surface 27d of the upper conductive structure 2d, the lateral peripheral surface 33d of the lower conductive structure 3d, and the lateral peripheral surface of the intermediate layer 12 are substantially coplanar with each other. Subsequently, the second lower circuit layer 38a' of the lower conductive structure 3d is electrically connected and bonded to the substrate 46 (e.g., a motherboard, such as a PCB) via a plurality of second connecting elements 48 (e.g., solder bumps or other conductive bumps).

[0191] Figures 54 to 57 Methods for manufacturing wiring structures according to some embodiments of the present disclosure are shown. In some embodiments, the method is used to manufacture... Figure 10 The wiring structure 1c shown. The initial stage of the process described is related to... Figures 17 to 47 The stages shown are the same or similar. Figure 54 Depicting Figure 47 The stage following the stage described.

[0192] refer to Figure 54Simultaneously, a reference mark 43 and a bottom first circuit layer 24 are formed, and the two are on the same layer. Therefore, the reference mark 43 is provided on the bottom surface 22 of the upper conductive structure 2c and protrudes from it. Subsequently, the upper conductive structure 2c, the carrier 65, the release layer 66, and the conductive layer 67 are simultaneously cut or separated individually to form multiple strips 2'. Each strip 2' contains the upper conductive structure 2c, which is a strip structure. Subsequently, the strips 2' are tested. Alternatively, the upper conductive structure 2c can be tested before the cutting process.

[0193] refer to Figure 55 Simultaneously, a reference mark 45 and a second upper circuit layer 38' are formed, and the two are on the same layer. Therefore, the reference mark 45 is disposed on the top surface 31 of the lower conductive structure 3c and protrudes from it. The lower conductive structure 3c includes a plurality of strip regions 3'. Subsequently, the strip regions 3' are tested. Subsequently, an adhesive layer 12 is formed or applied to the top surface 31 of the lower conductive structure 3c.

[0194] refer to Figure 56 The upper conductive structure 2c is attached to the strip region 3' of the lower conductive structure 3c via the adhesive layer 12. The upper conductive structure 2c faces and is attached to the lower conductive structure 3c. During the attachment process, the reference mark 43 of the upper conductive structure 2c is aligned with the reference mark 45 of the lower conductive structure 3c to ensure the relative positions of the upper conductive structure 2c and the lower conductive structure 3c. In some embodiments, a known good strip 2' is selectively attached to a known good strip region 3' of the lower conductive structure 3c. For example, wiring structure 1c ( Figure 10The desired yield can be set to 80%. That is, (yield of the upper conductive structure 2c) * (yield of the strip region 3' of the lower conductive structure 3c) is set to be greater than or equal to 80%. If the yield of the upper conductive structure 2c (or strip 2') is less than the predetermined yield, for example, 80% (which is designated as a defective or non-conforming component), then the defective (or non-conforming) upper conductive structure 2c (or strip 2') is discarded. If the yield of the upper conductive structure 2c (or strip 2') is greater than or equal to the predetermined yield, for example, 80% (which is designated as a known good or conforming component), then a known good upper conductive structure 2c (or strip 2') can be used. In addition, if the yield of the strip region 3' of the lower conductive structure 3c is less than the predetermined yield, for example, 80% (which is designated as a defective or non-conforming component), then the defective (or non-conforming) strip region 3' is marked and will not be bonded to any strip 2'. If the yield of the strip region 3' of the lower conductive structure 3c is greater than or equal to a predetermined yield, for example, 80% (which is designated as a known good or qualified component), then a known good upper conductive structure 2c (or strip 2') can be bonded to the known good strip region 3' of the lower conductive structure 3c. It should be noted that an upper conductive structure 2c (or strip 2') with a yield of 80% will not be bonded to the strip region 3' of the lower conductive structure 3c with a yield of 80%, because the wiring structure 1c ( Figure 10 The yield obtained is 64%, which is lower than the expected yield of 80%. The upper conductive structure 2c (or strip 2') with 80% yield can be bonded to the strip region 3' of the lower conductive structure 3c with 100% yield; therefore, the wiring structure 1c ( Figure 10 The yield obtained can be 80%. Additionally, the upper conductive structure 2c (or strip 2') with a 90% yield can be bonded to the strip region 3' of the lower conductive structure 3c with a yield greater than 90%, because the wiring structure 1c ( Figure 10 The yield rate can be greater than 80%.

[0195] refer to Figure 57 The adhesive layer 12 is cured to form the intermediate layer 12. Subsequently, the carrier 65, release layer 66, and conductive layer 67 are removed. Then, at least one surface trace 17, surface structure 16, and through-hole 163 in the surface structure 16 are formed on the top surface 21 of the upper conductive structure 2. The described process is... Figure 57 The stages following the stage shown are similar to Figures 52 to 53 The stage shown. Subsequently, the lower conductive structure 3c and the intermediate layer 12 are cut along the strip region 3' to obtain Figure 10 Wiring structure 1c.

[0196] Figures 58 to 65Methods for manufacturing wiring structures according to some embodiments of the present disclosure are shown. In some embodiments, the method is used to manufacture... Figure 12 The wiring structure 1e is shown. The initial stage of the process described is related to... Figures 17 to 25 The stages shown are the same or similar. Figure 58 Depicting Figure 25 The stage following the stage described.

[0197] refer to Figures 58 to 60 A lower conductive structure 3e is provided. The lower conductive structure 3e is manufactured as follows. (See reference...) Figure 58 At least one via 303a is formed by drilling or other suitable techniques to extend through the first lower dielectric layer 30a to expose a portion of the first lower circuit layer 34a. It should be noted that no vias are formed in the first upper dielectric layer 30.

[0198] refer to Figure 59 A second lower circuit layer 38a is formed or disposed on the first lower dielectric layer 30a. Subsequently, three second lower dielectric layers 36a and two second lower circuit layers 38a' are formed or disposed on the first lower dielectric layer 30a.

[0199] refer to Figure 60 A bottom lower circuit layer 38a' is formed or disposed on the bottom second lower dielectric layer 36a to obtain a lower conductive structure 3e. In the lower conductive structure 3e, the top surface 31 of the lower conductive structure 3e is the top surface 301 of the first upper dielectric layer 30, which is substantially flat.

[0200] refer to Figures 61 to 64 An upper conductive structure 2e is provided. The upper conductive structure 2e is manufactured as follows. (See reference...) Figure 61 A carrier 65 is provided. A release layer 66 is coated on the bottom surface of the carrier 65. A conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 using PVD technology or other suitable techniques. Subsequently, a topmost circuit layer 24' is formed on the conductive layer 67. The topmost circuit layer 24' includes a pad portion 245 that acts as a mask (or sacrificial layer) during the laser drilling process. The pad portion 245 defines a via 2453, which is formed by photolithography (e.g., exposure and development) rather than drilling.

[0201] refer to Figure 62 The topmost first dielectric layer 20 is formed on the conductive layer 67 by coating technology or other suitable technology to cover the topmost circuit layer 24'.

[0202] refer to Figure 63 At least one via 204 is formed by exposure and development techniques or other suitable techniques to extend through the topmost first dielectric layer 20 to expose a portion of the conductive layer 67.

[0203] refer to Figure 64 Multiple first dielectric layers 20, multiple circuit layers 24, and multiple internal vias 25 are formed on the topmost first dielectric layer 20 to obtain the upper conductive structure 2e. For example... Figure 64 As shown, the bottom first dielectric layer 20 can cover the bottom circuit layer 24. Therefore, the entire bottom surface 22 of the upper conductive structure 2e (e.g., the bottom surface 202 of the bottom first dielectric layer 20) is substantially flat.

[0204] refer to Figure 65 An adhesive layer 12 is formed or applied to the top surface 31 of the lower conductive structure 3e.

[0205] refer to Figure 66 A laser beam 9 is applied to the top surface 21 of the pad portion 245 and the upper conductive structure 2e. A first portion 91 of the laser beam 9 is blocked by the solid portion of the pad portion 245, and a second portion 92 of the laser beam 9 passes through the through-hole 2453 of the pad portion 245 to form through-hole 23 in the upper conductive structure 2e and the intermediate layer 12 to expose the circuit layer (e.g., the first upper circuit layer 34) of the lower conductive structure 3e.

[0206] Subsequently, the subsequent stages of the described process are the same as or similar to those described. Figure 53 The stages shown in the document are for obtaining... Figure 12 Wiring structure 1e.

[0207] Figure 67 Methods for manufacturing wiring structures according to some embodiments of the present disclosure are shown. In some embodiments, the method is used to manufacture... Figure 15 The wiring structure shown is 1g. The initial stage of the process described is related to... Figures 17 to 53 The stages shown are the same or similar. Figure 67 Depicting Figure 53 The stage following the one described. (See reference) Figure 67 At least one via 40 is further formed by drilling (e.g., laser drilling) to extend through at least a portion of the lower conductive structure 3g and the intermediate layer 12 to expose the circuit layer of the upper conductive structure 2g (e.g., the first circuit layer 24a). In some embodiments, the via 40 extends through the topmost circuit layer of the lower conductive structure 3g (e.g., the second upper circuit layer 38') and terminates at or above the bottommost circuit layer 24a of the upper conductive structure 2g (e.g., the first circuit layer 24a). Figure 67As shown, the through-hole 40 gradually narrows upwards; that is, the size of the top portion of the through-hole 40 is smaller than the size of the bottom portion. Subsequently, a metal layer is formed in the through-hole 23 by electroplating or other suitable techniques to form at least one upper through-hole 14 in the through-hole 23, and a metal layer is formed in the through-hole 40 to form at least one lower through-hole 15 in the through-hole 40, in order to obtain... Figure 15 The wiring structure is 1g.

[0208] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” “below,” etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, the limitation being that the advantage of the embodiments of this disclosure is not affected by such arrangement.

[0209] As used herein, the terms “approximately,” “substantially,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to examples in which the event or situation clearly occurred and examples in which the event or situation is very close to occurring. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value can be considered “substantially” the same as or equal to the second numerical value. For example, "substantially" perpendicular might refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, if the maximum value of a characteristic or quantity is within a variation of less than or equal to +10% of the minimum value of the characteristic or quantity, such as less than or equal to +5%, less than or equal to +4%, less than or equal to +3%, less than or equal to ±2%, less than or equal to +1%, less than or equal to +0.5%, less than or equal to +0.1%, or less than or equal to +0.05%, then the characteristic or quantity can be considered "substantially" consistent.

[0210] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0211] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple indicators.

[0212] As used herein, the terms "conductive" and "electrically conductive" refer to the ability to conduct electric current. Conductive materials are generally those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10.4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0213] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0214] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Artistic representations in this disclosure may differ from actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A wiring structure comprising: An upper conductive structure includes multiple upper dielectric layers, multiple upper circuit layers in contact with the multiple upper dielectric layers, and multiple internal vias, wherein the multiple internal vias gradually narrow upwards, and wherein the material of the upper dielectric layers is transparent. A lower conductive structure includes multiple lower dielectric layers and multiple lower circuit layers in contact with the multiple lower dielectric layers, wherein the line spacing of the lower circuit layers of the lower conductive structure is greater than the line spacing of the upper circuit layers of the upper conductive structure. An intermediate layer, which bonds the upper conductive structure and the lower conductive structure together, wherein the material of the intermediate layer is transparent; Surface structure, which is adjacent to the top surface of the upper conductive structure; as well as At least one upper through-hole extends through the surface structure, the upper conductive structure, and the intermediate layer, and is electrically connected to and terminates at the topmost circuit layer of the plurality of lower circuit layers of the lower conductive structure, and the upper through-hole gradually narrows downward.

2. The wiring structure according to claim 1, wherein the material of the surface structure comprises metal.

3. The wiring structure according to claim 1, wherein the surface structure comprises a first portion and a second portion, the first portion being adjacent to the upper through-hole and disposed between the second portion and the upper through-hole, and the thickness of the first portion being less than the thickness of the second portion.

4. The wiring structure according to claim 3, wherein the first portion has a different thickness and the second portion has a substantially uniform thickness.

5. The wiring structure according to claim 1, wherein the surface structure comprises a first portion and a second portion, the first portion being adjacent to the upper through-hole and disposed between the second portion and the upper through-hole, and the surface roughness of the first portion being greater than the surface roughness of the second portion.

6. The wiring structure according to claim 1, further comprising at least one surface trace adjacent to the top surface of the upper conductive structure and electrically connected to the surface structure.

7. The wiring structure according to claim 6, wherein the surface traces are integrally formed with the surface structure.

8. The wiring structure according to claim 1, further comprising an external circuit layer, wherein the external circuit layer includes a pad portion disposed on the surface structure and the upper through-hole.

9. The wiring structure according to claim 8, wherein the pad portion is integrally formed with the upper through-hole.

10. The wiring structure according to claim 8, wherein the pad portion and the upper through-hole are an integral structure.

11. The wiring structure of claim 8, wherein the external circuit layer further comprises at least one trace portion electrically connected to the pad portion.

12. The wiring structure of claim 11, wherein the trace portion of the outer circuit layer is adjacent to the top surface of the upper conductive structure.

13. The wiring structure of claim 11, further comprising at least one surface trace adjacent to the top surface of the upper conductive structure and electrically connected to the surface structure, wherein the trace portion of the external circuit layer is disposed on the surface trace.

14. The wiring structure according to claim 1, wherein the width of the upper through-hole is less than or equal to 20 μm.

15. The wiring structure according to claim 1, wherein the upper through-hole comprises a plurality of segments, each segment comprising a top portion, a middle portion and a bottom portion, wherein the width of the middle portion is greater than the width of the top portion and the width of the middle portion is greater than the width of the bottom portion.

16. The wiring structure according to claim 1, wherein the upper through-hole comprises a plurality of segments, and in cross-sectional view, the sidewalls of each segment are curved.

17. The wiring structure of claim 1, wherein the upper through-hole extends through a via defined by the upper circuit layer of the upper conductive structure, and a portion of the upper dielectric layer extends into the space between the surrounding surface of the upper through-hole and the inner surface of the via of the upper circuit layer.

18. The wiring structure of claim 1, wherein the upper through-hole extends through a plurality of vias defined by the upper circuit layer of the upper conductive structure, and the vias of the upper circuit layer are offset from each other.

19. The wiring structure of claim 1, wherein some of the plurality of internal vias are disposed between two adjacent upper circuit layers in the upper circuit layer to electrically connect the two adjacent upper circuit layers in the upper circuit layer, and other of the plurality of internal vias are exposed from the top surface of the upper conductive structure.

20. The wiring structure according to claim 1, wherein the upper conductive structure is a coreless substrate and the lower conductive structure is a core substrate.

21. The wiring structure according to claim 20, wherein the bottom surface of the upper through-hole is located in the intermediate layer and is higher than the bottom surface of the intermediate layer.

22. The wiring structure of claim 20, wherein the upper through-hole does not extend through the lower conductive structure.

23. The wiring structure according to claim 1, further comprising: At least one lower through-hole extends through the lower conductive structure and the intermediate layer, and terminates at the bottommost circuit layer of the plurality of upper circuit layers of the upper conductive structure, and the lower through-hole gradually narrows upward.

24. The wiring structure of claim 23, wherein the upper conductive structure further includes at least one reference mark, wherein the lower conductive structure further includes at least one reference mark, wherein the reference mark of the upper conductive structure is aligned with the reference mark of the lower conductive structure.

25. The wiring structure of claim 24, wherein the reference mark of the upper conductive structure and the bottommost circuit layer of the upper conductive structure are on the same layer and formed simultaneously, wherein the reference mark of the lower conductive structure and the topmost circuit layer of the lower conductive structure are on the same layer and formed simultaneously.

26. The wiring structure according to claim 23, wherein the top surface of the lower through-hole is located in the intermediate layer and is lower than the top surface of the intermediate layer.

27. The wiring structure of claim 23, wherein the lower through-hole does not extend through the upper conductive structure.

28. The wiring structure according to claim 23, wherein the upper through-hole and the lower through-hole horizontally overlap in the intermediate layer.

29. A method for manufacturing a wiring structure, comprising: (a) A lower conductive structure is provided, comprising a plurality of lower dielectric layers, a plurality of lower circuit layers in contact with the plurality of lower dielectric layers, and at least one reference mark; (b) An upper conductive structure is formed on a carrier, wherein the upper conductive structure comprises a plurality of upper dielectric layers, a plurality of upper circuit layers in contact with the plurality of upper dielectric layers, a plurality of internal vias and at least one reference mark, wherein the plurality of internal vias gradually narrow toward the carrier, wherein the material of the upper dielectric layers is transparent, and wherein the line spacing of the lower circuit layer of the lower conductive structure is greater than the line spacing of the upper circuit layer of the upper conductive structure; (c) Attaching the upper conductive structure and the carrier to the lower conductive structure, wherein the reference mark of the upper conductive structure is aligned with the reference mark of the lower conductive structure; (d) After the upper conductive structure is attached to the lower conductive structure, the carrier is removed; (e) forming a surface structure on the top surface of the upper conductive structure; and (f) Forming at least one upper through-hole extending through the surface structure, the upper conductive structure and the intermediate layer, wherein the at least one upper through-hole is electrically connected to and terminates at the topmost circuit layer of the plurality of lower circuit layers of the lower conductive structure, and the upper through-hole gradually narrows downward.

30. The method of claim 29, wherein (b) comprises: (b1) Cut the upper conductive structure and the carrier.

31. The method of claim 29, wherein after (a), the method further comprises: (a1) Test the electrical properties of the lower conductive structure; as well as Wherein, following (b), the method further includes: (b1) Test the electrical properties of the upper conductive structure.

32. The method of claim 29, wherein in (c), the upper conductive structure is attached to the lower conductive structure by an adhesive layer.

33. The method of claim 29, wherein (e) comprises: (e1) A metal layer is formed on the top surface of the upper conductive structure; and (e2) The metal layer is patterned by photolithography to form the surface structure and the vias in the surface structure.

34. The method of claim 29, wherein (f) comprises: (f1) Forming at least one through-hole by drilling, extending through at least a portion of the upper conductive structure, wherein the through-hole exposes the topmost circuit layer of the lower conductive structure; and (f2) The upper through-hole is formed in the through hole to contact the topmost circuit layer of the lower conductive structure.

35. The method of claim 34, wherein in (e), the surface structure defines a through-hole; wherein (f1) comprises: (f11) A laser beam is applied to the surface structure and the upper conductive structure, wherein a first portion of the laser beam is blocked by a solid portion of the surface structure, and a second portion of the laser beam is drilled through the through-hole of the surface structure to extend through the through-hole of the upper conductive structure to expose the topmost circuit layer of the lower conductive structure.

36. The method of claim 35, wherein in (f11), a portion of the solid portion of the surface structure is removed by the first portion of the laser beam.

37. The method of claim 29, further comprising: (g) Forming at least one lower through-hole to electrically connect the upper conductive structure and the lower conductive structure, wherein the at least one lower through-hole extends through the lower conductive structure and the intermediate layer, wherein the at least one lower through-hole is electrically connected to and terminates at the bottommost circuit layer of the plurality of upper circuit layers of the upper conductive structure, and the lower through-hole gradually narrows upward.

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