Wiring structure, package structure and manufacturing method thereof

Abstract

The present disclosure relates to a wiring structure, a packaging structure and a method of manufacturing the wiring structure. The wiring structure includes an upper conductive structure, a lower conductive structure, an intermediate layer and at least one through via. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The through via extends through the upper conductive structure, the intermediate layer and the lower conductive structure.

Description

Technical Field

[0001] This disclosure relates to a wiring structure, a packaging structure, and a manufacturing method, and to a wiring structure comprising at least two conductive structures attached or bonded together by an intermediate layer, and a method for manufacturing said wiring structure. Background Technology

[0002] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips are integrated with an increasing number of electronic components to achieve improved electrical performance and additional functionality. Therefore, semiconductor chips have more input / output (I / O) connections. To manufacture semiconductor packages containing semiconductor chips with an increased number of I / O connections, the size of the circuit layers in the semiconductor substrate that carries the semiconductor chip may increase accordingly. Consequently, the thickness and warpage of the semiconductor substrate may increase, and the yield of the semiconductor substrate may decrease. Summary of the Invention

[0003] In some embodiments, a wiring structure includes: (a) an upper conductive structure comprising at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer; (b) a lower conductive structure comprising at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer; (c) an intermediate layer disposed between the upper conductive structure and the lower conductive structure, and bonding the upper conductive structure and the lower conductive structure together; and (d) at least one through-hole extending through the upper conductive structure, the intermediate layer, and the lower conductive structure.

[0004] In some embodiments, a wiring structure includes: (a) a low-density stack structure including at least one dielectric layer and at least one low-density circuit layer in contact with the dielectric layer; (b) a high-density stack structure disposed on the low-density stack structure, wherein the high-density stack structure includes at least one dielectric layer and at least one high-density circuit layer in contact with the dielectric layer of the high-density stack structure; and (c) at least one via extending through the low-density stack structure and the high-density stack structure.

[0005] In some embodiments, a method for manufacturing a wiring structure includes: (a) providing a lower conductive structure comprising at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (b) providing an upper conductive structure comprising at least one dielectric layer and at least one circuit layer in contact with the dielectric layer of the upper conductive structure; (c) attaching the upper conductive structure to the lower conductive structure; and (d) forming at least one through-hole extending through the upper conductive structure and the lower conductive structure. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of some embodiments of this disclosure can be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This shows a cross-sectional view of a wiring structure according to some embodiments of the present disclosure.

[0008] Figure 2 This shows a cross-sectional view of a wiring structure according to some embodiments of the present disclosure.

[0009] Figure 2A A top view showing an example of a reference mark of an upper conductive structure according to some embodiments of the present disclosure.

[0010] Figure 2B A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of the present disclosure.

[0011] Figure 2C show Figure 2A The reference mark of the upper conductive structure and Figure 2B A top view of a composite image of the reference marks on the lower conductive structure.

[0012] Figure 2D A top view showing an example of a reference mark of an upper conductive structure according to some embodiments of the present disclosure.

[0013] Figure 2E A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of the present disclosure.

[0014] Figure 2F show Figure 2D The reference mark of the upper conductive structure and Figure 2E A top view of a composite image of the reference marks on the lower conductive structure.

[0015] Figure 2G A top view showing an example of a reference mark of an upper conductive structure according to some embodiments of the present disclosure.

[0016] Figure 2H A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of the present disclosure.

[0017] Figure 2I show Figure 2G The reference mark of the upper conductive structure and Figure 2H A top view of a composite image of the reference marks on the lower conductive structure.

[0018] Figure 3 This shows a cross-sectional view of a wiring structure according to some embodiments of the present disclosure.

[0019] Figure 4 A cross-sectional view showing the bonding between the package structure and the substrate.

[0020] Figure 5 This shows a cross-sectional view of a wiring structure according to some embodiments of the present disclosure.

[0021] Figure 6 A cross-sectional view showing the bonding between the package structure and the substrate.

[0022] Figure 7 This shows a cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0023] Figure 8 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0024] Figure 9 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0025] Figure 10 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0026] Figure 11 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0027] Figure 12 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0028] Figure 13 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0029] Figure 14 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0030] Figure 15 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0031] Figure 16 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0032] Figure 17 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0033] Figure 18 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0034] Figure 19 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0035] Figure 20 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0036] Figure 21 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0037] Figure 22 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0038] Figure 23 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0039] Figure 24 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0040] Figure 25 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0041] Figure 26 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0042] Figure 27 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0043] Figure 28This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0044] Figure 29 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0045] Figure 30 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0046] Figure 31 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0047] Figure 32 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0048] Figure 33 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0049] Figure 34 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0050] Figure 35 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0051] Figure 36 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0052] Figure 37 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0053] Figure 38 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0054] Figure 39 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0055] Figure 40 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0056] Figure 41This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0057] Figure 42 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0058] Figure 43 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0059] Figure 44 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0060] Figure 45 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0061] Figure 46 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0062] Figure 47 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0063] Figure 48 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0064] Figure 49 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0065] Figure 50 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0066] Figure 51 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0067] Figure 52 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0068] Figure 53 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0069] Figure 54This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0070] Figure 55 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0071] Figure 56 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0072] Figure 57 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0073] Figure 58 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0074] Figure 59 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0075] Figure 60 This illustrates one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. Detailed Implementation

[0076] Throughout the drawings and detailed description, common reference numerals are used to indicate the same or similar components. Embodiments of this disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0077] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0078] To meet specifications for increased I / O counts, the number of dielectric layers on the substrate should be increased. In some comparative embodiments, the manufacturing process of the core substrate may include the following stages. First, a core is provided, having two copper foils disposed on both sides. Subsequently, multiple dielectric layers and multiple circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in a corresponding dielectric layer. Therefore, the core substrate may contain multiple stacked dielectric layers and multiple circuit layers embedded in the dielectric layers on both sides of the core. Since the line width / line space (L / S) of the circuit layers in such a core substrate can be greater than or equal to 10 micrometers (μm) / 10 μm, the number of dielectric layers in such a core substrate is relatively large. Although the manufacturing cost of such a core substrate is low, the manufacturing yield of the circuit layers and dielectric layers in such a core substrate is also low, thus the yield of such a core substrate is low. In addition, each dielectric layer is relatively thick, and therefore, this core substrate is relatively thick. In some comparative embodiments, if the package has 10,000 I / Os, then this core substrate may contain twelve circuit layers and dielectric layers. The manufacturing yield of one layer (containing one circuit layer and one dielectric layer) of such a core substrate can be 90%. Therefore, the yield of this core substrate can be (0.9). 12 =28.24%. Furthermore, the warpage of the twelve circuit and dielectric layers can accumulate, and therefore the top layers can exhibit severe warpage. Consequently, the yield of this core substrate can be further reduced.

[0079] To address the aforementioned issues, in some comparative embodiments, a coreless substrate is provided. The coreless substrate may comprise multiple dielectric layers and multiple fan-out circuit layers. In some embodiments, the fabrication process of the coreless substrate may include the following stages: First, a carrier is provided. Subsequently, multiple dielectric layers and multiple fan-out circuit layers are formed or stacked on the surface of the carrier. One fan-out circuit layer may be embedded in a corresponding dielectric layer. Subsequently, the carrier is removed. Thus, the coreless substrate may comprise multiple stacked dielectric layers and multiple fan-out circuit layers embedded within the dielectric layers. Since the linewidth / spacing (L / S) of the fan-out circuit layers in this coreless substrate can be less than or equal to 2 μm / 2 μm, the number of dielectric layers in this coreless substrate can be reduced. Furthermore, the fabrication yield of the fan-out circuit layers and dielectric layers in such a coreless substrate is high. For example, the fabrication yield of one layer (comprising one fan-out circuit layer and one dielectric layer) in this coreless substrate can be 99%. However, the fabrication cost of such a coreless substrate is relatively high.

[0080] At least some embodiments of this disclosure provide wiring structures with an advantageous trade-off between yield and manufacturing cost. In some embodiments, the wiring structure includes an upper conductive structure and a lower conductive structure bonded to the upper conductive structure via an intermediate layer. At least some embodiments of this disclosure further provide techniques for manufacturing the wiring structures.

[0081] Figure 1 A cross-sectional view of a wiring structure 1 according to some embodiments of the present disclosure is shown. The wiring structure 1 includes an upper conductive structure 2, a lower conductive structure 3, an intermediate layer 12, at least one through via 16, and an external circuit layer 28. The wiring structure 1 defines at least one through hole 17 extending through the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3.

[0082] The upper conductive structure 2 includes at least one dielectric layer (including, for example, two first dielectric layers 20 and one second dielectric layer 26) and at least one circuit layer (including, for example, three circuit layers 24 formed of metal, metal alloy or other conductive material) in contact with the dielectric layer (e.g., the first dielectric layer 20 and the second dielectric layer 26). In some embodiments, the upper conductive structure 2 may resemble a coreless substrate and may be of wafer type, panel type or strip type. The upper conductive structure 2 may also be referred to as a "stacked structure" or a "high-density conductive structure" or a "high-density stacked structure". The circuit layers of the upper conductive structure 2 (including, for example, three circuit layers 24) may also be referred to as "high-density circuit layers". In some embodiments, the density of circuit lines (including, for example, traces or pads) in the high-density circuit layer is greater than the density of circuit lines in the low-density circuit layer. That is, the count of circuit lines (including, for example, traces or pads) per unit area of ​​the high-density circuit layer is greater than the count of circuit lines per unit area of ​​the low-density circuit layer, for example, about 1.2 times or more, about 1.5 times or more, or about 2 times or more. Alternatively or in combination, the linewidth / spacing (L / S) of the high-density circuit layer is smaller than that of the low-density circuit layer, for example, about 90% or less, about 50% or less, or about 20% or less. Furthermore, a conductive structure containing a high-density circuit layer may be designated as a "high-density conductive structure," and a conductive structure containing a low-density circuit layer may be designated as a "low-density conductive structure."

[0083] The upper conductive structure 2 has a top surface 21 and a bottom surface 22 opposite to the top surface 21. For example... Figure 1As shown, the upper conductive structure 2 includes multiple dielectric layers (e.g., two first dielectric layers 20 and a second dielectric layer 26), multiple circuit layers (e.g., three circuit layers 24), and at least one inner via 25. The dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) are stacked on top of each other. For example, the second dielectric layer 26 is disposed on the first dielectric layer 20, and therefore, the second dielectric layer 26 is the topmost dielectric layer. In some embodiments, the material of the dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) is transparent and can be seen or detected by the human eye or a machine. That is, a mark positioned adjacent to the bottom surface 22 of the upper conductive structure 2 can be identified or detected by the human eye or a machine from the top surface 21 of the upper conductive structure 2. In some embodiments, the transparent material of the dielectric layers has a transmittance of at least about 60%, at least about 70%, or at least about 80% for wavelengths in the visible range (or other relevant wavelengths used to detect the mark).

[0084] Furthermore, each of the first dielectric layers 20 has a top surface 201 and a bottom surface 202 opposite to the top surface 201, and defines a via 203 having an inner surface 2031. The second dielectric layer 26 has a top surface 261 and a bottom surface 262 opposite to the top surface 261, and defines a via 263 having an inner surface 2631. The bottom surface 262 of the second dielectric layer 26 is disposed on and in contact with the top surface 201 of the first dielectric layer 20. Therefore, the top surface 21 of the upper conductive structure 2 is the top surface 261 of the second dielectric layer 26, and the bottom surface 22 of the upper conductive structure 2 is the bottom surface 202 of the bottommost first dielectric layer 20.

[0085] The circuit layer 24 may be a fan-out circuit layer or a redistribution layer (RDL), and the L / S ratio of the circuit layer 24 may be less than or equal to about 2 μm / about 2 μm, or less than or equal to about 1.8 μm / about 1.8 μm. Each circuit layer 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. In some embodiments, the circuit layer 24 is embedded in a corresponding first dielectric layer 20, and the top surface 241 of the circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. In some embodiments, the circuit layer 24 may include a seed layer 243 and a conductive metal material 244 disposed on the seed layer 243. The circuit layer 24 may include a first circuit layer 24 (e.g., a first high-density circuit layer) and a second circuit layer 24 (e.g., a second high-density circuit layer). The first circuit layer 24 is the bottommost circuit layer, also referred to as the "first high-density circuit layer". The second circuit layer 24 is disposed above the first circuit layer 24. The thickness of the first circuit layer 24 may be substantially the same as or greater than the thickness of the second circuit layer 24. For example, the thickness of the first circuit layer 24 may be approximately 4 μm, and the thickness of the second circuit layer 24 may be approximately 3 μm. Figure 1As shown, the bottommost circuit layer 24 (e.g., the first circuit layer 24) is disposed on the bottom surface 22 of the upper conductive structure 2 (e.g., the bottom surface 202 of the bottommost first dielectric layer 20) and protrudes from it.

[0086] The upper conductive structure 2 includes a plurality of internal vias 25. Some internal vias 25 are disposed between two adjacent circuit layers 24 to electrically connect the two circuit layers 24. Some internal vias 25 are exposed from the second dielectric layer 26 to electrically connect to the semiconductor chip 42. Figure 4 In some embodiments, each internal via 25 may include a seed layer 251 and a conductive metal material 252 disposed on the seed layer 251. In some embodiments, each internal via 25 and the corresponding circuit layer 24 may be integrally formed as a monolithic or one-piece structure. Each internal via 25 tapers upwardly in the direction from the bottom surface 22 of the upper conductive structure 2 toward the top surface 21. That is, the size (e.g., width) of the top portion of the internal via 25 is smaller than the size (e.g., width) of the bottom portion of the internal via 25 closer to the bottom surface 22. In some embodiments, the maximum width of the internal via 25 (e.g., at the bottom portion) may be less than or equal to about 25 μm, for example, about 25 μm, about 20 μm, about 15 μm, or about 10 μm.

[0087] The lower conductive structure 3 includes at least one dielectric layer (including, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) and at least one circuit layer (including, for example, a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a') contacting the dielectric layer (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower circuit layers 36a), which is formed of metal, metal alloy, or other conductive material. In some embodiments, the lower conductive structure 3 may be similar to a core substrate further including a core portion 37, and may be wafer type, panel type, or strip type. The lower conductive structure 3 may also be referred to as a "stacked structure," a "low-density conductive structure," or a "low-density stacked structure." The circuit layer of the lower conductive structure 3 (including, for example, a first upper circuit layer 34; two second upper circuit layers 38, 38'; a first lower circuit layer 34a; and two second lower circuit layers 38a, 38a') can also be referred to as a "low-density circuit layer". For example... Figure 1As shown, the lower conductive structure 3 has a top surface 31 and a bottom surface 32 opposite to the top surface 31. The lower conductive structure 3 includes multiple dielectric layers (e.g., a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a and a second lower dielectric layer 36a), multiple circuit layers (e.g., a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a and two second lower circuit layers 38a, 38a'), and at least one internal via (including, for example, multiple upper interconnect vias 35 and multiple lower interconnect vias 35a).

[0088] The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371, and defines a plurality of first through-holes 373 and a plurality of second through-holes 374 extending through the core portion 37. Interconnect vias 39 are disposed or formed in each of the first through-holes 373 for vertical connection. In some embodiments, each interconnect via 39 includes a base metal layer 391 and an insulating material 392. The base metal layer 391 is disposed or formed on the sidewall of the first through-hole 373 and defines a central through-hole. The insulating material 392 fills the central through-hole defined by the base metal layer 391. In some embodiments, the insulating material may be omitted from the interconnect via 39, and it may comprise a monolithic metal material filling the first through-hole 373. The second through-holes 374 have an inner surface 3741.

[0089] A first upper dielectric layer 30 is disposed on the top surface 371 of the core portion 37. The first upper dielectric layer 30 has a top surface 301 and a bottom surface 302 opposite to the top surface 301, and defines a through-hole 303 having an inner surface 3031. Therefore, the bottom surface 302 of the first upper dielectric layer 30 contacts the top surface 371 of the core portion 37. A second upper dielectric layer 36 is stacked or disposed on the first upper dielectric layer 30. The second upper dielectric layer 36 has a top surface 361 and a bottom surface 362 opposite to the top surface 361, and defines a through-hole 363 having an inner surface 3631. Therefore, the bottom surface 362 of the second upper dielectric layer 36 contacts the top surface 301 of the first upper dielectric layer 30, and the second upper dielectric layer 36 is the topmost dielectric layer. In addition, a first lower dielectric layer 30a is disposed on the bottom surface 372 of the core portion 37. The first lower dielectric layer 30a has a top surface 301a and a bottom surface 302a opposite to the top surface 301a, and defines a via 303a having an inner surface 3031a. Therefore, the top surface 301a of the first lower dielectric layer 30a contacts the bottom surface 372 of the core portion 37. A second lower dielectric layer 36a is stacked or disposed on the first lower dielectric layer 30a. The second lower dielectric layer 36a has a top surface 361a and a bottom surface 362a opposite to the top surface 361a, and defines a via 363a having an inner surface 3631a. Therefore, the top surface 361a of the second lower dielectric layer 36a contacts the bottom surface 302a of the first lower dielectric layer 30a, and the second lower dielectric layer 36a is the bottommost dielectric layer. Figure 1 As shown, the top surface 31 of the lower conductive structure 3 is the top surface 361 of the second upper dielectric layer 36, and the bottom surface 32 of the lower conductive structure 3 is the bottom surface 362a of the second lower dielectric layer 36a.

[0090] The thickness of each dielectric layer of the upper conductive structure 2 (e.g., the first dielectric layer 20 and the second dielectric layer 26) is less than or equal to about 40%, less than or equal to about 35%, or less than or equal to about 30% of the thickness of each dielectric layer of the lower conductive structure 3 (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a). For example, the thickness of each dielectric layer of the upper conductive structure 2 (e.g., the first dielectric layer 20 and the second dielectric layer 26) may be less than or equal to about 7 μm, and the thickness of each dielectric layer of the lower conductive structure 3 (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a) may be about 40 μm.

[0091] The L / S ratio of the first upper circuit layer 34 can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first upper circuit layer 34 can be greater than or equal to about five times the L / S ratio of the circuit layer 24 of the upper conductive structure 2. The first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In some embodiments, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37 and is covered by the first upper dielectric layer 30. The bottom surface 342 of the first upper circuit layer 34 contacts the top surface 371 of the core portion 37. In some embodiments, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be formed of copper foil (e.g., may constitute part of copper foil). The second metal layer 344 is disposed on the first metal layer 343 and may be an electroplated copper layer. A third metal layer 345 is disposed on the second metal layer 344, and may be another electroplated copper layer. In some embodiments, the third metal layer 345 may be omitted.

[0092] The L / S ratio of the second upper circuit layer 38 can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second upper circuit layer 38 can be substantially equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the circuit layer 24 of the upper conductive structure 2. The second upper circuit layer 38 has a top surface 381 and a bottom surface 382 opposite to the top surface 381. In some embodiments, the second upper circuit layer 38 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 and is covered by the second upper dielectric layer 36. The bottom surface 382 of the second upper circuit layer 38 can contact the top surface 301 of the first upper dielectric layer 30. In some embodiments, the second upper circuit layer 38 is electrically connected to the first upper circuit layer 34 through an upper interconnect via 35. That is, the upper interconnect via 35 is disposed between the second upper circuit layer 38 and the first upper circuit layer 34 to electrically connect the second upper circuit layer 38 and the first upper circuit layer 34. In some embodiments, the second upper circuit layer 38 and the upper interconnect via 35 are integrally formed as a single-piece structure. Each upper interconnect via 35 gradually narrows downwards from the top surface 31 of the lower conductive structure 3 toward the bottom surface 32.

[0093] Additionally, in some embodiments, the second upper circuit layer 38' is disposed on and protrudes from the top surface 361 of the second upper dielectric layer 36. In some embodiments, the second upper circuit layer 38 is electrically connected to the second upper circuit layer 38' via an upper interconnect via 35. That is, the upper interconnect via 35 is disposed between the second upper circuit layers 38 and 38' to electrically connect the second upper circuit layers 38 and 38'. In some embodiments, the second upper circuit layer 38' and the upper interconnect via 35 are integrally formed as a single-piece structure. In some embodiments, the second upper circuit layer 38' is the topmost circuit layer of the lower conductive structure 3.

[0094] The L / S ratio of the first lower circuit layer 34a can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first lower circuit layer 34a can be greater than or equal to about five times the L / S ratio of the circuit layer 24 of the upper conductive structure 2. The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In some embodiments, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37 and is covered by a first lower dielectric layer 30a. The top surface 341a of the first lower circuit layer 34a contacts the bottom surface 372 of the core portion 37. In some embodiments, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be formed of copper foil. A second metal layer 344a is disposed on the first metal layer 343a, and may be an electroplated copper layer. A third metal layer 345a is disposed on the second metal layer 344a, and may be another electroplated copper layer. In some embodiments, the third metal layer 345a may be omitted.

[0095] The L / S ratio of the second lower circuit layer 38a can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second lower circuit layer 38a can be substantially equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the circuit layer 24 of the upper conductive structure 2. The second lower circuit layer 38a has a top surface 381a and a bottom surface 382a opposite to the top surface 381a. In some embodiments, the second lower circuit layer 38a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a and is covered by the second lower dielectric layer 36a. The top surface 381a of the second lower circuit layer 38a contacts the bottom surface 302a of the first lower dielectric layer 30a. In some embodiments, the second lower circuit layer 38a is electrically connected to the first lower circuit layer 34a through a lower interconnect via 35a. That is, the lower interconnect via 35a is disposed between the second lower circuit layer 38a and the first lower circuit layer 34a for electrically connecting the second lower circuit layer 38a and the first lower circuit layer 34a. In some embodiments, the second lower circuit layer 38a and the lower interconnect via 35a are integrally formed or a single-piece structure. Each lower interconnect via 35a gradually narrows upward along the direction from the bottom surface 32 of the lower conductive structure 3 toward the top surface 31.

[0096] In some embodiments, a second lower circuit layer 38a' is disposed on and protrudes from the bottom surface 362a of the second lower dielectric layer 36a. In some embodiments, the second lower circuit layer 38a' is electrically connected to the second lower circuit layer 38a through a lower interconnect via 35a. That is, the lower interconnect via 35a is disposed between the second lower circuit layers 38a and 38a' to electrically connect the second lower circuit layers 38a and 38a'. In some embodiments, the second lower circuit layer 38a' and the lower interconnect via 35a are integrally formed as a single-piece structure. In some embodiments, the second lower circuit layer 38a' is the bottommost low-density circuit layer of the lower conductive structure 3.

[0097] In some embodiments, each interconnect via 39 is electrically connected to the first upper circuit layer 34 and the first lower circuit layer 34a. The base metal layer 391 of the interconnect via 39, the second metal layer 344 of the first upper circuit layer 34, and the second metal layer 344a of the first lower circuit layer 34a can be integrally formed as a single-piece structure.

[0098] Additionally, an outer circuit layer 28 (e.g., a top low-density circuit layer) is disposed on and protrudes from the top surface 21 of the upper conductive structure 2 (e.g., the top surface 261 of the second dielectric layer 26). The L / S ratio of the outer circuit layer 28 may be greater than or equal to the L / S ratio of the circuit layer 24. In some embodiments, the L / S ratio of the outer circuit layer 28 may be substantially equal to the L / S ratio of the second lower circuit layer 38a'. Figure 1As illustrated in the embodiments, the horizontally extending or connected circuit layers are omitted in the second dielectric layer 26.

[0099] An intermediate layer 12 is inserted or disposed between the upper conductive structure 2 and the lower conductive structure 3 to bond the upper conductive structure 2 and the lower conductive structure 3 together. That is, the intermediate layer 12 adheres to the bottom surface 22 of the upper conductive structure 2 and the top surface 31 of the lower conductive structure 3. In some embodiments, the intermediate layer 12 may be an adhesive layer cured from an adhesive material (e.g., a cured adhesive material, such as an adhesive polymer). The intermediate layer 12 has a top surface 121 and a bottom surface 122 opposite to the top surface 121, and defines at least one through-hole 124 having an inner surface 1241. The top surface 121 of the intermediate layer 12 contacts the bottom surface 22 of the upper conductive structure 2 (that is, the bottom surface 22 of the upper conductive structure 2 is attached to the top surface 121 of the intermediate layer 12), and the bottom surface 122 of the intermediate layer 12 contacts the top surface 31 of the lower conductive structure 3. Therefore, the bottommost first circuit layer 24 (e.g., first circuit layer 24) of the upper conductive structure 2 and the topmost circuit layer 38' (e.g., second upper circuit layer 38') of the lower conductive structure 3 are embedded in the intermediate layer 12. In some embodiments, the bonding force between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2 is greater than the bonding force between the dielectric layer (e.g., the bottommost first dielectric layer 20) of the upper conductive structure 2 and the intermediate layer 12. The surface roughness of the boundary between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2 is greater than the surface roughness of the boundary between the dielectric layer (e.g., the bottommost first dielectric layer 20) of the upper conductive structure 2 and the intermediate layer 12, for example, in terms of root mean squared surface roughness, about 1.1 times or more, about 1.3 times or more, or about 1.5 times or more.

[0100] In some embodiments, the material of the intermediate layer 12 is transparent and can be seen through by the human eye or a machine. That is, markings positioned adjacent to the top surface 31 of the lower conductive structure 3 can be identified or detected by the human eye or a machine from the top surface 21 of the upper conductive structure 2. Through-holes 124 extend through the intermediate layer 12. In some embodiments, the through-holes 124 of the intermediate layer 12 may extend through the topmost circuit layer of the lower conductive structure 3 (e.g., the second upper circuit layer 38') and the bottommost circuit layer 24 of the upper conductive structure 2.

[0101] like Figure 1As shown, the via 263 of the second dielectric layer 26, the via 203 of the first dielectric layer 20, the via 124 of the intermediate layer 12, the via 363 of the second upper dielectric layer 36, the via 303 of the first upper dielectric layer 30, the second via 374 of the core portion 37, the via 303a of the first lower dielectric layer 30a, and the via 363a of the second lower dielectric layer 36a are aligned with and connected to each other. Therefore, the inner surface 2631 of the via 263 of the second dielectric layer 26, the inner surface 2031 of the via 203 of the first dielectric layer 20, the inner surface 1241 of the via 124 of the intermediate layer 12, the inner surface 3631 of the via 363, the inner surface 3031 of the via 303, the inner surface 3741 of the second via 374, the inner surface 3031a of the via 303a and the inner surface 3631a of the via 363 are coplanar with each other or aligned with each other. In some embodiments, the inner surface 2631 of the via 263 of the second dielectric layer 26, the inner surface 2031 of the via 203 of the first dielectric layer 20, the inner surface 1241 of the via 124 of the intermediate layer 12, the inner surface 3631 of the via 363, the inner surface 3031 of the via 303, the inner surface 3741 of the second via 374, the inner surface 3031a of the via 303a and the inner surface 3631a of the via 363 may be curved or straight surfaces, and are a portion of the inner surface 171 of a single continuous via 17 for accommodating the through hole 16. The vias 263 of the second dielectric layer 26, 203 of the first dielectric layer 20, 124 of the intermediate layer 12, 363 of the second upper dielectric layer 36, 303 of the first upper dielectric layer 30, 374 of the core portion 37, 303a of the first lower dielectric layer 30a, and 363a of the second lower dielectric layer 36a are configured to form or define a single via 17. Therefore, the single via 17 includes the vias 263 of the second dielectric layer 26, 203 of the first dielectric layer 20, 124 of the intermediate layer 12, 363 of the second upper dielectric layer 36, 303 of the first upper dielectric layer 30, 374 of the core portion 37, 303a of the first lower dielectric layer 30a, and 363a of the second lower dielectric layer 36a.

[0102] like Figure 1As shown, the cross-sectional view of one side of the inner surface 2631 of through hole 263, the inner surface 2031 of through hole 203, the inner surface 1241 of through hole 124 of intermediate layer 12, the inner surface 3631 of through hole 363, the inner surface 3031 of through hole 303, the inner surface 3741 of second through hole 374, the inner surface 3031a of through hole 303a, and the inner surface 3631a of through hole 363a is a line segment that is essentially a straight line. That is, cross-sectional views of one side of the inner surface 2631 of through-hole 263, the inner surface 2031 of through-hole 203, the inner surface 1241 of through-hole 124 of intermediate layer 12, the inner surface 3631 of through-hole 363, the inner surface 3031 of through-hole 303, the inner surface 3741 of the second through-hole 374, the inner surface 3031a of through-hole 303a, and the inner surface 3631a of through-hole 363a can extend along the same substantially straight line. A single through-hole 17 extends through the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3 (including the second lower circuit layer 38a'); that is, the single through-hole 17 extends from the top surface 21 of the upper conductive structure 2 to the bottom surface 32 of the lower conductive structure 3. The maximum width of the single through-hole 17 can be from about 100 μm to about 1000 μm. In some embodiments, the single through-hole 17 can be formed by mechanical drilling. Therefore, via 17 may not gradually narrow, and the inner surface 171 of via 17 may be substantially perpendicular to the top surface 21 of the upper conductive structure 2 and / or the bottom surface 32 of the lower conductive structure 3. That is, the dimensions of via 263 in the second dielectric layer 26, via 203 in the first dielectric layer 20, via 124 in the intermediate layer 12, via 363 in the second upper dielectric layer 36, via 303 in the first upper dielectric layer 30, the second via 374 in the core portion 37, the via 303a in the first lower dielectric layer 30a, and the via 363a in the second lower dielectric layer 36a are substantially equal to each other.

[0103] Each through-hole 16 is formed or disposed in a corresponding through-hole 17 and is made of metal, metal alloy, or other conductive material. Therefore, the through-hole 16 extends through the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3. For example... Figure 1As shown, the through-hole 16 extends through and contacts the bottommost circuit layer 24 of the upper conductive structure 2, the topmost circuit layer (e.g., the second upper circuit layer 38') of the lower conductive structure 3, and the bottommost circuit layer (e.g., the second lower circuit layer 38a') of the lower conductive structure 3. In some embodiments, the low-density circuit layer (e.g., the second upper circuit layer 38') of the low-density conductive structure (e.g., the lower conductive structure 3) is electrically connected to the high-density circuit layer (e.g., the first circuit layer 24) of the high-density conductive structure (e.g., the upper conductive structure 2) only through the through-hole 16. The length of the through-hole 16 (along the longitudinal axis) is greater than the thickness of the low-density conductive structure (e.g., the lower conductive structure 3) or the thickness of the high-density conductive structure (e.g., the upper conductive structure 2). In some embodiments, the through-hole 16 is an integral structure or a single-piece structure with a homogeneous material composition, and the surrounding surface 163 of the through-hole 16 is a substantially continuous surface without boundaries. The through-hole 16 and the outer circuit layer 28 may be integrally formed.

[0104] like Figure 1 As shown, the upper conductive structure 2 includes a high-density region 41 and a low-density region 47. In some embodiments, the density of circuit lines (including traces or pads) in the high-density region 41 is greater than the density of circuit lines in the low-density region 47. That is, the count of circuit lines (including traces or pads) per unit area in the high-density region 41 is greater than the count of circuit lines per unit area in the low-density region 47. Alternatively or in combination, the L / S ratio of the circuit layers in the high-density region 41 is less than the L / S ratio of the circuit layers in the low-density region 47. Additionally, a via 16 is disposed in the low-density region 47 of the high-density conductive structure (e.g., the upper conductive structure 2). In some embodiments, the high-density region 41 may be a chip bonding region. Furthermore, the size of the end portion (e.g., the bottom portion) of the via 16 is substantially equal to the size of the other end portion (e.g., the top portion) of the via 16. The via 16 may have a substantially uniform width (e.g., diameter).

[0105] like Figure 1As shown in the embodiments illustrated, the wiring structure 1 is a combination of an upper conductive structure 2 and a lower conductive structure 3. The circuit layer 24 of the upper conductive structure 2 has fine pitch, high yield, and low thickness; and the circuit layers of the lower conductive structure 3 (e.g., a first upper circuit layer 34, second upper circuit layers 38, 38', a first lower circuit layer 34a, and second lower circuit layers 38a, 38a') have low manufacturing cost. Therefore, the wiring structure 1 offers a favorable trade-off between yield and manufacturing cost, and has a relatively low thickness. In some embodiments, if the package has 10,000 I / Os, the wiring structure 1 comprises three circuit layers 24 of the upper conductive structure 2 and six circuit layers of the lower conductive structure 3 (e.g., a first upper circuit layer 34, second upper circuit layers 38, 38', a first lower circuit layer 34a, and second lower circuit layers 38a, 38a'). The manufacturing yield of one layer of the circuit layer 24 of the upper conductive structure 2 can be 99%, and the manufacturing yield of one layer of the circuit layer of the lower conductive structure 3 (e.g., the first upper circuit layer 34, the second upper circuit layers 38, 38', the first lower circuit layer 34a, and the second lower circuit layers 38a, 38a') can be 90%. Therefore, the yield of the wiring structure 1 can be improved. Furthermore, the warpage of the upper conductive structure 2 and the warpage of the lower conductive structure 3 are separate and do not affect each other. In some embodiments, the warpage shape of the upper conductive structure 2 may be different from the warpage shape of the lower conductive structure 3. For example, the warpage shape of the upper conductive structure 2 may be convex, and the warpage shape of the lower conductive structure 3 may be concave. In some embodiments, the warpage shape of the upper conductive structure 2 may be the same as the warpage shape of the lower conductive structure 3; however, the warpage of the lower conductive structure 3 does not accumulate on the warpage of the upper conductive structure 2. Therefore, the yield of the wiring structure 1 can be further improved.

[0106] Furthermore, during the manufacturing process, the lower conductive structure 3 and the upper conductive structure 2 can be tested separately before being joined together. Therefore, known good lower conductive structures 3 and known good upper conductive structures 2 can be selectively joined together. Defective (or unqualified) lower conductive structures 3 and defective (or unqualified) upper conductive structures 2 can be discarded. Therefore, the yield of the wiring structure 1 can be further improved.

[0107] In some embodiments, the via 16 may be a conductive via for vertical electrical connection. Furthermore, the via 16 may be a thermal via for heat dissipation. That is, the via 16 may be a combination of an electrical connection path and a heat dissipation path. Additionally, the via 16 is a rigid structure, which can reduce the warpage of the wiring structure 1.

[0108] Figure 2A cross-sectional view of a wiring structure 1a according to some embodiments of the present disclosure is shown. The wiring structure 1a is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2a and the lower conductive structure 3a. For example... Figure 2 As shown, both the upper conductive structure 2a and the lower conductive structure 3a are strip structures. Therefore, the wiring structure 1a is a strip structure. In some embodiments, the lower conductive structure 3a may be a panel structure carrying multiple strip upper conductive structures 2a. Therefore, the wiring structure 1a is a panel structure. From a top view, the length of the upper conductive structure 2a (e.g., about 240 mm) is greater than the width of the upper conductive structure 2a (e.g., about 95 mm). Additionally, from a top view, the length of the lower conductive structure 3a is greater than the width of the lower conductive structure 3a. Furthermore, the lateral peripheral surface 27 of the upper conductive structure 2a is not coplanar with the lateral peripheral surface 33 of the lower conductive structure 3a (e.g., it is recessed inward or otherwise offset from it). In some embodiments, during the manufacturing process, both the lower conductive structure 3a and the upper conductive structure 2a may be known good strip structures. Alternatively, the upper conductive structure 2a may be a known good strip structure, and the lower conductive structure 3a may be a known good panel structure. Therefore, the yield of wiring structure 1a can be further improved.

[0109] like Figure 2 As shown, the upper conductive structure 2a includes at least one fiducial mark 43 at its corner, and the lower conductive structure 3a includes at least one fiducial mark 45 at its corner. During the manufacturing process, the fiducial mark 43 of the upper conductive structure 2a is aligned with the fiducial mark 45 of the lower conductive structure 3a to ensure the relative positions of the upper conductive structure 2a and the lower conductive structure 3a. In one embodiment, the fiducial mark 43 of the upper conductive structure 2a is disposed on and protrudes from the bottom surface 22 of the upper conductive structure 2a (e.g., the bottom surface 202 of the bottommost first dielectric layer 20). The fiducial mark 43 and the bottommost circuit layer 24 may be on the same layer or partially on the same layer, and may be formed simultaneously. In addition, the fiducial mark 45 of the lower conductive structure 3a is disposed on and protrudes from the top surface 31 of the lower conductive structure 3a (e.g., the top surface 361 of the second upper dielectric layer 36). The reference mark 45 and the second upper circuit layer 38' can be on the same layer or partially on the same layer, and can be formed simultaneously.

[0110] Figure 2A A top view showing an example of a reference mark 43a of the upper conductive structure 2a according to some embodiments of the present disclosure. The reference mark 43a of the upper conductive structure 2a has a continuous cross shape.

[0111] Figure 2B A top view showing an example of a reference mark 45a of the lower conductive structure 3a according to some embodiments of the present disclosure. The reference mark 45a of the lower conductive structure 3a comprises four square segments at the four corners.

[0112] Figure 2C show Figure 2A The reference mark 43a of the upper conductive structure 2a and Figure 2B The combined image is a top view of the reference mark 45a of the lower conductive structure 3a. When the upper conductive structure 2a is precisely aligned with the lower conductive structure 3a, the combined image shows the complete reference mark 43a and the complete reference mark 45a, as shown. Figure 2C As shown. That is to say, from the top view, datum mark 43a does not cover or overlap datum mark 45a.

[0113] Figure 2D A top view showing an example of a reference mark 43b of the upper conductive structure 2a according to some embodiments of the present disclosure. The reference mark 43b of the upper conductive structure 2a is a continuously inverted "L" shape.

[0114] Figure 2E A top view showing an example of a reference mark 45b of a lower conductive structure 3a according to some embodiments of the present disclosure. The reference mark 45b of the lower conductive structure 3a has a continuously inverted "L" shape that is substantially the same as the reference mark 43b of the upper conductive structure 2a.

[0115] Figure 2F show Figure 2D The reference mark 43b of the upper conductive structure 2a and Figure 2E The combined image is a top view of the reference mark 45b of the lower conductive structure 3a. When the upper conductive structure 2a and the lower conductive structure 3a are precisely aligned, the combined image only shows the reference mark 43b of the upper conductive structure 2a, as shown. Figure 2F As shown. That is to say, from the top view, datum mark 43b completely covers or overlaps datum mark 45b.

[0116] Figure 2G A top view showing an example of a reference mark 43c of an upper conductive structure 2a according to some embodiments of the present disclosure. The reference mark 43c of the upper conductive structure 2a has a continuous circular shape.

[0117] Figure 2H A top view showing an example of a reference mark 45c of a lower conductive structure 3a according to some embodiments of the present disclosure. The reference mark 45c of the lower conductive structure 3a has a continuous circular shape that is larger than that of the reference mark 43c of the upper conductive structure 2a.

[0118] Figure 2I show Figure 2G The reference mark 43c of the upper conductive structure 2a and Figure 2H A top view of the combined image of the reference mark 45c of the lower conductive structure 3a. When the upper conductive structure 2a and the lower conductive structure 3a are precisely aligned, the combined image shows two concentric circles, as shown. Figure 2I As shown. That is, the reference mark 43c is set at the center of the reference mark 45c.

[0119] Figure 3 A cross-sectional view of a wiring structure 1b according to some embodiments of the present disclosure is shown. The wiring structure 1b is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the through-hole 18 and the external circuit layer 28'. For example... Figure 3 As shown, Figure 1 The guide hole 16 is replaced by the guide hole 18, and Figure 1 The external circuit layer 28 is replaced by an external circuit layer 28'. In some embodiments, the via 18 includes a conductive layer 181 (e.g., a metal layer) and an insulating material 182. The conductive layer 181 is disposed or formed on the inner surface 171 of the via 17 and defines a central via. The insulating material 182 fills the central via defined by the conductive layer 181. The conductive layer 181 and the external circuit layer 28' may be formed simultaneously and integrally.

[0120] Figure 4 This shows a cross-sectional view of the bonding between the package structure 4 and the substrate 46 according to some embodiments. The package structure 4 includes a wiring structure 1c, a semiconductor chip 42, a plurality of first connection elements 44, a plurality of second connection elements 48, and a heat sink 80. Figure 4 The wiring structure 1c is similar to Figure 2The wiring structure 1a shown differs in the structure of the upper conductive structure 2c and the lower conductive structure 3c. Both the upper conductive structure 2c and the lower conductive structure 3c are dies and can be individually divided simultaneously. Therefore, wiring structure 1c is a unitary structure. That is, the lateral peripheral surface 27c of the upper conductive structure 2c, the lateral peripheral surface 33c of the lower conductive structure 3c, and the lateral peripheral surface of the intermediate layer 12 are substantially coplanar with each other. The semiconductor chip 42 has an active surface 421 and a back surface 422 opposite to the active surface 421. The active surface 421 of the semiconductor chip 42 is electrically connected and bonded to the external circuit layer 28 of the upper conductive structure 2c via a first connecting element 44 (e.g., solder bump or other conductive bump). The second lower circuit layer 38a' of the lower conductive structure 3c is electrically connected and bonded to the substrate 46 (e.g., motherboard, such as a printed circuit board, PCB) via a second connecting element 48 (e.g., solder bump or other conductive bump).

[0121] The heat sink 80 covers the semiconductor chip 42, and a portion of the heat sink 80 is thermally connected to the through-hole 16. For example... Figure 4 As shown, an underfill 491 is included to cover and protect the first connection element 44 and the external circuit layer 28. The inner surface of the heat sink 80 is adhered to the back surface 422 of the semiconductor chip 42 via an adhesive layer 492. The bottom portion of the sidewall of the heat sink 80 is attached to the via 16 or a portion of the external circuit layer 28 integrally formed with the via 16. During operation of the semiconductor chip 42, there are two paths (including a first path 90 and a second path 91) to dissipate the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42) to the substrate 46. Taking the first path 90 as an example, a portion of the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42) is transferred upward through the body of the semiconductor chip 42, the back surface 422 of the semiconductor chip 42, and the adhesive layer 492 to the heat sink 80, then horizontally, and subsequently downward in the heat sink 80 to enter the via 16. Taking the second path 91 as an example, another portion of the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42) is transported downwards through the first connecting element 44, the external circuit layer 28, and the stacked internal via 25, and then horizontally transported in the bottommost circuit layer 24 of the upper conductive structure 2c to enter the through-via 16. Finally, the heat in the through-via 16 will be transported downwards to the substrate 46. Since there are two paths (including the first path 90 and the second path 91) to dissipate the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42), the heat will be dissipated effectively and rapidly.

[0122] Figure 5 A cross-sectional view of a wiring structure 1d according to some embodiments of the present disclosure is shown. The wiring structure 1d is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2d and the lower conductive structure 3d. In the upper conductive structure 2d, the second dielectric layer 26 is replaced by the topmost first dielectric layer 20. Furthermore, the upper conductive structure 2d may further include a topmost circuit layer 24'. The topmost circuit layer 24' may omit the seed layer and can be electrically connected to the lower circuit layer 24 via an internal via 25. The top surface of the topmost circuit layer 24' may be substantially coplanar with the top surface 21 of the upper conductive structure 2d (e.g., the top surface 201 of the topmost first dielectric layer 20). Therefore, the top surface of the topmost circuit layer 24' can be exposed from the top surface 21 of the upper conductive structure 2d (e.g., the top surface 201 of the topmost first dielectric layer 20). Additionally, the bottommost first dielectric layer 20 may cover the bottommost circuit layer 24. Therefore, the entire bottom surface 22 of the upper conductive structure 2d (e.g., the bottom surface 202 of the bottommost first dielectric layer 20) is substantially flat.

[0123] In the lower conductive structure 3d, the second upper dielectric layer 36 and the second upper circuit layers 38, 38' are omitted. Therefore, the top surface 31 of the lower conductive structure 3d is the top surface 301 of the first upper dielectric layer 30, which is substantially flat. In addition, it further includes two additional second lower dielectric layers 36a and two additional second lower circuit layers 38a'.

[0124] The intermediate layer 12 is adhered to the bottom surface 22 of the upper conductive structure 2d and the top surface 31 of the lower conductive structure 3d. Therefore, the entire top surface 121 and the entire bottom surface 122 of the intermediate layer 12 are substantially flat. The intermediate layer 12 does not contain or contact any horizontally extending or connected circuit layers. That is, no horizontally extending or connected circuit layers are disposed or embedded in the intermediate layer 12.

[0125] Figure 6 This shows a cross-sectional view of the bonding between a package structure 4a and a substrate 46 according to some embodiments. The package structure 4a includes a wiring structure 1e, a semiconductor chip 42, a plurality of first connection elements 44, a plurality of second connection elements 48, and a heat sink 80. Figure 6 The wiring structure 1e is similar to Figure 5The wiring structure 1d shown differs in the structure of the upper conductive structure 2e and the lower conductive structure 3e. The two ends of the through-hole 16 are exposed from the top surface 21 of the upper conductive structure 2e (e.g., a high-density conductive structure) and the bottom surface 32 of the lower conductive structure 3e (e.g., a low-density conductive structure), respectively. Both the upper conductive structure 2e and the lower conductive structure 3e are dies and can be simultaneously isolated. Therefore, the wiring structure 1e is a unitary structure. That is, the lateral peripheral surfaces 27e of the upper conductive structure 2e, 33e of the lower conductive structure 3e, and the lateral peripheral surfaces of the intermediate layer 12 are substantially coplanar. The semiconductor chip 42 is electrically connected and bonded to the topmost circuit layer 24 of the upper conductive structure 2e via a first connecting element 44 (e.g., solder bumps or other conductive bumps). The bottommost second lower circuit layer 38a' of the lower conductive structure 3e is electrically connected and bonded to the substrate 46 (e.g., motherboard, such as PCB) via a second connecting element 48 (e.g., solder bump or other conductive bump).

[0126] The heat sink 80 covers the semiconductor chip 42, and a portion of the heat sink 80 is thermally connected to the through-hole 16. For example... Figure 6 As shown, a bottom filler 491 is included to cover and protect the first connecting element 44. The inner surface of the heat sink 80 is adhered to the back surface 422 of the semiconductor chip 42 via an adhesive layer 492. The bottom portion of the sidewall of the heat sink 80 is attached to the through-hole 16. During operation of the semiconductor chip 42, the heat dissipation path between the semiconductor chip 42 and the substrate 46 is... Figure 4 The heat dissipation paths are essentially the same.

[0127] Figure 7 This diagram shows a cross-sectional view of a package structure 4b according to some embodiments of the present disclosure. The package structure 4b includes a wiring structure 1f, a semiconductor chip 42, a plurality of first connection elements 44, and at least one passive component 49. Figure 7 The wiring structure 1f is similar to Figure 4The wiring structure 1c shown differs in the structure of the upper conductive structure 2f and the lower conductive structure 3f. In the upper conductive structure 2f, one of the circuit layers 24 may include one or more traces (e.g., high-density traces) and a ground plane 245 for grounding. In some embodiments, a plurality of internal vias 25 may be stacked on top of each other to form a columnar structure, and the plurality of columnar structures may be arranged parallel to each other or laterally adjacent to each other to form a via wall (or fence structure). The upper conductive structure 2f can provide signal transmission between semiconductor chips 42, between semiconductor chips 42 and passive components 49, and / or between passive components 49. Such transmitted signals may not include electrical signals. For example, the upper conductive structure 2f can provide excellent stability for the transmission of radio frequency (RF) signals and high-speed digital signals. High-speed digital signals and RF / analog modulation signals may be arranged on the same layer or different layers. To prevent interference from high-speed digital signals to RF / analog modulation signals, two layouts can be designed for two different scenarios. In the first scenario, where the high-speed digital signal and the RF / analog modulation signal are arranged on the same layer, the via wall can achieve signal isolation. That is, the via wall can be placed between the high-speed digital signal and the RF / analog modulation signal. In the second scenario, where the high-speed digital signal and the RF / analog modulation signal are arranged on different layers, the ground plane 245 can achieve signal isolation. That is, the ground plane 245 can be placed between the high-speed digital signal and the RF / analog modulation signal.

[0128] In the lower conductive structure 3f, the second upper circuit layer 38', the second upper dielectric layer 36, the second lower circuit layer 38a', and the second lower dielectric layer 36a are omitted. Additionally, one of the circuit layers (e.g., the second upper circuit layer 38) may include one or more traces (e.g., low-density traces) and a ground plane 385 for grounding. The lower conductive structure 3f provides power signal transmission between semiconductor chips 42, between semiconductor chips 42 and passive components 49, and / or between passive components 49. It should be noted that the circuit layers (e.g., upper circuit layers 34, 38 and lower circuit layers 34a, 38a) have low DC impedance and low parasitic capacitance. Furthermore, the ground plane 385 provides signal isolation between the lower conductive structure 3f and the upper conductive structure 2f. Additionally, the plurality of through-holes 16 disposed parallel to or laterally adjacent to each other prevent signal leakage when they are positioned adjacent to the lateral surrounding surface of the wiring structure 1f.

[0129] Figures 8 to 41Methods for manufacturing wiring structures according to some embodiments of the present disclosure are shown. In some embodiments, the method is used to manufacture... Figure 1 The wiring structure 1 shown, and / or Figure 4 The encapsulation structure shown is 4.

[0130] refer to Figures 8 to 27 A lower conductive structure 3 is provided. The lower conductive structure 3 is manufactured as follows. (See reference) Figure 8 A core portion 37 is provided, having a top copper foil 50 and a bottom copper foil 52. The core portion 37 can be of wafer type, panel type, or strip type. The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371. The top copper foil 50 is disposed on the top surface 371 of the core portion 37, and the bottom copper foil 52 is disposed on the bottom surface 372 of the core portion 37.

[0131] refer to Figure 9 Multiple first through holes 373 are formed by drilling techniques (such as laser drilling or mechanical drilling) or other suitable techniques to extend through the core portion 37, the top copper foil 50 and the bottom copper foil 52.

[0132] refer to Figure 10 A second metal layer 54 is formed or disposed on the sidewalls of the top copper foil 50, the bottom copper foil 52, and the first through hole 373 by electroplating or other suitable techniques. A portion of the second metal layer 54 on the sidewall of each first through hole 373 defines a central through hole.

[0133] refer to Figure 11 An insulating material 392 is provided to fill the central through-hole defined by the second metal layer 54.

[0134] refer to Figure 12 The top third metal layer 56 and the bottom third metal layer 56a are formed or disposed on the second metal layer 54 by electroplating or other suitable techniques. The third metal layers 56 and 56a cover the insulating material 392.

[0135] refer to Figure 13 A top photoresist layer 57 is formed or disposed on the top third metal layer 56, and a bottom photoresist layer 57a is formed or disposed on the bottom third metal layer 56a. Subsequently, the photoresist layers 57 and 57a are patterned by exposure and development.

[0136] refer to Figure 14The portions of the top copper foil 50, second metal layer 54, and top third metal layer 56 not covered by the top photoresist layer 57 are removed using etching or other suitable techniques. The portions of the top copper foil 50, second metal layer 54, and top third metal layer 56 covered by the top photoresist layer 57 are retained to form the first upper circuit layer 34. Simultaneously, the portions of the bottom copper foil 52, second metal layer 54, and bottom third metal layer 56a not covered by the bottom photoresist layer 57a are removed using etching or other suitable techniques. The portions of the bottom copper foil 52, second metal layer 54, and bottom third metal layer 56a covered by the bottom photoresist layer 57a are retained to form the first lower circuit layer 34a. Meanwhile, the portions of the second metal layer 54 and insulating material 392 disposed in the first via 373 form interconnect vias 39. Figure 14 As shown, the first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In some embodiments, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37. The bottom surface 342 of the first upper circuit layer 34 contacts the top surface 371 of the core portion 37. In some embodiments, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be formed from a portion of the top copper foil 50. The second metal layer 344 is disposed on the first metal layer 343 and may be an electroplated copper layer formed from the second metal layer 54. The third metal layer 345 is disposed on the second metal layer 344 and may be another electroplated copper layer formed from the top third metal layer 56.

[0137] The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In some embodiments, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37. The top surface 341a of the first lower circuit layer 34a contacts the bottom surface 372 of the core portion 37. In some embodiments, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a, and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be formed from a portion of the bottom copper foil 52. The second metal layer 344a is disposed on the first metal layer 343a and may be an electroplated copper layer formed from the second metal layer 54. The third metal layer 345a is disposed on the second metal layer 344a and may be another electroplated copper layer formed from the bottom third metal layer 56a. The interconnect via 39 includes a base metal layer 391 formed from the second metal layer 54 and an insulating material 392. In some embodiments, the interconnect via 39 may comprise a monolithic metal material filling the first via 373. The interconnect via 39 electrically connects the first upper circuit layer 34 and the first lower circuit layer 34a.

[0138] refer to Figure 15 The top photoresist layer 57 and the bottom photoresist layer 57a are removed by stripping techniques or other suitable techniques.

[0139] refer to Figure 16 A first upper dielectric layer 30 is formed or disposed on the top surface 371 of the core portion 37 using lamination technology or other suitable techniques, to cover the top surface 371 of the core portion 37 and the first upper circuit layer 34. Simultaneously, a first lower dielectric layer 30a is formed or disposed on the bottom surface 372 of the core portion 37 using lamination technology or other suitable techniques, to cover the bottom surface 372 of the core portion 37 and the first lower circuit layer 34a.

[0140] refer to Figure 17 At least one via 303 is formed by drilling or other suitable techniques to extend through the first upper dielectric layer 30 to expose a portion of the first upper circuit layer 34. Simultaneously, at least one via 303a is formed by drilling or other suitable techniques to extend through the first lower dielectric layer 30a to expose a portion of the first lower circuit layer 34a.

[0141] refer to Figure 18 A top metal layer 58 is formed on the first upper dielectric layer 30 and in the via 303 using electroplating or other suitable techniques to form an upper interconnect via 35. Simultaneously, a bottom metal layer 60 is formed on the first lower dielectric layer 30a and in the via 303a using electroplating or other suitable techniques to form a lower interconnect via 35a. Figure 18 As shown, the upper interconnecting via 35 gradually narrows downwards, and the lower interconnecting via 35a gradually narrows upwards.

[0142] refer to Figure 19 A top photoresist layer 59 is formed or disposed on a top metal layer 58, and a bottom photoresist layer 59a is formed or disposed on a bottom metal layer 60. Subsequently, the photoresist layers 59 and 59a are patterned by exposure and development.

[0143] refer to Figure 20 The portion of the top metal layer 58 not covered by the top photoresist layer 59 is removed using etching or other suitable techniques. The portion of the top metal layer 58 covered by the top photoresist layer 59 is retained to form the second upper circuit layer 38. Simultaneously, the portion of the bottom metal layer 60 not covered by the bottom photoresist layer 59a is removed using etching or other suitable techniques. The portion of the bottom metal layer 60 covered by the bottom photoresist layer 59a is retained to form the second lower circuit layer 38a.

[0144] refer to Figure 21 The top photoresist layer 59 and the bottom photoresist layer 59a are removed by stripping techniques or other suitable techniques.

[0145] refer to Figure 22 A second upper dielectric layer 36 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 using lamination technology or other suitable techniques, to cover the top surface 301 of the first upper dielectric layer 30 and the second upper circuit layer 38. Simultaneously, a second lower dielectric layer 36a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a using lamination technology or other suitable techniques, to cover the bottom surface 302a of the first lower dielectric layer 30a and the second lower circuit layer 38a.

[0146] refer to Figure 23 At least one via 363 is formed by drilling or other suitable techniques to extend through the second upper dielectric layer 36 to expose a portion of the second upper circuit layer 38. Simultaneously, at least one via 363a is formed by drilling or other suitable techniques to extend through the second lower dielectric layer 36a to expose a portion of the second lower circuit layer 38a.

[0147] refer to Figure 24 A top metal layer 62 is formed on the second upper dielectric layer 36 and in the via 363 by electroplating or other suitable techniques to form an upper interconnect via 35. Simultaneously, a bottom metal layer 64 is formed on the second lower dielectric layer 36a and in the via 363a by electroplating or other suitable techniques to form a lower interconnect via 35a.

[0148] refer to Figure 25 A top photoresist layer 63 is formed or disposed on a top metal layer 62, and a bottom photoresist layer 63a is formed or disposed on a bottom metal layer 64. Subsequently, the photoresist layers 63 and 63a are patterned by exposure and development.

[0149] refer to Figure 26 The portion of the top metal layer 62 not covered by the top photoresist layer 63 is removed using etching or other suitable techniques. The portion of the top metal layer 62 covered by the top photoresist layer 63 is retained to form the second upper circuit layer 38'. Simultaneously, the portion of the bottom metal layer 64 not covered by the bottom photoresist layer 63a is removed using etching or other suitable techniques. The portion of the bottom metal layer 64 covered by the bottom photoresist layer 63a is retained to form the second lower circuit layer 38a'.

[0150] refer to Figure 27The top photoresist layer 63 and the bottom photoresist layer 63a are removed using a stripping technique or other suitable technique. Simultaneously, the lower conductive structure 3 is formed, and dielectric layers (including a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) are cured. At least one of the circuit layers (including, for example, a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a') is in contact with at least one of the dielectric layers (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a). Subsequently, the electrical characteristics (e.g., open circuit / short circuit) of the lower conductive structure 3 are tested.

[0151] refer to Figures 28 to 38 An upper conductive structure 2 is provided. The upper conductive structure 2 is manufactured as follows. (See reference...) Figure 28 A carrier 65 is provided. The carrier 65 can be a glass carrier and can be of wafer type, panel type or strip type.

[0152] refer to Figure 29 A release layer 66 is coated on the bottom surface of the carrier 65.

[0153] refer to Figure 30 A conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 by physical vapor deposition (PVD) or other suitable techniques.

[0154] refer to Figure 31 A second dielectric layer 26 is formed on the conductive layer 67 by coating technology or other suitable technology.

[0155] refer to Figure 32 At least one via 264 is formed by exposure and development techniques or other suitable techniques to extend through the second dielectric layer 26 to expose a portion of the conductive layer 67.

[0156] refer to Figure 33 A seed layer 68 is formed on the bottom surface 262 of the second dielectric layer 26 and in the via 264 using PVD technology or other suitable techniques.

[0157] refer to Figure 34 A photoresist layer 69 is formed on the seed layer 68. Subsequently, the photoresist layer 69 is patterned using exposure and development techniques or other suitable techniques to expose portions of the seed layer 68. The photoresist layer 69 defines a plurality of openings 691. At least one opening 691 of the photoresist layer 69 corresponds to and is aligned with a via 264 of the second dielectric layer 26.

[0158] refer to Figure 35Conductive material 70 (e.g., metallic material) is applied to the opening 691 of the photoresist layer 69 and the seed layer 68 by electroplating or other suitable techniques.

[0159] refer to Figure 36 The photoresist layer 69 is removed by stripping or other suitable techniques.

[0160] refer to Figure 37 The portion of the seed layer 68 not covered by the conductive material 70 is removed by etching or other suitable techniques. Simultaneously, a circuit layer 24 and at least one internal via 25 are formed. The circuit layer 24 may be a fan-out circuit layer or an RDL, and the L / S ratio of the circuit layer 24 may be less than or equal to about 2 μm / about 2 μm, or less than or equal to about 1.8 μm / about 1.8 μm. The circuit layer 24 is disposed on the bottom surface 262 of the second dielectric layer 26. In some embodiments, the circuit layer 24 may include a seed layer 243 formed by the seed layer 68 and a conductive material 244 disposed on the seed layer 243 and formed by the conductive material 70. The internal via 25 is disposed in the via 264 of the second dielectric layer 26. In some embodiments, the internal via 25 may include a seed layer 251 and a conductive material 252 disposed on the seed layer 251. The internal via 25 gradually narrows upwards.

[0161] refer to Figure 38 By repeating Figures 31 to 37 In this stage, multiple first dielectric layers 20 and multiple circuit layers 24 are formed. In some embodiments, each circuit layer 24 is embedded in a corresponding first dielectric layer 20, and the top surface 241 of the circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. At this time, an upper conductive structure 2 is formed, and dielectric layers (including first dielectric layer 20 and second dielectric layer 26) are cured. At least one of the circuit layers (including, for example, three circuit layers 24) is in contact with at least one of the dielectric layers (e.g., first dielectric layer 20 and second dielectric layer 26). Subsequently, the electrical characteristics (e.g., open circuit / short circuit) of the upper conductive structure 2 are tested.

[0162] refer to Figure 39 An adhesive layer 12 is formed or applied to the top surface 31 of the lower conductive structure 3.

[0163] refer to Figure 40An upper conductive structure 2 is attached to a lower conductive structure 3 via an adhesive layer 12. In some embodiments, a known good upper conductive structure 2 is attached to a known good lower conductive structure 3. Subsequently, the adhesive layer 12 is cured to form an intermediate layer 12. In some embodiments, the upper conductive structure 2 may be pressed onto the lower conductive structure 3. Therefore, the thickness of the intermediate layer 12 is determined by the gap between the upper conductive structure 2 and the lower conductive structure 3. The top surface 121 of the intermediate layer 12 contacts the bottom surface 22 of the upper conductive structure 2 (that is, the bottom surface 22 of the upper conductive structure 2 is attached to the top surface 121 of the intermediate layer 12), and the bottom surface 122 of the intermediate layer 12 contacts the top surface 31 of the lower conductive structure 3. Therefore, the bottommost circuit layer 24 of the upper conductive structure 2 and the second upper circuit layer 38' of the lower conductive structure 3 are embedded in the intermediate layer 12. In some embodiments, the bonding force between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2 is greater than the bonding force between the dielectric layer of the upper conductive structure 2 (e.g., the bottom first dielectric layer 20) and the intermediate layer 12. The surface roughness of the boundary between the two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2 is greater than the surface roughness of the boundary between the dielectric layer of the upper conductive structure 2 (e.g., the bottom first dielectric layer 20) and the intermediate layer 12.

[0164] refer to Figure 41 Remove the carrier 65, release layer 66 and conductive layer 67 to expose a portion of the internal via 25.

[0165] refer to Figure 42 At least one through-hole 17 is formed by drilling (e.g., mechanical drilling or laser drilling) to extend through the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3. The through-hole 17 may include through-holes 263 in the second dielectric layer 26, multiple through-holes 203 in the first dielectric layer 20, through-holes 124 in the intermediate layer 12, through-holes 363 in the second upper dielectric layer 36, through-holes 303 in the first upper dielectric layer 30, a second through-hole 374 in the core portion 37, and through-holes 303a in the first lower dielectric layer 30a and the second lower dielectric layer 36a. Figure 42 As shown, the through hole 17 may not gradually narrow; that is, the size of the top portion of the through hole 17 is substantially equal to the size of the bottom portion of the through hole 17.

[0166] Furthermore, the inner surfaces 2631 of through hole 263, 2031 of through hole 203, 1241 of through hole 124, 3631 of through hole 363, 3031 of through hole 303, 3741 of second through hole 374, 3031a of through hole 303a, and 3631a of through hole 363a are coplanar or aligned with each other. Therefore, the cross-sectional view of one side of the inner surfaces 2631 of through hole 263, 2031 of through hole 203, 1241 of through hole 124, 3631 of through hole 363, 3031 of through hole 303, 3741 of second through hole 374, 3031a of through hole 303a, and 3631a of through hole 363a is a substantially straight line segment. That is, the cross-sectional views of one side of the inner surface 2631 of through hole 263, the inner surface 2031 of through hole 203, the inner surface 1241 of through hole 124, the inner surface 3631 of through hole 363, the inner surface 3031 of through hole 303, the inner surface 3741 of the second through hole 374, the inner surface 3031a of through hole 303a, and the inner surface 3631a of through hole 363a can extend along the same substantially straight line. That is, the inner surface 171 of a single through hole 17 can be a substantially smooth or continuous surface.

[0167] refer to Figure 43 A metal layer 72 is formed on the top surface 21 of the upper conductive structure 2 and in the through hole 17 by electroplating or other suitable techniques, so as to form at least one through hole 16 in the through hole 17.

[0168] refer to Figure 44 A top photoresist layer 73 is formed or disposed on the metal layer 72, and a bottom photoresist layer 73a is formed or disposed on the bottom surface 32 of the lower conductive structure 3. Subsequently, the top photoresist layer 73 is patterned by exposure and development techniques or other suitable techniques.

[0169] refer to Figure 45 The portion of the metal layer 72 not covered by the top photoresist layer 73 is removed using etching or other suitable techniques. The portion of the metal layer 72 covered by the top photoresist layer 73 is retained to form the external circuit layer 28. Subsequently, the top photoresist layer 73 and the bottom photoresist layer 73a are removed using stripping or other suitable techniques to obtain... Figure 1Wiring structure 1. Since the upper conductive structure 2 and the lower conductive structure 3 are manufactured separately, the warpage of the upper conductive structure 2 is separate from the warpage of the lower conductive structure 3 and does not affect each other. In some embodiments, the warpage shape of the upper conductive structure 2 may differ from the warpage shape of the lower conductive structure 3. For example, the warpage shape of the upper conductive structure 2 may be convex, and the warpage shape of the lower conductive structure 3 may be concave. In some embodiments, the warpage shape of the upper conductive structure 2 may be the same as the warpage shape of the lower conductive structure 3; however, the warpage of the lower conductive structure 3 does not accumulate on the warpage of the upper conductive structure 2. Therefore, the yield of wiring structure 1 can be improved. Furthermore, the lower conductive structure 3 and the upper conductive structure 2 can be tested separately before being joined together. Therefore, known good lower conductive structures 3 and known good upper conductive structures 2 can be selectively joined together. Defective (or unqualified) lower conductive structures 3 and defective (or unqualified) upper conductive structures 2 can be discarded. Therefore, the yield of wiring structure 1 can be further improved.

[0170] In some embodiments, semiconductor chip 42 ( Figure 4 The upper conductive structure 2 is electrically connected and bonded to the outer circuit layer 28 of the upper conductive structure 2 via multiple first connecting elements 44 (e.g., solder bumps or other conductive bumps). Subsequently, the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3 are simultaneously separated to form... Figure 4 The package structure 4 shown is a wiring structure 1c and a semiconductor chip 42. Figure 4 The wiring structure 1c includes a separate upper conductive structure 2b and a separate lower conductive structure 3c. That is, the lateral peripheral surface 27c of the upper conductive structure 2c, the lateral peripheral surface 33c of the lower conductive structure 3c, and the lateral peripheral surface of the intermediate layer 12 are substantially coplanar with each other. Subsequently, the second lower circuit layer 38a' of the lower conductive structure 3c is electrically connected and bonded to the substrate 46 (e.g., motherboard, such as PCB) through a plurality of second connecting elements 48 (e.g., solder bumps or other conductive bumps).

[0171] Additionally, a heat sink 80 is provided to cover the semiconductor chip 42. A portion of the heat sink 80 is thermally connected to the through-hole 16. Figure 4 As shown, a bottom filler 491 is formed to cover and protect the first connection element 44 and the external circuit layer 28. The inner surface of the heat sink 80 is adhered to the back surface 422 of the semiconductor chip 42 via an adhesive layer 492. The bottom portion of the sidewall of the heat sink 80 is attached to the through-hole 16 or a portion of the external circuit layer 28 integrally formed with the through-hole 16.

[0172] Figures 46 to 49Methods for manufacturing wiring structures according to some embodiments of the present disclosure are shown. In some embodiments, the method is used to manufacture... Figure 2 The wiring structure 1a is shown. The initial stage of the process described is related to... Figures 8 to 38 The stages shown are the same or similar. Figure 46 Depicting Figure 38 The stage following the stage described.

[0173] refer to Figure 46 Simultaneously, a reference mark 43 and a bottom first circuit layer 24 are formed, and the two are on the same layer. Therefore, the reference mark 43 is provided on the bottom surface 22 of the upper conductive structure 2a and protrudes from it. Subsequently, the upper conductive structure 2a, the carrier 65, the release layer 66, and the conductive layer 67 are cut or separated simultaneously to form a plurality of strips 2'. Each strip 2' contains the upper conductive structure 2a, which is a strip structure. Subsequently, the strips 2' are tested. Alternatively, the upper conductive structure 2a can be tested before the cutting process.

[0174] refer to Figure 47 Simultaneously, a reference mark 45 and a second upper circuit layer 38' are formed, and the two are on the same layer. Therefore, the reference mark 45 is disposed on the top surface 31 of the lower conductive structure 3a and protrudes from it. The lower conductive structure 3a includes a plurality of strip regions 3'. Subsequently, the strip regions 3' are tested. Subsequently, an adhesive layer 12 is formed or applied to the top surface 31 of the lower conductive structure 3a.

[0175] refer to Figure 48 The upper conductive structure 2a is attached to the strip region 3' of the lower conductive structure 3a via the adhesive layer 12. The upper conductive structure 2a faces and is attached to the lower conductive structure 3a. During the attachment process, the reference mark 43 of the upper conductive structure 2a is aligned with the reference mark 45 of the lower conductive structure 3a to ensure the relative positions of the upper conductive structure 2a and the lower conductive structure 3a. In some embodiments, a known good strip 2' is selectively attached to a known good strip region 3' of the lower conductive structure 3a. For example, wiring structure 1a ( Figure 2The desired yield can be set to 80%. That is, (yield of the upper conductive structure 2a) * (yield of the strip region 3' of the lower conductive structure 3a) is set to be greater than or equal to 80%. If the yield of the upper conductive structure 2a (or strip 2') is less than the predetermined yield, for example, 80% (which is designated as a defective or non-conforming component), then the defective (or non-conforming) upper conductive structure 2a (or strip 2') is discarded. If the yield of the upper conductive structure 2a (or strip 2') is greater than or equal to the predetermined yield, for example, 80% (which is designated as a known good or conforming component), then a known good upper conductive structure 2a (or strip 2') can be used. In addition, if the yield of the strip region 3' of the lower conductive structure 3a is less than the predetermined yield, for example, 80% (which is designated as a defective or non-conforming component), then the defective (or non-conforming) strip region 3' is marked and will not be bonded to any strip 2'. If the yield of the strip region 3' of the lower conductive structure 3a is greater than or equal to a predetermined yield, for example, 80% (which is designated as a known good or qualified component), then a known good upper conductive structure 2a (or strip 2') can be bonded to the known good strip region 3' of the lower conductive structure 3a. It should be noted that an upper conductive structure 2a (or strip 2') with a yield of 80% will not be bonded to a strip region 3' of the lower conductive structure 3a with a yield of 80%, because the wiring structure 1a ( Figure 2 The yield obtained is 64%, which is lower than the expected yield of 80%. The upper conductive structure 2a (or strip 2') with 80% yield can be bonded to the strip region 3' of the lower conductive structure 3a with 100% yield; therefore, the wiring structure 1a ( Figure 2 The yield obtained can be 80%. Additionally, the upper conductive structure 2a (or strip 2') with a 90% yield can be bonded to the strip region 3' of the lower conductive structure 3a with a yield greater than 90%, because the wiring structure 1a ( Figure 2 The yield rate can be greater than 80%.

[0176] refer to Figure 49 The adhesive layer 12 is cured to form the intermediate layer 12. Subsequently, the carrier 65, release layer 66, and conductive layer 67 are removed. The described process is as follows: Figure 49 The stages following the shown stage are similar to Figures 42 to 45 The stage shown. Subsequently, the lower conductive structure 3a and the intermediate layer 12 are cut along the strip region 3' to obtain Figure 2 Wiring structure 1a.

[0177] Figures 50 to 60 Methods for manufacturing wiring structures according to some embodiments of the present disclosure are shown. In some embodiments, the method is used to manufacture... Figure 5 The wiring structure 1d shown, and / or Figure 6The packaging structure 4a is shown. The initial stage of the process described is related to... Figures 8 to 16 The stages shown are the same or similar. Figure 50 Depicting Figure 8 The stage following the stage described.

[0178] refer to Figures 50 to 52 A lower conductive structure 3D is provided. The lower conductive structure 3D is manufactured as follows. (Reference) Figure 50 At least one via 303a is formed by drilling or other suitable techniques to extend through the first lower dielectric layer 30a to expose a portion of the first lower circuit layer 34a. It should be noted that no vias are formed in the first upper dielectric layer 30.

[0179] refer to Figure 51 A second lower circuit layer 38a is formed or disposed on the first lower dielectric layer 30a. Subsequently, three second lower dielectric layers 36a and two second lower circuit layers 38a' are formed or disposed on the first lower dielectric layer 30a.

[0180] refer to Figure 52 A bottom lower circuit layer 38a' is formed or disposed on the bottom second lower dielectric layer 36a to obtain a lower conductive structure 3d. In the lower conductive structure 3d, the top surface 31 of the lower conductive structure 3d is the top surface 301 of the first upper dielectric layer 30, which is substantially flat.

[0181] refer to Figures 53 to 56 A 2d upper conductive structure is provided. The 2d upper conductive structure is manufactured as follows. (Reference) Figure 53 A carrier 65 is provided. A release layer 66 is coated on the bottom surface of the carrier 65. A conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 using PVD technology or other suitable techniques. Subsequently, a topmost circuit layer 24' is formed on the conductive layer 67.

[0182] refer to Figure 54 The topmost first dielectric layer 20 is formed on the conductive layer 67 by coating technology or other suitable technology to cover the topmost circuit layer 24'.

[0183] refer to Figure 55 At least one via 204 is formed by exposure and development techniques or other suitable techniques to extend through the topmost first dielectric layer 20 to expose a portion of the conductive layer 67.

[0184] refer to Figure 56 Multiple first dielectric layers 20, multiple circuit layers 24, and multiple internal vias 25 are formed on the topmost first dielectric layer 20 to obtain an upper conductive structure 2d. For example... Figure 56As shown, the bottom first dielectric layer 20 can cover the bottom circuit layer 24. Therefore, the entire bottom surface 22 of the upper conductive structure 2d (e.g., the bottom surface 202 of the bottom first dielectric layer 20) is substantially flat.

[0185] refer to Figure 57 An adhesive layer 12 is formed or applied to the top surface 31 of the lower conductive structure 3d.

[0186] refer to Figure 58 The upper conductive structure 2d is attached to the lower conductive structure 3d via an adhesive layer 12. Subsequently, the adhesive layer 12 is cured to form an intermediate layer 12. The intermediate layer 12 adheres to the bottom surface 22 of the upper conductive structure 2d and the top surface 31 of the lower conductive structure 3d. Therefore, the entire top surface 121 and the entire bottom surface 122 of the intermediate layer 12 are substantially flat. The intermediate layer 12 does not contain or contact any horizontally extending or connected circuit layers. That is, no horizontally extending or connected circuit layers are disposed or embedded in the intermediate layer 12.

[0187] refer to Figure 59 Remove the carrier 65, release layer 66, and conductive layer 67 to expose a portion of the internal via 25, the topmost circuit layer 24', and a portion of the topmost first dielectric layer 20. The top surface 241 of the topmost circuit layer 24' may be substantially coplanar with the top surface 201 of the topmost first dielectric layer 20.

[0188] refer to Figure 60 At least one through hole 17 is formed by drilling (e.g., mechanical drilling or laser drilling) to extend through the upper conductive structure 2d, the intermediate layer 12 and the lower conductive structure 3d.

[0189] Subsequently, the subsequent stages of the described process are the same as or similar to those described. Figures 43 to 45 The stages shown in the document are for obtaining... Figure 5 Wiring structure 1d.

[0190] In some embodiments, semiconductor chip 42 ( Figure 6 The upper conductive structure 2d is electrically connected and bonded to the topmost circuit layer 24' of the upper conductive structure 2d via multiple first connecting elements 44 (e.g., solder bumps or other conductive bumps). Subsequently, the upper conductive structure 2d, the intermediate layer 12, and the lower conductive structure 3d are simultaneously separated to form... Figure 6 The packaging structure 4a is shown. Figure 6The wiring structure 1e includes a separate upper conductive structure 2e and a separate lower conductive structure 3e. Subsequently, a second lower circuit layer 38a' of the lower conductive structure 3e is electrically connected and bonded to a substrate 46 (e.g., a motherboard, such as a PCB) via a plurality of second connecting elements 48 (e.g., solder bumps or other conductive bumps). Additionally, a heat sink 80 is provided to cover the semiconductor chip 42. A portion of the heat sink 80 is thermally connected to a through-hole 16.

[0191] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” “below,” etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, the limitation being that the advantage of the embodiments of this disclosure is not affected by such arrangement.

[0192] As used herein, the terms “approximately,” “substantially,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to examples in which the event or situation clearly occurred and examples in which the event or situation is very close to occurring. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value can be considered “substantially” the same as or equal to the second numerical value. For example, “substantially” vertical may refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0193] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0194] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple indicators.

[0195] As used herein, the terms "conductive" and "electrically conductive" refer to the ability to conduct electric current. Conductive materials are generally those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0196] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0197] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Artistic representations in this disclosure may differ from actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A wiring structure comprising: An upper conductive structure includes multiple upper dielectric layers, multiple upper circuit layers in contact with the multiple upper dielectric layers, multiple internal vias, and at least one reference mark, wherein the multiple internal vias gradually narrow upwards, wherein the material of the upper dielectric layers is transparent, wherein the reference mark of the upper conductive structure and the bottommost circuit layer of the multiple upper circuit layers of the upper conductive structure are on the same layer and formed simultaneously, wherein the upper conductive structure includes a low-density region and a high-density region located between the low-density regions, wherein there is no vertical conductive path between the upper conductive structure and the lower conductive structure within the vertical projection range of the high-density region; A lower conductive structure includes multiple lower dielectric layers, multiple lower circuit layers in contact with the multiple lower dielectric layers, and at least one reference mark, wherein the line spacing of the lower circuit layers of the lower conductive structure is greater than the line spacing of the upper circuit layers of the upper conductive structure, wherein the reference mark of the lower conductive structure and the topmost circuit layer of the multiple lower circuit layers of the lower conductive structure are on the same layer and formed simultaneously, wherein the reference mark of the upper conductive structure is aligned with the reference mark of the lower conductive structure; An intermediate layer joins the upper conductive structure and the lower conductive structure together, wherein the intermediate layer is made of a transparent material, and wherein the topmost circuit layer of the lower conductive structure and the bottommost circuit layer of the upper conductive structure are embedded in the intermediate layer; as well as At least one via extending through the upper conductive structure, the intermediate layer, and the lower conductive structure, wherein the at least one via has a uniform width, wherein the via is disposed in the low-density region of the upper conductive structure, and wherein the via extends through and contacts the bottommost circuit layer of the upper conductive structure, the topmost circuit layer of the lower conductive structure, and the bottommost circuit layer of the lower conductive structure.

2. The wiring structure of claim 1, wherein some of the plurality of internal vias of the upper conductive structure are disposed between two adjacent ones in the upper circuit layer to electrically connect the two adjacent ones in the upper circuit layer, and other some of the plurality of internal vias are exposed from the top surface of the upper conductive structure.

3. The wiring structure according to claim 1, wherein the through-hole comprises a conductive layer and an insulating material, the conductive layer defining a central hole, and the insulating material filling the central hole of the conductive layer, wherein the wiring structure further comprises: An external circuit layer is disposed on and protrudes from the top surface of the upper conductive structure, wherein the conductive layer and the external circuit layer are integrally formed.

4. The wiring structure according to claim 3, wherein the bottom surface of the conductive layer and the bottom surface of the bottommost circuit layer of the lower conductive structure are coplanar.

5. The wiring structure of claim 1, wherein the through-hole extends through and contacts the topmost circuit layer of the upper conductive structure.

6. The wiring structure according to claim 1, further comprising: An external circuit layer is disposed on the top surface of the upper conductive structure and protrudes therefrom, wherein the through-hole and the external circuit layer are integrally formed.

7. The wiring structure according to claim 6, wherein the external circuit layer directly contacts the plurality of internal vias of the upper conductive structure.

8. The wiring structure according to claim 1, wherein the upper conductive structure is a coreless substrate and the lower conductive structure is a core substrate.

9. The wiring structure according to claim 8, wherein the lower conductive structure further comprises: The core portion has a top surface and a bottom surface opposite the top surface, and defines a first through hole and a second through hole extending through the core portion, wherein the through hole extends through the second through hole; A substrate interconnect via is disposed in the first through-hole for vertical connection; and Multiple upper interconnect vias are used to electrically connect the multiple lower circuit layers, wherein each upper interconnect via gradually narrows downwards from the top surface to the bottom surface of the lower conductive structure, and the narrowing direction of the multiple upper interconnect vias of the lower conductive structure is different from the narrowing direction of the multiple internal vias of the upper conductive structure.

10. The wiring structure according to claim 9, wherein the line spacing of the lower circuit layer of the lower conductive structure is greater than five times the line spacing of the upper circuit layer of the upper conductive structure, and the thickness of the upper dielectric layer of the upper conductive structure is less than 40% of the thickness of the lower dielectric layer of the lower conductive structure.

11. The wiring structure according to claim 1, wherein the side surface of the lower conductive structure is offset from the side surface of the upper conductive structure, wherein the width of the upper conductive structure is smaller than the width of the intermediate layer.

12. The wiring structure according to claim 1, wherein the warping shape of the upper conductive structure is different from the warping shape of the lower conductive structure.

13. The wiring structure of claim 1, wherein the plurality of upper circuit layers of the upper conductive structure includes an upper ground plane, the topmost circuit layer of the lower conductive structure includes a lower ground plane, wherein the through-hole further extends through and contacts the upper ground plane and the lower ground plane.

14. A packaging structure comprising: The wiring structure according to claim 1; A semiconductor chip electrically connected to and bonded to the high-density region of the upper conductive structure; as well as A heat sink that covers the semiconductor chip, wherein the bottom portion of the sidewall of the heat sink is thermally connected to the through-hole.

15. The packaging structure of claim 14, wherein in a cross-sectional view, the length of the sidewall of the heat sink is less than the length of the through-hole, the length of the sidewall of the heat sink is greater than the thickness of the upper conductive structure and less than the thickness of the lower conductive structure, wherein the width of the sidewall of the heat sink is equal to the width of the through-hole.

16. The packaging structure according to claim 14, further comprising: An external circuit layer is disposed on and protrudes from the top surface of the upper conductive structure, wherein the through-hole and the external circuit layer are integrally formed, and wherein the active surface of the semiconductor chip is electrically connected to and bonded to the external circuit layer via solder bumps.

17. The packaging structure of claim 14, wherein the bottom surface of the through-hole is lower than the bottom surface of the lower conductive structure, and the bottom surface of the through-hole is electrically connected to and bonded to the substrate via solder bumps.

18. The packaging structure of claim 17, wherein the bottommost circuit layer of the lower conductive structure protrudes from the bottom surface of the lower conductive structure, and wherein the through-hole extends through and contacts the bottommost circuit layer of the lower conductive structure.

19. The packaging structure according to claim 14, wherein the through-hole is not located within the vertical projection range of the semiconductor chip.

20. The packaging structure of claim 14, wherein the intermediate layer does not contain a vertical conductive path within the vertical projection range of the semiconductor chip.

21. The packaging structure of claim 14, wherein the plurality of internal vias of the upper conductive structure are stacked on top of each other to form a columnar structure, and the plurality of columnar structures are arranged parallel to or laterally adjacent to each other to form via walls, wherein the via walls are located below the semiconductor chip.

22. The packaging structure of claim 21, wherein the at least one through-hole comprises a plurality of through-holes arranged parallel to or laterally adjacent to each other, configured to be adjacent to the lateral surrounding surface of the wiring structure to prevent signal leakage.

23. A method for manufacturing a wiring structure, comprising: (a) A lower conductive structure is provided, comprising a plurality of lower dielectric layers, a plurality of lower circuit layers in contact with the plurality of lower dielectric layers, and at least one reference mark, wherein the reference mark of the lower conductive structure and the topmost circuit layer of the plurality of lower circuit layers of the lower conductive structure are co-layered and formed simultaneously. (b) An upper conductive structure is formed on a carrier, wherein the upper conductive structure comprises a plurality of upper dielectric layers, a plurality of upper circuit layers in contact with the plurality of upper dielectric layers, a plurality of internal vias, and at least one reference mark, wherein the plurality of internal vias gradually narrow toward the carrier, wherein the material of the upper dielectric layers is transparent, wherein the line spacing of the lower circuit layer of the lower conductive structure is greater than the line spacing of the upper circuit layer of the upper conductive structure, wherein the reference mark of the upper conductive structure and the bottommost circuit layer of the plurality of upper circuit layers of the upper conductive structure are co-layered and formed simultaneously, wherein the upper conductive structure comprises a low-density region and a high-density region located between the low-density regions, wherein there is no vertical conductive path between the upper conductive structure and the lower conductive structure within the vertical projection range of the high-density region; as well as (c) The upper conductive structure and the carrier are attached to the lower conductive structure by an adhesive layer, wherein the reference mark of the upper conductive structure is aligned with the reference mark of the lower conductive structure, wherein the adhesive layer is made of a transparent material, and wherein the topmost circuit layer of the lower conductive structure and the bottommost circuit layer of the upper conductive structure are embedded in the adhesive layer; (d) After the upper conductive structure is attached to the lower conductive structure, the carrier is removed; as well as (e) Forming at least one through-hole that extends through and contacts the bottommost circuit layer of the upper conductive structure, the topmost circuit layer of the lower conductive structure, and the bottommost circuit layer of the lower conductive structure.

24. The method of claim 23, wherein (b) comprises: (b1) Cut the upper conductive structure and the carrier.

25. The method of claim 23, wherein after (a), the method further comprises: (a1) Test the electrical properties of the lower conductive structure; and Wherein, following (b), the method further includes: (b1) Test the electrical properties of the upper conductive structure.

26. The method of claim 23, wherein the carrier is a glass carrier.

27. The method of claim 23, wherein (e) comprises: (e1) Forming at least one through hole by mechanical drilling to extend through the upper conductive structure, the adhesive layer, and the lower conductive structure; and (e2) The through hole is formed in the through hole.

28. The method of claim 27, wherein the through-hole is disposed in the low-density region of the upper conductive structure.

29. The method of claim 23, wherein (e) comprises: (e1) An external circuit layer is formed on the top surface of the upper conductive structure and protrudes therefrom, wherein the through-hole and the external circuit layer are integrally formed; (e2) Electrically connect and bond the semiconductor chip to the external circuit layer; as well as (e3) A heat sink is provided to cover the semiconductor chip, wherein the bottom portion of the sidewall of the heat sink is attached to the through-hole.

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