Warpage-reduced trench capacitance

Abstract

The trench capacitor (150) includes a trench in a doped semiconductor surface layer (104) of a substrate (102). At least one dielectric layer (110) lines the surface of the trench. A doped second polysilicon layer (114) is located on the first polysilicon layer (112) on the dielectric layer (110) filling the trench. The second polysilicon layer (114) has a higher doping level than the first polysilicon layer (112).

Description

Technical Field

[0001] The present invention relates to an integrated trench capacitor and a semiconductor device including a packaged device, wherein the packaged device includes an integrated trench capacitor. Background Art

[0002] Integrated trench capacitors are known for their high density capacitor designs. The formation of integrated trench capacitors typically involves forming a deep trench structure in a highly doped silicon substrate, lining the trench sidewalls and bottom with at least one dielectric layer (usually silicon oxide), then filling the trench with polysilicon (i.e., doping in situ or post-deposition), and then patterning the polysilicon layer. Summary of the invention

[0003] The invention relates to an integrated trench capacitor including a trench in a doped semiconductor surface layer of a substrate. At least one dielectric layer is provided to line the bottom and sidewall surfaces of the trench. A doped second polysilicon layer is disposed on a first polysilicon layer on the dielectric layer filling the trench. The second polysilicon layer has a higher doping level than the first polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a cross-sectional view of an exemplary integrated circuit (IC) including a trench capacitor as described, according to an exemplary aspect.

[0005] Figure 2A-2L is a cross-sectional view illustrating a process progression of an example method of forming an integrated trench capacitor, according to example aspects.

[0006] Figure 3A An exemplary packaged device is shown including a synchronous buck converter including the trench capacitors in a package along with a controller IC and some stacked vertical field effect transistors (FETs), all shown on a common die pad.

[0007] Figure 3B An example of a simplified vertical metal oxide semiconductor field effect transistor (MOSFET) is shown as a cross-sectional depiction of a field effect transistor in a packaged device that may be used in the description. DETAILED DESCRIPTION

[0008] The drawings are not necessarily drawn to scale. In the drawings, similar figure numbers represent similar or equivalent elements. The order of the acts or events shown is not limited, as some acts or events may occur in a different order and / or simultaneously with other acts or events. In addition, some of the acts or events shown may be optional to achieve a method that complies with the specification.

[0009] As used herein, the terms "coupled to" or "coupled with..." (and similar words) describe either an indirect or direct electrical connection without further qualification. Thus, if a first device is "coupled" to a second device, the connection may be through a direct electrical connection with only parasitic effects in the path, or through an indirect electrical connection via intervening other devices and connections. For an indirect connection, the intervening items generally do not modify the information of the signal, but may adjust its current level, voltage level, and / or power level.

[0010] In order to obtain high-density integrated trench capacitors to generally provide capacitance in the nF range, integrated trench capacitors typically use a high-density deep trench process to increase the effective capacitor area, forming tens of thousands or hundreds of thousands of trenches, the depth of which is generally 10μm to 50μm to provide high capacitance (such as 10nF to 50nF). In order to provide low equivalent series resistance (ESR), traditional integrated trench capacitors use a highly doped substrate and a highly doped polysilicon layer to fill the trench after the dielectric lining of the trench as the top plate of the trench capacitor.

[0011] However, both the deep trench process and the polysilicon filling process change the stress distribution of the wafer, which makes the wafer warpage worse. It was found that the post-doped polysilicon deposition of a 200mm diameter wafer (about 200,000 grooves on each die with a depth of about 27μm) suffered from high warpage, with warpage exceeding 400μm. This high warpage caused the wafer to be rejected by the processing tools used for subsequent processing (such as polysilicon dry etching tools) and could not continue with subsequent processing. Lithography, etching and thin film tools generally require wafer warpage less than 100μm to work properly.

[0012] Figure 1 is a cross-sectional view of an exemplary IC 100 including the described trench capacitor 150 according to an exemplary aspect. Although shown on IC 100, the described trench capacitor may also be an independent (unconnected) capacitor including tens of thousands or hundreds of thousands of trenches, which are typically 10 μm to 50 μm deep, depending on the need for capacitance density. IC 100 is shown including functional circuit 180, which is simply shown as a block including metal 123b on filled vias 122b for node contacts. Functional circuit 180 includes circuit elements (including transistors, and generally diodes, resistors, capacitors, etc.), which are generally formed in at least one epitaxial layer 104 on a bulk substrate (substrate) 102 configured with trench capacitors, and are generally used to implement at least circuit functions. Example circuit functions include analog (e.g., amplifier, power converter or power field effect transistor), radio frequency (RF), digital or non-volatile memory functions. The circuit function provided by the functional circuit 180 can also be used to provide top-side grounding for the trench capacitor 150, so that Figure 1The metal 123b and filled via 122b shown in FIG. 1 are optional.

[0013] The substrate 102 and / or these epitaxial layers 104 may include silicon, silicon germanium, or another semiconductor material. Although not shown, as is known in the art, in the case of an IC, the IC typically includes a field oxide, such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS) in the epitaxial layer 104 for isolating adjacent devices.

[0014] The epitaxial layer 104 may include a lightly doped p-type epitaxial layer grown on a substrate 102 comprising a p+ substrate or a lightly doped n-type epitaxial layer grown on a substrate 102 comprising an n+ substrate. There may be multiple epitaxial layers having the same or different doping levels. On the bottom side of the substrate, two layers are shown as 103a and 103b, respectively, which may include a back polysilicon layer and a silicon oxide layer, respectively, which function as a sealant to prevent dopants from escaping from the bottom side of the substrate 102, which has a high doping property and may cause cross contamination problems in processing equipment (such as a gate oxidation furnace) that may be used to form the dielectric layer of the capacitor.

[0015] Trench capacitor 150 includes a trench formed completely in epitaxial layer 104. The trench depth is typically 10 μm to 50 μm, which is less than the thickness of epitaxial layer 104. Epitaxial layer 104 has a lower doping level than that in substrate 102. Dielectric layer 110 may include the same thermally grown gate oxide layer lining the trench surface for metal oxide semiconductor (MOS) transistors on the IC.

[0016] The thickness of dielectric layer 110 is typically in the range of 100 angstroms. The dielectric layer 110 may be deposited at a dielectric constant of 100 to 500 angstroms, typically depending on the capacitance density needs and power requirements. A dielectric layer 110 having a dielectric constant different from that of silicon oxide may also be deposited. The trench includes a second polysilicon layer 114 doped on a first polysilicon layer 112, which is typically deposited undoped on the dielectric layer 110 filling the trench. The first polysilicon layer 112 typically receives doping from the second polysilicon layer 114 during all significant thermal cycles. Both the first polysilicon layer 112 and the second polysilicon layer 114 are typically doped with a doping type that matches the doping in the epitaxial layer 104 and the substrate 102.

[0017] There may be a metal liner of about 1 μm or less between the first polysilicon layer 112 and the dielectric layer 110. The second polysilicon layer 114 has a higher doping level than the first polysilicon layer, which is typically deposited undoped but typically receives doping from the second polysilicon layer 114 during significant thermal processing received during manufacturing. Therefore, the first polysilicon layer 112 typically has its highest doping concentration at the intersection with the second polysilicon layer 114.

[0018] The trench capacitor 150 is shown including top side contacts to the top and bottom plates of the trench capacitor 150. The contacts include metal on a filled via formed through a pre-metal dielectric (PMD) layer 121, including metal 123a on a filled via 122a (e.g., W-filled) to the second polysilicon layer 114 to provide a top plate contact, and metal 123b on a filled via 122b that provides a bottom plate contact through the epitaxial layer 104. The functional circuit 180 also has metal 123c on the filled via 122c.

[0019] This trench capacitor contact arrangement is only one of at least two possible contact arrangements. Figure 1 As shown, the second trench capacitor contact arrangement has a top plate connected to metal 123a, but contact to the bottom plate involves removing (e.g., by wafer back grinding) layers 103b and 103a, and then depositing a backside metal (BSM) to provide a solderable die attach metal stack to ensure good electrical contact (ohmic contact) to the back side of the chip or proper bonding of the chip to its mounting box. The backside metal layer may include gold on nickel or silver on titanium.

[0020] The aspect ratio (AR) of the described trench capacitors generally depends on the design requirements, but for high density deep trench capacitors, the aspect ratio is typically greater than 10. For example, the aspect ratio may be 18 to 30.

[0021] Figure 2A-2L is a cross-sectional view illustrating a process progression of an example method of forming an integrated trench capacitor, according to example aspects. Figure 2A Epitaxial layers 104 are shown on substrate 102. On the bottom surface of substrate 102, the layers include a back polysilicon layer 103a with a silicon oxide layer 103b (as described above) thereon to seal in dopants from escaping from the back side of substrate 102.

[0022] Figure 2BA blanket photoresist layer 124 is shown, which is created and patterned so that trenches can be formed. For ease of illustration, only two deep trenches are shown, but typically more than two trenches (e.g., tens or hundreds of thousands of trenches) will be formed. The photoresist layer 124 covers the dielectric layer 120, which is typically a silicon oxide layer 120 that protects the surface of the grains. Although not shown, the photoresist layer 124 can be located on top of a hard mask (HM) layer, such as a high density plasma (HDP) oxide HM layer formed on the dielectric layer 120. When the photoresist layer 124 is thin or the trenches are deep enough, an oxide HM layer can be used so that the photoresist layer 124 will be completely destroyed during the trench etching process.

[0023] Figure 2C The trench capacitance is shown during processing after an anisotropic etch is used to form a deep trench 111 through the oxide HM (if used), the dielectric layer 120, and into the epitaxial layer 104 but not reaching the substrate 102. Although the photoresist layer 124 is shown as remaining intact after the trench etch, a large portion of the photoresist layer 124 may have been removed by the trench etch process.

[0024] In at least one aspect, a rounded trench layout is used to eliminate sharp corners, the trench width is about 0.5 μm to 3 μm, and the trench pitch is about 0.3 μm to 1.5 μm. Of course, the depth of the trench 111 can be deeper or shallower as required by the application and is suitable for the process parameters of capacitor integration, such as the thickness of the epitaxial layer 104 and the driving conditions of any wells. The photoresist layer 124 is then removed and the wafer is cleaned.

[0025] like Figure 2D As shown, a dielectric layer 110 is grown or deposited on the sidewalls and bottom of the trench 111. In one aspect, the dielectric layer 110 is entirely silicon oxide. For example, the silicon oxide layer may be arrive Thick, for example, for an expected operating voltage of 13.2V, As described above, a dielectric layer 110 may also be deposited. In a particular aspect, the dielectric layer 110 comprises an oxide nitride oxide (ONO) layer stack.

[0026] like Figure 2E As shown, an undoped polysilicon layer is then deposited as the first polysilicon layer 112, usually by a low pressure chemical vapor deposition (LPCVD) process to partially fill the trench 111, and its thickness is significantly less than 1 / 2 of the trench width to avoid filling the trench. Figure 2F As shown in the trench capacitor during the processing in , at least one doped polysilicon layer as the second polysilicon layer 114 is then deposited on the undoped polysilicon layer as the first polysilicon layer 112, usually again by an LPCVD process to completely fill and overfill the trench 111.

[0027] The second polysilicon layer 114 may include an in-situ doped layer (p+ polysilicon for a p-type epitaxial layer as the epitaxial layer 104 and a p-type substrate as the substrate 102; and n+ polysilicon for an n-type epitaxial layer as the epitaxial layer 104 and an n-type substrate as the substrate 102) or be furnace doped, and is typically deposited to a thickness of 0.8 μm to 1.1 μm and has a 5×10 18 / cm 3 to 1×10 20 / cm 3 The doping level of the doped polysilicon layer is deposited to completely fill and overfill the trench. In the final capacitor, the first polysilicon layer 112 is generally a compressive stress layer, and the second polysilicon layer 114, which is a relatively highly doped polysilicon layer, is generally a tensile stress layer.

[0028] Optionally, after forming the doped polysilicon layer, for example using a furnace doping process, the first polysilicon layer 112 and the second polysilicon layer 114 are typically removed from the back side of the substrate 102, for example using a wet etching process. After the back side polysilicon removal, a dielectric cap layer may be deposited. Figure 2G The resulting in-process trench capacitor is shown with a dielectric capping layer as shown at 126. The capping layer 126 is typically 60nm to 100nm and can be a tetraethoxysilane (TEOS) derived oxide layer deposited at about 680°C, but other low stress capping films can also be used. After depositing the capping layer 126, a furnace annealing process can be performed, for example at a temperature of 900°C to 1050°C for a time ranging from 10 minutes to 30 minutes. Rapid thermal annealing can also be used. This optional additional annealing helps relax (reduce) wafer warpage before polysilicon etching, and can also reduce ESR because the second polysilicon layer 114 diffuses into the first polysilicon layer 112.

[0029] The aspect balances the total stress through process cycles, particularly for trench polysilicon loops, by changing the trench gap fill film stack to a first polysilicon layer 112, which is typically a compressive stress layer on the bottom of the trench, a wafer backside film stack 103b on 103a, and adding an additional cap layer anneal to relax the warp, which typically reduces the wafer warp of a 300mm wafer from approximately 400μm to less than 100μm before polysilicon etching, as described in the following example. After the annealing process, the dielectric cap layer 126 is removed, and then a partial front polysilicon etch (e.g., etching approximately 60% of the total polysilicon layer 114 / 112 thickness) is optionally used, which typically includes a blanket dry etch. Partial etching of the polysilicon can reduce the cell and scribe area film step height and facilitate subsequent photolithography processes. Figure 2HFIG. 4 shows the during-process trench capacitance created after the dielectric cap layer 126 is removed and a partial front polysilicon etch is performed, where the entire thickness of the second polysilicon layer 114 on the sides of the trench is shown to be completely removed.

[0030] like Fig.2I In the trench capacitor shown during processing, a blanket photoresist layer 124 is created and patterned so that the polysilicon layer can be patterned. Because of the partial front polysilicon etch described above, only the second polysilicon layer 114 is shown patterned. Figure 2J The trench capacitance during processing after patterning of the second polysilicon layer 114 is shown.

[0031] Figure 2K The trench capacitor during processing is shown after a PMD layer 121 is deposited on a patterned polysilicon layer and a dielectric layer 120 on the side of the patterned polysilicon layer. The PMD layer 121 may include a TEOS-derived silicon oxide layer. TEOS deposition for a non-plasma deposition process may include LPCVD at a pressure of about 300 mTorr and a temperature of about 700° C. However, other dielectric layers including deposited silicon oxide may also be used, such as organic silicate glass (OSG), low-k dielectrics (i.e., dielectric constants smaller than silicon dioxide), doped dielectric layers, such as fluorine-doped quartz glass (FSG), or SiN layers or variations thereof (e.g., SiON). The thickness of the PMD layer 121 typically ranges from 600 nm to 800 nm.

[0032] Figure 2L A filled contact via is shown formed in the PMD layer 121, a metal layer is then deposited on the PMD layer 121, and then the metal layer is patterned to form a metal 123a on the filled via 122a on the second polysilicon layer 114 to contact the top plate of the trench capacitor, and a metal 123b on the filled via 122b to the epitaxial layer 104 to provide a trench capacitor in the process after contact with the bottom plate of the capacitor. The metal layer may include an aluminum-copper alloy, typically containing 0.5% to 4% copper by weight. Alternatively, the metal layer may include only copper, in which case a damascene process is typically performed. There may be one or more metal layers followed by a passivation process to expose the pads in the top metal layer.

[0033] Figure 3AAn exemplary packaged device 300 is shown including an exemplary synchronous buck converter including a trench capacitor shown as 150' in the package and a controller IC 320 which typically also includes an integrated gate driver, and a number of stacked vertical field effect transistors including a stacked high side (HS) vertical field effect transistor 325 on a low side (LS) vertical field effect transistor 330, all of which are located on a die pad 350 of a lead frame. The trench capacitor 150' shown in the figure includes a back side metal (BSM) layer 151 that provides a bottom plate contact, which is an alternative to the front side bottom plate contact provided to the trench capacitor 150 by the metal 123b on the filled via 122b. Otherwise, the trench capacitor 150' is connected to the lead frame. Figure 1 and Figure 2L The structure of the trench capacitor 150 shown in FIG. 1 is the same as that of the trench capacitor 150 shown in FIG.

[0034] Shown are metal clips, including a high-side clip 360 on the high-side vertical FET 325 and a low-side clip 365 between the high-side FET 325 and the low-side FET 330. The high current VIN (high-side FET 325 drain) and voltage switch (VSW) connections use a clip-bonding technique that typically replaces wire bond connections with solid copper bridges. This arrangement greatly reduces the on-resistance R compared to wire bonding. DS (ON) and conduction losses, and generally provides excellent thermal performance.

[0035] Trench capacitors 150 are located on the sides of the field effect transistor stack and controller IC 320 on the same die pad 350. The bond wires shown include bond wires 337 and 338 from the controller IC 320 to the bond pads coupled to the corresponding gates of the high-side field effect transistor 325 and the low-side field effect transistor 330. In a synchronous buck converter, such as the packaged device 300, the vertical current flow of field effect transistors 325 and 330 makes them ideal for stacking. For NMOS field effect transistors, the source terminal of the high-side field effect transistor 325 is located directly above the drain terminal of the low-side field effect transistor 330, which actually eliminates the resistance and parasitic inductance between these devices, thereby achieving faster switching. In addition, the source terminal of the low-side field effect transistor 330 is at ground potential and has a suitable BSM layer that can be directly soldered to the exposed pad of the package to achieve efficient heat transfer.

[0036] Figure 3BA simplified example vertical MOSFET 170 is shown, which is shown as a cross-sectional depiction of a MOSFET in a packaged device that can be used for the description. Although shown as a planar gate device, a trench gate MOSFET can also be used. The actual structure of an actual power MOSFET is generally more complex and includes various other structures including trenches, such as for the gate or field plate. The vertical MOSFET 170 includes an N+ source 178 formed in a P well 177 in the substrate 105.

[0037] The drain of the MOSFET device 170 shown as D is from the central area under the gate electrode 175 on the gate dielectric 176 to the bottom of the grain with the BSM layer 151 thereon. The channel 171 is shown to be horizontal under the gate electrode 175 on the gate dielectric 176, but it is shorter than a conventional MOSFET, and the current flow between the channel 171 and the drain contact at the BSM layer 151 is shown to be vertical. The short channel 171 provided means low on-resistance, which is a characteristic of a power device.

[0038] The above aspects overcome the high wafer warpage of integrated trench capacitors, which is caused by traditional trench and trench gap filling processes. The deeper the trench and the greater the trench density, the higher the wafer warpage caused. The traditional solution to reduce the warpage is to reduce the trench depth and trench density. The key performance indicator of high-density trench capacitors is high capacitance density. The capacitance density depends on the trench depth and trench density.

[0039] Deeper trenches and higher trench density can increase capacitance density. The described method includes using the stress properties of undoped and doped polysilicon to compensate for film stress, which can keep the trench depth and trench density high while reducing warpage. The doped polysilicon is a tensile stress layer, while the undoped polysilicon layer at the bottom of the trench is a compressive stress layer, which together can balance the wafer warpage. The as-deposited undoped polysilicon layer as the bottom polysilicon layer helps avoid tool contamination.

[0040] Another key performance indicator of high-density capacitors is low ESR, where the polysilicon layer acts as a top plate, and lower polysilicon resistance helps achieve low ESR. The additional annealing before polysilicon etching described above allows doped polysilicon to diffuse into undoped polysilicon to reduce the resistance of undoped polysilicon, while also reducing wafer warpage.

[0041] The described trench capacitors can be packaged with an IC chip as its input and output filtering network, or as discrete high-density capacitors. A semiconductor die having the described trench capacitors can include various components therein and / or layers thereon, including barrier layers, dielectric layers, device structures, active components and passive components, including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. In addition, the semiconductor die can be formed by various processes, including bipolar, insulated gate bipolar transistors (IGBT), CMOS, BiCMOS, and MEMS.

[0042] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A method for forming a trench capacitor, the method comprising: forming a plurality of trenches in a doped semiconductor surface layer of a substrate; forming a dielectric layer lining surfaces of the plurality of trenches; depositing an undoped first polysilicon layer on the dielectric layer; depositing a second polysilicon layer on the undoped first polysilicon layer to fill the plurality of trenches; doping the second polysilicon layer; Using the masking layer pattern, performing a top polysilicon etch to etch back the first polysilicon layer in a region transverse to the plurality of trenches and leave a remaining portion of the first polysilicon layer, the remaining portion electrically connecting a first portion of the second polysilicon layer in a first trench of the plurality of trenches to a second portion of the second polysilicon layer in a second trench of the plurality of trenches; as well as The method further includes removing the first polysilicon layer and the second polysilicon layer from a back side of the substrate after depositing the second polysilicon layer. 2 . The method according to claim 1 , wherein depositing the second polysilicon layer and doping the second polysilicon layer are both provided in an in-situ doped polysilicon deposition process. The method of claim 1 , wherein forming the dielectric layer comprises growing a thermal oxide layer.

4. The method according to claim 1 further includes depositing a dielectric cap layer on the back side of the substrate after removing the first polysilicon layer and the second polysilicon layer from the back side of the substrate, annealing the first polysilicon layer and the second polysilicon layer at a temperature in a range between 900°C and 1050°C, removing the dielectric cap layer, and performing a partial top surface etching of the second polysilicon layer on the first polysilicon layer before the top surface polysilicon etching.

5. The method of claim 1, wherein the doped semiconductor surface layer is part of a bulk base material comprising a plurality of the trench capacitors. The method of claim 1 , further comprising depositing a backside metal layer on the backside of the substrate. The method according to claim 1 , wherein the plurality of trenches have a depth of 10 μm to 50 μm.

8. A trench capacitor comprising: a plurality of trenches in a doped semiconductor surface layer of a substrate; a dielectric layer lining surfaces of the plurality of trenches; and a second polysilicon layer doped on the first polysilicon layer on the dielectric layer filling the plurality of trenches, the second polysilicon layer having a higher doping level than the first polysilicon layer, and A portion of the first polysilicon layer electrically connects a first portion of the second polysilicon layer within a first trench of the plurality of trenches to a second portion of the second polysilicon layer within a second trench of the plurality of trenches. 9 . The trench capacitor of claim 8 , wherein the first polysilicon layer has its highest doping concentration at a junction with the second polysilicon layer.

10. The trench capacitor of claim 8, wherein the doped semiconductor surface layer is part of a bulk base material, further comprising a backside metal layer on a bottom surface of the bulk base material.

11. The trench capacitor of claim 8, wherein the doped semiconductor surface layer comprises at least one epitaxial layer.

12. The trench capacitor of claim 8, wherein the dielectric layer comprises a thermal oxide layer. 13 . The trench capacitor according to claim 12 , wherein the thermal oxide layer has a thickness of 10 nm to 50 nm. 14 . The trench capacitor according to claim 8 , wherein a depth of the plurality of trenches is 10 μm to 50 μm.

15. A packaged semiconductor device comprising: Die pad for lead frame; a first die including a power transistor on the die pad; as well as a second die including a trench capacitor on the die pad, the trench capacitor including: a plurality of trenches in a doped semiconductor surface layer of a substrate having a back metal layer thereon providing a first electrode contact; a dielectric layer lining a surface of the plurality of trenches; a second polysilicon layer doped on the first polysilicon layer on the dielectric layer filling the plurality of trenches; and a portion of the first polysilicon layer electrically connecting a first portion of the second polysilicon layer within a first trench of the plurality of trenches to a second portion of the second polysilicon layer within a second trench of the plurality of trenches, and a metal providing a second electrode contact, the second electrode contact coupled to a fill contact contacting the second polysilicon layer; The second polysilicon layer has a higher doping level than the first polysilicon layer; and The first electrode contact is coupled to a first terminal of the power transistor, and the second electrode contact is coupled to a second terminal of the power transistor. 16 . The packaged semiconductor device of claim 15 , wherein the packaged semiconductor device comprises a Quad Flat No-Lead (QFN) package.

17. The packaged semiconductor device of claim 15, wherein the doped semiconductor surface layer comprises at least one epitaxial layer. 18 . The packaged semiconductor device of claim 15 , wherein a depth of the plurality of trenches is 10 μm to 50 μm.

19. A method for forming a trench capacitor, comprising: forming a plurality of trenches in a doped semiconductor surface layer of a substrate; forming a dielectric layer lining surfaces of the plurality of trenches; depositing an undoped first polysilicon layer on the dielectric layer; depositing a second polysilicon layer on the undoped first polysilicon layer to fill the plurality of trenches; doping the second polysilicon layer; as well as Using a masking layer pattern, top surface polysilicon etching is performed to etch back the first polysilicon layer in an area transverse to the multiple grooves and leave a remaining portion of the first polysilicon layer, which electrically connects a first portion of the second polysilicon layer within a first trench among the multiple grooves to a second portion of the second polysilicon layer within a second trench among the multiple grooves.

20. The method of claim 19, wherein depositing the second polysilicon layer and doping the second polysilicon layer are both provided in an in-situ doped polysilicon deposition process.

21. The method of claim 19, wherein forming the dielectric layer comprises growing a thermal oxide layer.

22. The method of claim 19, further comprising removing the first polysilicon layer and the second polysilicon layer from a back side of the substrate after depositing the second polysilicon layer.

23. The method according to claim 22 further includes depositing a dielectric cap layer on the back side of the substrate after removing the first polysilicon layer and the second polysilicon layer from the back side of the substrate, annealing the first polysilicon layer and the second polysilicon layer at a temperature in a range between 900°C and 1050°C, removing the dielectric cap layer, and performing a partial top surface etching of the second polysilicon layer on the first polysilicon layer before the top surface polysilicon etching.

24. The method of claim 22, further comprising depositing a backside metal layer on the backside of the substrate after the removing.

25. The method of claim 19, wherein a depth of the plurality of trenches is in a range between 10 μm and 50 μm.

26. A method for forming a trench capacitor, comprising: forming a plurality of trenches in a doped semiconductor surface layer of a substrate; forming a dielectric layer lining surfaces of the plurality of trenches; forming an undoped first polysilicon layer on the dielectric layer and on the back side of the substrate; forming a doped second polysilicon layer on the undoped first polysilicon layer in the trench and on the back side of the substrate; removing the first polysilicon layer and the second polysilicon layer from above the surface layer, leaving a first remaining portion of the second polysilicon layer in a first trench of the plurality of trenches, a second remaining portion of the second polysilicon layer in a second trench of the plurality of trenches, and a remaining portion of the first polysilicon layer electrically connecting the first remaining portion to the second remaining portion; and The first polysilicon layer and the second polysilicon layer are removed from over the back side of the substrate. 27 . The method of claim 26 , wherein when forming the second polysilicon layer, the first polysilicon layer is undoped, and the method further comprises doping the second polysilicon layer.

28. The method of claim 27, wherein the second polysilicon layer is doped in-situ during formation.

29. The method of claim 26, further comprising forming a silicon oxide capping layer over a back side of the substrate after removing the first polysilicon layer and the second polysilicon layer from over the back side. 30 . The method of claim 29 , further comprising thermally annealing the first polysilicon layer and the second polysilicon layer after forming the capping layer.

31. The method of claim 29, further comprising forming a first metal connection to the remaining portion of the first polysilicon layer, and forming a second metal connection to the doped semiconductor surface layer.

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