Memory and its Formation Method

Abstract

The present invention provides a memory and a method for forming the same. By making the bit line contact window in the memory have a larger opening size in the extending direction perpendicular to the bit line, it is beneficial to improve the removal effect of the conductive material at the end position of the bit line contact window when preparing the bit line contact part, so as to avoid the problem of conductive material residue in the bit line contact window and improve the device performance of the memory.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory and a method for forming the same. Background Art

[0002] A memory, such as a dynamic random access memory (DRAM), generally includes a storage capacitor and a storage transistor electrically connected to the storage capacitor.

[0003] Based on the existing memory, there are still problems of high manufacturing difficulty and complicated preparation process. For example, when preparing the bit line contact embedded in the substrate, it is usually necessary to first form a bit line contact window in the substrate, then fill the conductive material in the bit line contact window, and finally use an etching process to remove part of the conductive material in the bit line contact window to form the bit line contact. However, when etching to remove the conductive material in the bit line contact window, there is often a problem of incomplete etching, which can easily cause the problem of device leakage current. Summary of the invention

[0004] The object of the present invention is to provide a memory to solve the problem that the existing memory has residual conductive material, which easily causes device leakage current.

[0005] In order to solve the above technical problem, the present invention provides a memory, including a substrate and a bit line formed on the substrate, wherein the bit line extends along a first direction.

[0006] In which, multiple active areas are formed in the substrate, and a bit line contact window is also formed in the substrate, at least part of the active areas are exposed to the bit line contact window, and the opening size of the bit line contact window in the direction perpendicular to the extension direction of the bit line is larger than the opening size of the bit line contact window in the extension direction of the bit line.

[0007] Furthermore, the memory also includes a bit line contact portion, which is formed in the bit line contact window and electrically connected to the active area, and the bit line covers the top surface of the bit line contact portion, and the width dimension of the bit line contact portion in a direction perpendicular to the extension direction of the bit line is smaller than the opening dimension of the bit line contact window in the direction perpendicular to the extension direction of the bit line, so that the outer side wall of the bit line contact portion and the groove side wall of the bit line contact window are spaced apart from each other.

[0008] Optionally, a width dimension of the bit line contact portion in a direction perpendicular to an extension direction of the bit line is smaller than a width dimension of the bit line contact portion in the extension direction of the bit line.

[0009] Optionally, an opening size of the bit line contact window in a direction perpendicular to an extension direction of the bit line is greater than or equal to twice a minimum characteristic size, and an opening size of the bit line contact window in the extension direction of the bit line is less than twice a minimum characteristic size.

[0010] Optionally, the bit line contact window is elliptical in shape, and a major axis direction of the elliptical shape of the bit line contact window is perpendicular to an extension direction of the bit line.

[0011] Optionally, the width dimensions of the bit line and the bit line contact portion in a direction perpendicular to the extension direction of the bit line are both greater than or equal to a minimum characteristic dimension.

[0012] Optionally, the memory further includes a word line, which is buried in the substrate and extends along the second direction to intersect with the corresponding active area, and a portion of the active area intersecting with the word line is located on a side of a portion of the active area exposed to the bit line contact window.

[0013] Optionally, the bit line contact window also extends laterally to above the word line in the extension direction of the bit line.

[0014] Optionally, a word line groove is formed in the substrate, the word line is filled in the word line groove, and the top position of the word line is lower than the top position of the word line groove, and a spacing insulating layer is also filled in the space above the word line in the word line groove, and the bit line contact window extends laterally in the extension direction of the bit line to the spacing insulating layer above the word line.

[0015] Optionally, a width dimension of a portion of the bit line contact window that extends laterally into the spacer insulating layer is smaller than 0.6 times of a minimum feature dimension.

[0016] Optionally, the spacing insulating layer has a gap, and the bit line contact window extends laterally to the gap of the spacing insulating layer to directly contact the gap.

[0017] Optionally, the memory further includes a trench isolation structure, which is formed in the substrate and surrounds the periphery of the active area; and the bit line contact window also extends laterally into the trench isolation structure in a direction perpendicular to an extension direction of the bit line.

[0018] Optionally, a width dimension of a portion of the bit line contact window that extends laterally in the trench isolation structure is greater than or equal to 0.5 times the minimum feature dimension.

[0019] Optionally, a word line groove is formed in the substrate, the word line groove is filled with a word line and an isolation insulating layer in sequence, and the word line groove is located on the side of the bit line contact window, and the bit line contact window also extends laterally into the isolation insulating layer in the extension direction of the bit line.

[0020] Optionally, an average slope of a first trench sidewall in the trench isolation structure corresponding to the bit line contact window is greater than an average slope of a second trench sidewall in the spacer insulating layer corresponding to the bit line contact window.

[0021] Optionally, the top surface of the bit line contact portion is higher than the top surface of the substrate; and the memory also includes a connecting portion, which is formed on the top surface of the substrate and is alternately arranged with the bit line contact portion along the extension direction of the bit line to connect adjacent bit line contacts, and the bit line also covers the top surface of the connecting portion.

[0022] Another object of the present invention is to provide a method for forming a memory, comprising:

[0023] Providing a substrate, wherein a plurality of active regions are formed in the substrate;

[0024] forming a plurality of bit line contact windows in the substrate, wherein the bit line contact windows expose at least a portion of the active area, and the opening size of the bit line contact windows in the second direction is larger than the opening size of the bit line contact windows in the first direction;

[0025] forming a conductive material layer on the substrate, wherein the conductive material layer at least fills the bit line contact window, and a portion of the conductive material layer filling the bit line contact window constitutes a filling portion;

[0026] forming a bit line on the conductive material layer, the bit line extending along a first direction and covering the filling portion of the conductive material layer, and the width of the bit line in a second direction is smaller than the width of the filling portion in the second direction, so that an end portion of the filling portion extending along the second direction is exposed; and,

[0027] The conductive material layer is etched using the bit line as a mask to remove the end of the filling portion extending along the second direction, and the remaining filling portion is used to form a bit line contact portion.

[0028] Optionally, before forming the bit line contact window, the method further includes: forming a trench isolation structure in the substrate.

[0029] Optionally, after forming the trench isolation structure and before forming the bit line contact window, the method further includes:

[0030] forming a plurality of word lines in word line trenches of the substrate, wherein top positions of the word lines are lower than top positions of the word line trenches; and,

[0031] A spacer insulating layer is formed in the word line trench to cover the word line.

[0032] Optionally, the method for forming the bit line contact window includes:

[0033] forming a mask layer on the substrate, wherein an opening is formed in the mask layer, and the opening sizes of the opening in the first direction and the second direction may be equal; and,

[0034] An etching process is performed using the mask layer as a mask to form a bit line contact window corresponding to the opening; wherein the etching process includes: longitudinally etching the substrate to a predetermined depth position, wherein the predetermined depth position is higher than the top position of the word line; transversely etching the spacing insulating layer above the word line along a first direction to extend the bit line contact window laterally into the spacing insulating layer; and transversely etching the trench isolation structure along a second direction to extend the bit line contact window laterally into the trench isolation structure; and, in the etching process, the etching rate of the trench isolation structure is greater than the etching rate of the spacing insulating layer.

[0035] In the memory provided by the present invention, the bit line contact window has a larger opening size in the direction perpendicular to the extension of the bit line (for example, larger than the opening size of the bit line contact window in the direction of the extension of the bit line), so that when etching the conductive material in the bit line contact window to prepare the bit line contact portion, it is equivalent to increasing the removal space of the conductive material, which is conducive to the removal of the conductive material at the end position of the bit line contact window (for example, the side wall and the corner of the groove), and improves the problem that the conductive material at the end position of the bit line contact window is easily etched incompletely. In addition, because the bit line contact window has a larger width size in the direction perpendicular to the extension of the bit line, the outer side wall of the bit line contact portion and the groove side wall of the bit line contact window directly opposite to it have a larger spacing space, which is conducive to the subsequent filling of the insulating material to ensure the electrical isolation of the bit line contact portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a top view of a memory in one embodiment of the present invention;

[0037] Figure 2a for Figure 1 A schematic cross-sectional view of a memory device along the aa' direction in an embodiment of the present invention is shown;

[0038] Figure 2b for Figure 1 A schematic cross-sectional view of a memory device according to an embodiment of the present invention along the bb' direction is shown;

[0039] Figure 3 is a schematic flow chart of a method for forming a memory in one embodiment of the present invention;

[0040] Figure 4ais a top view of a method for forming a memory in one embodiment of the present invention when performing step S100;

[0041] Figure 4b is a cross-sectional schematic diagram of a method for forming a memory in an embodiment of the present invention when performing step S100;

[0042] Figure 5a and Figure 6a is a top view of a method for forming a memory in one embodiment of the present invention when performing step S200;

[0043] Figure 5b and Figure 6b is a cross-sectional schematic diagram of a method for forming a memory in one embodiment of the present invention when performing step S200;

[0044] Figure 7a is a top view of a method for forming a memory in one embodiment of the present invention when performing step S300;

[0045] Figure 7b is a cross-sectional schematic diagram of a method for forming a memory in one embodiment of the present invention when performing step S300;

[0046] Figure 8a is a top view of a method for forming a memory in one embodiment of the present invention when performing step S400;

[0047] Figure 8b is a cross-sectional schematic diagram of a method for forming a memory in an embodiment of the present invention when performing step S400;

[0048] Figure 9a is a top view of a method for forming a memory in one embodiment of the present invention when performing step S500;

[0049] Figure 9b FIG. 4 is a cross-sectional diagram of a method for forming a memory in an embodiment of the present invention when performing step S500 .

[0050] The reference numerals are as follows:

[0051] 100-substrate;

[0052] 110-bit line contact window;

[0053] 110a - first trench sidewall;

[0054] 110b - second trench sidewall;

[0055] 210- conductive layer;

[0056] 220- shielding layer;

[0057] 300-interval insulation layer;

[0058] 400-trench isolation structure;

[0059] 500-connection part;

[0060] 600-Isolation layer;

[0061] 700-mask layer;

[0062] 700a-opening;

[0063] 800-conductive material layer;

[0064] 800a-filling part;

[0065] 800b-upper part;

[0066] AA-active area;

[0067] BL-bit line;

[0068] WL-word line;

[0069] S / D1-first source / drain region;

[0070] S / D2-second source / drain region. DETAILED DESCRIPTION

[0071] The memory and the method for forming the memory provided by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0072] Figure 1 is a top view of a memory in one embodiment of the present invention, Figure 2a for Figure 1 The cross-sectional schematic diagram of the memory along the aa' direction in one embodiment of the present invention is shown in FIG. Figure 2b for Figure 1 The cross-sectional view of the memory along the bb' direction in one embodiment of the present invention is shown.

[0073] Combination Figure 1 and Figure 2a to Figure 2b As shown, the memory includes a substrate 100 and a bit line BL formed on the substrate 100, and the bit line BL extends along a predetermined direction. In this embodiment, the extending direction of the bit line BL is a first direction (Y direction).

[0074] Specifically, a plurality of active areas AA are formed in the substrate 100 , and the active area AA includes a first source / drain region S / D1 and a second source / drain region S / D2 .

[0075] In this embodiment, the active area AA extends obliquely relative to the first direction (i.e., the active area AA extends along the Z direction). Also, the first source / drain area S / D1 in each of the active areas AA corresponds to the middle area of ​​the active area AA, and the second source / drain area S / D2 is formed on both ends of the active area AA (i.e., two second source / drain areas S / D2 are respectively arranged on both sides of the first source / drain area S / D1).

[0076] The active area AA is used to form a memory cell of the memory, and the memory cell is, for example, a memory transistor. Also, the first source / drain area S / D1 and the second source / drain area S / D2 can be used to form a drain area and a source area of ​​the memory transistor, and the first source / drain area S / D1 is electrically connected to the bit line BL, and the second source / drain area S / D2 is electrically connected to a storage capacitor.

[0077] Continue to refer Figure 1 and Figure 2a to Figure 2b As shown, the substrate 100 is further formed with a bit line contact window 110, and at least a portion of the active area AA is exposed to the bit line contact window 110. In this embodiment, the first source / drain region S / D1 is exposed to the bit line contact window 110.

[0078] Further, the opening size of the bit line contact window 110 in the direction perpendicular to the extension direction of the bit line is greater than the opening size of the bit line contact window 110 in the extension direction of the bit line. That is, the opening size W1 of the bit line contact window 110 in the second direction (X direction) is greater than the opening size W2 of the bit line contact window 110 in the first direction (Y direction). The first direction is perpendicular to the second direction. In this embodiment, the shape of the bit line contact window 110 is elliptical, and the long axis direction of the ellipse of the bit line contact window 110 is perpendicular to the extension direction of the bit line, and the short axis direction of the ellipse of the bit line contact window 110 is parallel to the extension direction of the bit line.

[0079] That is, the bit line contact window 110 has a larger opening size in a direction perpendicular to the extension direction of the bit line, so that the outer sidewall of the bit line contact portion BC accommodated in the bit line contact window 110 can be far away from the trench sidewall of the bit line contact window 110 .

[0080] Specifically, the memory further includes a bit line contact BC, which is formed in the bit line contact window 110 and electrically connected to the active area AA. In this embodiment, the bit line contact BC is electrically connected to the first source / drain region S / D1.

[0081] Furthermore, the width dimension of the bit line contact portion BC in the direction perpendicular to the extension direction of the bit line is smaller than the opening dimension W1 of the bit line contact window 110 in the direction perpendicular to the extension direction of the bit line, so that the outer side wall of the bit line contact portion BC and the groove side wall of the bit line contact window 110 are spaced apart from each other.

[0082] As described above, since the opening size W1 of the bit line contact window 110 in the second direction (X direction) is relatively large, when the conductive material is filled in the bit line contact window 110 to prepare the bit line contact portion BC, the bit line contact window 110 can have a larger space in the area close to the side wall of the groove to realize the release of the conductive material, thereby avoiding the problem of conductive material residue on the side wall and corner position of the groove of the bit line contact window 110 when preparing the bit line contact portion BC.

[0083] In this embodiment, the width dimension of the bit line contact portion BC in the direction perpendicular to the extension direction of the bit line is further smaller than the width dimension of the bit line contact portion BC in the direction perpendicular to the extension direction of the bit line. In combination with the above-mentioned bit line contact window 110 having a larger opening dimension in the direction perpendicular to the extension direction of the bit line, it can be known that the outer sidewall of the bit line contact portion BC and the trench sidewall directly opposite thereto have a larger spacing dimension.

[0084] Specifically, the opening size W1 of the bit line contact window 110 in the direction perpendicular to the extension of the bit line is greater than or equal to 2 times the minimum characteristic size, that is, the opening size W1 of the bit line contact window 110 in the second direction is ≥ 2*F, where F is the minimum characteristic size that can be obtained under the current process conditions. And, the opening size W2 of the bit line contact window 110 in the direction of extension of the bit line is smaller than the opening size W1 of the bit line contact window 110 in the direction perpendicular to the extension of the bit line, for example, the opening size W2 of the bit line contact window 110 in the direction of extension of the bit line can be smaller than 2 times the minimum characteristic size (that is, the opening size W2 of the bit line contact window 110 in the first direction is < 2*F).

[0085] That is, in this embodiment, the elliptical shape of the bit line contact window 110 has a length dimension in the major axis direction that is greater than or equal to twice the minimum feature dimension, and a length dimension in the minor axis direction that is less than twice the minimum feature dimension.

[0086] It can be understood that the portion of the bit line contact window 110 directly above the active area corresponds to at least one minimum characteristic dimension F, based on which the bit line contact window 110 extends at least 0.5 of the minimum characteristic dimension in each of the two opposite directions from the active area AA in the direction perpendicular to the extension of the bit line (i.e., the size of the active area extended in each of the two opposite directions along the second direction by the bit line contact window 110 is ≥ 0.5*F), thereby obtaining that the opening size W1 of the bit line contact window 110 in the second direction is greater than or equal to 2 times the minimum characteristic dimension (2*F). In addition, the bit line contact window 110 can be made to extend no more than 0.6 of the minimum characteristic dimension in each of the two opposite directions from the active area AA in the direction of the extension of the bit line (i.e., the size of the active area extended in each of the two opposite directions along the first direction by the bit line contact window 110 is < 0.6*F), as long as the opening size of the bit line contact window 110 in the first direction is smaller than its opening size in the second direction.

[0087] In this embodiment, the width dimension of the bit line contact portion BC in the second direction corresponds to at least one minimum characteristic dimension F (that is, the width dimension of the bit line contact portion BC in the second direction is greater than or equal to a minimum characteristic dimension F), and the spacing dimension between the outer side wall of the bit line contact portion BC and the groove side wall opposite thereto is, for example, 0.5 times the minimum characteristic dimension.

[0088] Continue to refer Figure 1 as well as Figure 2a to Figure 2b As shown, the bit line BL extends along the first direction (Y direction) and also covers the bit line contact BC arranged in the extending direction thereof. In this embodiment, the bit line BL includes a conductive layer 210 and a shielding layer 220 stacked from bottom to top.

[0089] Specifically, the bit line BL covers the corresponding bit line contact portion BC, so that the conductive layer 210 in the bit line BL and the corresponding bit line contact portion BC are electrically connected, and further, electrical transmission to the memory cell can be achieved through the bit line BL.

[0090] Furthermore, the sidewall of the bit line BL is flush or nearly flush with the sidewall of the bit line contact BC. Specifically, when preparing the bit line contact BC, the bit line BL can be directly used as a mask pattern to define the pattern of the bit line contact BC.

[0091] Based on this, the width dimension of the bit line BL is also correspondingly smaller than the opening dimension W1 of the bit line contact window 110 in the second direction. For example, the width dimension of the bit line BL also corresponds to at least one minimum feature dimension F, that is, the width dimension of the bit line BL is greater than or equal to a minimum feature dimension F. In addition, the width dimension of the bit line BL and the bit line contact portion BC in the second direction may be further smaller than 1.5 times the minimum feature dimension (1.5*F).

[0092] Continue to refer Figure 1 as well as Figure 2a to Figure 2b As shown, the memory further includes a word line WL, which is buried in the substrate 100 and extends along the second direction (X direction) to intersect with the corresponding active area AA, and the portion of the active area AA intersecting with the word line WL is located on the side of the portion of the active area AA exposed to the bit line contact window 110.

[0093] In this embodiment, the first source / drain region S / D1 and the second source / drain region S / D2 in the active area AA are respectively arranged on both sides of the word line WL. In addition, in this embodiment, each active area AA intersects with two word lines WL, and the first source / drain region S / D1 in the active area AA is located between the two word lines WL.

[0094] Specifically, a word line groove is formed in the substrate 100, and the word line WL is filled in the word line groove. In this embodiment, the top surface of the word line WL is lower than the top of the word line groove, and a spacer insulating layer 300 is also filled in the space above the word line WL in the word line groove, and the spacer insulating layer 300 covers the word line WL accordingly. The material of the spacer insulating layer 300 includes, for example, silicon nitride.

[0095] Further, the bottom position of the bit line contact window 110 is higher than the top position of the word line WL, based on which, the bit line contact window 110 extends laterally along the first direction (i.e., the extension direction of the bit line) to the top of the word line WL, and at this time, it can still be ensured that the word line WL will not be exposed. Specifically, the bit line contact window 110 extends laterally from the active area AA along the first direction to the spacing insulating layer 300 above the word line WL, and based on the spacing insulating layer 300, the word line WL is electrically isolated from the bit line contact portion BC filled in the bit line contact window.

[0096] As described above, the width dimension of the bit line contact window 110 extending laterally from the active area AA in the first direction is less than 0.6 times the minimum characteristic dimension (0.6*F) of the active area. Based on this, it is equivalent to that the width dimension of the bit line contact window 110 extending in the spacing insulating layer 300 above the word line WL is less than 0.6 times the minimum characteristic dimension (0.6*F).

[0097] In a specific embodiment, the spacer insulating layer 300 further has a gap (the gap is, for example, formed in the middle of the spacer insulating layer 300 and extends along the height direction), and the bit line contact window 110 extends laterally in the first direction to the gap of the spacer insulating layer 300 to directly contact the gap. For example, the gap of the spacer insulating layer 300 is formed in the middle of the spacer insulating layer, and when the width dimension of the portion of the bit line contact window 110 extending laterally to the spacer insulating layer 300 is between 0.5 and 0.6 times the minimum feature dimension (0.5*F to 0.6*F), the bit line contact window 110 also extends to the gap position of the spacer insulating layer 300 accordingly.

[0098] Continue to refer Figure 1 as well as Figure 2a to Figure 2b As shown, the memory further includes a trench isolation structure 400, which is formed in the substrate 100 and surrounds the periphery of the active area AA. That is, adjacent active areas AA can be separated from each other by the trench isolation structure 400. It can be understood that by forming the trench isolation structure 400, the active area AA is further defined. Among them, the trench isolation structure 400 can be a shallow trench isolation structure (STI).

[0099] The trench isolation structure 400, for example, includes an isolation trench formed in the substrate 100, and an isolation material layer filled in the isolation trench. In this embodiment, the isolation material layer of the trench isolation structure 400, for example, has a material different from that of the spacer insulating layer 300, for example, the isolation material layer of the trench isolation structure 400 may include silicon nitride or the like.

[0100] Furthermore, the bit line contact window 110 also extends laterally from the active area AA in the second direction (X direction) to the trench isolation structure 400 adjacent to the corresponding active area. As described above, the bit line contact window 110 extends laterally from the active area AA in the second direction to a width dimension of the active area greater than or equal to 0.5 times the minimum feature dimension (0.5*F), based on this, it is equivalent to the width dimension of the bit line contact window 110 extending in the trench isolation structure 400 being greater than or equal to 0.5 times the minimum feature dimension (0.5*F).

[0101] Key References Figure 2a and Figure 2b As shown, in this embodiment, the first trench sidewall 110a in the bit line contact window 110 corresponding to the trench isolation structure 400 and the second trench sidewall 110b in the bit line contact window 110 corresponding to the spacer insulating layer 300 have different inclinations. Specifically, the average slope of the first trench sidewall 110a of the bit line contact window 110 is greater than the average slope of the second trench sidewall 110b. For example, the first trench sidewall 110a is a straight sidewall with a larger slope, and the second trench sidewall 110b is an arc-shaped sidewall with a larger curvature.

[0102] In other words, the bit line contact window 110 extends to the first trench portion in the trench isolation structure 400, which extends to a greater extent in the lateral and longitudinal directions in the trench isolation structure 400, and the bit line contact window 110 extends to the second trench portion in the spacer insulating layer 300, which extends to a smaller extent in the lateral and longitudinal directions in the spacer insulating layer 300 than the first trench portion. In this way, it is helpful to further ensure the isolation performance between the bit line contact portion BC filled in the bit line contact window 110 and the word line WL.

[0103] Continue to refer Figure 2a and Figure 2b As shown, the bit line contact portion BC further extends upward from the bit line contact window 110 , that is, the top surface of the bit line contact portion BC is higher than the top surface of the substrate 100 .

[0104] Furthermore, the memory further includes a connection portion 500, which is formed on the top surface of the substrate 100 and is alternately arranged with the bit line contact portion BC along the extension direction of the bit line (i.e., the first direction) to connect adjacent bit line contact portions BC. Based on this, the bit line contact portion BC and the connection portion 500 connected to each other extend along the extension direction of the bit line.

[0105] In this embodiment, the top surface of the bit line contact portion BC is flush with the top surface of the connecting portion 500, and the bit line BL covers the top surface of the bit line contact portion BC and the top surface of the connecting portion 500. It can be understood that the bit line contact portion BC and the connecting portion 500 can be formed using the same film layer, and corresponding patterns are defined under a mask based on the bit line BL during the preparation process.

[0106] Based on the memory described above, this embodiment also provides a method for forming the memory. Figure 3 FIG. 1 is a flow chart of a method for forming a memory in an embodiment of the present invention. Figure 3 As shown, the method for forming the memory may include:

[0107] Step S100, providing a substrate, wherein a plurality of active regions are formed in the substrate;

[0108] Step S200, forming a plurality of bit line contact windows in the substrate, wherein the bit line contact windows expose at least a portion of the active area, and the opening size of the bit line contact windows in the second direction is larger than the opening size of the bit line contact windows in the first direction;

[0109] Step S300, forming a conductive material layer on the substrate, wherein the conductive material layer at least fills the bit line contact window, and a portion of the conductive material layer filling the bit line contact window constitutes a filling portion;

[0110] Step S400, forming a bit line on the conductive material layer, wherein the bit line extends along a first direction and covers at least the filling portion of the conductive material layer, and a width of the bit line in a second direction is smaller than a width of the filling portion in the second direction, so that an end portion of the filling portion extending along the second direction is exposed;

[0111] Step S500: etching the conductive material layer using the bit line as a mask to remove the end of the filling portion extending along the second direction, and using the remaining filling portion to form a bit line contact portion.

[0112] The method for forming a memory is described in detail below in conjunction with the structural schematic diagrams of each step.

[0113] Figure 4a FIG. 1 is a top view of a method for forming a memory in an embodiment of the present invention when performing step S100. Figure 4b FIG. 4 is a cross-sectional diagram of a method for forming a memory in an embodiment of the present invention when performing step S100 .

[0114] In step S100, refer to Figure 4a and Figure 4b As shown, a substrate 100 is provided, and a plurality of active areas AA are formed in the substrate 100. In this embodiment, the active areas AA are inclined relative to the word lines and bit lines formed subsequently.

[0115] A plurality of trench isolation structures 400 may be first formed in the substrate 100 to define a plurality of active areas AA. Also, the first source / drain area S / D1 and the second source / drain area S / D2 in the active area AA may be formed by an ion implantation process.

[0116] Furthermore, a word line WL is formed in the substrate 100, and the word line WL is buried in the substrate 100 and extends along the second direction (X direction) to intersect with the corresponding active area AA. In addition, the first source / drain region S / D1 and the second source / drain region S / D2 in the active area AA are respectively located on both sides of the word line WL.

[0117] Specifically, the method for forming the word line WL includes the following steps, for example.

[0118] In the first step, a plurality of word line grooves are formed in the substrate 100 ; wherein the word line grooves extend along the second direction (X direction) and pass through the corresponding active area AA, so that the subsequently formed word lines WL intersect with the corresponding active area AA.

[0119] In the second step, a word line material is filled in the word line trench to form a word line WL extending along a second direction (X direction).

[0120] In this embodiment, after the word line material is deposited, an etch-back process may be further performed on the word line material to reduce the height of the word line WL so that the top position of the finally formed word line WL is lower than the top position of the word line trench 300a.

[0121] Continue to refer Figure 4b As shown, the word line WL does not completely fill the word line trench, so that the spacer insulating layer 300 can continue to be filled in the word line trench above the word line WL. The spacer insulating layer 300 covers the word line WL to prevent the word line WL from being electrically connected to other devices.

[0122] Furthermore, after forming the spacer insulating layer 300, an isolation layer 600 may be further formed on the substrate 100, and the isolation layer 600 covers the first source / drain region S / D1 and the second source / drain region S / D2. The materials of the spacer insulating layer 300 and the isolation layer 600 include, for example, silicon nitride (SiN).

[0123] It should be noted that, for the sake of clarity, Figure 4a The spacing insulating layer is shown schematically, but the isolation layer is not shown schematically.

[0124] Figure 5a and Figure 6a FIG. 1 is a top view of a method for forming a memory in an embodiment of the present invention when performing step S200. Figure 5b and Figure 6b FIG. 4 is a cross-sectional diagram of a method for forming a memory in an embodiment of the present invention when performing step S200 .

[0125] In step S200, refer to Figure 5a to Figure 5b and Figure 6a to Figure 6b As shown, a plurality of bit line contact windows 110 are formed in the substrate 100, wherein the bit line contact windows 110 expose at least a portion of the active area AA, and an opening size W1 of the bit line contact windows 110 in a direction perpendicular to the extension direction of the bit line is larger than an opening size W2 of the bit line contact windows 110 in the extension direction of the bit line.

[0126] The bit line contact window 200 a may be formed by performing a photolithography process based on a mask, and further performing an etching process on the substrate 100 .

[0127] It should be noted that the bit line contact window 110 formed in this embodiment has different opening sizes in different directions. Also, the bit line contact window 110 extends to different components in different directions. For example, the bit line contact window 110 extends to the spacer insulating layer 300 above the word line WL in the first direction (Y direction), and extends to the trench isolation structure 400 in the second direction (X direction). Based on this, in this embodiment, the bit line contact window 110 with different opening sizes in different directions can be formed by adjusting the etching process.

[0128] Specifically, the method for forming the bit line contact window 110 includes the following steps, for example.

[0129] The first step, specific reference Figure 5a and Figure 5b As shown, a mask layer 700 is formed on the substrate 100 . In this embodiment, the mask layer 700 is correspondingly formed on the isolation layer 600 .

[0130] Furthermore, an opening 700a is formed in the mask layer 700, and the position of the opening 700a corresponds to the position of the bit line contact window to be formed subsequently. The opening size of the opening 700a in the first direction and the second direction may be equal, for example, the shape of the opening 700a is circular.

[0131] The second step, specific reference Figure 6a and Figure 6b As shown, an etching process is performed using the mask layer 700 as a mask to form the bit line contact window 110 .

[0132] The etching process includes: longitudinally etching the isolation layer 600 and the substrate 100 in sequence to a predetermined depth position, wherein the predetermined depth position is higher than the top position of the word line WL; transversely etching the spacer insulating layer 300 so that the bit line contact window 110 extends transversely into the spacer insulating layer 300; and transversely etching the adjacent trench isolation structure 400 so that the bit line contact window 110 also extends transversely into the trench isolation structure 400.

[0133] It should be noted that the etching parameters of the etching process can be modulated accordingly according to the materials of the spacing insulating layer 300 and the trench isolation structure 400, so that the etching rate of the etching process on the trench isolation structure 400 is greater than the etching rate on the spacing insulating layer 300. In this way, the width dimension of the formed bit line contact window 110 extending in the second direction to the trench isolation structure 400 can be greater than the width dimension of the bit line contact window 110 extending in the first direction to the spacing insulating layer 300, and further the opening dimension W1 of the bit line contact window 110 in the second direction can be greater than the opening dimension W2 in the first direction.

[0134] Figure 7a FIG. 1 is a top view of a method for forming a memory in an embodiment of the present invention when performing step S300. Figure 7b FIG. 4 is a cross-sectional diagram of a method for forming a memory in an embodiment of the present invention when performing step S300 .

[0135] In step S300, refer to Figure 7a and Figure 7b As shown, a conductive material layer 800 is formed on the substrate 100, and the conductive material layer 800 at least fills the bit line contact window 110. The portion of the conductive material layer 800 filling the bit line contact window 110 constitutes a filling portion 800a.

[0136] In this embodiment, the conductive material layer 800 fills the bit line contact window 110 and further extends to cover the top surface of the substrate 100. The portion of the conductive material layer 800 covering the top surface of the substrate constitutes an upper portion 800b. In addition, the conductive material layer 800 is a planarized film layer, that is, the top surface of the conductive material layer 800 is a flat surface, and the top surfaces of the filling portion 800a and the upper portion 800b are flush.

[0137] It needs to be said that, for ease of understanding, Figure 8a The upper layer of the conductive material layer is not shown, but only the filling part of the conductive material layer is shown.

[0138] Figure 8aFIG. 4 is a top view of a method for forming a memory in an embodiment of the present invention when performing step S400. Figure 8b FIG. 4 is a cross-sectional diagram of a method for forming a memory in an embodiment of the present invention when performing step S400 .

[0139] In step S400, refer to Figure 8a and Figure 8b As shown, a plurality of bit lines BL are formed on the conductive material layer 800 , and the bit lines BL extend along a first direction (Y direction) and intersect with corresponding bit line contact windows 110 to at least cover the filling portion 800 a filled in the bit line contact windows 110 by the conductive material layer 800 .

[0140] The width of the bit line BL in the second direction is smaller than the width of the bit line contact window 110 in the second direction. At this time, the width of the bit line BL in the second direction is correspondingly smaller than the width of the filling portion 800a in the second direction, so that the end of the filling portion 800a extending along the second direction is exposed. In this embodiment, the bit line BL covers the filling portion 800a and the upper portion 800b arranged in the extending direction thereof.

[0141] Continue to refer Figure 8b As shown, the bit line BL includes, for example, a conductive layer 210 and a shielding layer 220 stacked up and down. The conductive layer 210 is, for example, a metal layer, and the shielding layer 220 is, for example, an insulating layer, which is used to prevent the conductive layer 210 from being exposed from above. In addition, the shielding layer 220 can also serve as a mask layer to mask and etch the conductive material layer 800 in subsequent processes.

[0142] Figure 9a FIG. 1 is a top view of a method for forming a memory in an embodiment of the present invention when performing step S500. Figure 9b FIG. 4 is a cross-sectional diagram of a method for forming a memory in an embodiment of the present invention when performing step S500 .

[0143] In step S500, refer to Figure 9a and Figure 9b As shown, the conductive material layer 800 is etched using the bit line BL as a mask to remove the end of the filling portion 800a extending along the second direction, and the remaining filling portion 800a is used to form a bit line contact portion BC.

[0144] As described above, the width dimension of the bit line contact window 110 in the second direction (X direction) is relatively large (i.e., larger than the width dimension of the bit line contact window 110 in the first direction (Y direction)), and accordingly, the size of the end portion of the bit line contact window 110 extending from below the bit line BL along the second direction is relatively large. Based on this, when etching the filling portion located at the end position of the bit line contact window, there is a relatively large space to implement the removal process of the conductive material, which is beneficial to improving the removal efficiency of the conductive material at the groove sidewall and corner of the bit line contact window 110, and avoiding the problem of incomplete etching at the groove sidewall and corner.

[0145] It should be noted that the opening size of the bit line contact window 110 in the second direction (X direction) is relatively large, which correspondingly allows a larger spacing space between the outer wall of the bit line contact portion BC and the groove side wall opposite thereto, thereby improving the filling performance of the insulating material when the insulating material is subsequently filled in the bit line contact window 110, thereby ensuring electrical isolation of the bit line contact portion BC.

[0146] In addition, in this embodiment, when etching the conductive material layer 800, the portion of the upper layer exposed to the bit line BL is removed. That is, the portion of the filling portion directly below the bit line BL is retained to form a bit line contact portion BC; and the portion of the upper layer portion directly below the bit line BL is retained to form a connecting portion 500, and the bit line contact portion BC and the connecting portion 500 are alternately connected in sequence and extend along the first direction.

[0147] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

[0148] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0149] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A memory, characterized in that: The memory comprises a substrate and a bit line formed on the substrate, wherein the bit line extends along a first direction; wherein A plurality of active regions are formed in the substrate, wherein the active regions include a first source / drain region and a second source / drain region, and a bit line contact window is further formed in the substrate, at least a portion of the active regions are exposed to the bit line contact window, and an opening size of the bit line contact window in a direction perpendicular to an extension direction of the bit line is larger than an opening size of the bit line contact window in the extension direction of the bit line; Furthermore, the memory also includes a bit line contact portion, which is formed in the bit line contact window and electrically connected to the active area, and the bit line covers the top surface of the bit line contact portion, and the width dimension of the bit line contact portion in a direction perpendicular to the extension direction of the bit line is smaller than the opening dimension of the bit line contact window in the direction perpendicular to the extension direction of the bit line, so that the outer side wall of the bit line contact portion and the groove side wall of the bit line contact window are spaced apart from each other.

2. The memory according to claim 1, wherein: The opening size of the bit line contact window in the direction perpendicular to the extension direction of the bit line is greater than or equal to 2 times the minimum characteristic size, and the opening size of the bit line contact window in the direction of the extension direction of the bit line is less than 2 times the minimum characteristic size, wherein the shape of the bit line contact window is elliptical, and the major axis direction of the ellipse of the bit line contact window is perpendicular to the extension direction of the bit line.

3. The memory according to claim 1, wherein: A word line groove is formed in the substrate, the word line groove is filled with a word line, and the top position of the word line is lower than the top position of the word line groove, and a spacing insulating layer is also filled in the space above the word line in the word line groove, and the bit line contact window extends laterally in the extension direction of the bit line to the spacing insulating layer above the word line.

4. The memory according to claim 3, wherein: The width dimension of the portion of the bit line contact window extending laterally into the spacer insulating layer is less than 0.6 times of the minimum feature dimension.

5. The memory according to claim 3, wherein: The spacing insulating layer has a gap, and the bit line contact window extends laterally to the gap of the spacing insulating layer to directly contact the gap.

6. The memory according to claim 1, wherein: The memory also includes a trench isolation structure, which is formed in the substrate and surrounds the periphery of the active area; and the bit line contact window also extends laterally into the trench isolation structure in a direction perpendicular to the extension direction of the bit line, and the width dimension of the portion of the bit line contact window extending laterally in the trench isolation structure is greater than or equal to 0.5 times the minimum characteristic dimension.

7. The memory according to claim 6, wherein: A word line groove is formed in the substrate, the word line groove is filled with a word line and an insulating spacer layer in sequence, and the word line groove is located on the side of the bit line contact window, and the bit line contact window also extends laterally into the insulating spacer layer in the extending direction of the bit line.

8. The memory according to claim 7, wherein: An average slope of a first trench sidewall in the trench isolation structure corresponding to the bit line contact window is greater than an average slope of a second trench sidewall in the spacer insulating layer corresponding to the bit line contact window.

9. A method for forming a memory, characterized in that: include: Providing a substrate, wherein a plurality of active regions are formed in the substrate; forming a plurality of bit line contact windows in the substrate, wherein the bit line contact windows expose at least a portion of the active area, and the opening size of the bit line contact windows in the second direction is larger than the opening size of the bit line contact windows in the first direction; forming a conductive material layer on the substrate, wherein the conductive material layer at least fills the bit line contact window, and a portion of the conductive material layer filling the bit line contact window constitutes a filling portion; forming a bit line on the conductive material layer, wherein the bit line extends along a first direction and covers the filling portion of the conductive material layer, and a width dimension of the bit line in a second direction is smaller than a width dimension of the filling portion in the second direction, so that an end portion of the filling portion extending along the second direction is exposed; as well as, The conductive material layer is etched using the bit line as a mask to remove the end of the filling portion extending along the second direction, and the remaining filling portion is used to form a bit line contact portion.

10. The method for forming a memory according to claim 9, wherein: Before forming the bit line contact window, the method further includes: forming a trench isolation structure in the substrate.

11. The method for forming a memory according to claim 10, wherein: After forming the trench isolation structure and before forming the bit line contact window, the method further includes: forming a plurality of word lines in word line trenches of the substrate, wherein top positions of the word lines are lower than top positions of the word line trenches; and, A spacer insulating layer is formed in the word line trench to cover the word line.

12. The method for forming a memory according to claim 11, wherein: The method of forming the bit line contact window includes: forming a mask layer on the substrate, wherein an opening is formed in the mask layer, and the opening sizes of the opening in the first direction and the second direction are equal; and, An etching process is performed using the mask layer as a mask to form a bit line contact window corresponding to the opening; wherein the etching process includes: longitudinally etching the substrate to a predetermined depth position, wherein the predetermined depth position is higher than the top position of the word line; transversely etching the spacing insulating layer above the word line along a first direction to extend the bit line contact window laterally into the spacing insulating layer; and transversely etching the trench isolation structure along a second direction to extend the bit line contact window laterally into the trench isolation structure; and, in the etching process, the etching rate of the trench isolation structure is greater than the etching rate of the spacing insulating layer.

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