Non-volatile memory device, method of operating same and storage device

Abstract

A non-volatile memory, its operation method, and a storage device are disclosed. The non-volatile memory device includes: a memory cell array comprising memory cells arranged in rows and columns; a row decoder circuit connected to the rows of the memory cells via word lines and controlling the voltage of the word lines; and a page buffer circuit connected to the columns of the memory cells via bit lines, and including a first transistor configured to sense the voltage of the bit lines and a second transistor configured to invert and sense the voltage of the bit lines. The page buffer circuit is configured to obtain a first value by performing a first sensing operation on a first bit line of the bit lines via the first transistor, and to obtain a second value by performing a second sensing operation on a second bit line of the bit lines via the second transistor, wherein the first or second value is inverted.

Description

Technical Field

[0001] The exemplary embodiments of the inventive concepts disclosed herein relate to semiconductor circuits including non-volatile memory devices, methods of operating non-volatile memory devices, and / or storage devices including non-volatile memory devices. Background Technology

[0002] Storage devices can be configured to store data under the control of host devices such as computers, smartphones, and smart tablets. As an example, storage devices can store data on disks such as hard disk drives (HDDs) or semiconductor memory, and in particular on non-volatile memory such as solid-state drives (SSDs) or memory cards.

[0003] Some examples of non-volatile memories include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0004] Some non-volatile memory devices can be configured to store data in memory cells. Various methods exist for reading memory cells of a non-volatile memory device based on its operating characteristics and requests for accessing and / or managing the device. However, there is still room for introducing new ways to read memory cells that could result in improved speed and / or reliability for the non-volatile memory device. Summary of the Invention

[0005] Some exemplary embodiments of some inventive concepts include a memory device capable of improving the speed of determining the state of data stored in memory cells of a non-volatile memory device, a method of operating the non-volatile memory device, and / or a storage device including the non-volatile memory device.

[0006] According to some example embodiments, a non-volatile memory device includes: a memory cell array including memory cells arranged in rows and columns; and processing circuitry connected to the rows of the memory cells via word lines and to the columns of the memory cells via bit lines, wherein the processing circuitry is configured to control the voltage of the word lines, sense the voltage of the bit lines, invert and sense the voltage of the bit lines, obtain a first value by performing a first sensing operation on a first bit line among the bit lines, obtain a second value by performing a second sensing operation on a second bit line among the bit lines, and invert one of the first value or the second value.

[0007] According to some example embodiments, a storage device may include: a non-volatile memory device including a first memory cell connected to a first bit line and a second memory cell connected to a second bit line; and a controller circuit configured to control the non-volatile memory device to: perform a first sensing operation to read the first memory cell in response to a request; perform a second sensing operation to read the first memory cell and the second memory cell after the first sensing operation; and perform a third sensing operation to read the second memory cell after the second sensing operation.

[0008] According to some example embodiments, an operation method for a non-volatile memory device includes a first memory cell, a second memory cell, a first bit line connected to the first memory cell, and a second bit line connected to the second memory cell. The operation method may include: applying a precharge voltage to the first bit line and the second bit line; performing a first sensing operation on the first bit line to obtain a first value; performing a second sensing operation on the second bit line to obtain a second value; and inverting one of the first value and the second value. Attached Figure Description

[0009] The above and other objects and features of some inventive concepts will become apparent from a detailed description of some exemplary embodiments thereof with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a non-volatile memory device according to some example embodiments of some inventive concepts.

[0011] Figure 2 It is shown Figure 1 A circuit diagram of an example memory block within a memory block.

[0012] Figure 3 This shows a selected memory cell and page buffer circuit in a selected memory block of a memory cell array.

[0013] Figure 4 This is a flowchart illustrating a method of operating a non-volatile memory device according to some exemplary embodiments of some inventive concepts.

[0014] Figure 5 An example of the k-th page buffer is shown as one of the buffers for pages one through eight.

[0015] Figure 6 It is a timing diagram of the signals applied to the page buffer circuit when the threshold voltage of the selected memory cell is sensed.

[0016] Figure 7 This illustrates an example of performing a page buffer sensing operation when the page buffer belongs to the first group of page buffers.

[0017] Figure 8 This illustrates an example of performing a page buffer sensing operation when the page buffer belongs to the second group of page buffers.

[0018] Figure 9 This shows an example of a change in the threshold voltage of a selected memory cell.

[0019] Figure 10 This is an enlarged view of the sixth and seventh programming states.

[0020] Figure 11 This is a flowchart illustrating a method for performing valley search using a non-volatile memory device according to some example embodiments of some inventive concepts.

[0021] Figure 12 When executing Figure 11 The method is a timing diagram of signals applied to a page buffer circuit.

[0022] Figure 13 An example is shown where the i-th page buffer is another of the first through eighth page buffers.

[0023] Figure 14 This is a block diagram illustrating a storage device according to some example embodiments of some inventive concepts.

[0024] Figure 15 This is a flowchart illustrating the operation of a storage device according to some example embodiments of some inventive concepts. Detailed Implementation

[0025] Below, some exemplary embodiments of the inventive concepts are described in detail.

[0026] Figure 1 This is a block diagram illustrating some example embodiments of a non-volatile memory device 100 according to some inventive concepts. (Refer to...) Figure 1 The non-volatile memory device 100 includes a memory cell array 110, a row decoder circuit 120, a page buffer circuit 130, a data input and output circuit 140, and a control logic circuit 150.

[0027] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz includes multiple memory cells. Each of the memory blocks BLK1 to BLKz can be connected to the line decoder circuit 120 via at least one ground select line GSL, a word line WL, and at least one serial select line SSL. Some of the word lines WL can be used as dummy word lines.

[0028] Each of the memory blocks BLK1 to BLKz can be connected to the page buffer circuit 130 via multiple bit lines BL. For example, multiple memory blocks BLK1 to BLKz can be connected to multiple bit lines BL, or different memory blocks can be connected to different bit lines BL. The memory cells of the multiple memory blocks BLK1 to BLKz can have the same or similar structures or can have different structures.

[0029] In some example embodiments, each of the memory blocks BLK1 to BLKz may correspond to a unit of erase operation. Memory cells of the memory cell array 110 may be erased in units of memory blocks. Memory cells belonging to one memory block may be erased simultaneously. In another example embodiment, each of the memory blocks BLK1 to BLKz may be divided into multiple sub-blocks. Each of the multiple sub-blocks may correspond to a unit of erase operation.

[0030] The row decoder circuit 120 can be connected to the memory cell array 110 via the ground select line GSL, the word line WL, and the serial select line SSL. The row decoder circuit 120 can operate under the control of the control logic circuit 150.

[0031] The line decoder circuit 120 can transmit data from an external device (e.g., via a first channel, or input and output channels) through a first channel. Figure 14 The controller circuit 420 receives the row address RA and decodes it, and can control the voltage applied to the serial select line SSL, word line WL and ground select line GSL based on the decoded address.

[0032] Page buffer circuit 130 can be connected to memory cell array 110 via multiple bit lines BL. In some example embodiments, a first memory cell of memory cell array 110 can be connected to a first bit line BL, such as even-numbered bit lines BL2, BL4, etc., and a second memory cell of memory cell array 110 can be connected to a second bit line BL, such as odd-numbered bit lines BL1, BL3, etc. Page buffer circuit 130 can be connected to data input and output circuit 140 via multiple data lines DL. Page buffer circuit 130 can operate under the control of control logic circuit 150.

[0033] In an example write operation, page buffer circuit 130 may store data to be written to the memory cell. Page buffer circuit 130 may apply voltage to one or more of the multiple bit lines BL based on the stored data. In an example read operation, or in an example verification read operation that can be performed in a write or erase operation, page buffer circuit 130 may sense the voltage of the bit line BL, and in some examples, may store the sensed result.

[0034] Data input and output circuit 140 can be connected to page buffer circuit 130 via multiple data lines DL. Data input and output circuit 140 can receive column address CA via a first channel. Based on column address CA, data input and output circuit 140 can output data read by page buffer circuit 130 to an external device via the first channel. Data input and output circuit 140 can also provide data received from an external device based on column address CA to page buffer circuit 130 via the first channel.

[0035] The control logic circuit 150 can receive commands CMD from an external device via a first channel and / or exchange control signals CTRL with an external device via a second channel (e.g., a control channel). In response to the control signal CTRL, the control logic circuit 150 can receive commands CMD via the first channel, and can route the row address RA and column address CA received via the first channel to the row decoder circuit 120 and the data input and output circuit 140, respectively, and / or can route the data "DATA" received via the first channel to the data input and output circuit 140.

[0036] Control logic circuitry 150 can decode the received command CMD, and in some examples, can control the non-volatile memory device 100 based on the decoded command. For example, control logic circuitry 150 can allow row decoder circuitry 120 and page buffer circuitry 130 to perform check operations for checking the state of memory cells. In some example embodiments, the check operation may involve page buffer circuitry 130 using two or more different methods to sense the voltage of bit line BL.

[0037] Figure 2 yes Figure 1 A circuit diagram of an example memory block BLKa from memory blocks BLK1 to BLKz. (Refer to...) Figure 1 and Figure 2 Multiple cell strings (CS) can be arranged in rows and columns on (or within) the substrate SUB. These cell strings can be collectively connected to a common source line (CSL) formed on (or within) the substrate SUB. Figure 2 In the example of the structure of memory block BLKa, the location of the substrate SUB is included.

[0038] In such Figure 2 In the example embodiment shown, the common source line CSL may be connected to the lower end of the cell string CS. In some example embodiments, the common source line CSL may be physically located at the lower end of the cell string CS. Figure 2 The diagram illustrates an example embodiment where the cell strings CS are arranged in a 4x4 matrix. In other example embodiments, the configuration of the cell strings CS can vary; for example, the number of cell strings CS in the memory block BLKa can be larger or smaller.

[0039] The cell string CS in each row can be connected to the corresponding ground select line among the first ground select line GSL1 to the fourth ground select line GSL4 and / or the corresponding string select line among the first string select line SSL1 to the fourth string select line SSL4. The cell string CS in each column can be connected to the corresponding bit line among the first bit line BL1 to the fourth bit line BL4. For simplicity, the cell string CS connected to the second string select line SSL2 and the third string select line SSL3 is shown as dashed lines.

[0040] Each of the cell strings CS may include at least one ground select transistor GST connected to the ground select line GSL, multiple memory cells MC1 to MC8 respectively connected to multiple word lines WL1 to WL8, and / or a string select transistor SST respectively connected to string select lines SSL1, SSL2, SSL3, or SSL4. For example, the string select line closer to bit lines BL1 to BL4 in the first row of string select lines SSL1 may be an upper string select line, which may be marked with the reference symbol "u" ​​as "SSL1u". The string select line closer to memory cells MC1 to MC8 in the first row of string select lines SSL1 may be a lower string select line, which may be marked with the reference symbol "l" as "SSL1l". That is, the first string select line SSL1 may include a first upper string select line SSL1u and a first lower string select line SSL1l. The second string select line SSL2 may include a second upper string select line SSL2u and a second lower string select line SSL2l. The third string select line SSL3 may include a third upper string select line SSL3u and a third lower string select line SSL3l. The fourth string select line SSL4 may include a fourth upper string select line SSL4u and a fourth lower string select line SSL4l. Similarly, the string select transistors SST in the first row may include a first upper string select transistor SST1u and a first lower string select transistor SST1l. The string select transistors SST in the second row may include a second upper string select transistor SST2u and a second lower string select transistor SST2l. The string select transistors SST in the third row may include a third upper string select transistor SST3u and a third lower string select transistor SST3l. The string select transistors SST in the fourth row may include a fourth upper string select transistor SST4u and a fourth lower string select transistor SST4l.

[0041] In each cell string CS, the ground selection transistor GST, memory cells MC1 to MC8, and / or string selection transistor SST may be connected (e.g., in series) and / or stacked sequentially in a direction perpendicular to the substrate SUB. In each cell string CS, one or more of the memory cells MC1 to MC8 may be used as dummy memory cells. In some example embodiments, the dummy memory cells may be unprogrammable, i.e., not programmed; in other example embodiments, the dummy memory cells may be programmed differently from the memory cells in MC1 to MC8 other than the dummy memory cells.

[0042] Figure 3 An example embodiment is shown, comprising a selected memory cell MC_S within a selected memory block BLK_S of memory cell array 110 and a page buffer circuit 130. As an example... Figure 3 The components corresponding to the first bit line BL1 through the eighth bit line BL8 are shown in the diagram. (See reference...) Figures 1 to 3 When sensing the state of a memory cell MC_S selected from memory cells MC1 to MC8 of the selected memory block BLK_S, the line decoder circuit 120 can apply a first pass voltage to the unselected word line in the word line WL of the selected memory block BLK_S. The first pass voltage can turn on the unselected memory cell. Therefore, the unselected memory cell is turned on and used as a channel for transmitting voltage. Figure 3 Unselected memory cells in the selected memory block BLK_S were omitted.

[0043] When the selected memory cell MC_S of the selected memory block BLK_S is sensed, the line decoder circuit 120 can apply a second pass voltage to the selected string select line corresponding to the selected memory cell MC_S, and can apply a first OFF voltage to the unselected string select line. The second pass voltage can turn on the selected string select transistor corresponding to the selected memory cell MC_S. Therefore, the selected string select transistor can be used as a channel for transmitting voltage and from... Figure 3 (Omitted). The first OFF voltage turns off the unselected string selection transistor. Therefore, the cell string corresponding to the unselected string selection transistor is electrically disconnected from the first bit line BL1 to the eighth bit line BL8.

[0044] Figure 3 The electrically disconnected unit string has been omitted.

[0045] When the selected memory cell MC_S of the selected memory block BLK_S is sensed, the line decoder circuit 120 can apply a third pass voltage to the selected ground selection line corresponding to the selected memory cell MC_S, and can apply a second OFF voltage to the unselected ground selection line. The third pass voltage can turn on the selected ground selection transistor corresponding to the selected memory cell MC_S. Therefore, the selected ground selection transistor can be used as a channel for transmitting voltage and from... Figure 3 (Omitted). The second OFF voltage turns off the unselected ground selection transistor. Therefore, the cell string corresponding to the unselected ground selection transistor is electrically disconnected from the common source line CSL. Figure 3 The electrically disconnected unit string has been omitted.

[0046] When sensing the selected memory cell MC_S of the selected memory block BLK_S, such as Figure 3 As shown, the memory cell array 110 can be simplified to a state in which the selected memory cells MC_S are connected between the first bit line BL1 to the eighth bit line BL8 and the common source line CSL of the supplied ground voltage GND.

[0047] When sensing a selected memory cell MC_S within a selected memory block BLK_S, the row decoder circuit 120 applies a voltage (e.g., a read voltage) to the selected word line WL_S. The page buffer circuit 130 senses the voltages of the first bit line BL1 through the eighth bit line BL8 and determines whether the threshold voltage of the selected memory cell MC_S is greater than (or equal to or less than) the sensed voltage. The first page buffer 131 through the eighth page buffer 138 output the result of the sensing operation to the data input and output circuit 140.

[0048] Page buffer circuit 130 may include first page buffers 131 to eighth page buffers 138 corresponding to the first bit line BL1 to the eighth bit line BL8, respectively. When sensing the selected memory cell MC_S of the selected memory block BLK_S, the first page buffers 131 to the eighth page buffers 138 may be divided into two or more groups, and the page buffers in the group may be controlled to sense the voltage of the corresponding bit line differently.

[0049] For example, page buffers 132, 134, 136, and 138, which are even-numbered from the first page buffer 131 to the eighth page buffer 138, can constitute the first page buffer group. The bit lines connected to the page buffers 132, 134, 136, and 138 of the first group (i.e., bit lines BL2, BL4, BL6, and BL8, which are even-numbered from the first bit line BL1 to the eighth bit line BL8) can constitute the first bit line group.

[0050] For example, page buffers 131, 133, 135, and 137, which are odd-numbered in the first page buffer 131 to the eighth page buffer 138, can constitute a second page buffer group. The bit lines connected to the page buffers 131, 133, 135, and 137 in the second group (i.e., the odd-numbered bit lines BL1, BL3, BL5, and BL7, which are the first bit line BL1 to the eighth bit line BL8) can constitute a second bit line group.

[0051] In the example embodiments, page buffers and bit lines may be grouped for even and odd numbers, but some example embodiments of some inventive concepts are not limited to this. For example, the reference for grouping page buffers and bit lines may be modified or changed based on the operating or process characteristics of the non-volatile memory device 100.

[0052] In some example embodiments, the first signal line SIGL1 for controlling the first group of page buffers 132, 134, 136 and 138 and the second signal line SIGL2 for controlling the second group of page buffers 131, 133, 135 and 137 can be set separately, so that the first group of page buffers 132, 134, 136 and 138 and the second group of page buffers 131, 133, 135 and 137 can sense the voltage of the corresponding bit lines using different methods.

[0053] In some example embodiments, the common signal line SIGC for the common portion of the operation of the first group of page buffers 132, 134, 136 and 138 and the second group of page buffers 131, 133, 135 and 137 may be provided together to the first group of page buffers 132, 134, 136 and 138 and the second group of page buffers 131, 133, 135 and 137.

[0054] Figure 4 This is a flowchart illustrating an operation method of a non-volatile memory device 100 according to an embodiment. (Refer to...) Figure 1 , Figure 3 and Figure 4 In operation S110, page buffer circuit 130 can precharge the first bit line BL1 to the eighth bit line BL8. First page buffer 131 to eighth page buffer 138 can apply voltage (e.g., power supply voltage) to the first bit line BL1 to the eighth bit line BL8 respectively.

[0055] In operation S120, page buffers 132, 134, 136, and 138 of the first group can perform a first sensing operation on bit lines BL2, BL4, BL6, and BL8 of the first group and obtain a first value. In operation S130, page buffers 131, 133, 135, and 137 of the second group can perform a second sensing operation on bit lines BL1, BL3, BL5, and BL7 of the second group and obtain a second value.

[0056] The first sensing operation may differ from the second sensing operation. For example, the result of the first sensing operation or the result of the second sensing operation may be inverted. As an example, a first value as the result of the first sensing operation can be obtained, and a second value can be obtained by inverting the result of the second sensing operation. As another example, the first value can be obtained by inverting the result of the first sensing operation, and a second value as the result of the second sensing operation can be obtained. As an example, the first sensing operation and the second sensing operation may be performed simultaneously and / or at least partially simultaneously. As another example, the first sensing operation and the second sensing operation may be performed sequentially, such as continuously over a period of time.

[0057] Figure 5 An example of a page k buffer 13k is shown, which is one of the page buffers 131 to 138. Figure 5 In the example embodiment, the components of the k-th page buffer 13k associated with the sensing operation are shown, and the remaining components are omitted. In the example embodiment, the structure of the first page buffer 131 to the eighth page buffer 138 can be compared with... Figure 5 The structure shown is the same. In some example embodiments, the page buffer circuit 130 may be configured to perform a first sensing operation and / or a second sensing operation. Furthermore, the page buffer circuit 130 may be configured to invert one of the first sensing voltage of the first sensing operation and the second sensing voltage of the second sensing operation in various ways. As such an example, the page buffer circuit 130 may invert the sensing voltage of a selected bit line in bit line BL during either the first or second sensing operation.

[0058] In some example embodiments and as Figure 1 , Figure 3 and Figure 5 As shown, the page k buffer 13k may include a sensing latch 210, a selection block 220, a precharge block 230, a latch block 240, a transmission block 250, a first transistor 260, a second transistor 270, and a first reset block 280.

[0059] In some example embodiments, controller circuit 420 (see Figure 14 The sensor latch 210 can be configured to control the non-volatile memory device 100 to store the result of a first sensing operation for a first memory cell in a first sensing operation, and to invert and store the result of a second sensing operation for the first memory cell. For example, the sensor latch 210 may include an inverter connected between a first node N1 and a second node N2. The inverter may be cross-coupled. The sensor latch 210 may be configured to store the result of a sensing operation performed on bit line BL.

[0060] Select block 220 is connected between bit line BL and sensing node SN. Select block 220 can be controlled by a select signal SEL provided via a signal line in the common signal line SIGC (e.g., the first common signal line). That is, select blocks 220 of the first page buffer 131 to the eighth page buffer 138 can be simultaneously controlled by the select signal SEL of the first common signal line. In response to the select signal SEL, select block 220 can electrically connect the sensing node SN and bit line BL, or disconnect the sensing node SN from bit line BL.

[0061] Precharge block 230 is connected to sensing node SN. Precharge block 230 can be controlled by a precharge signal PRE provided via a signal line in the common signal line SIGC (e.g., a second common signal line). That is, precharge blocks 230 of the first page buffer 131 to the eighth page buffer 138 can be simultaneously controlled by the precharge signal PRE on the second common signal line. In some example embodiments, page buffer circuit 130 can be configured to apply a precharge voltage to bit line BL before performing a first sensing operation and a second sensing operation. For example, precharge block 230 can apply a precharge voltage to sensing node SN in response to the precharge signal PRE.

[0062] Latch block 240 is connected to sensing node SN and to first transistor 260 and second transistor 270. Latch block 240 can be controlled by a latch signal LAT provided via a signal line in the common signal line SIGC (e.g., a third common signal line). That is, latch blocks 240 of the first page buffer 131 to the eighth page buffer 138 can be simultaneously controlled by the latch signal LAT on the third common signal line. Latch block 240 can transmit the voltage of sensing node SN to first transistor 260 and second transistor 270 in response to latch signal LAT.

[0063] Transmission block 250 is connected to first transistor 260 and second transistor 270. Transmission block 250 can be controlled by a transmission signal TRS provided through a signal line in the common signal line SIGC (e.g., the fourth common signal line). That is, transmission blocks 250 of the first page buffer 131 to the eighth page buffer 138 can be simultaneously controlled by the transmission signal TRS of the fourth common signal line. Transmission block 250 can output the voltage provided by the first transistor 260 or the second transistor 270 to the outside in response to the transmission signal TRS.

[0064] The first transistor 260 is connected between the first node N1 of the sensing latch 210 and the latch block 240. When the k-th page buffer 13k belongs to the first group of page buffers 132, 134, 136, and 138, the first transistor 260 can be controlled by the first sensing signal SEN1 transmitted through the signal line (e.g., the first line) in the first signal line SIGL1. That is, the first transistors 260 of the first group of page buffers 132, 134, 136, and 138 can be simultaneously controlled by the first sensing signal SEN1 of the first line in the first signal line SIGL1.

[0065] The second transistor 270 is connected between the second node N2 of the sensing latch 210 and the latch block 240. When the k-th page buffer 13k belongs to the first group of page buffers 132, 134, 136, and 138, the second transistor 270 can be controlled by the second sensing signal SEN2 transmitted through a signal line (e.g., the second line) in the first signal line SIGL1. That is, the second transistors 270 of the first group of page buffers 132, 134, 136, and 138 can be simultaneously controlled by the second sensing signal SEN2 of the second line in the first signal line SIGL1.

[0066] When the k-th page buffer 13k belongs to the second group of page buffers 131, 133, 135, and 137, the first transistor 260 can be controlled by a third sensing signal SEN3 transmitted through a signal line (e.g., the first line) in the second signal line SIGL2. That is, the first transistors 260 of the second group of page buffers 131, 133, 135, and 137 can be simultaneously controlled by the third sensing signal SEN3 of the first line in the second signal line SIGL2.

[0067] When the k-th page buffer 13k belongs to the second group of page buffers 131, 133, 135, and 137, the second transistor 270 can be controlled by the fourth sensing signal SEN4 transmitted through the signal line (e.g., the second line) in the second signal line SIGL2. That is, the second transistors 270 of the second group of page buffers 131, 133, 135, and 137 can be simultaneously controlled by the fourth sensing signal SEN4 of the second line in the second signal line SIGL2.

[0068] The first reset block 280 is connected to the first transistor 260 and the second transistor 270. The first reset block 280 can be controlled by a first reset signal RST1 provided through a signal line in the common signal line SIGC (e.g., the fifth common signal line). That is, the first reset blocks 280 of the first page buffer 131 to the eighth page buffer 138 can be simultaneously controlled by the first reset signal RST1 on the fifth common signal line. The first reset block 280 can apply a ground voltage (or power supply voltage) to the first transistor 260 or the second transistor 270 in response to the first reset signal RST1.

[0069] Figure 6 This is a timing diagram of the signal applied to the page buffer circuit 130 when the threshold voltage of the selected memory cell MC_S is sensed. (Refer to...) Figure 1 , Figure 3 , Figure 5 and Figure 6 At the first time T1, the first reset signal RST1 is activated and set to the ON voltage VON. When the first reset signal RST1 is set to the ON voltage VON, the first reset block 280 can apply the power supply voltage to the first transistor 260 and the second transistor 270.

[0070] When page buffer 13k belongs to page buffers 132, 134, 136, and 138 of the first group, page buffer 13k can receive the first sensing signal SEN1 and the second sensing signal SEN2. At the first time T1, the second sensing signal SEN2 remains inactive, and the first sensing signal SEN1 is activated and set to the ON voltage VON. The ON voltage VON enables the first transistor 260 to conduct.

[0071] With the first transistor 260 turned on, the first node N1 of the sensing latch 210 can be set to the power supply voltage (e.g., high level). The second node N2 of the sensing latch 210 can be set to the opposite voltage of the power supply voltage, such as ground (e.g., low level).

[0072] When page buffer 13k belongs to page buffers 131, 133, 135, and 137 of the second group, page buffer 13k can receive the third sensing signal SEN3 and the fourth sensing signal SEN4. At the first time T1, the fourth sensing signal SEN4 remains inactive, and the third sensing signal SEN3 is activated and set to the ON voltage VON. The ON voltage VON enables the first transistor 260 to conduct.

[0073] With the first transistor 260 turned on, the first node N1 of the sensing latch 210 can be set to a high level. The second node N2 of the sensing latch 210 can be set to a level opposite to the high level (e.g., a low level).

[0074] At the second time T2, the precharge signal PRE is activated and set to the ON voltage VON. As the precharge signal PRE is set to the ON voltage VON, the precharge block 230 can apply a voltage (e.g., power supply voltage) to the sensing node SN.

[0075] At the second time T2, the selection signal SEL is activated and set to the ON voltage VON. With the selection signal SEL set to the ON voltage VON, the selection block 220 can electrically connect the bit line BL and the sensing node SN. With the bit line BL and the sensing node SN electrically connected, the bit line BL can be charged (e.g., pre-charged) using a voltage (e.g., power supply voltage).

[0076] At the third time T3, the line decoder circuit 120 can apply a read voltage VRD to the selected word line WL_S. The read voltage VRD can be targeted at... Figure 6 The threshold voltage of the selected memory cell MC_S among the various levels shown is compared.

[0077] When the threshold voltage of the selected memory cell connected to bit line BL, which is connected to page buffer 13k, is greater than the read voltage VRD, the selected memory cell can be turned off. In this case, the precharge voltage of bit line BL can be maintained. When the threshold voltage of the selected memory cell connected to bit line BL, which is connected to page buffer 13k, is equal to or less than the read voltage VRD, the selected memory cell can be turned on. In this case, the precharge voltage of bit line BL can be discharged.

[0078] Reference Figure 6 This describes an example of applying a read voltage VRD to the selected word line WL_S after a precharge operation. However, the timing of performing the precharge operation and the timing of applying the read voltage VRD to the selected word line WL_S can be changed and modified.

[0079] At time T4, the latch signal LAT is activated and set to the ON voltage VON. The second sensing signal SEN2 and the third sensing signal SEN3 are also activated and set to the ON voltage VON. The first sensing signal SEN1 and the fourth sensing signal SEN4 can remain in an inactive state.

[0080] When page buffer 13k belongs to page buffers 132, 134, 136 and 138 of the first group, page buffer 13k can receive the second sensing signal SEN2. As the second sensing signal SEN2 is activated and set to the ON voltage VON, latch block 240 can be connected to sensing latch 210 through the second transistor 270.

[0081] When the latch signal LAT is set to the ON voltage VON, latch block 240 can apply the voltage level of sensing node SN to the second node N2 of sensing latch 210 via second transistor 270. As described above, the first node N1 of sensing latch 210 can have a power supply voltage (e.g., high level) or a ground voltage (e.g., low level) depending on any operation after the second time T2 and before the fourth time T4. Figure 12A more detailed embodiment is shown.

[0082] When the voltage of the sensing node SN is the pre-charge voltage, the latch block 240 can adjust the voltage of the second node N2 of the sensing latch 210 to ground voltage through the second transistor 270 in response to the ON voltage VON of the latch signal LAT. In this case, the second node N2 of the sensing latch 210 can be set to ground voltage.

[0083] When the voltage of sensing node SN is ground, latch block 240 can avoid adjusting the voltage of the second node N2 of sensing latch 210 in response to the ON voltage VON of latch signal LAT (or can retain the voltage of the second node N2 of sensing latch 210 without modification). Therefore, the first node N1 of sensing latch 210 can be maintained at the power supply voltage, and the second node N2 can be maintained at ground.

[0084] When page buffer 13k belongs to page buffers 131, 133, 135 and 137 of the second group, page buffer 13k can receive the third sensing signal SEN3. As the third sensing signal SEN3 is activated and set to the ON voltage VON, latch block 240 can be connected to sensing latch 210 through the first transistor 260.

[0085] When the latch signal LAT is set to the ON voltage VON, the latch block 240 can apply the voltage level of the sensing node SN to the first node N1 of the sensing latch 210 through the first transistor 260. As described above, the first node N1 of the sensing latch 210 may have a power supply voltage.

[0086] When the voltage of the sensing node SN is the pre-charge voltage, the latch block 240 can adjust the voltage of the first node N1 of the sensing latch 210 to ground voltage through the first transistor 260 in response to the ON voltage VON of the latch signal LAT. In this case, the first node N1 of the sensing latch 210 can be set to ground voltage.

[0087] When the voltage of sensing node SN is ground, latch block 240 can avoid adjusting the voltage of the first node N1 of sensing latch 210 in response to the ON voltage VON of latch signal LAT (or can retain the voltage of the first node N1 of sensing latch 210 without modification). Therefore, the second node N2 of sensing latch 210 can be maintained at the power supply voltage, and the first node N1 can be maintained at ground.

[0088] At the fifth time T5, the transmission signal TRS is activated and set to the ON voltage VON. When the transmission signal TRS is set to the ON voltage VON, the transmission block 250 can output a signal provided by the first transistor 260 or the second transistor 270.

[0089] When page buffer 13k belongs to page buffers 132, 134, 136, and 138 of the first group, page buffer 13k can receive the second sensing signal SEN2. At the fifth time T5, the second sensing signal SEN2 is activated and set to the ON voltage VON. The ON voltage VON can turn on the second transistor 270. Therefore, the transmission block 250 can output the logic level of the second node N2 of the sensing latch 210.

[0090] When page buffer 13k belongs to page buffers 131, 133, 135, and 137 of the second group, page buffer 13k can receive the fourth sensing signal SEN4. At the fifth time T5, the fourth sensing signal SEN4 is activated and set to the ON voltage VON. The ON voltage VON can turn on the second transistor 270. Therefore, the transmission block 250 can output the logic level of the second node N2 of the sensing latch 210.

[0091] Figure 7 This illustrates an example of a sensing operation performed on page buffer 13k when it belongs to page buffers 132, 134, 136, and 138 of the first group. (See also...) Figure 1 , Figure 3 , Figure 6 and Figure 7 The first node N1 of the sensing latch 210 can be initialized to a high level (e.g., power supply voltage). As indicated by the first arrow A1, a voltage change on the bit line BL can be transmitted to the latch block 240.

[0092] As indicated by the second arrow A2, latch block 240 can apply a voltage change of bit line BL to the second node N2 of sensing latch 210. A voltage change of bit line BL can also be applied to the first node N1 of sensing latch 210 via the cross-coupled inverter structure of sensing latch 210.

[0093] Figure 8 This illustrates an example of the sensing operation of page buffer 13k when it belongs to page buffers 131, 133, 135, and 137 of the second group. (Refer to...) Figure 1 , Figure 3 , Figure 6 and Figure 8 The first node N1 of the sensing latch 210 can be initialized to a high level (e.g., power supply voltage).

[0094] As indicated by the third arrow A3, a voltage change on bit line BL can be transmitted to latch block 240. As indicated by the fourth arrow A4, latch block 240 can apply a voltage change on bit line BL to the first node N1 of sensing latch 210.

[0095] In reference Figure 7In the described page buffer 13k, voltage changes on bit line BL are transmitted to the second node N2 of the sensing latch 210 without passing through the internal inverter of the sensing latch 210. (Refer to...) Figure 8 In the page buffer 13k described, the voltage change of bit line BL is transmitted to the second node N2 of the sense latch 210 through the internal inverter of the sense latch 210.

[0096] Right now, Figure 8 The page buffer 13k can invert the sensing result of the voltage change of bit line BL, and can apply the inverted sensing result to the second node N2 of the sensing latch 210. Figure 7 The page buffer 13k can apply the sensing result of the voltage change of bit line BL to the second node N2 of the sensing latch 210 without inverting it.

[0097] That is, each of the first page buffers 131 to the eighth page buffers 138 can perform a sensing operation on the selected memory cell in a different manner based on whether the respective page buffer belongs to any page buffer group. This sensing scheme can accelerate the checking operation of the non-volatile memory device 100 to determine the state of the selected memory cell MC_S.

[0098] Figure 9 This illustrates an example of a change in the threshold voltage of the selected memory cell MC_S. Figure 9 In the diagram, the horizontal axis represents the threshold voltage VTH of the memory cell, and the vertical axis represents the number of memory cells.

[0099] Reference Figure 1 , Figure 3 and Figure 9 Before performing a programming operation, for example, after performing an erase operation on the selected memory cell MC_S, the threshold voltage of the selected memory cell MC_S may fall within the range corresponding to the erase state "E", as shown in the first box B1.

[0100] After the programming operation is performed, the threshold voltage of the selected memory cell MC_S may fall within the range corresponding to the erase state "E" and the first programming state P1 to the seventh programming state P7, respectively, as shown in the second box B2. For example, each of the selected memory cells MC_S may be controlled to have a threshold voltage corresponding to one of the ranges corresponding to the erase state "E" and the first programming state P1 to the seventh programming state P7, based on the data to be written therein.

[0101] In the selected memory cell MC_S, after programming operations are performed on the selected memory cell MC_S, residual degradation may occur over time in the selected memory cell MC_S. As residual degradation occurs, the threshold voltage of some memory cells in the selected memory cell MC_S may exceed the range of some memory cells.

[0102] For example, retention degradation can become more severe as the boundary levels of the range to which the threshold voltage belongs become lower or higher. Retention degradation can occur weakly as the boundary levels of the range to which the threshold voltage belongs become closer to the center of the entire range of the threshold voltage. In some example embodiments, retention degradation occurring in erase state "E" and seventh programming state P7 is... Figure 9 The third-party box B3 is shown.

[0103] Referring to third-party box B3, the threshold voltage of some memory cells in the memory cell with erase state "E" may increase and may exceed the range of erase state "E". Additionally, the threshold voltage of some memory cells in the memory cell with seventh programming state P7 may decrease and may exceed the range of seventh programming state P7.

[0104] When retention degradation occurs, the threshold voltage of some memory cells in the erase state "E" may shift to the range of the first programming state P1. Additionally, the threshold voltage of some memory cells in the seventh programming state P7 may shift to the range of the sixth programming state P6. This shift can lead to errors in read operations.

[0105] In the event of an error during a read operation, the non-volatile memory device 100 may perform a check operation on the selected memory cell MC_S to resolve the error and complete the read operation. Additionally, the non-volatile memory device 100 can refer to... Figure 4 and Figure 6 The described sensing operations are used to perform the inspection operations, thus reducing the time required for the inspection operations. For example, controller circuitry 420 may be configured to control non-volatile memory 100 by sending a first request for checking the state of the first memory cell and the second memory cell and a second request for reading the first memory cell and the second memory cell. In response to the second request, controller circuitry 420 may also be configured to control non-volatile memory device 100 to perform a read operation on the first memory cell and the second memory cell, and then perform the first sensing operation and the second sensing operation after the read operation.

[0106] Figure 10 This is an enlarged view of the sixth programming state P6 and the seventh programming state P7. Figure 10In the diagram, the horizontal axis represents the threshold voltage VTH of the memory cell, and the vertical axis represents the number of memory cells.

[0107] Reference Figure 1 , Figure 3 and Figure 10 A valley “V” can be formed at the point where the threshold voltage distribution of the memory cell in the sixth programming state P6 intersects with the threshold voltage distribution of the memory cell in the seventh programming state P7. When a read voltage VRD (refer to) with a level corresponding to the valley “V” is used... Figure 6 This feature minimizes read errors when performing read operations.

[0108] The non-volatile memory device 100 can be configured to perform a check operation for searching for valleys "V", and this check operation is referred to as a "valley search". The non-volatile memory device 100 can be configured to perform a check operation using a reference... Figure 4 and 6 The described sensing operation reduces the time required for inspection operations.

[0109] Valley search can be performed by using a level close to the expected valley “V” level to perform a sensing operation and counting the number of memory cells based on the result of the sensing operation. For example, non-volatile memory device 100 can perform a sensing operation using a first voltage V1 and a second voltage V2, and can count memory cells having a threshold voltage between the first voltage V1 and the second voltage V2.

[0110] The non-volatile memory device 100 can perform a sensing operation using a second voltage V2 and a third voltage V3, and can count memory cells having a threshold voltage between the second voltage V2 and the third voltage V3. The non-volatile memory device 100 can identify valleys “V” based on the counting results.

[0111] As another example, the non-volatile memory device 100 can output the result of a sensing operation using a first voltage V1, a second voltage V2, and a third voltage V3 to an external device. The external device can perform a counting operation using the result of the sensing operation and can identify valleys “V”.

[0112] Figure 11 This is a flowchart illustrating a method for a non-volatile memory device 100 to perform a valley search according to some example embodiments of some inventive concepts. (Refer to...) Figure 1 , Figure 3 , Figure 5 , Figure 10 and Figure 11 During operation S210, the non-volatile memory device 100 can perform a reset operation and a precharge operation.

[0113] For example, as referenced Figure 6 Specifically, via the second transistor 270, each of the page buffers 132, 134, 136, and 138 in the first group can set the second node N2 of the sensing latch 210 to a low level and set the first node N1 of the sensing latch 210 to a high level. As another example, via the first transistor 260, each of the page buffers 132, 134, 136, and 138 in the first group can set the first node N1 of the sensing latch 210 to a low level and set the second node N2 of the sensing latch 210 to a high level.

[0114] The first page buffer 131 to the eighth page buffer 138 can precharge the first bit line BL1 to the eighth bit line BL8 to the power supply voltage through the selection block 220 and the precharge block 230.

[0115] In operation S220, the line decoder circuit 120 can adjust the voltage of the selected word line WL_S to a first voltage V1. In operation S230, the non-volatile memory device 100 can perform a third sensing operation on the bit lines BL2, BL4, BL6, and BL8 of the first group and obtain a third value. (See reference...) Figure 4 The third sensing operation is performed before the first sensing operation.

[0116] In operation S240, the line decoder circuit 120 can adjust the voltage of the selected word line WL_S to a second voltage V2. In operation S250, the non-volatile memory device 100 can perform a first sensing operation on the bit lines BL2, BL4, BL6, and BL8 of the first group and obtain a first value. The first sensing operation can correspond to a reference. Figure 4 The first sensing operation.

[0117] The third and first values ​​can be integrated in the page buffers 132, 134, 136, and 138 of the first group. In a particular page buffer among the page buffers 132, 134, 136, and 138 of the first group, the second node N2 of the sensing latch 210 being at a high level can indicate that the threshold voltage of a particular memory cell corresponding to that particular page buffer is greater than the first voltage V1 and is the second voltage V2 or less.

[0118] A low level at the second node N2 of the sensing latch 210 of a specific page buffer indicates that the threshold voltage of a specific memory cell is less than the first voltage V1 or greater than the second voltage V2. That is, the number of memory cells between the first voltage V1 and the second voltage V2 can be counted by counting the number of high levels at the second node N2 of the latches in the first group of page buffers 132, 134, 136, and 138.

[0119] In operation S260, the non-volatile memory device 100 can perform a second sensing operation on the bit lines BL1, BL3, BL5, and BL7 of the second group and obtain a second value. The second sensing operation can correspond to a reference. Figure 4 The second sensing operation.

[0120] In operation S270, the line decoder circuit 120 can adjust the voltage of the selected word line WL_S to a third voltage V3. In operation S280, the non-volatile memory device 100 can perform a fourth sensing operation on the bit lines BL1, BL3, BL5, and BL7 of the second group and obtain a fourth value. (See reference...) Figure 4 The fourth sensing operation is performed before the second sensing operation.

[0121] The second and fourth values ​​can be integrated in the page buffers 131, 133, 135, and 137 of the second group. In a specific page buffer among the page buffers 131, 133, 135, and 137 of the second group, the second node N2 of the sensing latch 210 being at a high level can indicate that the threshold voltage of a specific memory cell corresponding to that specific page buffer is greater than the second voltage V2 and is a third voltage V3 or less.

[0122] The fact that the second node N2 of the sensing latch 210 of a specific page buffer is at a low level indicates that the threshold voltage of a specific memory cell is less than the second voltage V2 or greater than the third voltage V3. That is, the number of memory cells between the second voltage V2 and the third voltage V3 can be counted by counting the number of high levels at the second node N2 of the latches in the second group of page buffers 131, 133, 135 and 137.

[0123] For reference Figure 11 The number of memory cells having a threshold voltage between a first voltage V1 and a second voltage V2 and the number of memory cells having a threshold voltage between a second voltage V2 and a third voltage V3 can be identified by performing a third sensing operation, a first sensing operation, a second sensing operation, and a fourth sensing operation.

[0124] Since the memory cells are counted completely in one operation from the reset and precharge operation to the data transfer operation, the time required for the check operation can be significantly reduced.

[0125] Figure 12 When executing Figure 11 The method is a timing diagram of the signals applied to the page buffer circuit 130. (Refer to...) Figure 1 , Figure 3 , Figure 5 and Figure 12 The first time T1 reset operation and the second time T2 pre-charge operation are referenced. Figure 6 The same execution applies to those described. Therefore, additional descriptions will be omitted to avoid redundancy.

[0126] At the third time T3, the row decoder circuit 120 can adjust the read voltage VRD to be applied to the selected word line WL_S to a first voltage V1. When the threshold voltage of the memory cell connected to the bit line BL is the first voltage V1 or less, the voltage of the bit line BL can discharge to ground. When the threshold voltage of the memory cell connected to the bit line BL is greater than the first voltage V1, the voltage of the bit line BL can be maintained at the precharge voltage.

[0127] At the fourth time T4, the third sensing operation can be performed. The latch signal LAT can be activated and set to the ON voltage VON; the first sensing signal SEN1 can be activated and set to the ON voltage VON. (See reference...) Figure 8 The latch block 240 can apply the sensing result of the voltage change of the bit line BL to the first node N1 of the sensing latch 210.

[0128] When the voltage of bit line BL is the precharge voltage, latch block 240 can change the voltage of the first node N1 of sensing latch 210 to ground. When the voltage of bit line BL is ground, latch block 240 can avoid changing the voltage of the first node N1 of sensing latch 210 (or can retain the voltage of the first node N1 of sensing latch 210 without modification). That is, through the first sensing operation, the first node N1 of the sensing latch 210 of the page buffer corresponding to the memory cell with a threshold voltage greater than the first voltage V1 in the first group of page buffers 132, 134, 136 and 138 can be set to a low level.

[0129] At the third time T5, the row decoder circuit 120 can adjust the read voltage VRD to the second voltage V2. When the threshold voltage of the memory cell connected to the bit line BL is the second voltage V2 or less, the voltage of the bit line BL can discharge to ground. When the threshold voltage of the memory cell connected to the bit line BL is greater than the second voltage V2, the voltage of the bit line BL can be maintained at the precharge voltage.

[0130] At time T6, the first sensing operation can be performed. The latch signal LAT can be activated and set to the ON voltage VON; the second sensing signal SEN2 can be activated and set to the ON voltage VON. (See reference...) Figure 7 The latch block 240 can apply the sensing result of the voltage change of bit line BL to the second node N2 of the sensing latch 210.

[0131] When the voltage of bit line BL is the precharge voltage, latch block 240 can change the voltage of the second node N2 of sensing latch 210 to ground. When the voltage of bit line BL is ground, latch block 240 can avoid changing the voltage of the second node N2 of sensing latch 210 (or can retain the voltage of the second node N2 of sensing latch 210 without modification). That is, through the first sensing operation, the second node N2 of the sensing latch 210 of the page buffer corresponding to the memory cell with a threshold voltage greater than the second voltage V2 in the first group of page buffers 132, 134, 136 and 138 can be set to a low level.

[0132] After performing the third sensing operation and the first sensing operation, a high level at the second node N2 of the sensing latch 210 of the page buffer 13k indicates that the threshold voltage of the memory cell connected to the bit line BL is between the first voltage V1 and the second voltage V2. A low level at the second node N2 of the sensing latch 210 of the page buffer 13k indicates that the threshold voltage of the memory cell connected to the bit line BL is less than the first voltage V1 or greater than the second voltage V2.

[0133] At the sixth time T6, a second sensing operation can be further performed. The second sensing operation can be performed in the same way as the third sensing operation, except that it is performed in the page buffers 131, 133, 135, and 137 of the second group. Therefore, additional descriptions will be omitted to avoid redundancy. The embodiment is described as the first and second sensing operations being performed simultaneously. However, the first and second sensing operations can be performed sequentially with a time difference based on the operating and process characteristics of the non-volatile memory device 100.

[0134] At the third time T7, the row decoder circuit 120 can adjust the read voltage VRD to the third voltage V3. When the threshold voltage of the memory cell connected to the bit line BL is the third voltage V3 or less, the voltage of the bit line BL can discharge to ground. When the threshold voltage of the memory cell connected to the bit line BL is greater than the third voltage V3, the voltage of the bit line BL can be maintained at the precharge voltage.

[0135] At time T8, a fourth sensing operation can be performed. The fourth sensing operation can be performed identically to the first sensing operation, except that it is performed in page buffers 131, 133, 135, and 137 of the second group. Therefore, additional descriptions will be omitted to avoid redundancy.

[0136] Following the fourth sensing signal, a page buffer in the second group of page buffers 131, 133, 135, and 137 with a high level at the second node N2 indicates that the corresponding memory cell has a threshold voltage between the second voltage V2 and the third voltage V3. A page buffer in the second group of page buffers 131, 133, 135, and 137 with a low level at the second node N2 indicates that the corresponding memory cell has a threshold voltage less than the second voltage V2 or greater than the third voltage V3.

[0137] At the ninth time T9, the second sensing signal SEN2, the fourth sensing signal SEN4, and the transmission signal TRS are activated and set to the ON voltage VON. The logic level of the second node N2 of the latches in the first page buffer 131 to the eighth page buffer 138 can be output through the second transistor 270 and the transmission block 250.

[0138] Figure 13 An example is shown of the i-th page buffer 13i, which is another of the first page buffer 131 to the eighth page buffer 138. (See also...) Figure 1 , Figure 3 and Figure 13 The page buffer 13i may include a sense latch 210, a select block 220, a precharge block 230, a latch block 240, a transfer block 250, a first transistor 260, a second transistor 270, a first reset block 280, a bias block 290, a data latch 310, a dump block 320, a second reset block 330, a data block 340, a third transistor 350, and a fourth transistor 360.

[0139] The configuration and operation of the sensing latch 210, selection block 220, precharge block 230, latch block 240, transmission block 250, first transistor 260, second transistor 270, and first reset block 280 can be referenced. Figure 5 The same as those mentioned above.

[0140] Bias block 290 is connected between the second node N2 and the sensing node SN of the sensing latch 210. Bias block 290 can be controlled by a bias signal BIAS provided via a signal line in the common signal line SIGC (e.g., the sixth common signal line). That is, the bias blocks 290 of the first page buffer 131 to the eighth page buffer 138 can be jointly controlled by the bias signal BIAS of the sixth common signal line. In programming operation, in response to the bias signal BIAS, bias block 290 can apply a voltage to bit line BL (or bias bit line BL) based on the logic level of the second node N2 of the sensing latch 210.

[0141] Data latch 310 may include an inverter connected between the third node N3 and the fourth node N4. The inverter may be cross-coupled. Data latch 310 may receive logic levels sensed by sensing latch 210 via transmission block 250 and may store the received logic levels. In addition, data latch 310 may receive logic levels to be transmitted to sensing latch 210 from an external device and may store the received logic levels.

[0142] Dump block 320 is connected between the fourth node N4 of data latch 310 and the sensing node SN. Dump block 320 can be controlled by a dump signal DUMP provided via a signal line in the common signal line SIGC (e.g., the seventh common signal line). That is, dump blocks 320 of the first page buffer 131 to the eighth page buffer 138 can be simultaneously controlled by the dump signal DUMP on the seventh common signal line. In programming operation, in response to the dump signal DUMP, dump block 320 can transmit the logic level of the fourth node N4 of data latch 310 to the sensing latch 210 via the sensing node SN and latch block 240.

[0143] The second reset block 330 is connected to the third transistor 350 and the fourth transistor 360. The second reset block 330 can be controlled by a second reset signal RST2 provided via a signal line in the common signal line SIGC (e.g., the eighth common signal line). That is, the second reset blocks 330 in the first page buffer 131 to the eighth page buffer 138 can be simultaneously controlled by the second reset signal RST2 on the eighth common signal line. The second reset block 330 can apply a ground voltage to the third transistor 350 or the fourth transistor 360 and to the data latch 310 in response to the second reset signal RST2.

[0144] Data block 340 can be configured to output the logic level of the third node N3 or the fourth node N4 of data latch 310 to an external device.

[0145] The third transistor 350 is connected between the third node N3 of the data latch 310 and the data block 340. The third transistor 350 can be controlled by a first signal S1 provided through a signal line in the common signal line SIGC (e.g., the ninth common signal line). That is, the third transistors 350 of the first page buffer 131 to the eighth page buffer 138 can be simultaneously controlled by the first signal S1 of the ninth common signal line. For example, for programming operations, the first signal S1 can have a logic level input to the page buffer 13i.

[0146] The fourth transistor 360 is connected between the fourth node N4 of the data latch 310 and the data block 340. The fourth transistor 360 can be controlled by a second signal S2 provided via a signal line in the common signal line SIGC (e.g., the tenth common signal line). That is, the fourth transistors 360 of the first page buffer 131 to the eighth page buffer 138 can be simultaneously controlled by the second signal S2 on the tenth common signal line. For example, for programming operations, the second signal S2 can have an inverted version of the logic level input to the page buffer 13i.

[0147] For reference Figure 13 The page buffer 13i may include two or more latches. The remaining latches besides the sensing latch 210 may be data latches. Data latches may be connected to the sensing node SN via the dump block 320 and may be connected to the transport block 250. Data latches may include a reset block, a data block, and transistors between the data block and the data latch. Data latches may be configured to exchange logic levels between the sensing latch 210 and external devices.

[0148] In some example embodiments, the page buffers 132, 134, 136, and 138 of the first group can be configured to perform sensing on the bit lines BL2, BL4, BL6, and BL8 of the first group using sense latch 210, and to perform sensing on the bit lines BL1, BL3, BL5, and BL7 of the second group using data latch 310. In this case, the node between the third transistor 350 and the data block 340, and the node between the fourth transistor 360 and the data block 340, can be further connected to latch block 240.

[0149] When page buffer 13i belongs to page buffers 132, 134, 136, and 138 of the first group, the first transistor 260 can be controlled by a first sensing signal SEN1 transmitted through a signal line (e.g., the first line) in the first signal line SIGL1. The second transistor 270 can be controlled by a second sensing signal SEN2 provided through a signal line (e.g., the second line) in the first signal line SIGL1.

[0150] When page buffer 13i belongs to page buffers 131, 133, 135, and 137 of the second group, the third transistor 350 can be controlled by a third sensing signal SEN3 transmitted via a signal line (e.g., the first line) in the second signal line SIGL2. The fourth transistor 360 can be controlled by a fourth sensing signal SEN4 provided via a signal line (e.g., the second line) in the second signal line SIGL2.

[0151] Figure 14 This is a block diagram illustrating some example embodiments of a storage device 400 according to some inventive concepts. (Refer to...) Figure 14The storage device 400 may include a non-volatile memory device 410 and a controller circuit 420.

[0152] The non-volatile memory device 410 may include a non-volatile memory device 100 according to some example embodiments of some inventive concepts. A controller circuit 420 may be configured to control the non-volatile memory device 410. The controller circuit 420 may provide commands CMD and addresses ADDR (including row address RA and column address CA) to the non-volatile memory device 410 via a first channel.

[0153] The controller circuit 420 can exchange data "DATA" with the non-volatile memory device 410 via a first channel. The data "DATA" may include two or more bits, each of which may include a logic level indicating one of a high or low level. The controller circuit 420 can exchange control signals CTRL with the non-volatile memory device 410 via a second channel.

[0154] Figure 15 This is a flowchart illustrating the operation of a storage device 400 according to some exemplary embodiments of some inventive concepts. (Refer to...) Figure 15 In operation S310, the controller circuit 420 can send the first command CMD1 and the first address ADDR1 to the non-volatile memory device 410. For example, the first command CMD1 may have a format for requesting an inspection operation.

[0155] In response to the first command CMD1, during operation S320, the non-volatile memory device 410 can execute references. Figure 11 and Figure 12 The operation, for example, includes a check operation to perform a valley search on the memory cell indicated by the first address ADDR1. In operation S330, the non-volatile memory device 410 may transmit the response of the check operation to the controller circuit 420.

[0156] For example, the response may include data “DATA” indicating the values ​​of each memory cell, each of which has a threshold voltage between a first voltage V1 and a second voltage V2 and Figure 11 The response is obtained in operations S230 and S250. Additionally, the response may include data "DATA" indicating the values ​​of each memory cell, each of which has a threshold voltage between the second voltage V2 and the third voltage V3. Figure 11 It is obtained from operations S260 and S280.

[0157] The controller circuit 420 can count the high levels from the response to calculate the number of memory cells each having a threshold voltage between a first voltage V1 and a second voltage V2, and to calculate the number of memory cells each having a threshold voltage between a second voltage V2 and a third voltage V3. The controller circuit 420 can identify valleys “V” based on the counts thus calculated. The controller circuit 420 can adjust parameters (e.g., the level of the read voltage VRD) for accessing the non-volatile memory device 100 based on the identified valleys “V”.

[0158] In operation S340, the controller circuit 420 may send the second command CMD2 and the second address ADDR2 to the non-volatile memory device 410. For example, the second command CMD2 may have a format for requesting a read operation.

[0159] In response to the second command CMD2, in operation S350, the non-volatile memory device 410 can perform the operation indicated by the second command CMD2, for example, a read operation on the memory cell indicated by the second address ADDR2. Based on the read operation, in operation S360, the non-volatile memory device 410 can perform a reference... Figure 11 and Figure 12 The operation, for example, includes a valley search check operation on the memory cell indicated by the second address ADDR2.

[0160] In operation S370, the non-volatile memory device 410 can transmit the response to the operation indicated by the second command CMD2 (e.g., the result of a read operation and a check operation) to the controller circuit 420. The response to the read operation may include data read from the memory cell indicated by the second address ADDR2. The response to the check operation may include data read according to… Figure 11 The value obtained by the method.

[0161] As discussed herein, some example embodiments may include various forms of processing circuitry, such as line decoder circuitry 120, page buffer circuitry 130, data input and output circuitry 140, control logic circuitry 150, and / or controller circuitry 420. In some example embodiments, the processing circuitry may include hardware such as logic circuitry; hardware / software combinations such as processors executing software; or combinations thereof. For example, the processor may include (but is not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0162] Furthermore, while some example embodiments may be described using example architectures, other example embodiments may include different architectures without departing from the scope of this disclosure. For example, in Figure 1 In this embodiment, the non-volatile memory device 100 includes a memory cell array 110, a row decoder circuit 120, a page buffer circuit 130, data input and output circuitry 140, and control logic circuitry 150. However, it will be understood that other example embodiments may include different structures of the processing circuitry, such as more or fewer components; different sets of relationships and interconnections; and / or different arrangements of functionality between components. In some example embodiments, a first component may include a second component, while in other example embodiments, the first and second components may be discrete and separate. In some example embodiments, functionality may be implemented by a single component, while in other example embodiments, functionality may be distributed across two or more components. In various example embodiments, two or more components may operate synchronously and / or asynchronously. In various example embodiments, two or more components may operate continuously and / or simultaneously.

[0163] According to some exemplary embodiments of some inventive concepts, a non-volatile memory device performs a first sensing operation on a first memory cell and a second sensing operation on a second memory cell, and inverts the result of one of the first and second sensing operations to obtain the inverted result. Therefore, a non-volatile memory device, a method of operating the non-volatile memory device, and a storage device including the non-volatile memory device are provided, the non-volatile memory device providing sensing operations enabling accelerated inspection operations for checking the state of data stored in the first and second memory cells.

[0164] Although some examples of the inventive concept have been described with reference to some exemplary embodiments of the inventive concept, it will be apparent to those skilled in the art that various changes and modifications may be made to some exemplary embodiments of the inventive concept without departing from the spirit and scope of some inventive concepts set forth in the appended claims.

Claims

1. A non-volatile memory device, comprising: A memory cell array comprising memory cells arranged in rows and columns; A row decoder circuit, which is connected to the row of the memory cell via word lines, is configured to control the voltage of the word lines; as well as A page buffer circuit, connected to a column of memory cells via bit lines, includes a first transistor and a second transistor. The first transistor is configured to transmit a voltage to be sensed on the bit lines, and the second transistor is configured to transmit a voltage to be inverted and sensed on the bit lines. The page buffer circuit is configured as follows: A first value is obtained by performing a first sensing operation on the first bit line of the bit line via the first transistor, and The second value is obtained by performing a second sensing operation on the second bit line of the bit line via the second transistor. The page buffer circuit includes, The first page buffer is connected to the first bit line respectively, and The second page buffer is connected to the second bit line respectively. Each of the first page buffer and the second page buffer is connected to a corresponding bit line. Each of the first page buffer and the second page buffer includes: Sensing nodes, which are connected to the corresponding bit lines in the bit lines. A latch block, connected to the sensing node, is configured to output a sensing voltage in response to the voltage of the sensing node, and A sensing latch, comprising a first node and a second node, and In each of the first page buffer and the second page buffer, a first transistor of the first transistor is connected between the latch block and the first node of the sensing latch to transmit the sensed voltage as one of the first values, and a second transistor of the second transistor is connected between the latch block and the second node of the sensing latch to transmit the sensed voltage as one of the second values.

2. The non-volatile memory device according to claim 1, wherein, The first bit line is different from the second bit line.

3. The non-volatile memory device according to claim 1, in, The first transistor of the first page buffer is controlled by the first signal line. In this configuration, the second transistor of the first page buffer is controlled by the second signal line. In this configuration, the first transistor of the second page buffer is controlled by a third signal line different from the first signal line, and... The second transistor of the second page buffer is controlled by a fourth signal line that is different from the second signal line.

4. The non-volatile memory device according to claim 1, in, Each of the first page buffer and the second page buffer includes a selection block configured to selectively connect the corresponding bit line and the sensing latch, and The selection block of each of the first page buffer and the second page buffer is configured to be controlled by a common signal line.

5. The non-volatile memory device according to claim 1, in, The page buffer circuit is configured to perform the first sensing operation and the second sensing operation, and The line decoder circuit is configured to apply voltage to a word line selected from the word lines and maintain the voltage.

6. The non-volatile memory device according to claim 1, wherein, The page buffer circuit is also configured to apply a precharge voltage to the bit line before performing the first sensing operation and the second sensing operation.

7. The non-volatile memory device according to claim 6, wherein, After the pre-charge voltage is applied and before the first sensing operation and the second sensing operation, the first page buffer is also configured to obtain a third value by performing a third sensing operation on the first bit line via the second transistor.

8. The non-volatile memory device according to claim 7, wherein, The page buffer circuit is also configured to prevent a sensing operation from being performed on the second bit line during the third sensing operation on the first bit line.

9. The non-volatile memory device according to claim 7, wherein, The line decoder circuit is configured to adjust the voltage of the word line selected from the word lines after the third sensing operation is performed.

10. The non-volatile memory device according to claim 7, wherein, Following the first sensing operation and the second sensing operation, the second page buffer is further configured to obtain a fourth value by performing a fourth sensing operation on the second bit line via the first transistor.

11. The non-volatile memory device according to claim 10, wherein, The page buffer circuit is also configured to prevent a sensing operation from being performed on the first bit line during the fourth sensing operation on the second bit line.

12. The non-volatile memory device according to claim 10, wherein, The line decoder circuit is configured to adjust the voltage of the word line selected from the word lines after the first sensing operation and the second sensing operation and before the third sensing operation.

13. The non-volatile memory device according to claim 10, wherein, The page buffer circuit is also configured to integrate and output the results of the first sensing operation, the second sensing operation, the third sensing operation, and the fourth sensing operation after the fourth sensing operation.

14. A storage device, comprising: A non-volatile memory device, comprising a first memory cell connected to a first bit line and a second memory cell connected to a second bit line; as well as A controller circuit is configured to control the non-volatile memory device: Perform a first sensing operation to read the first memory cell. A second sensing operation is performed after the first sensing operation to read the first memory cell and the second memory cell. A third sensing operation to read the second memory cell is performed after the second sensing operation, and The level of the read voltage to be applied to the first memory cell and the second memory cell is adjusted during the first sensing operation, the second sensing operation and the third sensing operation.

15. The storage device according to claim 14, wherein, The controller circuit is also configured to control the non-volatile memory device: The result of the first sensing operation stored in the first sensing operation for the first memory cell, and The result of the second sensing operation for the first memory cell is stored, and the result of the second sensing operation is inverted before being stored.

16. The storage device according to claim 14, in, The controller circuit is further configured to control the non-volatile memory device by sending a first request to check the state of the first memory cell and the second memory cell, and a second request to read the first memory cell and the second memory cell. In response to the second request, the controller circuit is further configured to control the non-volatile memory device: Perform read operations on the first memory cell and the second memory cell, and The first sensing operation, the second sensing operation, and the third sensing operation are performed after the reading operation.

17. A method of operating a non-volatile memory device, the non-volatile memory device comprising a first memory cell, a second memory cell, a first bit line connected to the first memory cell, and a second bit line connected to the second memory cell, the method comprising: Apply a pre-charge voltage to the first bit line and the second bit line; Perform a first sensing operation on the first bit line to obtain a first value; Perform a second sensing operation on the second bit line to obtain a second value; Invert one of the first value and the second value; After the pre-charge voltage is applied and before the first sensing operation and the second sensing operation, a third sensing operation is performed on the first bit line to obtain a third value; After the third sensing operation, a fourth sensing operation is performed on the second bit line to obtain a fourth value; as well as The results of the first sensing operation and the third sensing operation are integrated, the results of the second sensing operation and the fourth sensing operation are integrated, and the integrated result is output.

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