An optimized deep trench semiconductor device terminal

Abstract

The present invention relates to the field of semiconductor technology, and in particular to an optimized deep trench semiconductor device terminal, including a virtual dotted line, the dotted line to the left is a semiconductor active (cell) area, the dotted line to the right is a terminal protection area, in the top view plane of the semiconductor device, the cell active (cell) area is located at the center of the device, the terminal protection area is located in the outer ring of the active area and surrounds the active area, the device is based on a first conductive type drift area grown on a first conductive type substrate, the lower end of the first conductive type substrate is connected to a drain metal, a second conductive type body area is provided on the first conductive type drift area, and a first trench and a second trench are located in the second conductive type body area and penetrate into an epitaxial layer. The present invention forms a deeper field limiting ring by injecting second conductive type impurities at the bottom of the deep trench, so that the electric field at the bottom of the trench is dispersed, the terminal withstand voltage is higher than the active area, and the reliability is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an optimized deep trench semiconductor device terminal. Background Art

[0002] In the design of power semiconductor devices, the design of the terminal protection area is very important. The design of the active area determines the resistance, capacitance and breakdown voltage of the device, but it is limited by the effectiveness and area of ​​the terminal protection design. In a good terminal design, in order to ensure device reliability, the voltage breakdown point should fall in the active area, not the terminal protection area. At the same time, the area occupied by the terminal will directly affect the on-resistance of the active area.

[0003] As the device performance is better than traditional trench devices, deep trench devices occupy an increasingly larger proportion in power semiconductor devices. However, the terminal design of deep trench devices has become difficult because traditional terminal design cannot solve the problem that the longitudinal electric field distribution of deep trench devices is no longer balanced at the terminal. At present, the terminal of deep trench MOSFET usually directly adopts the oxide layer. Although the process compatibility is good, its terminal withstand voltage is lower than the cell withstand voltage, which limits the overall withstand voltage of the device, resulting in a high on-resistance of the device design and reduced reliability.

[0004] In the prior art, such as Figure 1 As shown, it is a traditional field limiting ring terminal design, which is usually only applicable to planar devices with lateral electric field distribution, and is not applicable to deep trench devices with longitudinal electric field distribution; Figure 2 As shown, it is a deep trench oxide junction voltage-resistant terminal design. The dotted line to the left is the active area 001 and to the right is the terminal protection area 002. The terminal trench relies on the oxide junction thickness to directly resist pressure. Since the electric field is uneven at the terminal, the terminal breakdown voltage is lower than the active area. The breakdown point usually occurs on the inner side of the terminal oxide junction close to the active area, which directly affects the device reliability. Summary of the invention

[0005] The purpose of the present invention is to solve the shortcomings in the prior art and to propose an optimized deep trench semiconductor device terminal.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] An optimized deep trench semiconductor device terminal includes a virtual dotted line, the dotted line to the left is a semiconductor active (cell) area, the dotted line to the right is a terminal protection area, in the top view plane of the semiconductor device, the cell active (cell) area is located at the center of the device, the terminal protection area is located in the outer ring of the active area and surrounds the active area, the device is based on a first conductive type drift area grown on a first conductive type substrate, the lower end of the first conductive type substrate is connected to a drain metal, a second conductive type body area is provided on the first conductive type drift area, a first trench and a second trench are located in the second conductive type body area and extend into the epitaxial layer, a certain thickness of insulating dielectric layer is grown in the first trench and the second trench as a field shielding insulating layer, and then filled with a first conductive polysilicon, a second conductive polysilicon, and a third conductive Polysilicon, fourth conductive polysilicon, fifth conductive polysilicon, sixth conductive polysilicon, a first conductive type source region is arranged on the second conductive type body region of the active region, the first conductive type source region is connected to the source metal, there are source polysilicon and second conductive polysilicon in the groove of the active region, they are respectively connected to the source metal and the gate metal, a second conductive type first well region is arranged at the bottom of the deep trench of the terminal protection region to act as a field limiting ring, the terminal second conductive type first well region A is a floating mesa not connected to the electrode, the source polysilicon is externally connected to the second conductive type first well region B, the source polysilicon is externally connected to the second conductive type first well region C, the source polysilicon is externally connected to the second conductive type second well region B, and so on, each source polysilicon is externally connected to the next adjacent second conductive type second well region.

[0008] Preferably, the widths of the first trench in the active area and the second trench in the terminal protection area may be the same or different, and the depths may be the same or different. The field shielding insulating medium in the deep trench may have the same or different thicknesses in the active area and the terminal protection area.

[0009] Preferably, in the active area, the spacing between adjacent first trenches is the same, and in the terminal protection area, the spacing between the second trench and the last first trench in the active area is less than or equal to the spacing between adjacent trenches in the active area, and then the spacing between adjacent second trenches is the same as that of the active area or gradually increases in the direction from the active area to the terminal protection area.

[0010] Preferably, the second conductivity type first well region A, the second conductivity type first well region B, the second conductivity type first well region C and the second conductivity type second well region A can be formed by implantation in the same process, with an implantation energy range of 10KeV-200KeV and an implantation dose range of 10 12 -10 16 .

[0011] Preferably, the number of deep trenches and field limiting rings designed in the terminal protection area may be more than or equal to one, which is determined by the breakdown voltage of the epitaxial layer and the device active region.

[0012] Preferably, the active area structure can be an up-down structure or a left-right structure, and the second conductive polysilicon can be vertically isolated from the source polysilicon by an insulating dielectric layer on top of the source polysilicon, or the second conductive polysilicon can surround the source polysilicon and be laterally isolated from it by an insulating dielectric layer.

[0013] Preferably, when the device withstands voltage, the first floating mesa of the terminal is designed so that the last mesa of the active area can still be in a charge balance state, and the voltage of the drift region at the lower end of the trench is laterally extended with the help of the deep channel field limiting ring. The terminal conductive polysilicon is connected to the next mesa so that the field limiting ring effect can be effectively transmitted between channels. Reasonable arrangement of the terminal deep channel field limiting ring will make the terminal withstand voltage not limited by the withstand voltage of the active area, thereby obtaining a withstand voltage higher than that of the active area.

[0014] Compared with the prior art, the present invention proposes an optimized deep trench semiconductor device terminal, which has the following beneficial effects:

[0015] The present invention can provide effective terminal protection for deep trench devices; by injecting second conductive type impurities at the bottom of the deep trench, a deeper field limiting ring is formed, so that the electric field at the bottom of the trench can be dispersed, the terminal withstand voltage is higher than the active area, and the reliability is improved; the deep trench oxide layer does not need to be very thick, so the epitaxial layer design can be optimized and the on-resistance of the trench MOSFET can be effectively improved; the deep trench depth design does not need to increase with the increase of voltage, which has a process advantage; the process is compatible, no additional thermal annealing is required, and the overall process of the device is slightly affected; because the second conductive type second well region is circular, the width of the terminal protection area can be effectively reduced, saving chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Designed for traditional field limiting rings;

[0017] Figure 2 This is a schematic diagram of a conventional deep trench oxide junction termination;

[0018] Figure 3 It is a cross-sectional schematic diagram after forming the source metal of the present invention;

[0019] Figure 4 Another form of the present invention;

[0020] Figure 5 It is a schematic cross-sectional view of an epitaxial wafer on a silicon substrate in the first step of the process of the present invention;

[0021] Figure 6 is a schematic cross-sectional view of the active area and the terminal area after the deep trenches are formed;

[0022] Figure 7 This is a schematic diagram of forming a second well region at the bottom of a deep trench and a first well region on the surface by a terminal second type of implantation;

[0023] Figure 8 It is a schematic cross-sectional view after an oxide layer is formed in a deep trench;

[0024] Fig. 9 is a schematic cross-sectional view after source polysilicon is formed in the deep trench oxide layer;

[0025] Fig.10 It is a cross-sectional schematic diagram after the source polysilicon in the active area is pulled back into the trench and covered with an insulating dielectric layer;

[0026] Fig.11 is a schematic cross-sectional view of a gate oxide layer and gate polysilicon after formation;

[0027] Fig.12 is a schematic cross-sectional view of the active region after the second type body region and the first type source region are implanted;

[0028] Fig.13 It is the potential distribution on the cross-sectional schematic diagram when the device is under voltage.

[0029] In the figure: 001 semiconductor active (cell) region, 002 terminal protection area, 1 drain metal, 2 first conductivity type substrate, 3 first conductivity type drift region, 4 field shielding insulating layer, 5 first conductive polysilicon, 6 second conductivity type body region, 7 first conductive type source region, 8 second conductive polysilicon, 9 third conductive polysilicon, 10 fourth conductive polysilicon, 11 fifth conductive polysilicon, 12 sixth conductive polysilicon, 13 second conductive type second well region A, 14 second conductive type first well region A, 15 second conductive type first well region B, 16 second conductive type first well region C, 17 second conductive type second well region B, 18 first trench, 19 second trench. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0032] Please refer to Figure 3-13, an optimized deep trench semiconductor device terminal, including a virtual dotted line, the dotted line to the left is a semiconductor active (cell) area 001, the dotted line to the right is a terminal protection area 002, in the top view plane of the semiconductor device, the cell active (cell) area 001 is located in the center of the device, the terminal protection area 002 is located in the outer ring of the active area and surrounds the active area 001, the device is based on a first conductive type drift area 3 grown on a first conductive type substrate 2, the lower end of the first conductive type substrate 2 is connected to a drain metal 1, a second conductive type body area 6 is provided on the first conductive type drift area, a first trench 18 and a second trench 19 are located in the second conductive type body area and extend into the epitaxial layer 3, a certain thickness of insulating dielectric layer is grown in the first trench 18 and the second trench 19 as a field shielding insulating layer 4, and then filled with a first conductive polysilicon 5, a second conductive polysilicon 8, and a third conductive polysilicon 9. The fourth conductive polysilicon 10, the fifth conductive polysilicon 11, and the sixth conductive polysilicon 12. The second conductive type body region of the active region 001 has a first conductive type source region 7, and the first conductive type source region 7 is connected to the source metal. The active region trench has a first conductive polysilicon 5 and a second conductive polysilicon 8, which are connected to the source metal and the gate metal respectively. At the bottom of the deep trench of the terminal protection zone, there is a second conductive type first well region 13 acting as a field limiting ring. The terminal second conductive type first well region A14 is a floating mesa and is not connected to the electrode. The fourth conductive polysilicon 10 is externally connected to the second conductive type first well region B15, the fifth conductive polysilicon 11 is externally connected to the second conductive type first well region C16, and the sixth conductive polysilicon 12 is externally connected to the second conductive type second well region B17, and so on. Each source polysilicon is externally connected to the next adjacent second conductive type second well region.

[0033] The widths of the first trench 18 in the active area 001 and the second trench 19 in the terminal protection area 002 may be the same or different, and their depths may be the same or different. The field shielding insulating medium in the deep trench may have the same or different thicknesses in the active area 001 and the terminal protection area.

[0034] In the active area 001, the spacing between adjacent first trenches 18 is the same, and in the terminal protection area 002, the spacing between the second trench 19 and the last first trench 18 in the active area is less than or equal to the spacing between adjacent trenches in the active area, and then the spacing between adjacent second trenches 19 is the same as that of the active area or gradually increases in the direction from the active area 001 to the terminal protection area 002.

[0035] The second conductivity type first well region A14, the second conductivity type first well region B15, the second conductivity type first well region C16 and the second conductivity type second well region A13 can be formed by implantation in the same process, with an implantation energy range of 10KeV-200KeV and an implantation dose range of 10 12 -10 16 .

[0036] The number of deep trenches and field limiting rings designed in the terminal protection zone may be more than or equal to one, which is determined by the breakdown voltage of the epitaxial layer and the device active region.

[0037] The active area structure can be an up-down structure or a left-right structure. The second conductive polysilicon 8 can be vertically isolated from the source polysilicon by an insulating dielectric layer on top of the source polysilicon, or the second conductive polysilicon 8 can surround the source polysilicon and be laterally isolated from the source polysilicon by an insulating dielectric layer.

[0038] When the device withstands voltage, the design of the first floating mesa of the terminal ensures that the last mesa of the active area can still be in a charge balance state, and the voltage of the drift region at the lower end of the trench is laterally extended with the help of the deep trench field limiting ring. The terminal conductive polysilicon is connected to the next mesa to enable the field limiting ring effect to be effectively transmitted between channels. Reasonable arrangement of the terminal deep trench field limiting ring will make the terminal withstand voltage not limited by the withstand voltage of the active area, thereby obtaining a withstand voltage higher than that of the active area.

[0039] In this embodiment, taking an N-type deep trench power semiconductor device as an example, a first conductive substrate 2 is provided on the drain metal 1, an N-type epitaxial layer 3 is provided on the first conductive substrate 2, a first trench 18 and a second trench 19 are located in the p-type body region and extend into the epitaxial layer 3, an insulating dielectric layer of a certain thickness is grown in the first trench 18 and the second trench 19 as a field shielding insulating layer 4, and is filled with a first conductive polysilicon 5, a second conductive polysilicon 8, a third conductive polysilicon 9, a fourth conductive polysilicon 10, a fifth conductive polysilicon 11, and a sixth conductive polysilicon 12, a first conductive type source region 7 is provided on the p-type body region of the active region 001, the first conductive type source region 7 is connected to the source metal, the first conductive polysilicon 5 and the second conductive polysilicon 8 are in the active region trench, they are connected to the source metal and the gate metal respectively, the periphery of the gate polysilicon is a gate oxide layer, a first p-type well region is provided at the bottom of the deep trench in the terminal protection zone to act as a field limiting ring, and a second p-type well region is provided on the terminal surface. The first second p-type well region 14 at the terminal is a floating mesa and is not connected to an electrode. The fourth conductive polysilicon 10 is externally connected to the second p-type well region 15. The fifth conductive polysilicon 11 is externally connected to the second p-type well region 16. The sixth conductive polysilicon 12 is externally connected to the second p-type well region 17. And so on. Each source polysilicon is externally connected to the next adjacent p-type well region mesa.

[0040] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An optimized deep trench semiconductor device terminal, characterized in that: The invention comprises a dotted line with a virtual setting, wherein the semiconductor active area is to the left of the dotted line, and the terminal protection area is to the right of the dotted line. On the top-view plane of the semiconductor device, the cell active area is located at the center of the device, and the terminal protection area is located at the outer circle of the active area and surrounds the active area. The device is based on a first conductive type drift area grown on a first conductive type substrate, and the lower end of the first conductive type substrate is connected to a drain metal. A second conductive type body area is arranged on the first conductive type drift area, and a first trench and a second trench are located in the second conductive type body area and extend into the epitaxial layer. An insulating dielectric layer of a certain thickness is grown in the first trench and the second trench as a field shielding insulating layer, and is then filled with a first conductive polysilicon, a second conductive polysilicon, a third conductive polysilicon, a fourth conductive polysilicon, and a first conductive polysilicon. The fifth conductive polysilicon and the sixth conductive polysilicon have a first conductive type source region on the second conductive type body region of the active region, the first conductive type source region is connected to the source metal, the active region trench has source polysilicon and second conductive polysilicon, they are connected to the source metal and the gate metal respectively, a second conductive type second well region A is provided at the bottom of the deep trench of the terminal protection zone to act as a field limiting ring, the terminal second conductive type first well region A is a floating mesa not connected to the electrode, the source polysilicon is externally connected to the second conductive type first well region B, the source polysilicon is externally connected to the second conductive type first well region C, the source polysilicon is externally connected to the second conductive type second well region B, and so on, each source polysilicon is externally connected to the next adjacent second conductive type second well region; The number of deep trenches and field limiting rings designed in the terminal protection zone is greater than or equal to one, which is determined by the breakdown voltage of the epitaxial layer and the device active region; The active area structure is an up-down structure or a left-right structure, the second conductive polysilicon is vertically isolated from the source polysilicon by an insulating dielectric layer, or the second conductive polysilicon surrounds the source polysilicon and is horizontally isolated from the source polysilicon by an insulating dielectric layer.

2. An optimized deep trench semiconductor device terminal according to claim 1, characterized in that: The width of the first trench in the active area and the second trench in the terminal protection area are the same or different, and the depth is the same or different. The field shielding insulating medium in the deep trench has the same or different thickness in the active area and the terminal protection area.

3. An optimized deep trench semiconductor device terminal according to claim 1, characterized in that: In the active area, the spacing between adjacent first grooves is the same, and in the terminal protection area, the spacing between the second groove and the last first groove in the active area is less than or equal to the spacing between adjacent grooves in the active area, and then the spacing between adjacent second grooves is the same as that of the active area or gradually increases in the direction from the active area to the terminal protection area.

4. An optimized deep trench semiconductor device terminal according to claim 1, characterized in that: The second conductivity type first well region A, the second conductivity type first well region B, the second conductivity type first well region C and the second conductivity type second well region A can be formed by implantation in the same process, and the implantation energy range is 10KeV-200KeV, and the implantation dose range is 10 12 -10 16 .

5. The optimized deep trench semiconductor device terminal according to claim 1, characterized in that: When the device withstands voltage, the design of the first floating mesa of the terminal ensures that the last mesa of the active area is still in a charge balance state, and the voltage of the drift region at the lower end of the trench is laterally extended with the help of the deep trench field limiting ring. The terminal conductive polysilicon is connected to the next mesa so that the field limiting ring effect is effectively transmitted between channels. Reasonable arrangement of the terminal deep trench field limiting ring will make the terminal withstand voltage not limited by the withstand voltage of the active area, thereby obtaining a withstand voltage higher than that of the active area.

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