Display Devices

Abstract

A display device includes: a display unit including a gate line, a data line, and a pixel electrically coupled to the gate line and the data line; a controller configured to calculate a load of input data; a data driver configured to generate a data signal corresponding to a grayscale value in the input data and provide the data signal to the data line; a gate driver configured to generate a gate signal having a pulse based on a gate-on voltage and provide the gate signal to the gate line; and a power supply configured to provide a gate-on voltage to the gate driver and change the gate-on voltage based on the load, wherein the gate-on voltage has a voltage level that turns on a first transistor, and wherein the brightness of the display unit increases as the load increases.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0022373, filed on February 26, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of some example embodiments of the present disclosure generally relate to a display device. Background Art

[0004] The display apparatus may display an image on a display panel by using a control signal applied from the outside.

[0005] The display panel includes pixels, and each of the pixels includes a light emitting element and a driving transistor for controlling the amount of driving current flowing through the light emitting element. As the amount of driving current flowing through the light emitting element increases, the light emitting element can emit light with high brightness. As the voltage applied between the gate electrode and one electrode of the driving transistor increases, the amount of driving current increases, but the power consumption of the display device also increases.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] Aspects of some example embodiments include a display device capable of emitting light having relatively high brightness while minimizing (or maintaining relatively low) an increase in average power consumption of the display device.

[0008] According to some example embodiments of the present disclosure, a display device includes: a display unit including a gate line, a data line, and a pixel electrically coupled to the gate line and the data line, wherein the pixel includes a first transistor electrically coupled to the gate line; a controller configured to calculate a load of input data; a data driver configured to generate a data signal corresponding to a grayscale value included in the input data and provide the data signal to the data line; a gate driver configured to generate a gate signal having a pulse based on a gate-on voltage and provide the gate signal to the gate line; and a power supply configured to provide a gate-on voltage to the gate driver and change the gate-on voltage based on the load, wherein the gate-on voltage has a voltage level that turns on the first transistor, wherein the brightness of the display unit increases as the load increases.

[0009] According to some example embodiments, the display unit may further include a first power line and a second power line. The pixel may further include a second transistor and a light emitting element electrically coupled in series between the first power line and the second power line. The first transistor may transmit the data signal to the gate electrode of the second transistor in response to the gate signal.

[0010] According to some example embodiments, each of the first transistor and the second transistor may be an N-type transistor.

[0011] According to some example embodiments, the power supply may provide the gate driver with a gate-off voltage having a voltage level that turns off the first transistor. The gate-off voltage may be constant and not changed. As the load increases, the power supply may linearly increase the difference between the gate-off voltage and the gate-on voltage.

[0012] According to some example embodiments, in a first range where the load is less than a first reference load, the gate-on voltage may be a constant voltage having a first reference voltage level.

[0013] According to some example embodiments, in a second range where the load is greater than a second reference load, the gate-on voltage may be a constant voltage having a second reference voltage level. The second reference load may be greater than the first reference load.

[0014] According to some example embodiments, the power supply may determine a target voltage level of the gate-on voltage based on the load, and linearly change the voltage level of the gate-on voltage to the target voltage level during a reference time.

[0015] According to some example embodiments, a change in gate-on voltage per unit time may be constant.

[0016] According to some example embodiments, the pixel may further include a third transistor electrically coupled between the reference power line and one electrode of the light emitting element.The power supply may generate and supply a reference voltage to the reference power line, and change the reference voltage based on the load.

[0017] According to some example embodiments, the power supply may generate a first power voltage and apply the first power voltage to the first power line, and change the first power voltage based on a load.

[0018] According to some example embodiments, a power supply may include: a voltage determiner configured to determine a target gate-on voltage based on a load; and a first voltage generator configured to generate the gate-on voltage based on the target gate-on voltage.

[0019] According to some example embodiments, the voltage determiner may determine each of the target reference voltage and the target power voltage based on the load. The power supply may further include: a second voltage generator configured to generate a reference voltage based on the target reference voltage; and a third voltage generator configured to generate the first power voltage based on the target power voltage.

[0020] According to some example embodiments, each of the first transistor and the second transistor may be a P-type transistor.

[0021] According to some example embodiments, as the load increases, the power supply may linearly decrease the voltage level of the gate-on voltage.

[0022] According to some example embodiments of the present disclosure, a display device includes: a display unit including a gate line, a data line, and a pixel electrically coupled to the gate line and the data line, wherein the pixel includes a first transistor electrically coupled to the gate line; a data driver configured to generate a data signal corresponding to a grayscale value included in input data and provide the data signal to the data line; a gate driver configured to generate a gate signal having a pulse based on a gate-on voltage and provide the gate signal to the gate line; and a power supply configured to provide the gate-on voltage to the gate driver and change the gate-on voltage based on a dimming level, wherein the gate-on voltage has a voltage level that turns on the first transistor, wherein a maximum brightness of the display unit changes according to the dimming level.

[0023] According to some example embodiments of the present disclosure, the display device changes the gate-on voltage that turns on the transistor provided in the pixel. Therefore, the display device can display an image with relatively high brightness while minimizing (or maintaining relatively low) the increase in average power consumption of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, however, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0025] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the text, the same reference numerals refer to the same elements.

[0026] Figure 1 is a diagram illustrating a display device according to some example embodiments of the present disclosure.

[0027] Figure 2 The diagram is included in Figure 1A circuit diagram of an example of a pixel in a display device shown in FIG.

[0028] Figure 3 It is shown in Figure 2 Graph showing an example of a waveform of a signal measured in a pixel shown in FIG.

[0029] Figure 4 The diagram is included in Figure 1 A block diagram of an example of a power supply in a display device is shown in FIG.

[0030] Figure 5 It is confirmed by the diagram Figure 4 An example of a target gate-on voltage in a power supply is shown in FIG.

[0031] Figure 6 The diagram is from Figure 4 An example of the gate-on voltage of the power supply output is shown in the diagram.

[0032] Figure 7 The diagram is included in Figure 1 A block diagram of another example of a power supply in a display device is shown in FIG.

[0033] Figure 8 It is confirmed by the diagram Figure 7 An example of a target reference voltage in a power supply is shown in FIG.

[0034] Fig. 9 It is confirmed by the diagram Figure 7 Graph of an example of a target power voltage in a power supply shown in FIG.

[0035] Fig.10 The diagram is from Figure 7 An example of the voltage output by a power supply is shown in the diagram.

[0036] Fig.11 It is confirmed by the diagram Figure 7 An example of a target gate-on voltage in a power supply is shown in FIG.

[0037] Fig.12 is a diagram illustrating a display device according to some example embodiments of the present disclosure.

[0038] Fig.13 The diagram is included in Fig.12 A circuit diagram of an example of a pixel in a display device shown in FIG.

[0039] Fig.14 It is shown in Fig.13 Graph showing an example of a waveform of a signal measured in a pixel shown in FIG. DETAILED DESCRIPTION

[0040] Hereinafter, aspects of some example embodiments are described in more detail with reference to the accompanying drawings so that those skilled in the art can more easily practice the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the example embodiments described in this specification.

[0041] In order to more clearly describe the present disclosure, certain parts or aspects that are not necessary for a person of ordinary skill in the art to understand the description of the embodiments of the present invention may be omitted, and throughout the specification, the same or similar components will be represented by the same reference numerals. Therefore, the same reference numerals may be used in different drawings to identify the same or similar elements.

[0042] Figure 1 is a diagram illustrating a display device according to some example embodiments of the present disclosure.

[0043] refer to Figure 1 , the display device 1 may include a display unit (or display) 110 , a data driver 120 , a gate driver 130 , a controller 140 , a power supply 150 , and a sensing driver 160 .

[0044] The display unit 110 may display an image. The display unit 110 may be implemented using a display panel.

[0045] The display unit 110 may include data lines DL1 to DLm (m is a positive integer), gate lines GL1 to GLn (n is a positive integer), sensing lines SEN1 to SENm (or reference power lines), control lines CL1 to CLn, and pixels PX. The pixels PX may be arranged in an area defined by the data lines DL1 to DLm and the gate lines GL1 to GLn. The pixels PX may be electrically coupled to the data lines DL1 to DLm and the gate lines GL1 to GLn. In addition, the pixels PX may be electrically coupled to the sensing lines SEN1 to SENm and the control lines CL1 to CLn.

[0046] However, the pixel PX is not limited thereto. For example, the pixel PX may be electrically coupled to a gate line corresponding to an adjacent row (e.g., a gate line corresponding to a row before the row in which the pixel PX is included and a gate line corresponding to a row after the row in which the pixel PX is included). According to some example embodiments, the pixel PX may be electrically coupled to a first power line and a second power line to receive a first power voltage VDD and a second power voltage VSS through the first power line and the second power line, respectively. The first power voltage VDD and the second power voltage VSS may be voltages necessary (or utilized) to drive the pixel PX.

[0047] The pixel PX may emit light having a brightness corresponding to a data signal provided through a corresponding data line in response to a gate signal provided through a corresponding gate line. Figure 2An example configuration and operation of the pixel PX is described in more detail.

[0048] The data driver 120 may generate a data signal based on the data control signal DCS and the image data DATA2 and provide the data signal to the data lines DL1 to DLm. The data control signal DCS is a signal for controlling the operation of the data driver 120 and may include a data enable signal and the like.

[0049] The gate driver 130 (or scan driver) may generate a gate signal based on the gate control signal GCS and provide the gate signal to the gate lines GL1 to GLn. The gate control signal GCS is a signal for controlling the operation of the gate driver 130 and may include a start signal, a clock signal, etc. For example, the gate driver 130 may sequentially generate and output a gate signal corresponding to the start signal (e.g., a gate signal having a waveform identical or similar to that of the start signal) by using a clock signal. The gate driver 130 may include a shift register.

[0050] In addition, the gate driver 130 may generate a control signal based on the gate control signal GCS and provide the control signal to the control lines CL1 to CLn. For example, the gate driver 130 may sequentially generate and output the control signal by using a clock signal. Although the case where the gate driver 130 generates the gate signal and the control signal is illustrated, the circuit for generating the control signal may be implemented using a separate driver independent of the gate driver 130.

[0051] In some embodiments, the gate driver 130 may be supplied with a gate-on voltage VON and a gate-off voltage VOFF from the power supply 150, and generates a gate signal (and a control signal) obtained by combining the gate-on voltage VON and the gate-off voltage VOFF. The gate-on voltage VON may have a voltage level that turns on a transistor provided in the pixel PX, the gate driver 130, etc., and the gate-off voltage VOFF may have a voltage level that turns off the transistor.

[0052] The controller 140 (or timing controller) may receive a control signal CS from an external source (eg, a graphics processor) and generate a gate control signal GCS and a data control signal DCS based on the control signal CS. The control signal CS may include a clock signal, a horizontal synchronization signal, a data enable signal, etc.

[0053] In addition, the controller 140 may receive input image data DATA1 (eg, RGB data) from an external source, convert the input image data DATA1 into image data DATA2 suitable for the pixel arrangement of the display unit 110, and then output the image data DATA2. The input image data DATA1 may include gray values ​​corresponding to the pixels PX.

[0054] In some embodiments, the controller 140 may calculate or predict the load LOAD (or load information) of the display device 1 based on the input image data DATA1. According to some example embodiments, the controller 140 may calculate the load LOAD by averaging the grayscale values ​​included in the input image data DATA1 provided at the current time. According to some example embodiments, the controller 140 may determine the load LOAD by calculating the on-pixel ratio of the pixels in the display unit 110 (e.g., the ratio of the pixels driven corresponding to the input image data DATA1) based on the input image data DATA1. The load LOAD (or load information) may be provided to the power supply 150. Meanwhile, although the case where the controller 140 analyzes the input image data DATA1 is described, the embodiments according to the present disclosure are not limited thereto.

[0055] The power supply 150 (or driving voltage generator) generates a gate-on voltage VON and a gate-off voltage VOFF, and may change the voltage level of the gate-on voltage VON based on the load LOAD. For example, when the load LOAD increases (for example, when the target brightness of the display device 1 increases as the load LOAD increases), the power supply 150 may increase the gate-on voltage VON. In some embodiments, the gate-off voltage VOFF may be constant and not changed. This will be referred to later. Figure 4 An example configuration of the power supply 150 that changes the gate-on voltage VON is described in more detail.

[0056] When the gate-on voltage VON increases, the voltage level of the gate signal generated by the gate driver 130 (eg, the voltage level of the gate-on voltage VON) increases, and the driving current flowing through the pixel PX increases. Therefore, the overall brightness of the display unit 110 can be increased.

[0057] In some embodiments, the power supply 150 may generate a reference voltage VREF (or an initialization voltage) and provide the reference voltage VREF to the sensing driver 160. The reference voltage VREF is a voltage applied in order for the sensing driver 160 to sense the characteristics of the pixel PX in the display unit 110 (e.g., a voltage applied to one end of the light emitting element of the pixel PX), and may have a voltage level lower than a threshold voltage of the light emitting element.

[0058] In some embodiments, the power supply 150 may change the reference voltage VREF based on the load LOAD. Similar to the gate-on voltage VON, the driving current flowing through the pixel PX may change according to the change of the reference voltage VREF, and thus, the overall brightness of the display unit 110 may change.

[0059] The sensing driver 160 is electrically coupled to the sensing lines SEN1 to SENm and senses the deviation of each of the sensing lines SEN1 to SENm (ie, deviation information of a channel). For example, the sensing driver 160 may sense the capacitance of a parasitic capacitor formed on each of the sensing lines SEN1 to SENm.

[0060] At the same time, despite Figure 1 , the sensing driver 160 is electrically coupled to the sensing lines SEN1 to SENm, but the embodiments of the present disclosure are not limited thereto. For example, the present disclosure may be applied to various external compensation methods currently known in the art, and the sensing driver 160 may be electrically coupled to the data lines DL1 to DLm. The sensing driver 160 may sense the capacitance of the parasitic capacitor formed on each of the data lines DL1 to DLm as deviation information.

[0061] The sensing driver 160 may sense characteristic information of the pixel PX. For example, the sensing driver 160 may apply a reference voltage VREF to the sensing lines SEN1 to SENm and sense threshold voltage information and mobility information of a driving transistor included in the pixel PX and / or degradation information of an organic light emitting diode included in the pixel PX as characteristic information of the pixel PX.

[0062] The sensing driver 160 may convert the deviation information of the channel and the characteristic information of the pixel PX into digital first sensing data and digital second sensing data DATA_S, respectively, and output the first sensing data and the second sensing data DATA_S. To this end, the sensing driver 160 may include an analog-to-digital converter (ADC). The first sensing data and the second sensing data DTAT_S output from the sensing driver 160 may be stored in a storage device.

[0063] The first sensing data and the second sensing data DTAT_S stored in the storage device may be used when converting the input image data DATA1 so that the characteristic deviation of the pixel PX may be compensated. For example, the controller 140 may remove the deviation of the channel from the second sensing data DATA_S by using the first sensing data, and compensate the image data DATA2 by using the second sensing data DATA_S in which the deviation of the channel is removed. The compensated image data DATA2 may be provided to the data driver 120.

[0064] Each of the data driver 120, the gate driver 130, the controller 140, the power supply 150, and the sensing driver 160 may be directly mounted on the display unit 110 in the form of at least one integrated circuit chip, may be attached to the display unit 110 in the form of a tape carrier package (TCP), or may be mounted on a separate printed circuit board. Alternatively, at least one of the data driver 120, the gate driver 130, the power supply 150, and the sensing driver 160 may be integrated on the display unit 110 together with the signal lines GL1 to GLn, DL1 to DLm, etc.

[0065] As reference Figure 1 As described, the power supply 150 changes the gate-on voltage VON (and the reference voltage VREF) based on the load LOAD of the display device 1 (the load LOAD is calculated based on the load input image data DATA1) so that the overall brightness of the display unit 110 can be increased.

[0066] At the same time, despite Figure 1 1 illustrates a case where the first power voltage VDD and the second power voltage VSS are independently provided to the display unit 110, but the embodiments of the present disclosure are not limited thereto. For example, the power supply 150 may generate the first power voltage VDD and the second power voltage VSS, and provide the first power voltage VDD and the second power voltage VSS to the display unit 110. In addition, the power supply 150 may change at least one of the first power voltage VDD and the second power voltage VSS based on the load LOAD.

[0067] Figure 2 The diagram is included in Figure 1 A circuit diagram of an example of a pixel in a display device shown in FIG.

[0068] refer to Figure 2 , the pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst, and a light emitting element LD.

[0069] The first to third transistors T1, T2 and T3 may be implemented using N-type transistors (e.g., NMOS transistors), but are not limited thereto according to the embodiments of the present disclosure. For example, at least one of the first to third transistors T1, T2 and T3 may be implemented using a P-type transistor (e.g., a PMOS transistor). In addition, the pixel PX may further include other transistors in addition to the first to third transistors T1, T2 and T3.

[0070] The first transistor T1 (or driving transistor) may include a first electrode electrically coupled to the first power line to which the first power voltage VDD is applied, a second electrode electrically coupled to the second node N2 , and a gate electrode electrically coupled to the first node N1 .

[0071] The second transistor T2 (or the switching transistor) may include a first electrode electrically coupled to the data line DL, a second electrode electrically coupled to the first node N1, and a gate electrode electrically coupled to the gate line GL. The data line DL may be Figure 1 One of the data lines DL1 to DLm shown in FIG. 1 , and the gate line GL may be Figure 1 One of the gate lines GL1 to GLn shown in FIG.

[0072] The second transistor T2 may be turned on in response to a gate signal provided through the gate line GL and transmit a data signal provided through the data line DL to the first node N1. For example, the gate signal may be a pulse-shaped signal or a pulse signal having a gate-on voltage VON (or an on voltage level) that turns on the transistor.

[0073] The storage capacitor Cst may be electrically coupled between the first node N1 and the second node N2. The storage capacitor Cst may temporarily store a data signal applied to the first node N1. The first transistor T1 may control the amount of the driving current Id flowing from the first power line through the light emitting element LD via the second node N2 in response to the data signal stored in the storage capacitor Cst.

[0074] The light emitting element LD (or light emitting diode) may include an anode electrode (or a first pixel electrode) electrically coupled to the second node N2 and a cathode electrode (or a second pixel electrode) electrically coupled to a second power line to which a second power voltage VSS is applied. For example, the light emitting element LD may be an organic light emitting diode or an inorganic light emitting diode. The light emitting element LD may emit light having a brightness corresponding to the driving current Id (or the amount of the driving current Id).

[0075] The third transistor T3 (or sensing transistor) may include a first electrode electrically coupled to a sensing line SEN (or a reference power line), a second electrode electrically coupled to a second node N2, and a gate electrode electrically coupled to a control line CL. The sensing line SEN may be Figure 1 One of the sensing lines SEN1 to SENm shown in FIG. 1 , and the control line CL may be Figure 1 One of the control lines CL1 to CLn shown in FIG.

[0076] The third transistor T3 can be turned on in response to a control signal provided through the control line CL, and transmit the reference voltage VREF provided through the sensing line SEN to the second node N2. For example, similar to the gate signal, the control signal can be a pulse signal having a gate-on voltage VON (or a turn-on voltage level) that turns on the transistor. For example, when the reference voltage VREF is applied to the second node N2, the second node N2 can be initialized by the reference voltage VREF, and the sensing current can be output to the outside from the first power line (i.e., the first power line to which the first power voltage VDD is applied) through the first transistor T1, the second node N2, the third transistor T3 and the sensing line SEN. Reference Figure 1 The described sensing driver 160 may sense characteristics (eg, threshold voltage information, mobility information, etc.) of the first transistor T1 based on the sensing current.

[0077] Reference Figure 3 An example operation of the pixel PX is described in more detail.

[0078] Figure 3 It is shown in Figure 2 2 is a waveform diagram of an example of a signal measured in a pixel shown in FIG. Figure 3 , the gate signal SCAN1, the control signal SCAN2, and the driving current Id according to the passage of time are illustrated.

[0079] refer to Figure 2 and Figure 3 , the gate signal SCAN1 may be changed from a logic low level VGL to a first logic high level VGH1 at a first time t1, and maintained as a first logic high level VGH1 between the first time t1 and the second time t2 (i.e., during the first period P1). The logic low level VGL may be a gate-off voltage VOFF that turns off the N-type transistor, and the first logic high level VGH1 may be a gate-on voltage VON that turns on the N-type transistor. The gate signal SCAN1 having the first logic high level VGH1 may allow the NMOS transistor to operate in a saturation region. In the first period P1, the control signal SCAN2 may have a logic low level VGL.

[0080] The second transistor T2 may be turned on in response to the gate signal SCAN1 having the first logic high level VGH1, the data signal of the data line DL may be applied to the first node N1, and the storage capacitor Cst may store or maintain the data signal. The first transistor T1 may transmit the driving current Id having the first amplitude I1 to the light emitting element LD in response to the data signal, and the light emitting element LD may emit light having a brightness corresponding to the driving current Id having the first amplitude I1.

[0081] Subsequently, at the third time t3, the gate signal SCAN1 may have a logic low level VGL, and the control signal SCAN2 may change from the logic low level VGL to the first logic high level VGH1. In addition, the control signal SCAN2 may be maintained at the first logic high level VGH1 between the third time t3 and the fourth time t4 (ie, during the second period P2).

[0082] The third transistor T3 may be turned on in response to the control signal SCAN2 having the first logic high level VGH1, and the reference voltage VREF of the sensing line SEN may be applied to the second node N2. A sensing current may flow through the third transistor T3 and the sensing line SEN corresponding to the reference voltage VREF, and the reference voltage VREF may be applied to the second node N2. Figure 1 The described sensing driver 160 may sense the characteristics of the pixel PX based on the sensing current. Alternatively, when the third transistor T3 is turned on in response to the control signal SCAN2 having the first logic high level VGH1, the voltage of the second node N2 may be output to the outside through the sensing line SEN, and the characteristics of the pixel PX may be sensed based on the voltage of the second node N2.

[0083] The signals SCAN1 and SCAN2 at the fifth time t5 may be substantially the same as the signals SCAN1 and SCAN2 at the first time t1. That is, a period between the first time t1 and the fifth time t5 may be defined as one frame 1FRAME, and the pixel PX may be repeatedly operated in units of frames.

[0084] In some embodiments, when the Figure 1 When the load LOAD of the input image data DATA1 of the display device 1 shown in increases, the voltage level of the gate-on voltage VON of the gate signal SCAN1 (and the control signal SCAN2 ) may increase.

[0085] exist Figure 3 At the sixth time t6 shown in FIG. , the load LOAD may have a value greater than the value of the load LOAD at the first time t1. For example, the average value of the grayscale value included in the input image data DATA1 may increase, and Figure 1 The target brightness of the display device 1 (or display unit 110) shown in FIG. 1 may be increased.

[0086] Therefore, the gate signal SCAN1 at the sixth time t6 may have a second logic high level VGH2. The second logic high level VHG2 is a voltage level greater than the first logic high level VGH1. For example, a voltage difference AP2 of the second logic high level VGH2 relative to the logic low level VGL may be greater than a voltage difference AP1 of the first logic high level VGH1 relative to the logic low level VGL.

[0087] The second transistor T2 may be turned on in response to the gate signal SCAN1 having the second logic high level VGH2. In theory, since the second transistor T2 operates in the saturation region, the operation of the second transistor T2 according to the second logic high level VGH2 (e.g., a switching operation, an amount of current flowing according to the switching operation, and a voltage transmitted according to the switching operation) may be substantially the same as the operation of the second transistor T2 according to the first logic high level VGH1. In addition, the operation of the pixel PX to which the gate signal SCAN1 having the second logic high level VGH2 is applied may be substantially the same as the operation of the pixel PX to which the gate signal SCAN1 having the first logic high level VGH1 is applied.

[0088] However, due to various reasons (e.g., the material of the second transistor T2, etc.), the driving current Id having the second amplitude I2 greater than the first amplitude I1 may flow through the pixel PX (or the light emitting element LD), and the pixel PX may emit light with higher brightness with respect to the same data (i.e., the same data signal as the data signal applied at the first time t1). That is, when the gate-on voltage VON of the gate signal SCAN1 increases, the display device 1 may display an image corresponding to the same input image data DATA1 with higher brightness.

[0089] At the same time, despite Figure 3 FIG. 4 illustrates a case where the gate-on voltage VON of the control signal SCAN2 has a second logic high level VGH2 greater than the first logic high level VGH1 when the load LOAD increases, but the embodiments of the present disclosure are not limited thereto. For example, when Figure 1 When the gate driver 130 shown in FIG. 1 independently receives each of the gate-on voltage VON having the first logic high level VGH1 and the gate-on voltage VON having the second logic high level VGH2 from the power supply 150, the gate driver 130 can generate the control signal SCAN2 having the first logic high level VGH1 using the gate-on voltage VON having the first logic high level VGH1 regardless of the load LOAD.

[0090] Figure 4 The diagram is included in Figure 1 A block diagram of an example of a power supply in a display device is shown in FIG.

[0091] refer to Figure 1 and Figure 4 , the power supply 150 may include a voltage determiner 151 and a first voltage generator 152 .

[0092] The voltage determiner 151 may determine a target voltage level (ie, a target gate-on voltage VON_T) of the gate-on voltage VON based on the load LOAD (or load information) provided from the controller 140 .

[0093] The first voltage generator 152 may generate a gate-on voltage VON having a voltage level corresponding to the target gate-on voltage VON_T determined by the voltage determiner 151 (i.e., having a voltage level according to the target gate-on voltage VON_T), and provide the gate-on voltage VON to the gate driver 130. According to some example embodiments, when the first voltage generator 152 is provided with a variable resistor electrically coupled to an output terminal of the first voltage generator 152, the first voltage generator 152 may change the gate-on voltage VON by linearly changing the variable resistor. According to some example embodiments, when the first voltage generator 152 is implemented using a converter including a switching transistor, the first voltage generator 152 may change the gate-on voltage VON by changing a switching speed of the switching transistor.

[0094] Reference Figure 5 A more detailed operation of the voltage determiner 151 is described.

[0095] Figure 5 It is confirmed by the diagram Figure 4 An example of a target gate turn-on voltage in a power supply is shown in FIG. Figure 5 , the change of the target gate-on voltage VON_T with respect to the change of the load LOAD is illustrated.

[0096] refer to Figure 5 , in a range (or period) where the load LOAD is less than the first reference load LOAD_REF1 (for example, when the load LOAD is the first load LOAD1), the voltage determiner 151 may determine the minimum gate-on voltage VON_MIN (or the first reference voltage level) as the target gate-on voltage VON_T. The minimum gate-on voltage VON_MIN is a voltage having a minimum value among the voltages that cause the transistor to operate in the saturation region. For example, the minimum gate-on voltage VON_MIN may be 20V like the conventional gate-on voltage. The first reference load LOAD_REF1 is the minimum load for which the brightness of the display device 1 needs to be compensated. For example, the first reference load LOAD_REF1 may be about 70% relative to the maximum brightness of the display device 1.

[0097] In a range where the load LOAD is greater than the first reference load LOAD_REF1 and less than the second reference load LOAD_REF2 (e.g., when the load LOAD is the second load LOAD2), the voltage determiner 151 may linearly change the target gate-on voltage VON_T according to the load LOAD. The second reference load LOAD_REF2 is the maximum load for which the brightness of the display device 1 needs to be compensated. For example, the second reference load LOAD_REF2 may be about 90% relative to the maximum brightness of the display device 1.

[0098] When the load LOAD increases from the first reference load LOAD_REF1 to the second reference load LOAD_REF2 , the voltage determiner 151 may linearly increase the target gate-on voltage VON_T from the minimum gate-on voltage VON_MIN (eg, 20 V) to the maximum gate-on voltage VON_MAX (eg, 30 V).

[0099] For example, the brightness of the display device 1 to which the gate signal SCAN1 having the minimum gate-on voltage VON_MIN (e.g., 20V) is applied may be 158 nits, the brightness of the display device 1 to which the gate signal SCAN1 having a voltage between the minimum gate-on voltage VON_MIN and the maximum gate-on voltage VON_MAX (e.g., 25V) is applied may be 296 nits, and the brightness of the display device 1 to which the gate signal SCAN1 having the maximum gate-on voltage VON_MAX is applied may be 430 nits. That is, the brightness of the display device 1 may increase as the gate-on voltage VON increases.

[0100] In a range where the load LOAD is greater than the second reference load LOAD_REF2 (eg, when the load LOAD is the third load LOAD3 ), the voltage determiner 151 may determine the maximum gate-on voltage VON_MAX (or the second reference voltage level) as the target gate-on voltage VON_T.

[0101] As reference Figure 5 As described, when the load LOAD is relatively large, the voltage determiner 151 linearly increases the target gate-on voltage VON_T in proportion to the increase of the load LOAD, and thus, the first voltage generator 152 may generate and output a relatively high gate-on voltage VON.

[0102] When the gate-on voltage VON has a relatively high voltage level, the stress of the transistor in the display unit 110 (or the pixel PX) may increase, and the life of the display unit 110 (or the pixel PX) may be shortened. Therefore, the display device 1 adaptively changes the gate-on voltage VON according to the load LOAD, so that the increase in stress relative to the display unit 110 (or the increase in power consumption corresponding to the display unit 110) can be minimized, and an image can be displayed at a higher brightness when necessary.

[0103] In some embodiments, the power supply 150 (or the first voltage generator 152 ) may change the gate-on voltage VON at a specific rate of change or time.

[0104] Reference Figure 6 A more detailed operation of the power supply 150 is described.

[0105] Figure 6 The diagram is from Figure 4An example of the gate-on voltage of the power supply output is shown in FIG. Figure 6 , the change of the gate-on voltage VON with respect to the change of the load LOAD is illustrated.

[0106] refer to Figure 4 and Figure 6 , in the reference frame F0, the load LOAD may be changed to a second load LOAD2 which is larger than the first load LOAD1. Figure 3 The description corresponds to a frame 1FRAME. Figure 5 As described, the first load LOAD1 may be less than Figure 5 The first reference load LOAD_REF1 shown in , and the second load LOAD2 may be greater than the first reference load LOAD_REF1.

[0107] The power supply 150 (or the first voltage generator 152) can change the gate-on voltage VON from the first gate-on voltage VON1 (e.g., the minimum gate-on voltage VON_MIN) to the second gate-on voltage VON2 (e.g., the maximum gate-on voltage VON_MAX) based on the reference change rate GRAD. For example, the reference change rate GRAD can be 1V / FRAME, that is, 1V per frame. When the voltage level of the gate-on voltage VON changes rapidly, the brightness of the display device 1 increases rapidly. Therefore, the flicker of the image can be viewed by the user, or the stress temporarily applied to the display device 1 can be increased. Therefore, the power supply 150 gradually increases the gate-on voltage VON so that the flicker viewed by the user and the stress temporarily applied to the display device 1 can be reduced.

[0108] Meanwhile, when the target gate-on voltage VON_T is reset while the gate-on voltage VON is changed, the gate-on voltage VON may be changed to be the same as the reset target gate-on voltage VON_T with respect to the corresponding time.

[0109] In an embodiment, the power supply 150 (or the first voltage generator 152) can change the gate-on voltage VON from the first gate-on voltage VON1 (e.g., the minimum gate-on voltage VON_MIN) to the second gate-on voltage VON2 (e.g., the maximum gate-on voltage VON_MAX) during the reference time P_EN (or the entry time). The reference time P_EN is the time allocated for changing the gate-on voltage VON, and can be, for example, one frame to ten frames. For example, the power supply 150 can change the gate-on voltage VON during the time between the reference frame F0 and the kth frame Fk (k is a positive integer). Therefore, the flickering observed by the user due to the rapid change of the gate-on voltage VON can be prevented, and the stress temporarily applied to the display device 1 can be reduced.

[0110] As reference Figure 6 As described, the power supply 150 (or the first voltage generator 152 ) may gradually change the gate-on voltage VON based on the reference change rate GRAD or the reference time P_EN.

[0111] Figure 7 The diagram is included in Figure 1 A block diagram of another example of a power supply in a display device is shown in FIG.

[0112] refer to Figures 4 to 7 , Figure 7 The power supply 150 shown in FIG. Figure 4 The power supply 150 shown in FIG. 1 is different in that Figure 7 The power supply 150 shown in further includes a second voltage generator 153 and a third voltage generator 154 .

[0113] The voltage determiner 151 may determine a target voltage level of the reference voltage VREF (i.e., a target reference voltage VREF_T) based on the load LOAD (or load information) provided from the controller 140. In addition, the voltage determiner 151 may determine a target voltage level of the first power voltage VDD (i.e., a target power voltage VDD_T (or a first target power voltage)) based on the load LOAD.

[0114] The second voltage generator 153 may generate a reference voltage VREF corresponding to (i.e., having a voltage level according to) the target reference voltage VREF_T determined by the voltage determiner 151. Similarly, the third voltage generator 154 may generate a first power voltage VDD corresponding to (i.e., having a voltage level according to) the target power voltage VDD_T determined by the voltage determiner 151. Each of the second voltage generator 153 and the third voltage generator 154 is substantially the same as or similar to the first voltage generator 152, and therefore, repeated descriptions will be omitted to avoid redundancy.

[0115] Reference Figure 8 The operations of the voltage determiner 151 and the second voltage generator 153 are described.

[0116] Figure 8 It is confirmed by the diagram Figure 7 An example of a target reference voltage in a power supply is shown in FIG.

[0117] refer to Figure 8, when the load LOAD is less than the third reference load LOAD_REF3, the voltage determiner 151 may determine the maximum reference voltage VREF_MAX as the target reference voltage VREF_T. The maximum reference voltage VREF_MAX is a voltage having a maximum value among voltages smaller than the threshold voltage of the light emitting element LD. For example, the maximum reference voltage VREF_MAX may be 2.8V like the conventional reference voltage VREF. The third reference load LOAD_REF3 is a load when the reference voltage VREF needs to be changed. According to some example embodiments, the third reference load LOAD_REF3 may be the same as the reference voltage VREF. Figure 5 The first reference load LOAD_REF1 described is the same, but according to the embodiments of the present disclosure, it is not limited thereto. For example, the third reference load LOAD_REF3 may be about 80% relative to the maximum brightness of the display device 1. According to some example embodiments, the third reference load LOAD_REF3 may be greater than the second reference load LOAD_REF2. The third reference load LOAD_REF3 is set to be different from the first reference load LOAD_REF1, so that the stress of the display device 1 according to the change of both the gate-on voltage VON and the reference voltage VREF can be dispersed.

[0118] In a period when the load LOAD is greater than the third reference load LOAD_REF3 and less than the fourth reference load LOAD_REF4 (for example, when the load LOAD is the fourth load LOAD4), the voltage determiner 151 may linearly change the target reference voltage VREF_T according to the load LOAD. The fourth reference load LOAD4_REF4 may be Figure 5 The second reference load LOAD_REF2 described is the same, but embodiments according to the present disclosure are not limited thereto.

[0119] When the load LOAD increases from the third reference load LOAD_REF3 to the fourth reference load LOAD_REF4 , the voltage determiner 151 may linearly reduce the target reference voltage VREF_T from the maximum reference voltage VREF_MAX (eg, 2.8V) to the minimum reference voltage VREF_MIN (eg, 0.4V).

[0120] For example, the brightness of the display device 1 to which the reference voltage VREF having the maximum reference voltage VREF_MAX (e.g., 2.8V) is applied may be 395 nits, the brightness of the display device 1 to which the reference voltage VREF having the voltage between the minimum reference voltage VREF_MIN and the maximum reference voltage VREF_MAX (e.g., 2V or 1.2V) is applied may be 510 nits to 607 nits, and the brightness of the display device 1 to which the reference voltage VREF having the minimum reference voltage VREF_MIN is applied may be 715 nits. That is, the brightness of the display device 1 may increase as the reference voltage VREF decreases.

[0121] When the load LOAD is the third load LOAD3 which is greater than the fourth reference load LOAD_REF4 , the voltage determiner 151 may determine the minimum reference voltage VREF_MIN as the target reference voltage VREF_T.

[0122] Similar to the first voltage generator 152 , the second voltage generator 153 may gradually change the reference voltage VREF at a specific change rate or entry time.

[0123] As reference Figure 8 As described, when the load LOAD is relatively large, the voltage determiner 151 linearly decreases the target reference voltage VREF_T in proportion to the increase of the load LOAD, and thus, the second voltage generator 153 may generate and output a relatively low reference voltage VREF.

[0124] Reference Fig. 9 The operations of the voltage determiner 151 and the third voltage generator 154 are described.

[0125] Fig. 9 It is confirmed by the diagram Figure 7 Graph of an example of a target power voltage in a power supply shown in FIG.

[0126] refer to Fig. 9 , when the load LOAD is less than the fifth reference load LOAD_REF5, the voltage determiner 151 may determine the minimum power voltage VDD_MIN as the target power voltage VDD_T. The fifth reference load LOAD_REF5 may be Figure 5 The first reference load LOAD_REF1 described is the same as or equal to the reference Figure 8 The third reference load LOAD_REF3 is described to be the same, but the embodiments according to the present disclosure are not limited thereto. For example, the fifth reference load LOAD_REF5 may be greater than the fourth reference load LOAD_REF4.

[0127] In a period when the load LOAD is greater than the fifth reference load LOAD_REF5 and less than the sixth reference load LOAD_REF6 (for example, when the load LOAD is the fifth load LOAD5), the voltage determiner 151 may linearly change the target power voltage VDD_T according to the load LOAD. The sixth reference load LOAD_REF6 may be Figure 5 The second reference load LOAD_REF2 described is the same as or the same as the reference Figure 8 The fourth reference load LOAD_REF4 described is the same, but embodiments according to the present disclosure are not limited thereto.

[0128] When the load LOAD increases from the fifth reference load LOAD_REF5 to the sixth reference load LOAD_REF6 , the voltage determiner 151 may linearly increase the target power voltage VDD_T from the minimum power voltage VDD_MIN (eg, 22 V) to the maximum power voltage VDD_MAX (eg, 26 V).

[0129] For example, the brightness of the display device 1 to which the minimum power voltage VDD_MIN (e.g., 22V) is applied may be 262 nits, the brightness of the display device 1 to which a power voltage between the minimum power voltage VDD_MIN and the maximum power voltage VDD_MAX (e.g., 24V) is applied may be 296 nits, and the brightness of the display device 1 to which the maximum power voltage VDD_MAX is applied may be 330 nits. That is, the brightness of the display device 1 may increase as the first power voltage VDD increases.

[0130] When the load LOAD is greater than the sixth reference load LOAD_REF6 , the voltage determiner 151 may determine the maximum power voltage VDD_MAX as the target power voltage VDD_T.

[0131] Similar to the first voltage generator 152 , the third voltage generator 154 may gradually change the first power voltage VDD at a specific change rate or entry time.

[0132] As reference Fig. 9 As described, when the load LOAD is relatively large, the voltage determiner 151 linearly increases the first power voltage VDD in proportion to the increase in the load LOAD, and thus, the third voltage generator 154 may generate and output a relatively high first power voltage VDD.

[0133] At the same time, the power supply 150 can sequentially change the gate-on voltage VON, the reference voltage VREF and the first power voltage VDD. For example, as the load LOAD increases, the power supply 150 can first or preferentially change (or increase) the gate-on voltage VON. Subsequently, as the load LOAD further increases, the power supply 150 can secondly change (or reduce) the reference voltage VREF. Subsequently, as the load LOAD further increases, the power supply 150 can change (or increase) the first power voltage VDD.

[0134] Fig.10 The diagram is from Figure 7 An example of the voltage output by a power supply is shown in the diagram. Fig.10 , changes in the gate-on voltage VON, changes in the reference voltage VREF, and changes in the first power voltage VDD with respect to changes in the load LOAD are illustrated.

[0135] refer to Figure 7 and Fig.10 , in the reference frame F0, the load LOAD may be changed to a second load LOAD2 that is larger than the first load LOAD1.

[0136] The first voltage generator 152 may change (or increase) the gate-on voltage VON based on a first reference change rate or reference time P_EN. The first reference change rate or reference time P_EN may be respectively related to the reference Figure 6 The described reference change rate GRAD and reference time P_EN are substantially the same.

[0137] Similarly, the second voltage generator 153 may change (or reduce) the reference voltage VREF based on a second reference change rate or reference time P_EN, and the third voltage generator 154 may change (or increase) the first power voltage VDD based on a third reference change rate or reference time P_EN.

[0138] Therefore, the overall brightness of the display device 1 may be gradually increased based on a specific change rate or during the reference time P_EN (eg, during ten frames).

[0139] For example, according to the first load LOAD1, the display device 1 can display an image by using a gate-on voltage VON of 25 V, a reference voltage VREF of 2 V, and a first power voltage VDD of 22 V. In addition, according to the second load LOAD2, the display device 1 can display an image with higher brightness by using a gate-on voltage VON of 29 V, a reference voltage VREF of 1 V, and a first power voltage VDD of 26 V.

[0140] Fig.11 It is confirmed by the diagram Figure 7 An example of a target gate-on voltage in a power supply is shown in FIG.

[0141] refer to Figures 7 to 11 , the voltage determiner 151 may determine the target gate-on voltage VON_T based on the dimming level DM of the display device 1. The dimming level DM may define the maximum brightness (or maximum display brightness) of the display device 1, and may determine one of a plurality of dimming levels based on an external input or a display environment. For example, the maximum brightness of the display device 1 may increase as the dimming level DM increases.

[0142] like Fig.11 As shown in , when the dimming level DM is less than the first reference dimming level DM_REF1 (for example, in the first dimming level DM1), the voltage determiner 151 may determine the minimum gate-on voltage VON_MIN as the target gate-on voltage VON_T. The first reference dimming level DM_REF1 is the minimum dimming level for which the brightness of the display device 1 needs to be compensated. For example, the first reference dimming level DM_REF1 may have a brightness of about 70% relative to the maximum brightness of the display device 1.

[0143] In a period in which the dimming level DM is greater than the first reference dimming level DM_REF1 and less than the second reference dimming level DM_REF2 (e.g., in the second dimming level DM2), the voltage determiner 151 may linearly change the target gate-on voltage VON_T according to the dimming level DM. The second reference dimming level DM_REF2 is the maximum dimming level for which the brightness of the display device 1 needs to be compensated. For example, the second reference dimming level DM_REF2 may have a brightness of about 99% relative to the maximum brightness of the display device 1.

[0144] When the dimming level DM increases from the first reference dimming level DM_REF1 to the second reference dimming level DM_REF2 , the voltage determiner 151 may linearly increase the target gate-on voltage VON_T from the minimum gate-on voltage VON_MIN (eg, 20 V) to the maximum gate-on voltage VON_MAX (eg, 30 V).

[0145] When the dimming level DM is greater than the second reference dimming level DM_REF2 (eg, in the third dimming level DM3 ), the voltage determiner 151 may determine the maximum gate-on voltage VON_MAX as the target gate-on voltage VON_T.

[0146] As reference Fig.11 As described, when the dimming level DM is relatively large, the voltage determiner 151 linearly increases the target gate-on voltage VON_T in proportion to the increase in the dimming level DM, and thus, the first voltage generator 152 may generate and output a relatively high gate-on voltage VON.

[0147] Similarly, the voltage determiner 151 may determine each of the target reference voltage VREF_T and the target power voltage VDD_T based on the dimming level DM of the display device 1 .

[0148] Fig.12 is a diagram illustrating a display device according to another embodiment of the present disclosure. Fig.13 The diagram is included in Fig.12 A circuit diagram of an example of a pixel in a display device shown in FIG.

[0149] First, refer to Figure 1 and Fig.12 , Fig.12 The display device 1 shown in FIG. Figure 1 The display device 1 shown in FIG. 1 is different in that Fig.12 The display device 1 shown in FIG. 1 does not include the sensing driver 160 . Fig.12 The display device 1 shown in FIG. Figure 1 The display device 1 shown in FIG. 1 is substantially the same or similar except for the sensing driver 160 and a circuit configuration related thereto (eg, an external compensation circuit), and thus, repeated descriptions will be omitted to avoid redundancy.

[0150] The display unit 110 may include data lines DL1 to DLm (m is a positive integer), gate lines GL1 to GLn (n is a positive integer), and pixels PX. The pixels PX may be disposed in a region defined by the data lines DL1 to DLm and the gate lines GL1 to GLn and may be electrically coupled to the data lines DL1 to DLm and the gate lines GL1 to GLn.

[0151] refer to Fig.13 , the pixel PX may include a first transistor T1, a second transistor T2, a storage capacitor Cst, and a light emitting element LD.

[0152] The first transistor T1 and the second transistor T2 may be implemented using a P-type transistor (e.g., a PMOS transistor), but the embodiments of the present disclosure are not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 may be implemented using an N-type transistor (e.g., an NMOS transistor). In addition, the pixel PX may further include other transistors in addition to the first transistor T1 and the second transistor T2.

[0153] The coupling configuration of the first transistor T1 and the second transistor T2 is Figure 2 The coupling configurations of the described first transistor T1 and the second transistor T2 are substantially the same, and thus, repeated descriptions will be omitted to avoid redundancy.

[0154] When the second transistor T2 is implemented using a P-type transistor, the second transistor T2 can be based on a logic low level VGL (see Figure 3 ) instead of being turned on by the gate-on voltage VON of the logic high level.

[0155] The storage capacitor Cst may be electrically coupled between the first node N1 and a first power line (ie, a power line for transmitting the first power voltage VDD). The storage capacitor Cst may temporarily store a data signal applied to the first node N1.

[0156] The light emitting element LD (or light emitting diode) can be electrically coupled between the second node N2 and the second power line (i.e., the power line to which the second power voltage VSS is applied) and emit light having brightness corresponding to the driving current Id (or data signal) provided by the first transistor T1.

[0157] Reference Fig.14 Describe in more detail Fig.13 An example operation of a pixel PX is shown in FIG.

[0158] Fig.14 It is shown in Fig.13 Graph showing an example of a waveform of a signal measured in a pixel shown in FIG.

[0159] refer to Figure 3 and Fig.14 , the gate signal SCAN1 (or the change of the gate signal SCAN1 and the operation of the pixel PX according to the change of the gate signal SCAN1) and the reference Figure 3 The described gate signal SCAN1 (or the change of the gate signal SCAN1 and the operation of the pixel PX according to the change of the gate signal SCAN1) is basically the same or similar, except that the gate signal SCAN1 has a first logic low level VGL1 as a gate-on voltage VON and has a logic high level VGH as a gate-off voltage VOFF, and therefore, repeated descriptions will be omitted to avoid redundancy.

[0160] exist Fig.14 At the sixth time t6 shown in , the load LOAD may have a value greater than the value of the load LOAD at the first time t1.

[0161] Therefore, the gate signal SCAN1 may have a second logic low level VGL2 lower than the first logic low level VGL1 at the sixth time t6. The second logic low level VGL2 may have a voltage difference greater than that of the first logic low level VGL1 with respect to the logic high level VGH (or gate-off voltage).

[0162] As reference Figure 3As described, as the gate-on voltage VON of the gate signal SCAN1 decreases (or as the voltage difference or amplitude of the gate-on voltage VON relative to the gate-off voltage VOFF increases), the display device 1 can display an image corresponding to the same input image data DATA1 with higher brightness.

[0163] As reference Figure 12 to Figure 14 As described, the configuration of increasing the brightness of the display device 1 by changing the gate-on voltage VON can be applied to a display device 1 that does not include a sensing driver 160, and can be applied to a display device 1 that includes various pixel circuits (for example, a pixel circuit including an N-type transistor or a P-type transistor).

[0164] At the same time, reference Figure 4 and Figure 7 Power supplies described and referenced Figure 5 , Figure 6 and Figures 8 to 10 The operation of the power supply 150 described may be applied to Fig.12 The power supply 150 shown in FIG.

[0165] Aspects of certain example embodiments have been disclosed herein, and although specific terms are used, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly stated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims and their equivalents.

Claims

1. A display device, comprising: A display unit, comprising a gate line, a data line, and a pixel electrically coupled to the gate line and the data line, wherein the pixel comprises a first transistor electrically coupled to the gate line; A controller configured to calculate a load on input data; a data driver configured to generate a data signal corresponding to a grayscale value in the input data and provide the data signal to the data line; a gate driver configured to generate a gate signal having a pulse based on a gate-on voltage and provide the gate signal to the gate line; and a power supply configured to provide the gate-on voltage to the gate driver and to change the gate-on voltage based on the load, wherein the gate-on voltage has a voltage level that turns on the first transistor, wherein the brightness of the display unit increases as the load increases, wherein the voltage level of the gate signal provided to the gate line varies according to the change of the gate-on voltage, and Wherein as the load increases within a range where the load is greater than a first reference load and less than a second reference load, the power supply increases the voltage level of the gate-on voltage.

2. The display device according to claim 1, wherein: The display unit further includes a first power line and a second power line, wherein the pixel further comprises a second transistor and a light emitting element electrically coupled in series between the first power line and the second power line, and The first transistor is configured to transmit the data signal to a gate electrode of the second transistor in response to the gate signal.

3. The display device according to claim 2, wherein: The power supply is configured to provide the gate driver with a gate-off voltage having a voltage level that turns off the first transistor; wherein the gate cutoff voltage is constant and does not change, and As the load increases, the power supply linearly increases the difference between the gate-off voltage and the gate-on voltage.

4. The display device according to claim 3, wherein: In a first range where the load is less than the first reference load, the gate-on voltage is a constant voltage having a first reference voltage level, wherein, in a second range where the load is greater than the second reference load, the gate-on voltage is a constant voltage having a second reference voltage level, and The second reference load is greater than the first reference load.

5. The display device according to claim 3, wherein: The power supply is configured as: determining a target voltage level of the gate-on voltage based on the load; as well as The voltage level of the gate-on voltage is linearly changed to the target voltage level during a reference time.

6. The display device according to claim 3, wherein: The pixel further includes a third transistor electrically coupled between the reference power line and one electrode of the light emitting element, and The power supply is configured as follows: Generate reference voltage; supplying the reference voltage to the reference power line; and The reference voltage is varied based on the load.

7. The display device according to claim 6, wherein the power supply is configured as: generating a first power voltage; applying the first power voltage to the first power line; and The first power voltage is changed based on the load.

8. The display device according to claim 7, wherein: The power supply comprises: a voltage determiner configured to determine a target gate-on voltage based on the load; and A first voltage generator is configured to generate the gate-on voltage based on the target gate-on voltage.

9. The display device according to claim 8, wherein: The voltage determiner is further configured to determine a target reference voltage and a target power voltage, respectively, based on the load, The power supply further comprises: a second voltage generator configured to generate the reference voltage based on the target reference voltage; and A third voltage generator is configured to generate the first power voltage based on the target power voltage.

10. A display device, comprising: A display unit, comprising a gate line, a data line, and a pixel electrically coupled to the gate line and the data line, wherein the pixel comprises a first transistor electrically coupled to the gate line; a data driver configured to generate a data signal corresponding to a grayscale value in input data and provide the data signal to the data line; a gate driver configured to generate a gate signal having a pulse based on a gate-on voltage and provide the gate signal to the gate line; and a power supply configured to provide the gate-on voltage to the gate driver and to change the gate-on voltage based on a dimming level, wherein the gate-on voltage has a voltage level that turns on the first transistor, wherein the maximum brightness of the display unit changes according to the dimming level, wherein the voltage level of the gate signal provided to the gate line varies according to the change of the gate-on voltage, and The power supply increases the voltage level of the gate-on voltage as the dimming level increases within a range where the dimming level is greater than a first reference dimming level and less than a second reference dimming level.

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