Time coded data communication protocol, apparatus and method for generating and receiving data signals

Abstract

An apparatus for generating a data signal includes a processing circuit configured to generate a data signal comprising a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type. The first and second signal edges are separated by a first time period corresponding to first data to be transmitted, and the second and third signal edges are separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 559,814, filed on September 18, 2017, which is incorporated herein by reference in its entirety. Technical Field

[0003] The examples involve time-coded data communication protocols, apparatus for generating data signals, and apparatus for receiving data signals. Background Technology

[0004] Interconnects used for data transmission may need to meet various requirements depending on the application using the interconnect. For example, it may be desirable to achieve high throughput with moderate power consumption. Additionally, it may be desirable to avoid interference between the interconnect and other components present in the system using the interconnect, such as mobile devices / telephones, computers, memory / storage systems, sensor systems, and so on.

[0005] For example, digital interfaces between storage devices such as hard disk drives (HDDs) or solid-state drives (SSDs) can be based on Peripheral Component Interconnect Express (PCI-E) or Serial AT Attachment (SATA), which can require too much power within mobile devices for each bit of information transmitted. Analog or digital connections between mobile telecommunications equipment, such as the radio frequency front-end and additional signal processing circuitry, can be expensive and consume considerable space. There may be a need for interconnects with enhanced features. Attached Figure Description

[0006] Figure 1a The diagram illustrates the interconnection of data signals;

[0007] Figure 1b The diagram illustrates the STEP interconnect;

[0008] Figure 1c The diagram illustrates the architecture of a time-to-digital converter;

[0009] Figure 1d An example of a device for receiving data signals is illustrated;

[0010] Figure 1e Another example of a device for receiving data signals is illustrated;

[0011] Figure 1f An example of a device for generating data signals is illustrated;

[0012] Figure 1g Another example of a device for generating data signals is illustrated;

[0013] Figure 1h The flowchart illustrates an example of a method for generating data signals;

[0014] Figure 1i The flowchart illustrates an example of a method for receiving data signals;

[0015] Figure 2a An example of a device for generating differential signal pairs is illustrated;

[0016] Figure 2b An example of a differential signal is illustrated;

[0017] Figure 2c An example of a device for processing differential signal pairs is illustrated;

[0018] Figure 2d Another example of a device for processing differential signal pairs is illustrated;

[0019] Figure 2e The illustration shows an example of a processing circuit used to determine the properties of a differential signal pair;

[0020] Figure 2f The diagram shows... Figure 2e An example of a signal present in the processing circuit;

[0021] Figure 2g The illustration shows another example of a processing circuit used to determine the properties of a differential signal pair;

[0022] Figure 2h The flowchart illustrates an example of a method for receiving data signals;

[0023] Figure 2i The flowchart illustrates an example of a method for generating data signals;

[0024] Figure 3a The illustration shows an example of a method for generating data signals based on a series of data symbols;

[0025] Figure 3b The diagram illustrates the process of... Figure 3a A series of examples of data transmission generated by the method;

[0026] Figure 3c This illustration shows another example of a method for generating data signals based on a series of data symbols;

[0027] Figure 3d An example of a device for generating data signals is illustrated;

[0028] Figure 3e Another example of a device for generating data signals is illustrated;

[0029] Figure 3f The illustration shows an example of a method for receiving data signals;

[0030] Figure 3g An example of a device for receiving data signals is illustrated;

[0031] Figure 3h The diagram illustrates the use of Figures 3a to 3g The example shown in the illustration demonstrates an improvement in the spectrum of the generated data signal;

[0032] Figure 4a Examples of I delimiters, SOP delimiters, and EOP delimiters are shown in the diagram;

[0033] Figure 4b Further examples of the I delimiter, SOP, and EOP delimiters are illustrated.

[0034] Figure 4c The illustration shows an example of a data signal containing successive delimiters of the same type according to a conventional scheme;

[0035] Figure 4d The illustration shows an example of a data signal generated by an example of a device for generating data signals;

[0036] Figure 4e The diagram is used to generate Figure 4d Examples of devices for data signals;

[0037] Figure 4f The diagram illustrates the process of generating Figure 4d A flowchart illustrating an example of a data signaling method;

[0038] Figure 4g The diagram illustrates the process of generating Figure 4d Another example of a device for displaying data signals;

[0039] Figure 4h The diagram illustrates the process of generating Figure 4d A flowchart illustrating another example of a data signaling method;

[0040] Figure 5a The diagram illustrates a leak from one interconnect to another;

[0041] Figure 5b The diagram illustrates leakage from one interconnect to another via crosstalk;

[0042] Figure 5c An example of a sending system is illustrated;

[0043] Figure 5dThe illustration shows an example of a filter circuit used for leakage mitigation;

[0044] Figure 5e An example of a data receiving system is illustrated;

[0045] Figure 5f The flowchart illustrates an example of a method for mitigating leakage in the first interconnect to the second interconnect.

[0046] Figure 6a The diagram illustrates the STEP interconnect link;

[0047] Figure 6b The flowchart illustrates an example of a method for processing data signals;

[0048] Figure 6c The flowchart illustrates an example of a method for generating data signals;

[0049] Figure 6d An example of a device for processing data signals is illustrated;

[0050] Figure 6e An example of a device for generating data signals is illustrated;

[0051] Figure 6f An example of an interconnect used for data transmission is illustrated;

[0052] Figure 6g The diagram illustrates when using... Figures 6b to 6f One of the examples described is an example of the performance gains that can be achieved;

[0053] Figure 7a The flowchart illustrates an example of a method for determining the assignment of time period and symbol width to each payload data symbol of a communication protocol;

[0054] Figure 7b The diagram illustrates the probability distribution of edge locations of payload data symbols;

[0055] Figure 7c The diagram illustrates a STEP interconnect link with an equal probability distribution of all payload data symbols;

[0056] Figure 7d The diagram illustrates STEP interconnect links with unequal probability distributions of payload data symbols;

[0057] Figure 7e The flowchart illustrates an example of a method for generating data signals;

[0058] Figure 7f The flowchart illustrates an example of a method for processing data signals;

[0059] Figure 7g An example of a device for generating data signals is illustrated;

[0060] Figure 7h An example of a device for processing data signals is illustrated;

[0061] Figure 7i The diagram illustrates a time-to-digital converter;

[0062] Figure 8a The diagram illustrates the data signals according to the STEP protocol;

[0063] Figure 8b The flowchart illustrates an example of a method for determining the payload data symbols within a data signal;

[0064] Figure 8c The diagram illustrates the use of Figure 8b Examples of methods for processing data signals;

[0065] Figure 8d An example of a device for processing data signals is illustrated;

[0066] Figure 8e An example of a communication system is illustrated;

[0067] Figure 8f An example of STEP interconnection is illustrated;

[0068] Figure 9a A flowchart illustrating an example of a method for sending a sequence of data symbols;

[0069] Figure 9b The illustration shows an example of data processing within an interconnect link.

[0070] Figure 9c The flowchart illustrates an example of a method for processing a series of received data symbols;

[0071] Figure 9d An example of a device for transmitting a sequence of data symbols is illustrated;

[0072] Figure 9e The illustration shows an example of a device for processing a series of received data symbols;

[0073] Figure 10a The flowchart illustrates an example of a method for generating a data signal of a predetermined number of bits for transmission in a serially ordered manner;

[0074] Figure 10b The illustration shows an example of a two-dimensional representation of data;

[0075] Figure 10cThe illustration shows examples of locations where control symbol indicators and control symbols are inserted into a series of transmit symbols;

[0076] Figure 10d The flowchart illustrates an example of a method for processing data signals;

[0077] Figure 10e An example of an apparatus for generating a data signal to transmit a predetermined number of bits in a serial sequence is illustrated.

[0078] Figure 11a An example of a device for processing data signals is illustrated.

[0079] Figure 12a Another example of a device for generating data signals is illustrated;

[0080] Figure 12b An example of a data signal is illustrated;

[0081] Figure 12c The illustration shows a first example of bit rearrangement between the physical layer representation and the medium access control layer representation;

[0082] Figure 12d The illustration shows a second example of bit rearrangement between the physical layer representation and the medium access control layer representation;

[0083] Figure 12e The illustration shows a third example of bit rearrangement between the physical layer representation and the medium access control layer representation;

[0084] Figure 12f The illustration shows a fourth example of bit rearrangement between the physical layer representation and the medium access control layer representation;

[0085] Figure 12g The illustration shows a fifth example of bit rearrangement between the physical layer representation and the medium access control layer representation;

[0086] Figure 12h The illustration shows a sixth example of bit rearrangement between the physical layer representation and the medium access control layer representation;

[0087] Figure 12i Another example of a data signal is illustrated;

[0088] Figure 12j Another example of a device for generating data signals is illustrated;

[0089] Figure 12k An example of a device for decoding data signals is illustrated;

[0090] Figure 12l Another example of a device for decoding data signals is illustrated;

[0091] Figure 12m The flowchart illustrates an example of a method for generating data signals;

[0092] Figure 12n The diagram illustrates another example of a method for generating data signals;

[0093] Figure 12o The flowchart illustrates an example of a method for decoding data signals;

[0094] Figure 12p The diagram illustrates a flowchart of another example of a method for decoding data signals;

[0095] Figure 12q An example of a device for generating data signals is illustrated;

[0096] Figure 12r An example of a device for generating data signals is illustrated;

[0097] Figure 12s An example of a device for decoding data signals is illustrated;

[0098] Figure 12t Another example of a device for decoding data signals is illustrated;

[0099] Figure 12u The flowchart illustrates an example of a method for generating data signals;

[0100] Figure 12v The diagram illustrates another example of a method for generating data signals;

[0101] Figure 12w The flowchart illustrates an example of a method for decoding data signals;

[0102] Figure 12x The diagram illustrates a flowchart of another example of a method for decoding data signals;

[0103] Figure 13a An example of a device for generating data signals is illustrated;

[0104] Figure 13b An example of a device for generating data signals is illustrated;

[0105] Figure 13c An example of a device for decoding data signals is illustrated;

[0106] Figure 13d Another example of a device for decoding data signals is illustrated;

[0107] Figure 13e The flowchart illustrates an example of a method for generating data signals;

[0108] Figure 13f The diagram illustrates another example of a method for generating data signals;

[0109] Figure 13g The flowchart illustrates an example of a method for decoding data signals;

[0110] Figure 13h The diagram illustrates a flowchart of another example of a method for decoding data signals;

[0111] Figure 13i An example of an apparatus for transmitting a first data packet having a first priority and a second data packet having a higher second priority is illustrated.

[0112] Figure 13j Another example of a data signal is illustrated;

[0113] Figure 13k The diagram illustrates a flowchart of an example of a method for sending a first data packet with a first priority and a second data packet with a higher second priority;

[0114] Figure 14a An example of a communication system is illustrated;

[0115] Figure 14b The diagram illustrates an example of data flow between two communication devices;

[0116] Figure 14c An example of a communication system is illustrated;

[0117] Figure 14d This illustration shows another example of a communication system;

[0118] Figure 14e This illustration shows another example of a communication system;

[0119] Figure 14f The flowchart illustrates an example of a communication method for a communication device;

[0120] Figure 14g The flowchart illustrates another example of a communication method for a communication device;

[0121] Figure 14h The flowchart illustrates another example of a communication method for a communication device;

[0122] Figure 14i The flowchart illustrates another example of a communication method for a communication device;

[0123] Figure 15a An example of a device for generating data signals is illustrated;

[0124] Figure 15b An example of a state diagram for power states is shown;

[0125] Figure 15c An example of a device for decoding data signals is illustrated;

[0126] Figure 15d An example of a communication device is illustrated;

[0127] Figure 16a An example of a device for generating data signals is illustrated;

[0128] Figure 16b An example of a data signal is illustrated;

[0129] Figure 16c Another example of a data signal is illustrated;

[0130] Figure 16d Another example of a device for generating data signals is illustrated;

[0131] Figure 16e An example of a device for decoding data signals is illustrated;

[0132] Figure 16f The flowchart illustrates an example of a method for generating data signals;

[0133] Figure 16g The diagram illustrates another example of a method for generating data signals;

[0134] Figure 16h The flowchart illustrates an example of a method for decoding data signals;

[0135] Figure 17a An example of a communication system is illustrated;

[0136] Figure 17b A flowchart illustrating an example of a communication method is shown;

[0137] Figure 17c A flowchart illustrating another example of a communication method is shown;

[0138] Figure 18a An example of a device for generating data signals is illustrated;

[0139] Figure 18b An example of a device for decoding data signals is illustrated;

[0140] Figure 18c An example of a communication system in its first operating mode is illustrated.

[0141] Figure 18d An example of a communication system in the second operating mode is illustrated;

[0142] Figure 18e Another example of a communication system in the second operating mode is illustrated;

[0143] Figure 18f The flowchart illustrates an example of a method for generating data signals;

[0144] Figure 18g The flowchart illustrates an example of a method for decoding data signals;

[0145] Figure 19 Another example of a device for generating data signals is illustrated;

[0146] Figure 20a An example of a device for regulating the supply signal generated by a low-dropout regulator for electronic equipment is illustrated.

[0147] Figure 20b The illustration shows an exemplary time progression of the voltage across the capacitor;

[0148] Figure 20c The illustration shows an exemplary comparison of electric current;

[0149] Figure 20d An example of a communication device is illustrated;

[0150] Figure 20e Another example of a communication device is illustrated;

[0151] Figure 20f The diagram illustrates a flowchart of an example of a method for regulating a supply signal generated by a low-dropout regulator for an electronic device;

[0152] Figure 21 An example of a communication system is illustrated;

[0153] Figure 22a The diagram illustrates an example of a current-mode logic to complementary metal-oxide-semiconductor (CMOS) conversion circuit.

[0154] Figure 22b The diagram illustrates an exemplary relationship between the input and output of an inverter;

[0155] Figure 22c The diagram shows... Figure 22a The circuit shown illustrates the exemplary process of signals within it;

[0156] Figure 22d This illustration shows another example of a current-mode logic to complementary metal-oxide-semiconductor (CMOS) conversion circuit.

[0157] Figure 22e Another example of a communication device is illustrated;

[0158] Figure 23a An example of a digital-to-time converter is illustrated;

[0159] Figure 23b Another example of a digital-to-time converter is illustrated;

[0160] Figure 23c Another example of a digital-to-time converter is illustrated;

[0161] Figure 23d Another example of a digital-to-time converter is illustrated;

[0162] Figure 23e An example of a device for generating data signals is illustrated;

[0163] Figure 24a Another example of a digital-to-time converter is illustrated;

[0164] Figure 24b The diagram illustrates the relationship between the oscillation signal and the data signal;

[0165] Figure 25a This illustration shows an example of current distribution in a time-to-digital converter;

[0166] Figure 25b The diagram illustrates an exemplary time progression of the supplied voltage;

[0167] Figure 25c An example of a device for regulating the supply voltage is illustrated.

[0168] Figure 25d The diagram illustrates another exemplary time progression of the supply voltage;

[0169] Figure 25e Another example of a device for regulating the supply voltage is illustrated.

[0170] Figure 25f Another example of a device for regulating the supply voltage is illustrated.

[0171] Figure 25g An example of a communication device is illustrated;

[0172] Figure 25h Another example of a communication device is illustrated;

[0173] Figure 25i The diagram illustrates a flowchart of an example method for regulating the supply voltage;

[0174] Figure 25j A flowchart illustrating an example of a method for communication is shown;

[0175] Figure 25k The flowchart illustrates another example of a method used for communication;

[0176] Figure 26a The diagram illustrates an example of a protection circuit against electrostatic discharge.

[0177] Figure 26b The illustration shows an example of a receiver used for differential data signals;

[0178] Figure 26c An example of a device for receiving differential data signals is illustrated.

[0179] Figure 27a A block diagram of the radio head-end RH system is shown;

[0180] Figure 27b A block diagram of an apparatus for generating an amplified high-frequency transmission signal is shown.

[0181] Figure 27c A block diagram of an RFEM module with transmitter TX digital predistortion (DPD) on a STEP interconnect is shown.

[0182] Figure 27d A block diagram of the baseband processor is shown;

[0183] Figure 27e A flowchart is shown for a method of generating an amplified high-frequency transmission signal;

[0184] Figure 27f A flowchart is shown for a method for determining the predistortion setting;

[0185] Figure 28a An example of a transmitter is illustrated;

[0186] Figure 28b The diagram illustrates an exemplary relationship between symbol timing error and frequency error;

[0187] Figure 28c Another example of a transmitter is illustrated;

[0188] Figure 28d The illustration shows an exemplary time progression of frequency and symbol rate;

[0189] Figure 29a A block diagram of an apparatus for generating data signals is shown;

[0190] Figure 29b The illustration shows an example of an adaptive delimiter used for reference timing settings;

[0191] Figure 29c An example of STEP timing with a low reference frequency is shown;

[0192] Figure 29d An example of STEP timing with a high reference frequency is shown;

[0193] Figure 29e A block diagram of an apparatus for decoding data signals is shown;

[0194] Figure 29f A block diagram of the STEP system and high reference extraction is shown;

[0195] Figure 29g A block diagram of a mobile device is shown;

[0196] Figure 29h A flowchart of a method for generating data signals is shown;

[0197] Figure 29i A flowchart of a method for decoding data signals is shown;

[0198] Figure 30a A block diagram of an apparatus for generating data signals is shown;

[0199] Figure 30b An example using two output levels is shown;

[0200] Figure 30c An example using 3 output levels is shown;

[0201] Figure 30d A block diagram of an apparatus for decoding data signals is shown;

[0202] Figure 30e A block diagram of an apparatus for generating a pair of data signals is shown;

[0203] Figure 30f An example of a data signal is shown;

[0204] Figure 30g A block diagram of an apparatus for receiving a pair of data signals is shown;

[0205] Figure 30h A flowchart of a method for generating data signals is shown;

[0206] Figure 30i A flowchart of a method for decoding data signals is shown;

[0207] Figure 30j A flowchart is shown for a method of generating a pair of data signals;

[0208] Figure 30k A flowchart is shown for a method of receiving a pair of data signals;

[0209] Figure 31a A block diagram of an apparatus for generating data signals is shown;

[0210] Figure 31b An example of a set of three data signals is shown;

[0211] Figure 31c An example of a set of three transmission lines between a transmitter and a receiver is shown;

[0212] Figure 31d A block diagram of a device for receiving data signals is shown;

[0213] Figure 31e A block diagram of the receiver is shown;

[0214] Figure 31f A flowchart of a method for generating data signals is shown;

[0215] Figure 31g A flowchart of a method for receiving data signals is shown;

[0216] Figure 32a An example of a communication system is illustrated;

[0217] Figure 32b The illustration shows an example of a device used to generate output data;

[0218] Figure 32c The illustration shows an example of a time-to-digital converter at its first resolution;

[0219] Figure 32d The illustration shows an example of a second resolution time-to-digital converter;

[0220] Figure 32e The illustration shows an example of the relationship between the input data signal and the quantization level of a time-to-digital converter;

[0221] Figure 32f An example of a time-to-digital converter is illustrated;

[0222] Figure 32g The illustration shows an example of an uncalibrated time-to-digital converter;

[0223] Figure 32h An example of a histogram is shown;

[0224] Figure 32i The illustration shows an example of a calibrated time-to-digital converter;

[0225] Figure 32j This illustration shows another example of a communication system;

[0226] Figure 32k The flowchart illustrates an example of a method for generating output data;

[0227] Figure 33a A block diagram of a device for generating output data signals is shown;

[0228] Figure 33b Examples of DTC and XOR output signals are shown;

[0229] Figure 33c Another example of DTC output signal and XOR output signal is shown;

[0230] Figure 33d A block diagram of an apparatus for generating data signals is shown;

[0231] Figure 33e A STEP connection using interleaved data signals is shown;

[0232] Figure 33f A flowchart is shown for a method of generating output data signals;

[0233] Figure 33g A flowchart of a method for generating data signals is shown;

[0234] Figure 34a A block diagram of an apparatus for generating data signals is shown;

[0235] Figure 34b A block diagram of the STEP system using FDD is shown;

[0236] Figure 34c A block diagram of another STEP system using FDD is shown;

[0237] Figure 34d A block diagram of another STEP system using FDD is shown;

[0238] Figure 34e A block diagram of a STEP system using TDD is shown;

[0239] Figure 34f A flowchart is shown for the method used to generate output data;

[0240] Figure 34g A block diagram of the STEP system is shown;

[0241] Figure 35a A block diagram of an apparatus for generating data signals is shown;

[0242] Figure 35b A schematic bandwidth diagram of multiple STEP streams on a single channel is shown;

[0243] Figure 35c A block diagram of an apparatus for generating data signals is shown;

[0244] Figure 35d A block diagram of a STEP system using orthogonal STEP streams on a single channel and a single carrier is shown;

[0245] Figure 35e A block diagram of a STEP system that uses baseband STEP stream and high-frequency STEP stream to transmit over a single transmission line is shown.

[0246] Figure 35f A block diagram of a STEP system that uses baseband STEP streams and orthogonal high-frequency STEP streams to transmit over a single transmission line is shown.

[0247] Figure 35g A flowchart is shown for the method used to generate output data;

[0248] Figure 35h A flowchart of another method for generating output data is shown;

[0249] Figure 36a An example of an adapter circuit for data signals is illustrated.

[0250] Figure 36b The illustration shows an example of a receiver used for data signals;

[0251] Figure 36c The flowchart illustrates an example of a method for determining attenuation levels;

[0252] Figure 36d The diagram illustrates the use of Figure 36a An example of jitter degradation in the adapter circuit shown;

[0253] Figure 36e The illustration shows an example of the interconnection of means for generating data signals and means for processing data signals;

[0254] Figure 36f An example of a device for processing data signals is illustrated;

[0255] Figure 37a The illustration shows a first example of a device for generating data signals;

[0256] Figure 37b The first example of an eye diagram is illustrated;

[0257] Figure 37c The second example of an eye diagram is illustrated;

[0258] Figure 37d The illustration shows a second example of a device for generating data signals;

[0259] Figure 37e The diagram illustrates a traditional communication link;

[0260] Figure 37f The diagram illustrates a comparison between the transmitted and received data signals;

[0261] Figure 37g The flowchart illustrates an example of a method for generating data signals;

[0262] Figure 37h The diagram illustrates another example of a method for generating data signals;

[0263] Figure 38a The diagram illustrates a model of inter-symbol interference;

[0264] Figure 38b The concept of predistortion is illustrated.

[0265] Figure 38c The illustration shows an example of a method for determining the time interval between two signal edges using a time-to-digital converter with coarse resolution;

[0266] Figure 38d The illustration shows an example of scaling the time interval between a series of successive signal edges within a data signal by a calibration factor;

[0267] Figure 38e The diagram illustrates a model of reflections on an interconnect link;

[0268] Figure 38f The illustration shows an example of the effect of reflection on data signals;

[0269] Figure 38g An example of a device for processing data signals is illustrated;

[0270] Figure 38h An example of a device for generating data signals is illustrated;

[0271] Figure 38i The illustration shows an example of three repetitions of a series of payload data symbols used for calibration;

[0272] Figure 39a An example of a device for generating data signals is illustrated;

[0273] Figure 39b The illustration shows an example of a data stream that includes control symbol indicators, control symbols indicating a series of calibration symbols, and a sequence of calibration symbols;

[0274] Figure 39c An example of a device for processing data signals is illustrated;

[0275] Figure 39d An example of a method for generating data signals is illustrated;

[0276] Figure 39e The illustration shows an example of a method for processing data signals;

[0277] Figure 40a An example of a method for calibrating a variable delay element is illustrated;

[0278] Figure 40b The diagram illustrates a TDC including a variable delay element;

[0279] Figure 40c The illustration shows an example of a method for mutually calibrating the DTC and the time period within the TDC coupled to the DTC;

[0280] Figure 40d An example of a TDC including a variable delay element is illustrated;

[0281] Figure 40e The diagram illustrates an example of a circuit that degrades the jitter of digital signals;

[0282] Figure 41a An example of an electronic device is illustrated;

[0283] Figure 41b Another example of an electronic device is illustrated;

[0284] Figure 41c The diagram illustrates a system comprising two coupled electronic devices;

[0285] Figure 41d An example of a data cable is shown in the diagram;

[0286] Figure 41e Another example of a data cable is shown in the diagram;

[0287] Figure 42a An example of semiconductor packaging is illustrated;

[0288] Figure 42b An example of a semiconductor wafer is illustrated;

[0289] Figure 42c This illustration shows another example of semiconductor packaging;

[0290] Figure 43a The illustration shows an example of a data aggregation device used for vehicles;

[0291] Figure 43b The illustration shows an example of a data processing device used in a vehicle;

[0292] Figure 43c An example of a vehicle is shown in the illustration;

[0293] Figure 44a An example of an electronic device is illustrated;

[0294] Figure 44b Another example of an electronic device is illustrated;

[0295] Figure 44c Another example of an electronic device is illustrated;

[0296] Figure 45a An example of a user device is illustrated;

[0297] Figure 45b An example of a base station is illustrated;

[0298] Figure 46a The illustration shows a first example of a radio system;

[0299] Figure 46b The illustration shows a second example of a radio system;

[0300] Figure 46c The illustration shows a third example of a radio system;

[0301] Figure 47a The illustration shows a fourth example of a radio system;

[0302] Figure 47b The image shows a mobile device;

[0303] Figure 47c The illustration shows a fifth example of a radio system;

[0304] Figure 47d The illustration shows a sixth example of a radio system;

[0305] Figure 48a An example of a semiconductor wafer is illustrated;

[0306] Figure 48b An example of a storage device is illustrated;

[0307] Figure 48c A flowchart illustrating an example of a method for selecting between different communication protocols is shown; and

[0308] Figure 49 An example of a computing device is illustrated. Detailed Implementation

[0309] The various examples will now be described more fully with reference to the accompanying drawings, which illustrate some of the examples. In the drawings, the thickness of lines, layers, and / or areas may be exaggerated for clarity.

[0310] Therefore, while the other examples can have various modifications and substitutions, some specific examples are shown in the accompanying drawings and will be described in detail thereafter. However, this detailed description does not limit the other examples to the specific forms described. The other examples cover all modifications, equivalents, and substitutions falling within the scope of this disclosure. Identical or similar reference numerals throughout the description of the drawings refer to similar or analogous elements that, when compared with each other, can be implemented identically or modified, while providing the same or similar function.

[0311] It should be understood that when an element is said to be "connected" or "coupled" to another element, these elements can be connected or coupled directly or through one or more intermediary elements. If two elements A and B are combined using "or," it should be understood that all possible combinations are disclosed, i.e., only A, only B, and A and B, unless otherwise explicitly or implicitly defined. Alternative wording for the same combination is "at least one of A and B" or "A and / or B." This also applies by analogy to combinations of more than two elements.

[0312] The terminology used in this document to describe specific examples is not intended to limit other examples. Whenever the singular form such as “a,” “an,” and “the” is used and only a single element is neither explicitly nor implicitly required to be mandatory, other examples may use multiple elements to achieve the same functionality. Similarly, when a function is subsequently described as being implemented using multiple elements, other examples may use a single element or processing entity to achieve the same functionality. It should also be understood that the terms “comprising” and / or “including”, when used, specify the presence of the described features, integers, steps, operations, processes, actions, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, actions, elements, components, and / or any group thereof.

[0313] Unless otherwise defined, all terms (including technical and scientific terms) are used herein in the ordinary sense of the field to which the examples belong.

[0314] The Serial Time Encoded Physical Layer (STEP) can be an interconnect that supports high throughput of tens of Gb / s while having low power requirements, such as a bit efficiency of 1-2 pJ / bit. STEP uses time coding to modulate digital pulses and transmits multiple bits for each signal edge present in the data signal transmitted via the interconnected transmission link. This eliminates the need for a separate clock channel or clock recovery circuitry. The transmission link between the transmitter and receiver of the STEP interconnect can be differential, using two separate transmission lines, or it can be single-ended, using a single transmission line.

[0315] For example, data is encoded by the time interval between each pair of complementary signal edges (rising edge to falling edge or falling edge to rising edge) of the data signal in the STEP interconnect, such as... Figure 1a As shown. In Figure 1a In the example, each signal edge represents 3 bits of payload data, as shown by eight pairs of possible rising signal edges and subsequent falling signal edges. The first portion of the payload data is encoded by the time period (or time difference) between rising signal edge 1 and one of the eight possible subsequent falling signal edges 2, 3, 4, 5, 6, 7, 8, and 9, thus allowing 3 bits of data to be encoded in that pair of adjacent complementary signal edges. The data encoded and transmitted by the time period between pairs of adjacent complementary signal edges is also called a symbol or data symbol. Figure 1a In the data signal shown, the first symbol is encoded by the time period between the rising signal edge 1 and the selected signal edges 2 to 9 of the falling signal edges.

[0316] The subsequent symbol is encoded by the time interval between the selected falling edge of the first data symbol and the subsequent rising edge 10. Assuming the first data symbol is "7", it is encoded by rising edge 1 and falling edge 9. Figure 1 illustrates the subsequent transmitted data symbol "0", which is encoded by falling edge 9 and rising edge 10, separated only by the minimum pulse width.

[0317] Although Figure 1a The example illustration shows an instance where each data symbol (a time interval between consecutive complementary signal edges) has 3 bits of data, but other examples could similarly use any different number of bits for each symbol, such as 1, 2, 4, 5, or any other integer. If each symbol represents an integer N bits, then there are 2 bits between successive signal edges. N There are several possible time periods. Another example could also be used that does not correspond to producing 2. N Instead of using an integer number of bits for each possible time period, an encoding scheme using any number of possible time periods (e.g., 3, 5, 6, 7, or any other integer) between successive signal edges is used.

[0318] For implementation reasons, a minimum pulse width may be required between any pair of successive complementary signal edges (e.g., between rising signal edge 1 and the first possible falling signal edge 2), which is longer than the time difference between any pair of adjacent falling signal edges (e.g., between falling signal edges 2 and 3). The time difference between two possible adjacent signal edges of the same type may also be referred to as the symbol separation time. An alternative implementation may not require a minimum pulse width, and thus the symbol "0" will also be encoded by a time period equal to the symbol separation time.

[0319] like Figure 1aAs shown, the data signal transmitted in the STEP interconnect can be characterized as a sequence including a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type, wherein the first signal edge and the second signal edge are separated by a first time period corresponding to the first data to be transmitted, and the second signal edge and the third signal edge are separated by a second time period corresponding to the second data to be transmitted.

[0320] Alternatively, the data signal may be characterized as comprising three signal edges that follow each other, wherein a first time interval between a first signal edge and a second signal edge of the three signal edges corresponds to a first transmitted symbol, and a second time interval between a second signal edge and a third signal edge of the three signal edges corresponds to a second transmitted symbol.

[0321] The two previous representations of the data signals for STEP interconnects can be used interchangeably, and whenever one representation is used, the other representation can be used instead.

[0322] Based on the prior considerations, an example of an apparatus capable of generating a data signal (STEP signal) for a STEP interconnect (e.g., within a transmitter) may be characterized by including processing circuitry configured to generate a data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type, wherein the first and second signal edges are separated by a first time period corresponding to a first data to be transmitted, and the second and third signal edges are separated by a second time period corresponding to a second data to be transmitted.

[0323] Alternatively, the apparatus for generating a data signal may be characterized by including a processing circuit configured to generate the data signal, wherein the processing circuit is configured to adjust the time interval between the successive signal edges of the data signal based on the various data portions to be transmitted.

[0324] The two previous representations of the data signals for STEP interconnects can be used interchangeably, and whenever one representation is used, the other representation can be used instead.

[0325] Optionally, the apparatus for generating the data signal may further include an output interface circuit configured to output the data signal.

[0326] Figure 1bThe illustration schematically depicts an example of a STEP interconnect for bidirectional communication. In a bidirectional implementation, STEP interfaces 12 and 14, communicating with each other, are both capable of sending and receiving data signals. STEP interfaces 12 and 14 can be connected by a single transmission link 16. Transmission link 16 can operate in time-division duplex (half-duplex) mode to enable bidirectional communication via the single transmission link 16. Alternatively, for full-duplex (double simplex) communication, two transmission links 16a and 16b can be used, each connecting the output driver stage of one STEP interface to the input driver stage of the other STEP interface. A single transmission link can be single-ended, using a single transmission line, or it can be differential, using two or more transmission lines. STEP interfaces 12 and 14 and their associated transmission links constitute a STEP interconnect. In an alternative example, a STEP interconnect can also be established for unidirectional communication.

[0327] Since both STEP interfaces 12 and 14 share the same architecture, only STEP interface 12 will be discussed further. STEP interface 12 includes digital processing circuitry 18 for digital signal processing. For transmission, digital processing may include modulating payload data into payload data symbols according to the STEP protocol. Additionally, digital processing may include assigning time periods to each payload data symbol and optional additional symbols used in the STEP implementation. To generate a data signal based on the assigned time periods, a digital-to-time converter 22 may be used to generate a series of complementary signal edges in the data signal. A power amplifier may be coupled to DTC 22 to drive the transmission link.

[0328] To receive data signals, the STEP interface 12 includes a low-noise amplifier coupled to the transmission link 16 and a subsequent time-to-digital converter 20 (TDC) to determine the time intervals between two successive signal edges within the data signal. The TDC 20 determines a digital quantity for each time interval between signal edges, which can be further processed within digital processing circuitry 18. For reception purposes, digital processing may include assigning payload data symbols to each determined time interval and demodulating the payload data symbols to determine the payload data.

[0329] A battery-powered voltage converter 24 (DC / DV converter) can be used to provide power to the STEP interface 12, while other examples can similarly be powered by AC power. Although Figure 1bThis focuses on components used within the physical layer controller for the data interface, but other examples may also include higher-level processing of the protocol stack, such as processing circuitry for Medium Access Control (MAC). In cases where the physical layer (PHY) controller uses a STEP interface, the input / output interfaces within the PHY controller can be used to connect to a dedicated MAC layer controller.

[0330] Some examples of TDC used within the STEP interface can directly determine the time interval between two successive complementary signal edges within a data signal. Figure 1c The illustration shows an exemplary implementation of a time-to-digital converter (TDC) determining the time interval between two successive complementary signal edges within a data signal (between rising and subsequent falling signal edges, and between falling and subsequent rising signal edges). TDC determination Figure 1a The data signal includes a sequence of complementary signal edges of a first type, a second type, and a third type, and measures the time interval between successive complementary signal edges.

[0331] Figure 1c The TDC schematically illustrated is implemented as a sequence of inverters 30a to 30f, where each inverter operates as a delay element. The delay introduced by each inverter can be fixed, while other implementations may allow individual adjustment of the inverter's delay. A data signal is input to the first inverter 30a in this series and simultaneously to a trigger inverter 32. Through each inverter, signal edges present in the data signal are delayed, while the signal state changes (from high to low or vice versa). The outputs of each delay element 30a to 30f are coupled to the inputs of a first set of edge-triggered triggers 34a and a second set of edge-triggered triggers 34b.

[0332] All flip-flops in both sets 34a and 34b are jointly reset by trigger inverter 32. However, the flip-flops in the first set 34a are triggered by a positive edge, while the flip-flops in the second set 34b are triggered by a negative edge. With this setup, the first set of flip-flops 34a outputs a signal when a negative signal edge is present within the data signal, while the second set of flip-flops 34b outputs a signal when a positive signal edge is present within the data signal. However, the signal pattern at the output of the first set of flip-flops allows inference of how long before the previous positive signal edge was received within the data signal. Specifically, an inverter with the same signal state at its output and at its input (read out using the corresponding flip-flop) indicates the position of the previous positive signal edge within the delay line and thus indicates the time period between the triggering of the negative signal edge and the previous positive signal edge. Therefore, the readout of the first set of flip-flops 34a by the positive pulse decoder 36a allows the determination of the time period during which the received data signal was in a high state and thus provides the time period associated with the received symbol.

[0333] Similarly, the negative pulse decoder 36b allows for the determination of the time period during which the received data signal is in a low state and thus provides the time period associated with the received symbol. If Figure 1c The TDC received such as Figure 1a The data signal shown indicates that the TDC determines a sequence of first signal edges of type one, second signal edges of type two, and third signal edges of type one. The first and second signal edges are separated by a first time period corresponding to the first data to be transmitted, and the second and third signal edges are separated by a second time period corresponding to the second data to be transmitted. Pulse decoders 36a and 36b determine the time periods of high and low pulses with a resolution given by the delays of inverters 30a to 30f, a resolution that allows for the maximum length of a single time period (the dynamic range of the TDC) depending on the total number of inverters causing the overall delay of the delay line.

[0334] Based on the foregoing considerations, examples of devices capable of generating (e.g., within a transmitter) or receiving (e.g., within a receiver) STEP signals can be defined as follows.

[0335] According to an example, an apparatus for generating a data signal includes a processing circuit configured to generate a data signal comprising a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type, wherein the first and second signal edges are separated by a first time period corresponding to first data to be transmitted, and the second and third signal edges are separated by a second time period corresponding to second data to be transmitted; and an output interface circuit configured to output the data signal.

[0336] For example, the first type is an ascending edge and the second type is a descending edge, or the second type is an ascending edge and the first type is a descending edge.

[0337] The sum of the first and second time periods can be less than 1*10. -7 s (or less than 5*10) -7 s, less than 1*10 -8 s or less than 5*10 -8 s).

[0338] For example, the processing circuit can also be configured to generate a second data signal that is inverted relative to the first data signal.

[0339] The first data may be represented by a first data symbol and the second data may be represented by a second data symbol to be sent according to a data communication protocol.

[0340] For example, the device may also include at least one digital-to-time converter configured to generate the data signal.

[0341] The output interface circuit can be configured to output data signals to a wired transmission link consisting of one or more transmission lines.

[0342] According to an example, an apparatus for receiving a data signal includes a processing circuit configured to determine a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type in the data signal. Additionally, the apparatus includes a demodulation circuit configured to determine first data based on a first time period between the first and second signal edges, and to determine second data based on a second time period between the second and third signal edges.

[0343] For example, the first type is an ascending edge and the second type is a descending edge, or the second type is an ascending edge and the first type is a descending edge.

[0344] The sum of the first and second time periods can be less than 10. -7 s (or less than 5*10) -7 s, less than 1*10 -8 s or less than 5*10 -8 s).

[0345] The processing circuit can also be configured to receive a second data signal, which is inverted relative to the given data signal. Additionally, the processing circuit can be configured to determine a first signal edge, a second signal edge, and a third signal edge based on the second data signal.

[0346] The time interval between two signal edges can correspond to the data symbols of the communication protocol.

[0347] The device may also include at least one time-to-digital converter configured to determine a first time period and a second time period.

[0348] According to an example, an apparatus for generating a data signal includes a processing circuit configured to generate a data signal comprising alternating signal edges of a first type and a second type. The time interval between each pair of successive signal edges corresponds to data to be transmitted. The number of time intervals per second can be greater than 1*102. 7 (or higher than 5*10) - 7 s, higher than 1*10 -8 s or higher than 5*10 -8 s).

[0349] The time interval between two signal edges can correspond to the data symbols of the communication protocol.

[0350] Data signals can be digital signals transmitted using wired transmission links.

[0351] According to an example, an apparatus for generating a data signal includes a processing circuit configured to generate a data signal comprising a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type, wherein the first and second signal edges are separated by a first time period corresponding to first data to be transmitted, and the second and third signal edges are separated by a second time period corresponding to second data to be transmitted.

[0352] According to an example, an apparatus for generating a data signal includes a processing circuit configured to generate the data signal, wherein the processing circuit is configured to adjust the time interval between the sequential signal edges of the data signal based on the various data portions to be transmitted.

[0353] The STEP interconnect examples implement multiple features to achieve goals depending on the implementation and allow for the use of interconnect examples for a variety of use cases. Some of these features will then be described using individual examples. The various examples will be described in groups related to different aspects of the interconnect.

[0354] The discussion will begin with examples involving the physical interface (Phy) and the algorithms used to run said interface, followed by examples involving media access control (MAC) and related algorithms. Then, examples of circuits involving the various functions of the interconnect will be described. Subsequent sections will discuss examples related to the calibration of interconnect components, followed by examples related to specific architectural aspects of the interconnect. The discussion will conclude with examples of different use cases enabled by the interconnect.

[0355] Any of the examples disclosed thereafter may be combined with any aspect of the previously described examples of the apparatus for generating data signals or the apparatus for receiving data signals.

[0356] In a STEP system, the receiver (RX) can be "self-triggering," meaning that at least the clock operating the PHY is derived from the data signal itself. Therefore, there is no need to pass a clock signal between the transmitter (TX) and RX. RX clocking is performed by the received signal, which minimizes the number of channels between TX and RX. Additionally, power consumption is reduced because no PLL or CDR is needed in the RX, and system latency is reduced because there is no need to wait until the PLL / CDR in the RX is locked.

[0357] Figure 1d An example of a device for receiving data signals that is to operate in a self-triggered receiver (e.g., within a STEP system) is illustrated.

[0358] Device 102 includes a demodulation circuit 106, a processing circuit 104, a detection circuit 108, and an oscillator circuit 110. Device 100 receives, for example, data signals generated by a STEP-compliant transmitter 112, in... Figure 1a The data signal is shown for illustrative purposes only. Demodulation circuit 106 is configured to demodulate a data signal conforming to STEP. If, for example, two data symbols are received, demodulation circuit 106 determines first data based on a first time period between a first signal edge and a second signal edge within the data signal, and determines second data based on a second time period between a second signal edge and a third signal edge within the data signal. Processing circuit 104 determines a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type within the data signal. Processing circuit 104 may, for example, include a time-to-digital converter (TDC) that transmits the determined first and second time periods to demodulation circuit 106.

[0359] The detection circuit 108 is configured to generate a trigger signal when no data is identified in the first or second data. The detection circuit 108 may be coupled to the demodulation circuit 106, or, as shown in FIG1, to the processing circuit 104. Detection may be performed, for example, by identifying one or more successive time periods that do not correspond to data. Alternatively, the detection circuit 108 may infer that no data has been transmitted if the processing circuit 104 fails to identify signal edges within the data signal for a predetermined period of time, or if the processing circuit 104 receives a specific pattern of successive complementary signal edges.

[0360] Based on the trigger signal, oscillator circuit 110 generates a clock signal. This clock signal can then be used to clock internal components within the receiver, which would otherwise operate using a clock derived from the received data signal itself. Oscillator circuit 110 thus allows operation of components of device 102 even if no data is received via the data signal. The generated clock signal can, for example, be used to further process data within the signal processing chain of the receiver or device 102, even if no further data is received via processing circuit 104, ultimately resulting in a lack of a self-triggering clock. However, data already present in the signal processing chain can be processed using the clock signal from oscillator circuit 110 until the end of the chain to ensure that all received data is forwarded to a higher protocol layer of the receiver, such as the MAC layer. Using device 102 with detection circuit 108 and oscillator circuit 110 allows the STEP receiver to derive a clock from the data signal itself without the risk of data loss at the end of transmission. According to some examples, the data that might be missing from the data signal could be payload data.

[0361] In summary, the instantaneous data rate on the data link depends on the data itself, as the STEP uses a time-modulated signal generated by a digital-to-time converter (DTC) and received via the TDC. The TDC data processing circuit operates using the instantaneous CLK generated by the TDC receiving data. This is a valuable feature because the STEP RX can be self-triggered without requiring CLK / PLL / CDR. Once the TX finishes transmitting payload data symbols or data signals, the payload data existing in the components of the RX "pipeline" may not be further processed because the clock signal for the operating components may be missing. This could, for example, cause the data to fail to reach the MAC. As long as the STEP receives data, the demodulation circuit (receiver) can use its own generated CLK to deliver the received symbols to a First-In-First-Out (FIFO) circuit for further processing (this FIFO circuit can, for example, act as a rate converter to operate at two clocks, being filled at the rate of the TDC within the PHY and read out at a second rate using the first clock used within the MAC layer). Once payload data stops (e.g., at the end of packet processing), the TDC will stop generating the CLK signal, and data samples between the TDC output and the FIFO input will no longer be transmitted or further processed. This is achieved using... Figure 1a The device 102 shown is used to avoid this. Figure 1aThe first example is presented, in which we propose detecting the end of a transmission in the RX PHY layer and generating a synthesized CLK to pass data from the TDC output to the FIFO input. Doing this in the PHY layer (and, for example, not in the MAC layer) minimizes link latency.

[0362] Figure 1e The diagram illustrates a device for receiving data signals. Figure 1a The device shown is another example of sharing multiple components. Figure 1e In a specific example, the oscillator circuit 110 includes a ring oscillator 110a and a counter 110b. Upon a trigger signal, the ring oscillator begins to oscillate, while the counter 110b counts each oscillation. After a predetermined number of oscillations, the counter 110b stops the ring oscillator 110a from oscillating. Figure 1e The illustration shows a specific example of an oscillator circuit generating a clock signal that includes only a predetermined number of oscillations. This can be a beneficial implementation if the number of processing operations within the self-triggering processing pipeline of device 102 is well-defined. By having the oscillator circuit 110 generate only the number of oscillations required to clear the pipeline, energy is not wasted on unnecessary oscillations known in advance.

[0363] Following Figure 1d Example, Figure 1e The device 102 includes a MAC interface 112 configured to transmit payload data from the PHY layer to the MAC layer. According to some examples, the MAC interface includes an asynchronous FIFO to interface between different clock domains of the PHY and MAC. When no further payload data is received at the PHY, the FIFO is filled using a clock signal generated by the oscillator circuit 110.

[0364] According to another example, device 100 may include at least one data processing circuit other than a FIFO operated using a clock signal from oscillator circuit 110, which is only used as a specific example of clock-controlled processing circuit.

[0365] According to some examples, the detection circuit is configured to identify the End of Packet (EOP) symbol within the data signal and generate a trigger signal after EOP identification. This configuration allows for the safe clearing of the signal processing pipeline within the receiver after each data packet is received (indicated by the EOP), and further allows for a lower power state of the receiver after each EOP. In other words, the synthesized CLK is generated after the End of Packet (EOP) detection. Detection circuit 108 acts as an EOP detection block to enable the triggered ring oscillator. CLK generation is limited to N cycles by counter 110b. N cycles can be predetermined to the maximum number of cycles required in the worst-case scenario.

[0366] Figure 1f An example of a device 120 for generating a data signal is illustrated, wherein a clock signal required to properly enable the operation of a self-triggered receiver at the end of transmission is generated within the transmitter. Device 120 includes an input interface 122 for payload data and processing circuitry configured to generate a data signal output via an output interface 126. The generated data signal includes a first signal edge 128a of a first type, a second signal edge 128b of a second type, and a third signal edge 128c of a first type. A first time interval separating the first signal edge 128a and the second signal edge 128b, and a second time interval separating the second signal edge 128b and the third signal edge 128c, are generated by processing circuitry 124 differently depending on whether payload data is received at the input interface 122.

[0367] If payload data is received at input interface 122, the first time period is based on a first payload data symbol and the second time period is based on a second payload data symbol, depending on the payload received at input interface 122. However, if no payload data is received at input interface 122, the first time period is based on a first predetermined clock cycle time and the second time period is based on a second predetermined clock cycle time, so as to include a clock signal in the data signal, which can be used by the receiver to generate a clock signal for operating its internal components in the absence of payload data.

[0368] According to some examples, the processing circuitry 124 may therefore include a memory 124a storing a first predetermined clock cycle time and a second predetermined clock cycle time to provide an appropriate clock signal in the absence of payload data. To generate an appropriate data signal for the payload data, the processing circuitry 124 may, for example, include a modulator 124b configured to associate time periods with received payload data samples according to the STEP communication protocol. The sequence of edges within the data signal may, for example, be generated using a digital-to-time converter (DTC).

[0369] Depending on the specific implementation, the first and second time periods generated in the absence of payload data can be the same, resulting in oscillations with a 50% duty cycle, while alternative implementations can use different time periods. Furthermore, the frequency of the oscillations generated in the absence of payload data does not need to be constant. Instead, any number of time periods can be read from memory to generate the absence of data signal and payload data, such that the data signal can include successive complementary signal edges separated by time periods varying according to the sequence of time periods read from memory.

[0370] According to another example, device 120 may also include an oscillator circuit coupled to output interface 126 in the absence of payload data, such as Figure 1g As shown. In Figure 1g In the example, the apparatus 130 for generating the data signal includes an output interface 132, a modulator 134, a detector circuit 136, and an oscillator circuit 138. A STEP-compliant receiver 140 is shown for illustrative purposes only. The modulator 134 generates time intervals between successive signal edges based on the received payload data. The detector circuit 136 determines when no more payload data is being processed by the modulator 134. If no more payload data is being processed, the detector circuit 136 causes the oscillator circuit 138 to begin oscillating, causing the output interface 132 to incorporate the oscillation of the oscillator circuit 138 into the data signal.

[0371] In other words, Figure 1f and 1g The following example illustrates how the end of a transmission is detected in the TX PHY layer, which generates composite DATA or data symbols to be sent, allowing the RX to pass data from the TDC output to the FIFO input. Performing this operation in the PHY layer (rather than in the MAC layer) minimizes link latency. The end of the transmission is identified on the TX side (TX PHY), and composite data (not sent by the MAC layer) is generated to push data through the RX pipeline.

[0372] The method performed by any of the previously discussed devices will then be briefly illustrated using a flowchart. Figure 1h The diagram illustrates a flowchart of an example method for generating a data signal. The method includes determining a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type in a data signal 152. The method further includes determining first data 154 based on a first time period between the first and second signal edges, and determining second data 154 based on a second time period between the second and third signal edges. Additionally, the method includes generating a clock signal 156 when no payload data is identified within either the first or second data.

[0373] Figure 1iThe diagram illustrates a flowchart of an example method for receiving a data signal. The method includes generating a data signal 162 comprising a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type, the first and second signal edges being separated by a first time period, and the second and third signal edges being separated by a second time period. The method further includes determining a first time period 164 based on first payload data symbols and a second time period 164 based on second payload data symbols when payload data is available; or determining a first time period 166 based on a first predetermined clock cycle time and a second time period 166 based on a second predetermined clock cycle time when no payload data is available.

[0374] Differential interfaces require correct polarity connections at both ends of the transmission link for proper operation. If the transmission link is established via two separate transmission lines (e.g., coaxial cable), this requirement necessitates crossover transmission lines to connect the positive and negative lines to the correct polarity on both sides. Crossover transmission lines can, for example, degrade signal quality due to crosstalk and also consume more space, which can be limited within electronic devices. Due to electrical properties, not all standard interconnects allow for transmission line flips / crosses, thus limiting platform cabling.

[0375] Some interconnects, such as Fast PCIe, support polarity checking. In PCIe, polarity checking is triggered by the MAC, which sends a dedicated symbol called the polarity on each recovery stream. After such an initiated polarity check begins, the interface uses a dedicated message stream to perform polarity checks on the transmission lines of the differential transmission link and flips its inputs if necessary. Having a dedicated stream can complicate the system and increase exit latency by sending a polarity pattern that includes no data and requires special symbols only to indicate the start of the stream. Not supporting polarity checking can further complicate the overall system, requiring good alignment between the two sides. Platform routing can cause trace crossings, leading to degraded trace matching. For example, DPHYs completely disallow flipping between the positive and negative contacts of a differential transmission link. Implementing polarity checking on the link simplifies platform routing. Additionally, it avoids crossings along the transmission lines for better line matching. It also eliminates the need for pre-adjustment to avoid crossings. Providing polarity checking for transmission lines with low overhead may be desirable.

[0376] Figure 2aAn example of an apparatus for generating differential signal pairs is illustrated, which allows polarity checking to be performed at the receiving end of a transmission link. Apparatus 202 generates differential signal pairs for transmission through transmission link 204, which includes two transmission lines 204a and 204b. Output interface circuitry 203 of apparatus 202 is configured to simultaneously provide a first signal of the differential signal pair to the first transmission line 204a of transmission link 204 and a second signal of the differential signal pair to the second transmission line 204b of transmission link 204. During normal operation, the first and second signals are complementary states; that is, either the first signal is high while the second signal is low, or the first signal is low while the second signal is high. For polarity detection, the two signals may initially be in the same state for a period of time. The signals being in the same state for a period of time can also be used to control the power state of the receiver, as described in more detail later, for example. Figure 2b An example of a first signal 206a and a second signal 206b that can be generated to enable an associated receiver to determine the correct polarity of transmission lines 204a and 204b is illustrated. For the following discussion of the signals in the signal pair, it can be assumed that positive polarity is associated with the first signal 206a selected for the first transmission line 204a. Of course, in another embodiment, positive polarity may also be selected for the second transmission line 204b.

[0377] The first signal 206a and the second signal 206b are both initially at a first signal level, which is high in this specific example. In another example, similarly, both signals may initially be low. To enable polarity detection, the device 202 also includes a processing circuit 208 configured to change the signal level of the first signal 206a to a second signal level if the first signal 206a has a first polarity. Figure 2b In the example shown, the high level of signal 206a is switched to a low level at time 210, so that the processing circuit 208 is configured to change the signal level of the first signal 206a to a second signal level by generating a falling signal edge in the first signal 206a.

[0378] Using the apparatus 202 as described above enables the receiver to correctly determine the polarity of both transmission lines 204a and 204b by already determining within the PHY which of the transmission lines exhibits a change in signal level. As noted above, the polarity of the two transmission lines can be arbitrarily chosen, so that in an alternative example, the processing circuit 208 can also be configured to change the signal level of the second signal 206b to a second signal level and maintain the first signal 211a at the first signal level.

[0379] Polarity information can only be collected after power-on on the STEP interconnect and before the transmission of the first payload data begins. However, some examples may also maintain the STEP interface in power-saving mode after initial power-on when no payload data is to be transmitted. For this purpose, the processing circuit 208 may also be configured to maintain (hold) the second signal 206b at the first signal level if the first signal 206a has the first polarity, until payload data is to be transmitted.

[0380] Implementing polarity checking in the PHY, as exemplified by one of the examples, can significantly reduce system exit latency from power-saving mode. Polarity checking also allows for support of symmetrical connectors that can be inserted in both directions, which may be required in some solutions.

[0381] After indicating the polarity of the differential signal pair, the processing circuit can also be configured to submit payload data by generating one or both of the first signal 206a and the second signal 206b into a sequence including a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type. The first signal edge and the second signal edge are separated by a first time period corresponding to the first data to be transmitted, and the second signal edge and the third signal edge are separated by a second time period corresponding to the second data to be transmitted.

[0382] For example, for a first transmission line, a signal edge of type one can be a rising edge and a signal edge of type two can be a falling edge, while a second transmission line receives complementary signal edges, i.e., for the second transmission line, the first type is a falling edge and the second type is a rising edge. Alternatively, the second type of the first transmission line can be a rising edge and the first type can be a falling edge.

[0383] In the STEP system, the sum of the first and second time periods can, for example, be less than 10. -7 s (e.g., 10) -8 10 -9 10 -10 10 -11 Or less (seconds). In other words, in some examples of STEP systems, the minimum or average frequency of the data signal may be higher than 10 MHz (e.g., 100 MHz, 1 GHz, 10 GHz, 100 GHz or greater). The first data may be, for example, a first data symbol to be transmitted according to a data communication protocol and the second data may be a second data symbol to be transmitted according to a data communication protocol.

[0384] Contact the proposed technology or one or more examples described above or below (e.g.) Figures 2a to 2i(This is to refer to further details and aspects of device 2100a.) Device 202 may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples described above or below.

[0385] In summary, the STEP PHY layer can include two distinct states (as part of the power state flow, which will also be detailed later): when TX is de-energized to RX, RX outputs both P and N high. When TX exits the de-energized mode, it goes to idle or packet start, which forces P low and N high. The RX side can also use this information to determine polarity.

[0386] Figure 2c Further illustration shows a device 212 for processing differential signal pairs, which may be used, for example, within a STEP receiver. Device 212 includes an input interface circuit 214 configured to simultaneously receive a first signal of a differential signal pair from a first transmission line 204a of transmission link 204 and a second signal of a differential signal pair from a second transmission line 204b of transmission link 204. Both the first and second signals are initially at a first (logic) signal level (e.g., high or low). Device 212 also includes processing circuitry 216 configured to determine that the first signal has a first polarity if the signal level of the first signal changes from the first signal level to the second signal level. Determining that the first signal has a first polarity is equivalent to determining that the first transmission line 204a is the one used to transmit the signal of the first polarity, thereby allowing device 212 or a corresponding receiver to be appropriately configured. Figure 2b In the example signal shown, if a first signal 206a received via the first transmission line 204a changes its signal level from high to low, while a second signal 206b maintains the signal level at high, then device 212 determines that the first transmission line 204a is used for positive polarity. In other words, processing circuitry 216 can also be configured to determine that the first signal has a first polarity if the second signal maintains (remains) at the first signal level. For this purpose, processing circuitry 216 can, for example, be configured to determine the change from the first signal to the second signal level using a falling edge in the first signal.

[0387] In another example, the processing circuit 212 may also be configured to determine that the first signal has a second polarity if the signal level of the second signal 212b changes to a second signal level and if the first signal remains at the first signal level.

[0388] Figure 2d The illustration shows another example of a device for processing differential signal pairs, which is based on Figure 2c The example shown is from [the text]. Figure 2dIn this example, the device also includes another signal processing circuit 218. The other signal processing circuit 218 is implemented within the MAC layer, while the device 212 is implemented within the PHY layer. Figure 2d This illustration demonstrates that polarity detection, using the example described herein, can be implemented entirely within the PHY layer, resulting in very low latency during system startup or wake-up because no MAC layer interaction is required. Implementing this functionality in the MAC layer would require both the PHY and MAC layers to be fully awake before polarity detection can be performed. However, according to the... Figures 2a to 2i In the example described, polarity detection is performed automatically as part of the wake-up process when the system is powered on or woken up, and therefore has the lowest latency and the lowest signaling overhead.

[0389] In examples supporting the STEP protocol, device 212 may further include circuitry to receive and process payload data between successive signal edges. In these examples, processing circuitry 212 may also be configured to determine a sequence of first-type first signal edges, second-type second signal edges, and third-type first signal edges based on at least one of a first signal and a second signal. Furthermore, device 212 may include demodulation circuitry configured to determine first data based on a first time period between the first and second signal edges, and second data based on a second time period between the second and third signal edges.

[0390] Figure 2e An example of a processing circuit 220 for determining the properties of a differential signal pair to enable polarity detection is illustrated. Figure 2f The diagram shows... Figure 2e An example of the signals present within the processing circuit. Next, we will discuss... Figure 2e The description of the function of the example shown in the figure depends on Figure 2b The signal flow is shown in the diagram. Processing circuitry 220 includes a NAND gate 222 with inputs coupled to two transmission lines 204a and 204b. A first input of a first NOR gate 224a is coupled to the first transmission line 204a, while a second input is coupled to the output of the NAND gate 222. A first input of a second NOR gate 224b is coupled to the second transmission line 204b, while a second input of the NOR gate 224b is coupled to the output of the NAND gate 222. The output of the first NOR gate 224a is coupled to the set input of latch 226. The output of the second NOR gate 224b is coupled to the reset input of latch 226. The output of latch 226 indicates the properties of the differential signal pair, including information about which of the transmission lines is used for positive polarity.

[0391] like Figure 2fAs shown, once the signal on transmission line 204a (P line) goes low first, the latch outputs high, indicating that the polarity on transmission line 204a is positive. If transmission line 204b (N line) goes low first, the latch will output low, indicating that the polarity is negative and the data needs to be inverted.

[0392] exist Figure 2e In the example, the processing circuitry includes a NAND gate configured to generate a logic signal based on a first signal and a second signal. Additionally, the processing circuitry includes a first NOR gate configured to generate a first decision signal based on the first signal and the logic signal, and a second NOR gate configured to generate a second decision signal based on the second signal and the logic signal. The processing circuitry also includes a flip-flop circuit configured to output a polarity signal indicating the polarity of the first signal based on the first and second decision signals.

[0393] Figure 2g Another processing circuit 230 is illustrated, which includes a time-to-digital converter (TDC) 231 configured to simultaneously sample a first signal 232a and a second signal 232b based on a reference clock signal. The TDC 231 is also configured to provide an information signal 240 indicating which of the first and second signals changes from a first signal level to a second signal level to determine whether the first signal 232a and the second signal 232b should be inverted. XOR gates 236a and 236b serve as a signal switching circuit that inverts both signals 232a and 232b simultaneously if a logic "1" is provided to one of its two inputs while the other input is connected to the transmission line. If a logic "0" is provided, the signals are not inverted.

[0394] The logic "1" or "0" is provided by latch 242, which is active once the two transmission lines are held at different levels. The holding of the two transmission lines at different levels is evaluated by an AND gate 238 coupled to the two transmission lines. Latch 242 is enabled by a reference clock signal 234, and an information signal 240 is input to the data input of latch 242. When generating the information signal 240, TDC is used as a polarity detector. When the PHY is powered down, TDC is inactive and does not generate a clock. When TX begins transmitting payload data (or other signals, such as delimiters), TDC 231 will acquire a first edge (e.g., a long pulse followed by a short pulse at its end) before the first data ends. By examining the first signal edge of the received data (e.g., delimiter indication) and by determining whether a low or high pulse is received at the transmission line, the positive or negative polarity of the corresponding transmission line can be identified. Therefore, it can be determined whether the TDC input should be switched, and if so, the information signal 240 can be set to logic "1".

[0395] As already noted, if the polarity is determined to be different from that required by the receiver, the processing circuit 230 may invert the first signal received via the first transmission line and the second signal received via the second transmission line to subsequently process the signal with the correct polarity.

[0396] For this purpose, the processing circuit may further include a signal switching circuit 236 configured to receive the first signal and the second signal. The signal switching circuit 236 is configured to provide one of the first signal and the second signal to a first input of the TDC 231 based on the information signal 240, and to provide the other of the first signal and the second signal to a second input of the TDC based on the information signal.

[0397] exist Figure 2g In the example shown, the flipping is logically performed by using an XOR gate to invert the two signals. Other examples could use different signal switching circuitry, such as a multiplexer, to redirect the transmission line to different inputs instead of inverting the signals on the transmission line.

[0398] Figure 2h The diagram illustrates a flowchart of an example method for generating differential signal pairs, including simultaneously providing a first signal 262 of the differential signal pair to a first transmission line of a transmission link and providing a second signal 262 of the differential signal pair to a second transmission line of the transmission link, both the first and second signals initially being at a first signal level. The method further includes changing the signal level 264 of the first signal to the second signal level if the first signal corresponds to a first polarity.

[0399] Figure 2i The diagram illustrates a flowchart of an example method for processing differential signal pairs, including simultaneously receiving 272 a first signal of a differential signal pair from a first transmission line of a transmission link and a second signal of a differential signal pair from a second transmission line of the transmission link, wherein both the first and second signals are at a first signal level. The method further includes determining 274 that the first signal corresponds to a first polarity if the signal level of the first signal changes to the second signal level.

[0400] As noted above, this disclosure proposes a solution for interconnects to address differential line polarity in order to avoid data misunderstandings caused by misconnections between positive and negative lines along the system wiring. To achieve this, a mechanism is proposed in the PHY layer that detects polarity before the data, so that the MAC layer will correctly receive the data without needing to handle polarity. The previously described examples can also be applied to STEP interconnects.

[0401] Some examples of the proposed solutions can use the power state flow supported in STEP and add polarity checking on top of it without adding extra flow / symbols. In some STEP interconnects, when the PHY is off, TX is in a high-impedance (high Z) state. RX recognizes this as both lines (P and N) being in logic state "1", the only case where both transmission lines are maintained at equal signal levels. When TX exits this state, it sends a specific delimiter that instructs RX to power on. This delimiter sets the P line high and the N line low, so RX sees one of the lines go from logic state "1" to "0". This line is now set positive and knows the correct polarity from now on, without any MAC involvement.

[0402] In other words, in some examples, polarity checking is performed at the PHY layer, without requiring a dedicated message stream from the MAC layer. Additional symbols / delimiters may not be needed at the PHY layer to support polarity checking. Furthermore, if TDC capabilities are used to determine the link polarity, there is no latency penalty for polarity checking. For example, this process can be performed once upon power-up. The determined value can be written to the always-on register. Alternatively, the process can be performed every time the TX is powered on (without requiring additional HW support). The proposed technique also supports hot-plugging: when no TX device is inserted, the RX is in a power-down state (both lines are in logic state "1"), and when the TX device is inserted, the TX sends an exit from the power-down state with the correct delimiter.

[0403] The STEP interface uses time coding to modulate digital pulses and transmits multiple bits for each signal edge within the data signal (i.e., between a rising edge and a subsequent falling edge, and between a falling edge and a subsequent rising edge), eliminating the need for a clock channel or clock recovery circuitry. Data is encoded in the time difference between successive edges, so the instantaneous frequency of the data signal transmitted via the transmission link depends on the data itself. This can affect performance at the receiver or cause buffer overload / underload at the receiver, for example, if the average frequency becomes too high over a long period due to the payload data being transmitted.

[0404] Figure 3a The illustration shows an example of a method for generating data signals based on a series of data symbols. Figure 3a A block diagram illustrates how data signals based on a series of data symbols can be generated, maintaining desired signal properties or characteristics regardless of the data to be transmitted. An example of the desired signal properties will be given in one of the following paragraphs. This is for illustrative purposes only. Figure 3aThe method also illustrates receiving a series of data symbols 302, which is optional. Depending on the implementation, the method can also be performed based on the payload data before the payload data is modulated into data symbols for transmission via the PHY interface. During signal evaluation 304, a deviation from the desired signal properties is determined for a set of data symbols as the current deviation. The method can directly use the data symbols to calculate the deviation from the desired signal properties for that set of data symbols, or the calculation can be performed based on the payload data upon which the data symbols depend. For example, if the data symbols are generated based on a series of data bits generated within the MAC layer, the deviation calculation can be performed based on the data bits before the data bits are modulated into data symbols for transmission by the PHY layer, where modulation assigns several bits to a single symbol that is transmitted via the PHY interface. Some examples of STEP interfaces, such as modulating 3 bits of data into data symbols, are examples of this.

[0405] The method also includes comparing the current deviation with a cumulative deviation 307 306, the cumulative deviation being based on previous data symbols in the series of data symbols. The cumulative deviation 307 may be stored, for example, in memory, etc. A set of transmit symbols is generated during transformation 308. This set of transmit symbols is generated such that if both the current deviation and the cumulative deviation have the same property (e.g., the same symbol), then it has an inverse data symbol for each data symbol in the set. If the current deviation and the cumulative deviation have different properties, then the set of transmit symbols is generated to include the data symbols themselves. Determining whether the deviation from the desired signal property for an individual group of data symbols has the same (or similar) property as the cumulative deviation determined for previous data symbols allows for changing the data symbols within the individual group so that, on average, the desired signal property is maintained within the generated data signal. Depending on how the deviation from the desired signal property is determined, different average characteristics or properties of the data signal can be maintained or controlled. The following will detail how the average frequency and / or average common mode of the data signal on the transmission link of the STEP interface can be maintained according to an example of the method.

[0406] Figure 3b An example of a set of transmission symbols that can be generated by the methods described herein is illustrated. Figure 3b The diagram illustrates a series of eight payload data symbols 310a to 310h. This group of transmitted signals also includes two status symbols 312a and 312b. At least one of the status symbols indicates whether the group of transmitted symbols includes an inverted symbol, allowing the receiver to correctly determine the payload data transmitted within the data signal. Status symbols can also carry payload data. For example, if one bit modulated into a status symbol is used to indicate whether the group of transmitted symbols includes an inverted symbol, the remaining bits modulated into the status symbol can be used to transmit payload data.

[0407] According to some examples, the method also includes updating the cumulative offset based on the group of transmitted symbols. For this purpose, the previously determined current offset 304 can be used to update the cumulative offset 307, additionally taking into account whether the data symbols within that group of data symbols are to be converted. Updating the cumulative offset 307 for each group of data symbols processed allows the desired signal properties to be maintained over a long period.

[0408] In the case of STEP interconnection, maintaining the average frequency of the data signal is equivalent to ensuring that the average time length associated with each data symbol within that set of transmitted symbols is constant. As illustrated in Figure 1, the payload data is encoded by one of several possible time periods during which the data signal on the transmission line is maintained at a constant level. Although Figure 1 illustrates two possible levels, other examples may use multiple different levels to additionally achieve amplitude modulation. It is assumed that multiple successive short symbols within the payload data will therefore result in a data signal with a higher frequency than the data signal generated by a series of multiple successive long symbols.

[0409] In the STEP system, the desired average frequency can be defined in any way, for example, by requiring the average length of the time period to be 50% of the maximum length of the transmitted symbols associated with the payload data. In the example of Figure 1, eight possible transmitted symbols are illustrated, and the average length of the time period would then correspond to 50% of the time period associated with symbol 7 transmitted via the falling edge 9. According to another possible implementation, the average length of the time period can be defined as the middle between the lengths of the shortest symbol 0 and the longest symbol 7. The latter requirement can be achieved, for example, by requiring the average value of the transmitted symbols to be equal to 3.5.

[0410] Whenever the desired average signal properties are required to be maintained, the symbols of this set of symbols are inverted. Symbols can be inverted by inverting each bit of the symbol's binary representation and modulating the inverted binary representation onto the symbol according to the standard modulation scheme of Figure 1. Another way to invert symbols is to use the following relationship: for a symbol X with 2^N states, the sum of symbol X and its inverted symbol Y is (2^N-1): X + Y = (2^N) - 1.

[0411] Therefore, Y = (2^N)-1-X. For example, if the sign to be inverted, X, is 7, then the sign to be inverted, Y, will be 0, resulting in the desired change in the frequency of the data signal, as clearly seen in Figure 1.

[0412] Based on the above considerations, specific solutions regarding how to maintain the average frequency of the STEP interconnect are described below.

[0413] For each STEP data symbol within a set of data symbols (and for control symbols or control symbol indicators), the STEP encoder can calculate the sum of the symbol differences to the expected average for each new symbol, hereinafter referred to as sum[n], where n is the index of the nth symbol identifying the sequence. 2 N The number of data symbols (for N=3, it is, for example, 8) results in each symbol being [0,…,2]. N -1] is one of them. The average of the symbols is (2 N -1) / 2 (3.5 for N=3). Therefore, for the nth symbol, the deviation of all symbols from the expected average is calculated as follows:

[0414] sum[n] = sum[n-1] + symbol - (2 N -1) / 2.

[0415] In a specific example, the encoder samples a set or series of m input symbols (n = n0, ..., n0+m-1), calculates the average sign of these m symbols, and compares it with the total sign of the sum up to this point (total sign).

[0416] If the two positive and negative symbols are the same, it can be inferred that keeping m symbols unchanged will increase the deviation from the desired signal properties, and therefore the m symbols are inverted. The inverted data symbols are sent so that the new deviation from the desired average (sum[n0+m-1]) is closer to zero.

[0417] Some receivers can also be sensitive to the common-mode signal. Therefore, even if the transmitted data consists of high and low pulses with a fixed average frequency, it is still necessary to balance the common-mode to ensure that receiver performance is not degraded. The common-mode is the difference between the cumulative time of the data signal being in the high state and the cumulative time of the data signal being in the low state (the sum of the high pulses and the sum of the low pulses). For example, a sequence of symbols 0, 7, 0, 7, ... will produce a data signal with a constant average frequency, but will cause the maximum common-mode.

[0418] Maintaining the average common mode of the signals in the STEP interconnect shown in Figure 1 is equivalent to ensuring the following as a signal property: the difference between the average durations of the two possible signal states (high and low) shown in Figure 1 is zero.

[0419] According to some examples, if the previously given method for maintaining an average time period for transmitted symbols is executed in parallel and independently for both signal pulses transmitted in the high state and signal pulses transmitted in the low state, the average common mode of the signal is maintained. If both the low and high states are controlled to exhibit an average time period for their associated pulses, then the common mode, on average, lies in the middle between the high and low states, which may be desirable. Separately controlling the high and low states transforms into considering every other symbol in a series of symbols using the previously given method, such as by... Figure 3c The flowchart is shown.

[0420] An example of a method for generating a data signal thus includes: determining, 320, a deviation from a desired signal attribute as a first current deviation for every other data symbol in a group of data symbols, and determining, 322, a deviation from the desired signal attribute as a second current deviation for the remaining data symbols in the group of data symbols. The first current deviation is compared, 324, with a first cumulative deviation based on every other data symbol in a previous group of data symbols. Similarly, the second current deviation is compared, 326, with a second cumulative deviation based on the remaining data symbols in a previous group of data symbols. In comparison process 328, the group of transmit symbols is generated. Based on the results of comparisons 324 and 326, the group of transmit symbols is generated such that if both the first current deviation and the first cumulative deviation have the same attribute, it includes the inverse data symbol of every other data symbol in the group of data symbols; or if both the first current deviation and the first cumulative deviation have different attributes, it includes every other data symbol in the group of data symbols. Additionally, if the second current deviation and the second cumulative deviation have the same properties, then the group of transmitted symbols includes the inverse data symbol of each remaining data symbol in the group of data symbols; or if the second current deviation and the second cumulative deviation have different properties, then it includes each remaining data symbol in the group of data symbols.

[0421] In other words, to summarize Figure 3c The common mode is the difference between the sum of high pulses and the sum of low pulses. To maintain the average common mode, one or two additional bits are added and the encoder tracks and corrects the two sums, one for high pulses and one for low pulses (or falling and rising edges). That is, if sum[n] is calculated and individually adjusted to satisfy the target of 0 for both low and high pulses, both the desired average frequency and average common mode suppression are achieved. In doing so, each sum (sum[n]) is... high and sum low The sum converges to a zero average. Therefore, each sum maintains the average frequency and the combination also maintains the average DC value (or common mode) of the signal.

[0422] Depending on the implementation, the number *m* of symbols to be coupled according to one of the previous standards can be arbitrarily chosen. However, a specific number of *m* may be advantageous depending on the choice of modulation to simultaneously transmit a predetermined number of bits within a single payload data symbol. For example, if three bits of data can be submitted by a single payload data symbol, then processing 22 symbols of data as described above might be a beneficial choice. 22 symbols correspond to 66 bits of data, which allows for the insertion of two additional status bits to indicate whether the positive and / or negative periods of the transmitted signal carry inverted payload data symbols without incurring signaling overhead for the byte-by-byte MAC layer. For example, transmitting 8 bytes (64 bits) from the MAC layer of a STEP system requires 22 symbols. However, 22 symbols can transmit 66 bits, providing the possibility of including two status bits without incurring additional overhead. A similar option is to couple 44 data symbols. In the case of 44 symbols, 4 bits of data can be used as status bits. The encoder can also add two identical bits within the (additional) status symbols to indicate the polarity of one of the signal states. If, for example, 2 bits represent the status information of a signal state (high or low), then for subgroups of symbols processed independently, two identical bits can be used to pad the data bits to avoid errors. The first subgroup includes every other data symbol in a set of data symbols, and the second subgroup includes the remaining data symbols in that set. The status bits of different subgroups can also be submitted using two separate transmitted symbols.

[0423] An alternative to increasing the reliability of state bit transmission is to use a highly reliable modulation scheme for each symbol to transmit state information to avoid errors. For example, each possible data symbol above a threshold can be interpreted as one state (e.g., possible data symbols 6 and 7), and each possible data symbol below another threshold can be interpreted as another state (e.g., possible data symbols 0 and 1).

[0424] As another example, we additionally utilize Gray code to sort the code, and filling the state bits into the MSB will similarly allow it to be protected from errors, since Gray code is a mirror code.

[0425] In other words, summarizing the previous considerations, instead of simply transmitting pure payload data, some redundancy can be added to form an encoding scheme that allows the transmitter (TX) to manipulate the transmitted data to maintain average frequency and common-mode. This redundancy informs the receiver (RX) about changes so that it can correctly decode the information. The TX can track the currently transmitted data and calculate the average frequency (or phase drift) and accumulated common-mode. For each data symbol, or for a series of input data symbols, calculations are performed to determine the impact on frequency and / or common-mode. To satisfy frequency and / or common-mode conditions, a single data symbol or an entire series of data symbols can be inverted. The encoding scheme adds several bits at predetermined positions to inform the RX whether the transmitted data (pulses) or symbols are in their original or inverted form. Thus, the TX can control the average data and ensure average frequency and common-mode. This scheme allows for the maintenance of average frequency and common-mode and reduces design effort and circuit constraints from the system.

[0426] For example, the proposed scheme allows for limiting the receiver's buffer size and depends on the average data rate.

[0427] Besides the average frequency and common mode, the generation of spurious emissions, which are the presence of one or more peaks within the power spectral density, can be a problem. In some implementations, spurious emission should be avoided.

[0428] While the previously described method can be used to ensure the maintenance of the desired average frequency, this mechanism can also be used to avoid the generation of spurious signals. According to some examples, the average target frequency used in the previously described method for generating data signals is changed to another average target frequency. For another set of data symbols following the previous set which has been compared to the average target frequency, the deviation from the other average target frequency is determined. In other words, the average target frequency can be changed during the ongoing method. Changing the target frequency results in a broadening of the power spectral density, which is used to avoid spurious signals in the spectrum of the generated data signal.

[0429] Changing or altering the average target frequency can be done through various means. For example, a sequence of average target frequencies can be used such that another target frequency is selected from a predetermined sequence of average target frequencies. In another example, a random number generation method can be used to determine the average target frequency.

[0430] In other words, we can change the expected average AV according to the following formula. des To further modulate the average frequency, this might be suitable for the spectrum of the data signal created by diffusion: sum[n] = sum[n-1] + sign -AV desThe effective frequency for changing the average target frequency can be arbitrary. For example, the average target frequency can be changed for each group of data symbols being jointly processed. According to another example, the average target frequency can be changed for every two groups, every three groups, or every N groups of data symbols being jointly processed.

[0431] A particular implementation of how to modulate the average target frequency will be discussed in the following paragraphs.

[0432] In some examples, this is achieved by examining the sum of the symbols and comparing it with the average symbol s. avg The average time period of the PHY is controlled by multiplying by the number of symbols N in the PHY unit (e.g., 44) to control the PHY for the group of data symbols (e.g., for 44 data symbols, the latter corresponds to 22 DTC cycles).

[0433] Having value S i The sum of the offsets of a set of data symbols O k (The deviation from the signal attribute "average frequency") is defined as:

[0434] O k =∑S i -Ns avg

[0435] Furthermore, the total weight is the integral over all offsets after deciding whether to flip the bits and change the addition / subtraction:

[0436] W k =O k-1 ±O k

[0437] (Where "k" is the cell index, i.e., the number of the symbol group currently under consideration, "i" is the run index on the symbol within a specific cell, and "N" = the number of symbols in the cell)

[0438] This is a closed loop with a constant reference, which can generate spurious signals. To avoid this, we give an expression for O. k The new addition utilizes the diffusion factor R to create a new offset reference:

[0439] O k =∑S i -Ns avg +R k .

[0440] In other words, the cumulative value O of the signal attributes of the data symbols within this group of data symbols. k It is modified by adding a diffusion factor to the cumulative value to determine the current estimate of the signal properties.

[0441] R kIt is a sequence of diffusion factors with two fundamental parameters. The minimum and maximum values ​​set the diffusion factor, producing the diffusion width in the spectrum. Furthermore, the sequence is periodic, and this period represents the time taken to complete diffusion.

[0442] Sequences can be generated based on several options. The first option is pseudo-random generation, for example, using LFSR. Here, the number of bits is set to a diffusion period of T = 2NT. cycle Furthermore, the diffusion factor is set by dividing the LFSR by a specific value. Both the number of bits and the division factor are configurable to provide control over both diffusion parameters.

[0443] The second option is to use a deterministic sequence—for example, to implement a triangular sequence that runs from negative to a positive “x” value set by the diffusion factor, and the step window “y” is configured to eventually set the diffusion cycle to T = 2xyT_cycle.

[0444] If a certain modulation is required, a variable step window can also be configured.

[0445] In other words, some examples consider a diffusion factor for the set of data symbols. Some examples involve determining a cumulative value of the signal attribute for the data symbols within the set, adding a diffusion factor to the cumulative value to determine a current estimate of the signal attribute, and comparing the current estimate with the expected signal attribute to determine the current deviation.

[0446] A series of diffusion factors can be arbitrarily generated. Some examples select diffusion factors from a predetermined sequence. Other examples use random number generation methods to determine the diffusion factors.

[0447] A set of data symbols processed jointly by one of the described methods can also be characterized as a Basic Transmission Unit (BTU). A BTU can be the amount of data processed jointly by data processing methods within the PHY interface. For example, encoding / decoding or interleaving / deinterleaving (scrambling / descrambling) can be performed on the data according to the block size of the BTU. The data in the BTU is passed from the MAC layer to the STEP layer. The interface from the MAC layer to the PHY layer can be a parallel link, but it can also be a serial interface between MAC layers. The data constituting the BTU can be characterized by data structures used within the MAC layer (such as bits and bytes) or by data structures used within the PHY layer. The amount of data within the BTU can be arbitrary. For example, a BTU can be given by 44 data symbols or by 88 data symbols, corresponding to 264 data bits (33 bytes) or 528 data bits (66 bytes) of the MAC layer, respectively.

[0448] Figure 3dAn example of an apparatus 330 for generating a data signal is illustrated, which can perform one of the aforementioned methods. Apparatus 330 includes a monitoring circuit 332 configured to determine a deviation from a desired signal attribute as a current deviation for a set of data symbols. The apparatus also includes a decision circuit 334 configured to compare the current deviation with a cumulative deviation 338 based on previous data symbols in the series. Additionally, the apparatus includes a circuit 336 configured to generate a set of transmit symbols that includes, if the current deviation and the cumulative deviation have the same sign, the inverted data symbol of each data symbol in the set; or includes the data symbols in the set if the current deviation and the cumulative deviation have different signs.

[0449] Figure 3e The diagram illustrates the basis Figure 3d Another example of a device for generating data signals. Following... Figure 3d The apparatus of FIG3 includes a multiplexer circuit 340 configured to include a set of transmit data symbols and at least one status data symbol in the data signal, the at least one status data symbol indicating whether the set of transmit data symbols includes an inverted data symbol.

[0450] Previously, many signal generation methods have been discussed. Figure 3f and 3g Examples of methods in a device capable of receiving data signals generated by one of the aforementioned examples are briefly summarized.

[0451] Figure 3f An example of a method for receiving a data signal is illustrated. The method includes receiving 342 a set of transmitted symbols comprising at least one status data symbol and a set of data symbols. Additionally, the method includes inverting the data symbols of the set of transmitted symbols 344 if the status data symbol indicates that the set of transmitted symbols includes inverted data symbols.

[0452] Figure 3g An example of an apparatus for receiving data signals is illustrated. The apparatus includes input circuitry 350 configured to receive a set of transmit symbols comprising at least one status data symbol and a set of data symbols. Additionally, the apparatus includes inverting circuitry 352 configured to invert the data symbols of the set of transmit symbols when a status data symbol indicates that the set of transmit symbols includes inverted data symbols.

[0453] Figure 3h The diagram illustrates the use of... Figure 3c An example of the method that improves the spectrum of the generated data signal. Figure 3h The diagram illustrates the following: Figure 3cThe power spectral density of the data signal generated by this method is compared with the power spectral density without target frequency variation. This data signal is based on a random sequence of payload data. From Figure 3h It is clearly visible that when using the example method, spurious peaks 360a, 360b, 360c, and 360d are eliminated. When using (high-speed) communication interfaces as interconnects between electronic devices or components, it may be necessary to define a set of controls between the transmitting and receiving circuits on both sides of the interconnect. For example, controls may be used for synchronization, power management, flow control, etc. These controls should not be confused with any other payload data transmission to minimize the penalty to overall data throughput. Ambiguous controls can create a greater obstacle than missing payload data.

[0454] In standard protocols like PCIe Gen 1 and 2 and M-Phy, the transmitter uses overhead on the data bits (e.g., 8-bit to 10-bit mapping, and 128-130 mapping for PCIe Gen 3 and 4) to increase the number of transitions within the data signal so that the receiver can recover the clock from the data signal. The additional codes or symbols created in this way can be used to submit control words from the transmitter to the receiver to control the operation of the interconnect. Control words or control symbols are also referred to as tags in other interface technologies. To further enable the balancing of dynamic parameters of the data signal, such as frequency and common-mode voltage, several codes or symbols can be mapped to a single tag.

[0455] Traditional mechanisms can incur significant data overhead, which can compromise throughput. Control words / symbols may also be unprotected, allowing bit errors within the control word to be obfuscated and converted into data words.

[0456] In the STEP interface, the message or message stream used for control (control word) is called a "delimiter". A delimiter is represented by at least two successive pulses or symbols, a control symbol indicator, and a subsequent or preceding control symbol. The subsequent discussion of delimiters can also be applied to other communication interfaces besides STEP.

[0457] The STEP protocol is based on pulse-width modulation of the data to be transmitted, and each symbol is associated with a time period between two successive complementary signal edges. The time period used for the data is subsequently referred to as the payload data symbol. To avoid wasting payload data symbols on delimiters, the protocol assigns out-of-band / unique symbols to delimiters, allowing the receiver to easily detect them without any overhead penalty. In some examples, the time period associated with the delimiter is longer than the longest time period associated with the payload data. Furthermore, to balance the dynamic parameters of the line, delimiters can be mapped to a special clock period that balances itself without requiring any special processing from MAC / Phy. Delimiters can also be protected by mapping in a way that prevents errors from causing false detections. In summary, STEP assigns out-of-band symbols as delimiters, and delimiters can be self-balanced at both the frequency and DC levels. Delimiters can be unique and cannot be mistaken for data. Additionally, delimiters can be highly reliable and cannot be confused with any other delimiters.

[0458] For easy and protected / reliable reception of delimiters, out-of-band high / low pulses are used. Each delimiter is represented by at least two successive symbols (also called two successive pulses) within the data signal, a control symbol I indicator, and a subsequent control symbol. The control symbol indicator has an associated time period that is longer than the time period of any payload data symbol. In other words, the control symbol indicator is out-of-band in this respect.

[0459] While the out-of-band control symbol indicator indicates the presence of a delimiter, the control symbol—which can be in-band (with the length of the payload data symbol) or out-of-band—indicates the type of the delimiter and thus its content. Alternatively, more than one control symbol can be used with the control symbol indicator to increase the number of available delimiters (control statements).

[0460] Using the same phase separation as the payload data symbols for control symbols creates seven possible delimiters—assuming three payload data bits are transmitted for each symbol. Each delimiter has a long high or low pulse as a control symbol indicator and may have a short pulse following or preceding it to indicate the delimiter type.

[0461] A typical implementation defines at least three delimiters. The Start of Packet (SOP) includes a control symbol indicating the start of the packet. The End of Packet (EOP) includes a control symbol indicating the end of the packet. The Idle (I delimiter) includes a control symbol indicating idle mode, such as when the MAC has no payload data to send. For example, before transitioning to low-power mode, control symbols indicating idle mode may be sent.

[0462] Other examples of delimiters could be the Start of Calibration Cycle (SOC) with different types of calibration such as short / long / margin, the Start of Ultra-Reliable Packet Format (SOR), and so on.

[0463] Figure 4a Examples of the I delimiter, SOP delimiter, and EOP delimiter compared to the payload data symbol are illustrated. Figure 4a The example illustrates a first alternative to the submission delimiter, where control symbol indicator 402 is submitted first, followed by control symbol 404. Figure 4a In a specific example, the control symbol indicator 402 is submitted by a pulse width that is longer than the longest time period of the payload data symbol. Figure 4a Assume a modulation scheme in which three bits are modulated into the payload data symbol at once, producing a falling edge 406 corresponding to the longest time period of the payload data symbol "7". The control symbol indicator is longer than the longest payload data symbol and higher than the payload data threshold. Control symbol indicator 402 ( Figure 4a The initial high time (in the code) does not carry any real data, but instead indicates the commit of the delimiter. Control symbol 404 ( Figure 4a The subsequent low time interval (in the data) indicates the type of delimiter. In the example shown in Figure 4A, the three possible delimiters are distinguished by the positions of the rising signal edges 408a, 400b, and 408c. The I delimiter consists of the shortest control symbol (signal edge 408a), the SOP delimiter consists of a medium-length control symbol (signal edge 408b), and the EOP delimiter consists of the longest control symbol (signal edge 408c). However, other embodiments may similarly use another control symbol to indicate the I delimiter. To reliably detect the type of delimiter, the different control symbols are separated by a time interval longer than the payload data symbol—in the data interval (in the data interval). Figure 4a In the example, there are 3 steps between different delimiter types, i.e. between different control symbols, while the payload data symbols are separated by a single step.

[0464] Figure 4b The illustration shows one possible replacement for the submission delimiter, whereby control symbol 410 precedes control symbol indicator 412. Figure 4b In the example shown, the delimiter uses the low time as the long time period and the low time does not carry additional information, while the high time carries the delimiter type and constitutes the control symbol 410.

[0465] such as by Figure 4a and 4b As shown, the data signal of the delimiter includes a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type. The first and second signal edges are separated by a first time interval, and the second and third signal edges are separated by a second time interval. At least one of the first and second time intervals is longer than the time interval of any payload data symbol defined by the communication protocol. The longest time interval of any payload data symbol defined by the communication protocol can also be referred to as the payload data threshold.

[0466] Delimiter types other than the 'I' delimiter will be referred to in later paragraphs. Figures 12a to 12x More detailed description, and with Figures 4c to 4g The description will focus on the attractive use of the free space delimiter.

[0467] The idle delimiter can be used for power management. An idle delimiter can be sent when the MAC is not transmitting any payload data, for example, until the end of a unit being processed (e.g., n bits). However, if there is a long period of time without payload data to transmit, then... Figure 4c Long sequences of the I delimiters shown can occur.

[0468] Figure 4c The illustration shows an example of a data signal containing three successive delimiters of the same type, 420, 422, and 424, according to a conventional scheme. Because... Figure 4c The diagram illustrates a repetitive signal, which can produce glitches or spurious signals at the frequency of the main harmonic. As an example, if the length of the I delimiter is 0.8 nanoseconds (800 picoseconds), glitches will be generated at 1.25 GHz, 2.5 GHz, 3.75 GHz, and so on (n * 1.25 GHz).

[0469] Figure 4d The illustration shows an example of a data signal generated by an example of a device for generating data signals. The control symbol indicator (the long portion of the delimiter—whether high or low) can have any length higher than the payload data threshold (e.g., higher than 9 in the example shown). Therefore, by adjusting the length of the long portion of the delimiter, i.e., by adjusting the control symbol indicator ( Figure 23d High-time modulation (in the middle) to any number greater than the payload data threshold can avoid the generation of glitches. For example... Figure 4d As shown, the time period for sending the first control symbol indicator 424 is different from the time periods for subsequent control symbol indicators 426 and 428.

[0470] However, the time periods for successive control symbols 425, 427, and 429 are the same, indicating the same type of delimiter, such as the I delimiter. By modulating the length of the control symbol indicator, the overall length of the I delimiter varies between successive I delimiters, and spurious generation can be avoided.

[0471] The data signal generated based on this principle is characterized by a sequence of a first signal edge 420 of the first type, a second signal edge 432 of the second type, a third signal edge 434 of the first type, a fourth signal edge 436 of the second type, and a fifth signal edge 438 of the first type. The first and second signal edges are separated by a first time period 424, the second and third signal edges are separated by a second time period 425, the third and fourth signal edges are separated by a third time period 426, and the fourth and fifth signal edges are separated by a fourth time period 427. The first time period 424 is longer than the effective payload data threshold, the second time period 425 is shorter than the effective payload data threshold, the third time period 426 is longer than the effective payload data threshold and is different from the first time period 424, and the fourth time period 427 is equal to the second time period 425.

[0472] Alternative embodiments can be used similarly, such as Figure 4b The replacement pattern for the submission delimiter shown begins with a control symbol, followed by the control symbol indicator to be modulated. The correspondingly generated data signal includes a sequence of first signal edges of type 1, second signal edges of type 2, third signal edges of type 1, fourth signal edges of type 2, and fifth signal edges of type 1. The first and second signal edges are separated by a first time interval, the second and third signal edges are separated by a second time interval, the third and fourth signal edges are separated by a third time interval, and the fourth and fifth signal edges are separated by a fourth time interval. The first time interval is shorter than the payload data threshold, the second time interval is longer than the payload data threshold, the third time interval is equal to the first time interval, and the fourth time interval is longer than the payload data threshold and different from the second time interval.

[0473] The modulation scheme for the time period used to control the symbol indicator can be selected as needed. For example, the modulation could be adopted by starting with a minimum of 9, ramping up to 25, then decreasing back to 9, and then starting again. Alternatively, the length can be selected by a random number generator. Furthermore, the length does not necessarily have to change for every I delimiter. Instead, it can remain constant for a finite number of I delimiters until it is changed again. For example, the time period could remain at a length of 9 for several delimiters, then increase to 10, and so on; these are just a few examples.

[0474] Figure 4eAn example of a device 440 for generating a data signal is illustrated. The device 440 includes a processing circuit 442 configured to generate a data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, a third signal edge of a first type, a fourth signal edge of a second type, and a fifth signal edge of a first type. The first and second signal edges are separated by a first time interval, the second and third signal edges are separated by a second time interval, the third and fourth signal edges are separated by a third time interval, and the fourth and fifth signal edges are separated by a fourth time interval. The first time interval is longer than a payload data threshold, the second time interval is shorter than a payload data threshold, the third time interval is longer than a payload data threshold and different from the first time interval, and the fourth time interval is equal to the second time interval. Additionally, the device includes an output interface circuit 444 configured to output the data signal.

[0475] Figure 4f Another example of an apparatus 448 for generating a data stream is illustrated. Apparatus 448 includes processing circuitry 450 configured to generate a data stream comprising a sequence of control symbol indicators, control symbols indicating an idle state, another control symbol indicator, and another control symbol indicating an idle state; wherein the control symbol indicator is associated with a first time period, the control symbol is associated with a second time period, the other control symbol indicator is associated with a third time period, and the other control symbol is associated with the second time period. Additionally, apparatus 448 includes modulator circuitry 452 configured to determine the first and third time periods by changing the time periods within a time period interval according to a predetermined modulation scheme.

[0476] Figure 4g The diagram illustrates a flowchart of an example method for generating a data signal. The method includes generating a sequence of first signal edges of a first type, second signal edges of a second type, third signal edges of a first type, fourth signal edges of a second type, and fifth signal edges of a first type. The first and second signal edges are separated by a first time interval, the second and third signal edges are separated by a second time interval, the third and fourth signal edges are separated by a third time interval, and the fourth and fifth signal edges are separated by a fourth time interval. The first time interval is longer than a payload data threshold, the second time interval is shorter than a payload data threshold, the third time interval is longer than a payload data threshold, and the fourth time interval is equal to the second time interval. Additionally, the method includes changing the third time interval 462 to be different from the first time interval.

[0477] Figure 4hThe diagram illustrates a flowchart of another example of a method for generating a data signal. The method includes generating a 464-bit data stream comprising a sequence of control symbol indicators, control symbols indicating an idle state, another control symbol indicator, and another control symbol indicating an idle state; wherein the control symbol indicators are associated with a first time period, the control symbols are associated with a second time period, the other control symbol indicator is associated with a third time period, and the other control symbol is associated with the second time period. Additionally, the method includes varying the 466 time periods within a time interval to generate the first time period and different third time periods.

[0478] Some applications may use multiple channels or interconnects in parallel due to bandwidth requirements or architectural reasons. For example, a CPU may use multiple interconnects (STEP channels) in parallel to connect to memory / graphics / etc. In mobile devices, a single AP may use, for example, multiple STEP interconnects to drive LTE, WiFi, 5G, etc. If multiple interconnects are used in parallel, leakage can occur between adjacent interconnects. For example, in a STEP system, leakage between transmission links can increase jitter and degrade link quality. Other interconnects may experience other reasons for degraded link quality. The main contributor to leakage may originate from the output of devices (e.g., transmitters and / or receivers) or from crosstalk between transmission links, which are implemented as channels on a PCB, for example. Each implementer of interconnects such as STEP links designs its own PCB and routes the transmission lines of the transmission links according to PCB constraints. We cannot predict in advance what the main sources of leakage will be, because the combination of adjacent channels / transmission links on the PCB can be arbitrary.

[0479] While the primary sources of leakage cannot be reliably predicted in advance, leakage may exhibit at least one of the following characteristics: Leakage may have a high-pass frequency response, implying good isolation at low frequencies, which deteriorates as the frequency increases. The frequency response may be due to capacitive coupling or electromagnetic coupling. Leakage may have one or more primary sources, such as crosstalk between two adjacent transmission links.

[0480] Leaks can occur between any interconnect pairs, even if the affected transmitters and receivers are spaced apart. Figure 5a and 5b The diagram illustrates two setups where leakage may occur between interconnects. Figure 5a The diagram illustrates three interconnections 502, 504, and 506, consisting of transmitters 502a, 504a, and 506a and their associated receivers 502b, 504b, and 504b, respectively. These transmitters and receivers are connected via transmission links 502c, 504c, and 506c. Figure 5aIn the example, the interconnect layout is completely parallel, meaning the transmitters and receivers are adjacent to each other and the transmission links are wired so that they are adjacent to each other, identical to their associated transmitters and receivers. Figure 5a In the configuration, leakage can be dominated by crosstalk between transmission links 502c, 504c and 506c or by crosstalk from the transmitter output to adjacent transmission links or to the output of adjacent transmitters.

[0481] Figure 5b The illustration shows a setup with four transmitters 510a to 516a in a single chip 518 or package and two chips 519 and 520 including associated receivers 510b to 516b. Transmission links 510c to 516c connect the transmitters and receivers. Although transmitters 510a and 516a are spaced apart in chip 518, leakage can still occur between their interconnections due to the wiring of transmission links 510c and 516c. For example, the wiring on the PCB is unpredictable by the manufacturer of chips 518, 519, and 520.

[0482] It may be desirable to have means to compensate for or mitigate leakage between transmission links / data links or between interconnections.

[0483] Figure 5c An example of a sending system 530 is illustrated.

[0484] Transmission system 530 includes a first transmitter 532a coupled to a first output interface 532b for a first data link 532c. A second transmitter 534a is coupled to a second output interface 534b for a second data link 534c. Multiplexer circuit 536 is configured to switch a signal derived from a first data signal generated by the first transmitter 532a to a filter circuit 538 coupled to the second output interface 532b. Filter circuit 538 operates on data signals relating to data signals transmitted via the first transmission link 532c. In the event of leakage from a first interconnect link 532 including the first transmitter 532a and the first transmission link 532c to a first interconnect 534 including the second transmitter 534a and the second transmission link 534c, the leakage can be eliminated or at least reduced by applying a correction signal derived using filter circuit 538 to the output interface 532b used by the second interconnect. Figure 5c The transmission system allows for mitigation of the negative impact of leaks, regardless of the primary source of the leak. The use of a multiplexer also allows for the omission of correction signals unless a leak is identified between the first and second interconnects.

[0485] Other examples may include more than two interconnected transmitters, such as... Figure 5cThe diagram also shows a third transmitter 540a with an output interface 540b, and a first transmitter 542a with an associated output interface 542b. To ensure maximum system flexibility, the multiplexer 536 can be configured to switch the signal derived from the data signals generated by all transmitters 532a to 542a to any output interface via associated filter circuitry.

[0486] Another example could be configured to switch signals from two or more transmitters to a single output interface via two or more filter circuits in order to mitigate signal degradation caused by multiple interconnects leaking into a single interconnect simultaneously.

[0487] According to another example, filter circuit 538 exhibits variable filter characteristics, allowing the tuned filter circuit 538 to reproduce the characteristics of leakage between two interconnects in order to suppress signal degradation caused by leakage as much as possible. According to another example, filter circuit 538 has high-pass filter characteristics.

[0488] In other words, Figure 5c A general solution for leakage cancellation is shown. Each data signal from the transmitter (e.g., a STEP channel) is sampled and multiplexed by a MUX 536 to its crosstalk channel. If cancellation is performed on the transmitting side, such as Figure 5c As shown, the signal can also be copied directly from the transmitter (e.g., from the DTC within the STEP system) without sampling. Generally, the signal derived from the data signal associated with the transmitter is used for leakage elimination. Figure 5c The illustration only shows single-channel leakage cancellation, but the same principle can be applied to multiple cancellation signals injected to account for crosstalk from multiple channels to a single channel.

[0489] Figure 5d The schematic illustration shows an example of a filter circuit 550 for adaptive leakage cancellation from one channel to another. Specifically, Figure 5dAn example is illustrated where the destructive superposition of a correction signal derived from a data signal in a first interconnect is achieved by cross-coupling the positive and negative components of the interconnect links. Filter circuit 550 includes a positive input 552a for the positive component of the differential data signal and a negative input 552b for the negative component of the differential data signal. Filter circuit 550 also includes a positive output 554a for the positive component of the differential data signal and a negative output 554b for the negative component of the differential data signal. Filter circuit 556 is coupled between the positive input 552a and the negative output 552b, and between the negative input 552b and the positive output 554a. When the input for the positive component of the differential signal is coupled to the output for the negative component of the differential signal, the filtered input signal constituting the correction signal is automatically subtracted from the signal connected to the output of filter circuit 550 to mitigate leakage between the first interconnect 546 and the second interconnect 548. Figure 5d The illustration shows leakage cancellation for a single channel, but the same principle can be applied to multiple cancellation signals injected to account for crosstalk from multiple channels to a single channel, such as by... Figure 5c and 5e As shown.

[0490] like Figure 5d As further illustrated, adaptive leak elimination can be performed on the RX side or the TX side. Figure 5c The example illustration shows a transmission system capable of performing leak elimination, while Figure 5e The diagram illustrates a data receiving system capable of performing leak elimination on the RX side. In other words, Figure 5e The illustration shows RX-side leakage elimination using a MUX for proper cross-coupling and leakage elimination.

[0491] Figure 5e The diagram illustrates a data receiving system 580, which includes a first receiver 582a coupled to a first input interface 582b for a first data link 582c. A second receiver 584a is coupled to a second input interface 584b for a second data link 584c, and a multiplexer circuit 586 is configured to switch a signal derived from a first data signal received at the first input interface 582b to a filter circuit 585, the output of which is coupled to the second input interface 584b.

[0492] The general principles of filter circuits 585 and leakage elimination are related to... Figure 5c The descriptions of the sending systems are similar, so please refer to the relevant paragraphs here. Because... Figure 5e The data receiving system 580 operates on the receiving side, so the first data signal received at the first input interface 582b may need to be sampled or directly copied to the filter circuit 585 before being copied, so that a correction signal can be generated by the filter circuit 585. Figure 5cSimilar to the example shown, multiple additional receivers, such as receiver 586a and receiver 588a, may exist within other examples of the data receiving system, together with their input interfaces 586b and 588b, to build a highly flexible system.

[0493] and Figure 5c Similar examples exist. Figure 5e Examples may include a filter circuit 585 with high-pass characteristics. According to another example, the filter characteristics may be variable to tune the transfer function of the filter circuit 585 to the transfer function of the leakage between the two interconnects during operation, since the transfer function is not known in advance.

[0494] use Figures 5c to 5e One example of this is avoiding the requirement for high isolation between data channels as a specification for both the PCB and the RFIC outputs of the interconnect, which would impose large separations between channels and result in inefficient PCBs and RFICs.

[0495] exist Figures 5c to 5e The illustration shows examples of data transmission and reception systems that enable leak elimination. Figure 5f The diagram illustrates a method for mitigating leakage in the first interconnect to the second interconnect by means of one or both of the previously described systems.

[0496] A method for mitigating leakage in a first interconnect to a second interconnect includes deriving a data signal 592 from a first data signal generated by a first transmitter of the first interconnect to generate an original signal. The method further includes filtering the original signal 594 to generate a correction signal and applying the correction signal 596 to a second data link used by the second interconnect.

[0497] According to some examples, deriving a data signal from a first data signal may include, for example, sampling the first data signal if the method is implemented on the receiver side. According to another example, deriving a data signal from a first data signal may include, for example, copying the first data signal if the method is implemented on the transmitter side.

[0498] Based on some examples, filtering uses a high-pass characteristic for the reasons detailed earlier.

[0499] Some examples also include adjusting at least one of the amplitude, phase, and delay of the correction signal. Adjusting one of these parameters can be used to tune the correction signal so that it corresponds as closely as possible to the signal leaking from the first interconnect into the second interconnect and eliminates the leaked signal as well as possible.

[0500] In order to determine how well the leakage has been eliminated and / or how well the filtering of the original signal has simulated the leaked signal, additional examples include determining the signal characteristics of the second data signal on the second data link.

[0501] In some examples, this characteristic is either the Bit Error Rate (BER) or jitter. The BER or jitter of the second data signal impaired by leakage allows us to determine how severely the leakage is damaging the signal. For example, if the BER is high, we can infer that the current leakage is indeed still causing a significant degradation in signal quality. Similarly, a high jitter rate allows for the same inference. On the other hand, if both signal characteristics are low, we can infer that leakage cancellation is still working well.

[0502] Another example involves changing filter characteristics to filter the original signal until the signal characteristics meet a predetermined criterion. Repeatedly evaluating the signal characteristics until the predetermined criterion is met while changing the filter characteristics helps to adjust the filter characteristics during operation to match the leakage properties as well as possible. For example, if the signal characteristics exhibit a minimum value or if the signal characteristics are below a predetermined threshold, the predetermined criterion is met. If a minimum value of a specific signal characteristic is experienced at a given filter characteristic within a given search space of filter characteristics, it can be inferred that the signal characteristic exhibits a minimum value. The given filter characteristics thus determined can then be used during operation to mitigate signal impairment caused by leakage from the first interconnect to the second interconnect.

[0503] The filter characteristics to be changed could be, for example, signal attenuation at a certain frequency, phase shift of the signal applied within the filter, the effective low and / or high frequencies of the filter, or any other characteristic of the filter. According to some examples, the filter's transfer function can be changed.

[0504] Such as Figure 6a Interconnects such as the STEP interface shown often require operation at very low bit error rates (BER, in the case of STEP interconnects, can be as low as 1e-12). In a STEP interconnect, STEP transceiver 602 includes a transmitter 602a coupled to a first transmission link 606a and a STEP receiver 602b coupled to a second transmission link 606b. Similarly, STEP transceiver 604 includes a transmitter 604a coupled to a second transmission link 606b and a STEP receiver 604b coupled to a first transmission link 606a to establish a STEP interconnect comprising two unidirectional transmission lines.

[0505] STEP generation can support BAUD rates of 20Gbps and even higher, such as 40Gbps. Increasing the BAUD rate of STEP interconnects means that the time difference between symbols (symbol separation time) needs to become shorter, without necessarily reducing noise and jitter. For example, in the case of STEP, low BER requires very low jitter in the data signal to avoid errors in symbol determination. For other interconnects besides STEP, the requirements for parameters other than jitter may be equally stringent in order to achieve low BER.

[0506] However, increasing the interconnect bandwidth (BAUD) without increasing the bit error rate may be desirable.

[0507] Figure 6b The diagram illustrates a flowchart of an example of a method for processing data signals.

[0508] according to Figure 6b In the example shown, a set of payload data symbols is received 610. If the set of data symbols contains an error, a negative acknowledgment signal 612 is issued. Additionally, if an error is detected, a second set of payload data symbols is received 614 after a predetermined number of sets of payload data symbols following the issuance of the negative acknowledgment signal, or after a predetermined number of sets of payload data symbols following the reception of the first set. The method also includes using 616 the second set of payload data symbols instead of the set of payload data symbols.

[0509] Issuing a negative acknowledgment (NACK) signal in the presence of an error can, for example, allow the transmitter to retransmit the information contained in the second set of payload data symbols. The receiver or means for processing the received data signal can then use the retransmission via the second set of data symbols to determine the correct payload data. Due to the use of... Figure 6b The round-trip time of the interconnection in the method shown can be known, so the elapsed time until a retransmission via the second set of payload data symbols or the number of sets of received payload data symbols is predictable. Therefore, a receiver implementing this method can know in advance which subsequent set of payload data symbols includes the retransmission. Thus, any additional overhead required to notify the currently received set of payload data symbols that it includes the retransmission can be avoided. In a first alternative, the counting of the sets of symbols waiting until a retransmission via the second set of payload data symbols is received begins from the set of payload data symbols containing the error. In a second alternative, the counting may begin when a negative acknowledgment signal is issued.

[0510] If no error is determined for a set of payload data symbols, an embodiment of one method then skips replacing that set of payload data symbols, such as by... Figure 6b The optional step 618 is shown in the diagram.

[0511] Based on some examples, different demodulation schemes can be used to demodulate the first set of payload data symbols and the second set of payload data symbols used for retransmission. For example, a more robust modulation scheme can be selected for retransmission within the second set of payload data symbols. A more robust modulation scheme is one that is more tolerant of errors in signal parameters that affect the data signal during transmission. For example, in the case of STEP interconnection, a more robust modulation scheme can use a longer symbol separation time to distinguish adjacent symbols. A longer symbol separation time allows for higher jitter without causing demodulation errors. Using a more robust modulation scheme thus avoids repeatedly receiving corrupted payload data.

[0512] In some examples, the set of payload data symbols is received via a first transmission link, while the negative acknowledgment signal is received via a second transmission link. Using a different transmission link avoids switching the first transmission link from receive mode to transmit mode, thus saving the delay until the negative acknowledgment signal is sent, and therefore also avoiding the additional delay until the second set of retransmitted data symbols is received.

[0513] Errors within this set of payload data symbols can be determined, for example, using cyclic redundancy check (CRC) or any other error detection method. Cyclic redundancy checks can be advantageous because they can be calculated continuously as data is received serially via the interconnect.

[0514] As shown in the example, sending only negative acknowledgment messages saves the overhead of sending positive acknowledgment messages, while still being able to retransmit data contained in corrupted payload data symbols.

[0515] Figure 6c The diagram illustrates a flowchart of an example method for generating data signals, which may be implemented, for example, within a transmitter.

[0516] The method includes sending a set of payload data symbols 620. If a negative acknowledgment signal is received, the method further includes sending a second set of payload data symbols associated with that set of payload data symbols 622. As previously referenced... Figure 6bIn detail, the second set of payload data symbols can be transmitted after a predetermined number of payload data symbols following the transmission of this set of payload data symbols, or after a predetermined number of payload data symbols following the receipt of a negative acknowledgment signal. Once the round-trip time on the interconnect or the propagation delay of the data signal is known, the receipt of the negative acknowledgment signal is sufficient to identify that the previously transmitted set of payload data symbols contained errors. For example, the second set of payload data symbols can be transmitted immediately after receiving the negative acknowledgment signal. After receiving the negative acknowledgment signal, the payload data contained in the predetermined number of previously transmitted payload data symbols is then retransmitted. Figure 6c As shown, if no negative acknowledgment message is received, the method may optionally skip sending the second set of data symbols in step 624.

[0517] Various other examples can also be implemented within methods for processing data signals, as already referenced. Figure 6b The details include aspects such as using different modulation schemes for modulation. For a discussion of these alternative implementations, please refer to [link to relevant documentation]. Figure 6b The description is omitted to avoid redundancy.

[0518] Subsequently, Figure 6d and 6e A brief, schematic illustration shows the apparatus for processing data signals and for generating data signals, which can achieve... Figure 6b and 6c The method.

[0519] The apparatus 630 for processing data signals includes a receiver circuit 632 configured to receive multiple sets of payload data symbols. The apparatus 630 also includes an error detection circuit 634 configured to generate a negative acknowledgment signal if a set of payload data symbols contains an error. The error detection circuit 636 is configured to replace the first set of payload data symbols with a second set of payload data symbols received after a predetermined number of payload data symbols following the issuance of the negative acknowledgment signal, or after a predetermined number of payload data symbols following the receipt of the first set of payload data symbols.

[0520] The apparatus 640 for generating a data signal includes a transmitter circuit 642 configured to transmit a set of payload data symbols. The apparatus 640 also includes an input interface 644 configured to receive a negative acknowledgment signal. The transmitter circuit 642 is further configured to transmit a second set of payload data symbols associated with the first set of payload data symbols, either after transmitting a predetermined number of payload data symbols following the first set of payload data symbols or after receiving a predetermined number of payload data symbols following the negative acknowledgment signal.

[0521] Figure 6f An example of an interconnect for data transmission is illustrated, particularly a STEP interconnect. This interconnect includes a first physical layer controller 650 within a transmitter, a second physical layer controller 660 within a receiver, and a transmission link 670 connecting the first physical layer controller 650 and the second physical layer controller 660.

[0522] The second physical layer controller 660 may include, for example, such as Figure 6d The apparatus 630 shown is for processing data signals. Similarly, the first physical layer controller 650 may include, for example, a device such as... Figure 6e The device 640 shown is used to generate data signals. Because... Figure 6e The STEP interconnect link is illustrated, so the transmitter includes a digital-to-time converter 652 to generate a data signal based on a series of data symbols, while the receiver includes a time-to-digital converter 662 to generate data symbols based on the received data signal. Amplifiers 654 and 664 are used to amplify the data signal and the received data signal, respectively. Since the STEP interface is a serial interface, a parallel-to-serial converter 656 (PISO) and a serial-to-parallel converter 666 (SIPO) are used to serialize the data before sending it to a higher-order protocol layer and to deserialize the data after receiving it from a higher-order protocol layer (e.g., from the MAC layer). Figure 6f The error detection circuit 668 of the physical layer controller 660 shown in the example is connected to the output of the time-to-digital converter 662 to operate directly on the series of received data symbols. Depending on, for example, the error detection method used, other examples may similarly have an error detection circuit also connected to the data stream after the serial-to-parallel converter 666. Figure 6f The diagram illustrates a transmission link 670 connecting a sending physical layer controller 650 to a receiving physical layer controller 660. For the transmission of NACK messages from the receiving physical layer controller 660 to the sending physical layer controller 650, another transmission link can be used. Alternatively, interconnections operating according to communication protocols different from STEP can also be used to transmit NACKs.

[0523] Examples using the methods or apparatus described above allow for a lower bit error rate on the transmission link while maintaining the desired overall bit error rate, because errors within individual groups of data symbols are recovered by retransmitting erroneous payload data using a second set of data symbols. The combination of accepting more errors in groups of data symbols due to the higher net bandwidth of the interconnect link with a low-overhead controlled retransmission mechanism within the physical layer controller results in higher bandwidth at a higher bit error rate. In other words, the additional errors caused by the higher net data rate (lower symbol separation time for the STEP interface) are compensated for by a highly efficient retransmission mechanism. The latency cost of this retransmission mechanism is kept very low compared to retransmissions initiated by the MAC layer.

[0524] In other words, the previously described example can be summarized based on the following principles. The BER on the STEP link is intentionally reduced (e.g., from BER = 1e-12 to 1e-4) to allow for operation with shorter symbol-separated times, thereby increasing net bandwidth. Error detection is performed at the PHY layer, and only NACK (negative acknowledgment) is sent over the link (e.g., another transmission line different from the one used for receiving), which can be the STEP transmission link or another transmission link. Due to low latency requirements, retransmission is performed only once. The transmitted packets can be sent with a better net BER (lower number of active symbols), for example, with a more robust modulation scheme. Since the link delay is known in advance, NACK switches the TX side at a known time, causing it to automatically resubmit the correct set of data symbols (packets), resulting in low NACK detection and data preparation time.

[0525] exist Figure 6g The diagram illustrates a specific example used to evaluate the performance of a STEP interface. This performance is compared to a standard STEP implementation with a BAUD rate of approximately 20 Gbps at symbol separation times of approximately 24 ps and 12 picoseconds. Doubling the BAUD rate to 48 Gbps reduces the symbol separation time to approximately 9 or 6 picoseconds. Since noise will be constant and inter-symbol interference will increase due to the higher spectral content, the net BER (BER) on the transmission link will increase. However, using a reference... Figures 6b to 6f The described example (Fast Repeat) allows operation with such short pulses. For example, low BER on the STEP is acceptable and errors can be corrected using a Fast Repeat (FRT) mechanism.

[0526] like Figure 6gAs shown, even a BER of 1e-4 can be accepted for the transmission link. Without FRT, a noise budget of 8.55 ps_p2p is obtained (for BER = 1e-12), while with FRT, a noise budget of 5.6 ps_p2p is obtained (BER = 1e-4 and BER = 1e-12 after FRT).

[0527] To expedite the retransmission mechanism, only NACK is sent. NACK can be sent on another trace / transmission link (not a transmission link in TX mode). If the other transmission link is inactive (it may be in low-power GPIO mode), it can still be used for NACK transmission. If the other transmission link is active in STEP mode, a special delimiter can be used to submit the NACK, accelerating NACK detection.

[0528] Retransmission link propagation is known (measurable), so while the STEP rate is not constant, the location of retransmitted packets can be fixed (e.g., retransmitted packets will be sent to RX after a fixed number of packets from the moment NACK is generated from RX). Due to the fact that the actual BER on the link is low, much below 1e-12, the number of bad packets can be high, and the number of consecutive packets can also be high (compared to BER = 1e-12). Therefore, retransmitted packets can be sent in a protected manner (e.g., by switching from a normal 8-symbol and BER = 1e-12 to 4-symbol and BER << 1e-12).

[0529] Within a STEP interconnect, symbols can be generated with a uniform distribution, meaning each symbol is transmitted with an equal probability. However, due to implementation limitations and impairments, symbols transmitted over a STEP transmission link and subsequently recovered by a STEP receiver may have an unequal probability of error. Different symbols may experience different probabilities of being impaired and incorrectly received. Because the overall bit error rate (BER) is sensitive to the distribution of the error probabilities of individual symbols, this can lead to suboptimal interconnect performance. It may be desirable to increase the BER of high-speed interconnects (such as STEP interconnects).

[0530] exist Figure 7a The diagram illustrates an example of a method for determining the assignment of time period and symbol width to each payload data symbol of a communication protocol.

[0531] The method includes a modification process 702, which alters the symbol width and time period assigned to at least one payload data symbol. Changing the symbol width and time period alters the probability of determining the associated symbol in the presence of data signal degradation, which can, for example, increase jitter. Increasing the symbol width results in greater acceptable jitter while still correctly identifying the symbol. Increasing the symbol width of one symbol can reduce the available symbol width for the remaining symbols. The method also includes determining the probability of reception error (BER) 704 for all payload data symbols, which allows the impact of changes in the symbol width and time period of one symbol on the remaining symbols to be considered. Additionally, the method includes assigning the current time period and symbol width to the payload data symbol 706 if the BER of all payload data symbols are equal within a predetermined tolerance range. Applying the criterion of making the BER of all payload data symbols as equal as possible yields the best achievable overall BER for the interconnect link, as will be shown in the following considerations.

[0532] Figure 7b This illustration shows an example of the probability distribution of arrival times for signal edges of payload data symbols in a STEP interconnect link. Figure 7b In a specific example, the probability distribution P j Assumed to be Gaussian, therefore the time period 708u associated with the payload data symbol j. j It is symmetrical and has a standard deviation σ. j :

[0533]

[0534] Symbol width 710 is defined as the time interval near time period 708 of the payload data symbol, during which edges received by the receiver are interpreted as payload data symbol j. Edges received outside the time interval defined by time period 708 and symbol width 710 result in false detection of payload data symbol j, thus increasing the reception error probability P of payload data symbol j. ej The standard deviation σ of this distribution j It could be dominated by random jitter, for example.

[0535] Given the standard deviation σ of the distribution j For a specific payload data symbol to achieve the required symbol width of 710 for a specific BER, it can be achieved as follows: Figure 7b The figure on the right shows the standard deviation σ. j To express.

[0536] However, the BER of the entire interconnect link also has contributions from other possible payload data symbols, such as those obtained through... Figure 7cAs shown in an exemplary system, the system has N = 5 symbols 712, 714, 716, 718 and 720, which have associated nominal time periods 712a, 714a, 716a, 718a and 720a. Figure 7c The following configuration is illustrated, where all payload data symbols have the same P. ej That is to say, σ j (And therefore, symbol widths of 712b, 714b, 716b, 718b, and 720b) ​​are the same for all payload data symbols. Additionally, assume the probability of transmitting a particular symbol is P. S Furthermore, its symbols are identical for all payload data to calculate the overall BER.

[0537]

[0538] In STEP, there can be both deterministic jitter (calibration or signal-dependent jitter) and Gaussian random jitter (from random noise sources). Assume P... j If dominated by Gaussian random jitter, then all symbols experience the same P. ej This assumption may be reasonable. To obtain BER = 1e-12 (corresponding to 7.1σ), it is necessary to ensure that each symbol adheres to: This means that the symbol width needs to be greater than 14.2σ for a range of 712b to 720b.

[0539] However, due to implementation details, different symbols can also experience different probability distributions P. j Especially those with different standard deviations σ j .

[0540] Figure 7d The diagram illustrates the relationship with Figure 7c The same system, except that payload data symbol 3 (718) experiences more jitter and therefore a lower Pe (e.g., Pe3 >> Pe), resulting in an overall BER of:

[0541]

[0542] In these cases, the overall BER can be dominated by payload data symbol 3. Assuming... Figure 7d The payload data symbol 3 has higher random jitter, resulting in a symbol width of 718b(T). LSB ) = J S3 = ±5.7σ, then the result of the above consideration is Pe3 = 1e-8, resulting in an overall BER of approximately 1e-9, which is not optimal.

[0543] However, according to Figure 7aThe method shown allows the symbol width and time period of symbol 3 to be changed until the reception error probabilities of all payload data symbols become as equal as possible. This can be achieved, for example, by requiring all error probabilities to be within a predetermined tolerance range. The reception error probability indicates the probability that a payload data symbol generated using an assigned time period will be received within a time interval given by the assigned symbol width centered on the assigned time period. For a given time budget, changing the symbol width of one payload data symbol will result in adjusting the time periods and symbol widths of other payload data symbols or at least one additional payload data symbol. According to some examples, it may be required to re-determine the reception error probabilities for all payload data symbols after the change. This can be achieved, for example, by transmitting a predetermined sequence of payload data symbols and determining the sequence of received payload data symbols. Comparing the predetermined sequence of payload data symbols with the sequence of received payload data symbols allows the inference of the reception error probabilities of all symbols. Determining the reception error probability generally involves transmitting a data signal comprising data pulses having widths assigned to the time periods of the payload data symbols and receiving the data signal. If a data pulse with a width within a time interval centered on the symbol width is received within the data signal, it is considered that the payload data symbol has been received.

[0544] If a time-to-digital converter is used to determine the symbol, the symbol width can be varied in finite steps of the time-to-digital converter's resolution. Similarly, varying the time period can include varying the time period in finite steps of the digital-to-time converter's resolution.

[0545] If the reception error probability of the payload data symbols meets the requirements, the current time period and the current symbol width are assigned to symbols that have undergone changes. According to this method, it is possible to ensure that all payload data symbols experience nearly the same or identical reception error probabilities, resulting in the best achievable overall BER as previously considered. Utilizing, for example... Figure 7d The method shown reduces the symbol widths of symbols #0, #1, #2, #4 (712, 714, 716, and 720) and increases the width of symbol #3 (718) to achieve an equal Pe for all symbols. In this specific example, we increase the symbol width of payload data symbol 3 by ~20% and decrease the symbol widths of the other four symbols by ~5%. By doing so, we obtain equally spaced time periods and symbol widths for all payload data symbols, approximately ±6.8σ, resulting in an overall BER of approximately 1e-11, which is significantly better than the 1e-9 dominated by payload data symbol 3 in the example without using the method to assign individual time periods and symbol widths.

[0546] An example of this method can be characterized as a water-splashing method, which allows for BER optimization on communication interconnect links (e.g., STEP interconnect links).

[0547] Figure 7a The method can be performed, for example, as an online calibration, such as when the interconnect is powered on or during a specific calibration cycle. The method can also be performed once during the factory calibration of the interconnect.

[0548] By Figure 7a Some parts of the illustrated method can be performed on the receiving side, while others can be performed on the transmitting side of the interconnecting link. Although changes in symbol width can only be performed on the receiving side by the method for processing data signals, changes in symbol width associated with payload data symbols can be performed both on the receiving side by the method for processing data signals and on the transmitting side by the method for generating data signals.

[0549] Figure 7e The diagram illustrates a flowchart of an example method for generating data signals, which can be executed on the transmitting side of an interconnect link.

[0550] The method includes assigning time periods 730 within a data signal to each payload data symbol, wherein adjacent pairs of time periods for payload data symbols are separated by associated symbol separation times. The time periods are assigned such that at least a first symbol separation time differs from at least a second symbol separation time. The method also includes generating a 732 data signal. By assigning time periods to individual payload data symbols such that the symbol separation times between adjacent payload data symbols can differ, the method allows for the generation of data signals with equal reception error probabilities for all payload data symbols at the receiver side. Therefore, the overall BER of the communication interconnect link can be prioritized.

[0551] Figure 7f The diagram illustrates a flowchart of an example of a method for processing data signals (when the method can be performed on the receiving side). The method includes assigning a time period and symbol width of 734 to each payload data symbol of a communication protocol, wherein at least a first symbol width differs from at least a second symbol width. The method also includes receiving a data signal comprising a series of data pulses at 736. Additionally, the method includes determining, at 738, that a payload data symbol has been received if a data pulse with a width within a time interval given by the assigned symbol width centered on the assigned time period is received within the data signal. Allowing different symbol widths and time periods for individual payload data symbols can reduce the overall BER of the interconnect link.

[0552] For example, compared to STEP implementations where all payload data symbols have uniform conditions in TX and RX, channel and STEP impairments can now be taken into account by reducing the non-uniform distribution probability of errors that lower the overall BER.

[0553] While some examples of this method can be performed as online or factory calibration, other examples can be based on prior knowledge about the communication interconnection links using a predetermined set of individual time periods and symbol widths.

[0554] For example, in a STEP interconnect link, systematic impairments to the data signal can exist, leading to a non-uniform probability of reception errors. For instance, if the dominant impairment originates from vendor modulation of the time-to-digital converter (TDC) used to receive the data signal, such as... Figure 7i As shown in the diagram, the larger the number of symbols, the higher the potential error in determining the edges of the associated signals. Figure 7i As shown, the TDC can be implemented as a sequence of inverters 762a to 762f, which operate as delay elements. This, depending on the implementation, also allows tuning of individual delay elements composed of inverters. The output of each delay element 762a to 762f is coupled to two flip-flops, which reset when a signal edge occurs within the data signal. With this setup, the first set of flip-flops 764 outputs a signal when a positive signal edge is present within the data signal, while the second set of flip-flops 766 outputs a signal when a negative signal edge is present within the data signal. Due to this implementation, the power consumption of the TDC depends on the received payload data symbols, as longer payload data symbols result in more digital components being operated within the TDC 760. More components consume more power and cause greater variations in the power supply, translating to more errors within the system. Due to variations in the power supply, payload data symbols with longer time periods experience higher errors (jitter). Furthermore, for higher-order (longer) symbols, the individual errors of a higher number of delay elements add up to a higher error rate compared to shorter symbols.

[0555] Some examples take into account the systematic nature of the data, since time periods are assigned to payload data symbols in such a way that the symbol separation time increases with increasing time periods, i.e., it increases for higher-order symbols.

[0556] Other interconnects can be dominated by signal degradation caused by inter-symbol interference (ISI), for example, if long and lossy cables are used in the transmission link between the transmitter and receiver. Symbols with shorter time intervals are more sensitive to ISI due to their higher spectral content. Another example can be considered given this property, since time intervals are assigned to payload data symbols in such a way that the symbol separation time decreases with increasing time intervals. In other words, a system with decreasing symbol separation (S0 to S1 has the highest separation) will be designed.

[0557] Some of the examples described earlier can be implemented in software, while others can be implemented in hardware. Figure 7g and 7h An apparatus capable of performing one of the previously described methods is schematically illustrated.

[0558] Figure 7g An example of an apparatus 740 for generating a data signal is illustrated. The apparatus includes a mapping circuit 742 configured to assign time periods within the data signal to each payload data symbol, wherein adjacent pairs of time periods of the payload data symbols are separated by associated symbol separation times, wherein at least a first symbol separation time differs from at least a second symbol separation time. The apparatus also includes a memory 744 configured to store the time periods.

[0559] Some examples may optionally also include an output interface 746 configured to output a data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type, wherein the first and second signal edges are separated by a first time period assigned to a first payload data symbol, and the second and third signal edges are separated by a second time period assigned to a second payload data symbol.

[0560] Figure 7h An example of an apparatus 750 for processing data signals is illustrated. The apparatus includes a memory 752 for assigning time periods and symbol widths to each payload data symbol of a communication protocol, wherein at least a first symbol width differs from at least a second symbol width. Additionally, the apparatus includes a demapping circuit 754 configured to determine that a payload data symbol has been received if a data pulse having a width within a time interval given by the corresponding assigned symbol width centered on the corresponding assigned time period is received within the data signal.

[0561] Some examples may optionally also include an input interface 756 configured to receive a data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type, the first and second signal edges constituting a first data pulse, and the second and third signal edges constituting a second data pulse.

[0562] STEP interconnection measurements are assigned to time periods for payload data symbols and other symbols (e.g., control symbols). Figure 8a As shown, symbols 802, 804, and 806 are transmitted by the time period between the falling and rising edges or by the time period between the rising and falling edges of the data signal.

[0563] Timing errors and the resulting erroneous symbol measurements can occur due to jitter. However, it's not just time-domain errors that can affect the measured time period. Along the STEP interconnect cabling, there can be sources of additive noise that add noise to the STEP data signal 810. For example... Figure 8a As shown, once the data signal 810 passes through the limiter to generate the data signal 811, the additive noise 812 that alters the amplitude of the data signal 810 is also converted into jitter 814 because the edges of the data signal 8a are not infinitely steep. An inverter is a concrete example of a limiter. For example, in... Figure 7i Within the TDC shown, the sign is determined based on the zero-crossing of the data signal, which is a form of clipping. This applies to the STEP data before and after the time-to-digital converter (TDC) (e.g., with an input inverter stage acting as a clipper). In the absence of additive noise, the zero-crossing 813 of the data signal 810 will be exactly in the middle of the rising and falling edges of the data.

[0564] However, as Figure 8a As shown, additive noise is added to the STEP data signal 810. Once the altered data signal 810 passes through a limiter to determine, for example, a zero-crossing, the additive amplitude noise 812 acts as jitter 814, altering the zero-crossing of the data signal 810, causing an incorrect time period to be used to identify the symbol in the data signal 811 output by the limiter (e.g., by a TDC). In a STEP system, when a symbol is represented between two adjacent complementary signal edges, the additive noise affects the two successive edges (positive and negative, or vice versa) in opposite directions, thus doubling the timing error in symbol determination. For example, the falling edge of symbol 804 is shifted to a longer time, while the subsequent rising edge is shifted to a shorter time, effectively reducing the time period between the edges by a factor of two compared to the error of a single edge. Additive amplitude noise can thus cause significant timing errors and lead to potential misreadings of received payload data symbols.

[0565] It may be desirable to mitigate the negative impact of additive noise in communication interconnect links.

[0566] Figure 8b The flowchart illustrates an example of a method for determining the payload data symbols within data signal 830. See also... Figure 8c The method is described using data signals. The method includes receiving a sequence of a first signal edge 832 of a first type, a second signal edge 834 of a second type, a third signal edge 836 of a first type, and a fourth signal edge 838 of a second type in a data signal 814. The method also includes determining a first time period 840 between the first signal edge 832 and the third signal edge 836, and determining a second time period 842 between the second signal edge 834 and the fourth signal edge 838. Additionally, the method includes determining a payload data symbol 818 corresponding to the time period 846 between the third signal edge 836 and the fourth signal edge 838 based on the first time period 840 and the second time period 842. The time period corresponding to the payload data symbol is not determined by directly measuring the time between successive complementary signal edges 836 and 838, but by measuring two time periods between successive edges of the same type. Since signal edges of the same type receive the same timing error in the presence of additive noise, the time difference between the two signal edges remains unaffected by constant additive noise. Utilizing two time periods unaffected by additive noise to determine the received payload data symbols makes the determination of payload data symbols virtually unaffected by additive noise. TDC, which cannot determine the time period between the edges of two successive signals of the same type, can be based on... Figure 7i TDC.

[0567] In other words, to avoid the source of the aforementioned misunderstanding, it is proposed to change the symbols so that each symbol will be represented or demodulated using the time between rising to rising and falling to falling, such as... Figure 8c As shown in the diagram. When doing this, the possible zero-crossing errors on the sign edge cancel each other out, because the same edge (positive or negative) receives the same error, as... Figure 8c As shown in the image.

[0568] A concrete example of how the sign can be determined can be assumed to be the added flicker noise. Figure 8c The sources of error are shown. STEP symbols are very short (80-160 picoseconds), while flicker noise and additive DC glitches are slow compared to STEP symbols (they have very long durations). Adding slow noise to the STEP signal adds almost the same voltage error at both the rising and falling edges of each symbol, as... Figure 8c As shown in the image.

[0569] It is also assumed that unwanted noise added to the STEP signal introduces an error in TERR at each signal edge of the symbol. As noted above, these errors will add up and cause a timing error of 2*TERR for each symbol when directly determining the time interval between successive complementary signal edges.

[0570] However, according to Figure 8b The method involves determining the sign between rising to rising and falling to falling (optionally, this is also how it is generated). This results in the cancellation of additive, slow noise.

[0571] Each time interval K[n] between the edges of two successive signals of the same type is the sum of the time intervals of the two successive symbols and their timing errors (D[n]; TERR):

[0572] K[n]=D[n]+2*TERR+D[n+1]–2*TERR=D[n]+D[n+1].

[0573] This method cancels out timing errors.

[0574] During reconstruction, the first time interval K[n] is subtracted from the second time interval K[n+1], resulting in D[n+2] + D[n+1] - D[n+1] – D[n] = D[n+2] – D[n]. This means that the symbol D[n+2] can be determined independently of the previous symbol D[n+1] without knowledge of the previous symbol. In other words, symbols can be constructed and decoded such that we can optionally sum every two consecutive original data symbols in TX and regenerate them in RX by subtraction. An alternative example conventionally generates payload data symbols in the transmitter by directly generating two successive complementary signal edges spaced apart by the time intervals assigned to the payload data symbols using DTC.

[0575] As shown above, determining the payload data symbol may include subtracting the first time period K[n] from the second time period K[n+1] to determine the time period D[n+2] of the symbol. In some examples, the method may optionally include storing the latest two time periods or symbols for optional use in determining the payload data symbol as well. The determined time periods may then be assigned to the payload data symbols according to the communication protocol.

[0576] According to some embodiments, the time period between the first signal edge and the second signal edge may correspond to a control symbol indicating the start of a packet with a predetermined duration, which can further reduce the probability of false detection because the method starts at a pre-known time period.

[0577] Figure 8b The flowchart illustrates an example of a method for determining the payload data symbols within a data signal. Figure 8d and 8e The schematic diagram illustrates an example of a device configured to perform the method.

[0578] Figure 8d An example of an apparatus 850 for processing data signals is illustrated. Apparatus 850 includes processing circuitry 852 configured to determine a sequence of first signal edges of a first type, second signal edges of a second type, third signal edges of a first type, and fourth signal edges of a second type in the data signal. Demodulation circuitry 854 is configured to determine payload data symbols corresponding to the time interval between the third and fourth signal edges based on a first time interval between the first and third signal edges and a second time interval between the second and fourth signal edges.

[0579] In some examples, the processing circuit 852 may optionally include a first edge detector 856a configured to determine a first type of signal edge in the data signal and a second edge detector 856b configured to determine a second type of signal edge in the data signal.

[0580] Figure 8e An example of a communication system 860 is illustrated. The communication system includes a means 862 for generating a data signal, which includes a processing circuit 864 configured to generate a data signal comprising a sequence of first signal edges of a first type, second signal edges of a second type, third signal edges of a first type, and fourth signal edges of a second type. The first and second signal edges are separated by a first time period corresponding to a first payload data symbol; the second and third signal edges are separated by a second time period corresponding to a second payload data symbol; and the third and fourth signal edges are separated by a third time period corresponding to a third payload data symbol. The means 862 also includes an output interface circuit 866 configured to output the data signal. Additionally, the communication system 860 includes a means 870 for receiving data signals, comprising a processing circuit 872 configured to determine a sequence of first signal edges, second signal edges, third signal edges, and fourth signal edges in the data signal; and a demodulation circuit 874 configured to determine a third payload data symbol using a first reception time period between the first and third signal edges and a second reception time period between the second and fourth signal edges.

[0581] According to the reference Figures 8a to 8eExamples of methods and apparatus described can reduce the effects of additive noise. Possible sources of this noise include flicker noise, power supply glitches (from the DC / DC converter and other blocks connected to the same DC / DC converter), and other external attackers (which may be slower than the time period assigned to the symbol in the STEP, such as CLK, Fref, control, etc.). Alternatively, one could also attempt to reduce the effects of additive noise by trying to reduce the level of noise itself. However, this would have the disadvantages of higher power consumption and a more complex DC scheme (DC / DC + LDO) with large filtering components (primarily capacitors).

[0582] By utilizing methods for determining the payload data symbols within a data signal, STEP interconnects or any other communication interconnects can be made more immune to flicker noise, power supply glitches, and other additively correlated noise. The result can be a better link noise budget (fewer errors) and the possibility of using simpler and lower-cost DC power supplies. Since flicker noise is inversely proportional to the area (length and width) of (CMOS) devices, reducing flicker noise levels would require increasing the size of the (CMOS) devices. However, increasing the size of the (CMOS) devices increases their capacitance, which in turn increases power consumption. Examples of methods using this approach allow for the use of smaller devices, resulting in power-efficient implementations.

[0583] Figure 8f The illustration shows an example of the previously illustrated STEP interconnect, further illustrating different possible sources of additive noise, such as flicker noise from the power and low-noise amplifier 880, additive noise from an external attacker 882 that crosstalks into the transmission link, and noise caused by load modulation of the power supply 884.

[0584] Figures 9a to 9e Examples are provided regarding how errors caused by damage to data signals transmitted via interconnected transmission links can be mitigated.

[0585] Some applications require the exchange of payload data with high robustness and immunity to errors. This can be achieved by adding error correction codes (ECC). The overhead of ECC depends on the amount of data that needs to be protected and the number of potential errors to be corrected. It may be advantageous to provide a means to mitigate errors caused by damage to data signals transmitted via interconnected transmission links without adding overhead.

[0586] Figure 9aThe diagram illustrates a flowchart of an example method for transmitting a sequence of data symbols. The method includes encoding the sequence of data symbols using Gray code 902 to generate a sequence of encoded data symbols. Gray code is an ordering of binary numbers such that two consecutive values ​​differ by only one bit (binary digit). In other words, in the Gray code representation of a sequence of data bits representing an integer, if the number increases or decreases by 1, only one bit changes. The number of possible Gray codes depends on the number of bits to be encoded. For a sequence of n bits, there can be n! (n factorial) Gray codes with the aforementioned property. For example, in the case of transmitting a STEP interconnect with 3 bits per symbol, there can be 6 Gray codes, and each of them can be used by this method. Encoding of data symbols can therefore be performed by encoding the sequence of bits assigned to the data symbols and then modulating the encoded bit sequence into encoded data symbols, or by directly transforming the data symbols into encoded data symbols based on knowledge of the modulation scheme. The first option can be described as encoding the bit sequence associated with a single data symbol using Gray code to generate an encoded bit sequence and modulating the encoded bit sequence into encoded data symbols using the modulation scheme of the communication protocol.

[0587] The method further includes differentially dividing the sequence of encoded data symbols by 904 to generate a sequence of transmitted data symbols and transmitting the sequence of transmitted data symbols by 906. In other words, as... Figure 9b As illustrated again, before submission, the data symbol is encoded using Gray code 908, and the encoded data symbol is then differentiated 910 (differentiated) before being sent.

[0588] At the receiver, the two actions are reversed, beginning with integrating a series of received data symbols 912 to generate a series of integrated data symbols, and then decoding the sequence of integrated data symbols using a Gray decoder 914 to generate information about the sequence of data symbols. Differentiation of symbols is performed by subtracting the value of a previous symbol from the value of the symbol to be transmitted to generate the transmitted symbol. Subtraction is performed modulo the number of data symbols. Differentiation of the sequence of encoded data symbols can also include the first data symbol of the transmitted sequence without altering it. Similarly, integration is performed by adding received symbols to the sequence of data symbols to be determined. Addition can be performed modulo the number of data symbols in the modulation scheme.

[0589] Depending on the implementation, the start of the data symbol sequence can be given by the start of the data frame. Therefore, the data symbol sequence can begin with a predetermined data symbol, such as a control symbol of the communication protocol, to indicate the start of the data frame.

[0590] In coding schemes such as the STEP interface, the receiver measures each edge twice: once at the start time of the symbol / pulse and a second time at the end time. A single signal edge thus affects two adjacent data symbols. If a single signal edge is determined to be in the wrong location, both adjacent data symbols can be received incorrectly. Differentiating the data symbols before transmission ensures that once the receiver inverts the differential by integrating a series of received data symbols, only a single data symbol can be corrupted by incorrectly detecting a signal edge on the receiver side. Assuming that an incorrectly determined data symbol is adjacent to a correct data symbol, applying Gray code to the sequence of data symbols ensures that only a single bit error occurs if a data symbol is incorrectly determined.

[0591] according to Figure 9a The combination of Gray coding and differential coding of the symbols in the method shown thus stipulates that a misdetection of a single signal edge within the data signal shown in Figure 1 results only in a single bit error within the bit sequence modulated into the data symbol.

[0592] If, for some reason (e.g., due to noise, distortion, or an external event), the receiver misreads the incoming payload data symbol, the resulting bit sequence corresponding to the misread payload data symbol will differ from the transmitted bit sequence by only a single bit. A disturbance at a signal edge results in a one-bit error. In other words, according to Figure 9a The encoding scheme of the method shown in the figure results in a single symbol error due to a single edge error, which in turn leads to a single bit error.

[0593] Figure 9c The flowchart illustrates an example of a method for processing a series of received data symbols. The received data symbols can be generated using... Figure 9a The method involves integrating a series of received data symbols 920 to generate a series of integrated data symbols, and decoding the sequence of integrated data symbols using a Gray code 922 to generate information about the sequence of data symbols. Similar to encoding, the sequence of decoded data symbols can be given as data symbols according to a communication protocol or as a sequence of data bits for each data symbol. In the latter case, decoding may include demodulating the integrated data symbols using a modulation scheme of the communication protocol to generate an encoded bit sequence; and decoding the encoded bit sequence using Gray code to generate a decoded bit sequence.

[0594] The following provides a specific example of a hypothetical error during the submission of a sequence of data symbols via a STEP interconnect, which uses three bits per data symbol to produce data symbols from the group [0,…,7].

[0595] Suppose the transmitter sends a sequence of data symbols 012321 and there is jitter on one edge, then the receiver can receive a series of received data symbols 012411. A single edge error is associated with two successive symbols because the edge is used for two symbols, and therefore a single corrupted signal edge will cause two data symbols to be received incorrectly.

[0596] However, the example using the method described above only resulted in a single bit error when errors occurred at the edge of the received signal.

[0597] According to this method, instead of the sequence 012321 of the transmitted data symbols, the data symbols are passed through Gray code to the classification code, producing, for example, the sequence 013231 of the encoded data symbols (for this specific example, one of the six possible Gray codes is arbitrarily chosen). Differentiating the sequence produces the sequence 012716 of the transmitted data symbols.

[0598] Assuming the error occurs at the edge of the fifth signal, the receiver may receive a series of received data symbols 013616, where two adjacent symbols are different from the sequence of transmitted data symbols.

[0599] In an example of the implementation, the received sequence of data symbols is integrated, which produces a series of integrated data symbols 014231 (for this example with 8 payload data symbols, integration is performed modulo 8). Finally, the sequence of integrated data symbols 014231 is decoded using a classification-to-Gray code that matches the Gray-to-classification code, producing a sequence of data symbols 016321.

[0600] In summary, the transmitter sent 012321, and the receiver decoded 016321 in response to the symbol edge error. This means that data symbol 2 becomes data symbol 6, which is a single-bit error (010 vs. 110). Without Gray code, the received symbol 4 would be converted into the bit sequence 100, which is a two-bit error.

[0601] The previous figures illustrated examples of methods for sending and receiving sequences of data symbols, while Figure 9d and 9e The apparatus will then be schematically illustrated as being configured to perform one of these methods.

[0602] Figure 9d An example of an apparatus 930 for transmitting a sequence of data symbols is illustrated. Apparatus 930 includes encoder circuitry 932 configured to encode a sequence of data symbols using a Gray encoder to generate a sequence of encoded data symbols, and circuitry 934 configured to differentially process the sequence of encoded data symbols to generate a sequence of transmitted data symbols. Output interface 936 is configured to output the sequence of transmitted data symbols.

[0603] Figure 9e An example of a device 940 for processing a series of received data symbols is illustrated.

[0604] The apparatus includes an integrator circuit 942 configured to integrate a series of received data symbols to generate a series of integrated data symbols. A decoder circuit 944 is configured to decode the sequence of integrated data symbols using Gray code to generate a sequence of data symbols. Optionally, the apparatus may also include an input interface 946 for receiving the series of received data symbols.

[0605] Especially for implementations within the STEP interconnect, and where the TDC in the receiver provides a higher resolution than the symbol threshold separating adjacent payload data symbols, a soft-decision method may be optionally added to at least partially replace symbol differentiation. If the TDC provides a data symbol close to the symbol decision threshold and the next data symbol is also close to the symbol decision threshold, the offset of the first symbol is subtracted from the next symbol. If one symbol is longer, the other will be shorter. This exacerbates errors but ensures greater correlation between errors, and thus Gray coding ensures only a single bit error. (If both symbols are at the decision threshold, another possibility is that due to quantization and noise, one is incorrectly decided and the other is decided as the correct value, which could ultimately result in two errors). A corresponding device may feature an encoder circuit configured to encode the sequence of data symbols using a Gray encoder to generate a sequence of transmitted data symbols. The processing circuit of the device generates a data signal, which includes a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type. The first signal edges and second signal edges are separated by a first time period corresponding to the first data symbol of the sequence of transmitted data symbols, and the second signal edges and third signal edges are separated by a second time period corresponding to the second data symbol of the sequence of transmitted data symbols.

[0606] A corresponding device on the receiving side of a STEP interconnect link for processing a series of received data symbols may include processing circuitry configured to determine a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type in a received data signal including the series of received data symbols. Demodulation circuitry is configured to determine first received data symbols of the series based on a first time period between the first and second signal edges; and to determine second received data symbols of the series based on a second time period between the second and third signal edges. Decoder circuitry within the device is configured to decode the sequence of received data symbols using Gray code to generate a sequence of data symbols.

[0607] The following paragraphs explain the possibility of correcting errors caused by damage to the data signal during transmission. The methods and apparatus described subsequently include processing the data at both the transmitting and receiving sides.

[0608] For the sending side, Figure 10a The diagram schematically illustrates an example of a method for transmitting a predetermined number of bits in a serial sequence. The method includes generating at least one error correction bit for data bits within each of a plurality of subgroups of bits. Generating the error correction bit 1002 allows for the identification or correction of errors within the subgroups of bits. The amount of detectable or correctable error depends on the strength of the error correction code (ECC) used.

[0609] The method also includes sorting the bits of each subgroup and their associated error correction bits along the first dimension of the multidimensional representation of the data 1004.

[0610] Additionally, the method involves reading 1006 data bits along a second dimension from the multidimensional representation to determine a series of transmit bits; and modulating this series of transmit bits 1008 times into a series of transmit symbols. Reading the transmit bits in another dimension before transmitting them via transmit symbols—also known as interleaving—reduces the probability of multiple bits in the same subgroup being affected by transmission errors, because the bits of the subgroup can be transmitted via different transmit symbols. Therefore, a weaker ECC that incurs less overhead can be used. Other examples may also use different interleaving schemes that result in adjacent bits being physically transmitted by different payload data symbols.

[0611] Additionally, the method includes inserting a control symbol indicator and a control symbol 1010 at positions within the series of transmit symbols that depend on the group of bits indicating control commands within that series of bits. In the STEP implementation, the control symbol indicator and associated control symbol can also be jointly represented as delimiters. Inserting the control symbol indicator and its associated control symbol at predetermined positions within the transmit symbols allows the use of special control symbols within the data signal that exhibit different properties than the payload data symbols used to transmit payload data, while maintaining the benefits of interleaving.

[0612] According to some examples, control symbol indicators and control symbols are inserted within transmit symbols generated from bits identified by an index for the second dimension within the multidimensional representation, corresponding to the number of the byte of the control command within the group of indicator bits. Inserting the transmit symbols at predetermined positions allows the group of bits indicating control commands (which can be modulated into the data signal by the control symbol indicator and its associated control symbols) to be rearranged at the receiver to their appropriate positions within the multidimensional representation without additional signaling overhead.

[0613] Figure 10b The illustration shows a specific example of generating data signals for a STEP interconnect. Figure 10b In the example, the multidimensional representation has two dimensions; bits are sorted or filled according to the columns of a 2D matrix, while they are read out row by row to determine... Figure 10c The diagram shows a series of transmitted bits. In other words, the first dimension 1020 is given by columns, and the second dimension 1022 is given by rows. Other examples may also utilize more than two dimensions. Similarly, bit sorting can be performed along the row dimensions, while reading can be performed along the column dimensions, thus enabling... Figure 10b The examples are swapped compared to the first and second dimensions.

[0614] exist Figure 10b In the example, data bits are provided by successive bytes, which may be generated, for example, within the MAC layer of the protocol stack. Three bytes, 1024a, 1024b, and 1024c, indicate control commands, such as an indication of the start of a data packet consisting of multiple bytes.

[0615] For each subgroup of 57 bits, 6 error correction bits are generated, and the bits of each subgroup and their associated error correction bits are sorted along the first dimension 1020, resulting in a single column of a 2D representation. Figure 10b In the example, a series of data bits to be processed includes 512 data bits, producing a matrix with 9 columns. As a result, the first dimension of the multidimensional representation includes 63 entries and the second dimension includes 9 entries.

[0616] Other examples may combine different numbers of bits, such as data bits that are multiples of 512. Similarly, the number of bits within a subgroup may differ from the 57 bits illustrated in this example. Likewise, the number of correction bits may be chosen differently to use stronger or weaker ECC.

[0617] exist Figure 10cThe diagram illustrates a series of transmitted bits read along the second dimension 1022. This series of transmitted bits is modulated into a series of transmitted symbols. In the STEP implementation, three consecutive bits are assigned to a single symbol. For each control command 1024a, 1024b, and 1024c, a control symbol indicator and a control symbol (delimiter) are inserted into the series of transmitted symbols before transmission at positions dependent on the position of the group of bits indicating the control command within that series of bits. Figure 10c In the example, the number of the byte containing the control command within a certain number of bits of the serially ordered sequence defines the row number to which the associated delimiter is inserted before transmission. For example, control command 1024a is contained in byte number 1 within a predetermined number of bits of the serially ordered sequence to be processed within the matrix. The corresponding control symbol indicator and control symbol 1034a are inserted at the beginning of row #1. Figure 10b The elements of the matrix can be identified by a first index, which gives the number of the entry relative to the first dimension (the number of the column where the entry is located), and a second index, which gives the number of the entry relative to the second dimension (the number of the row where the entry is located). In other words, the control symbol indicator and control symbol 1034a are inserted into the transmit symbol generated from the bits identified by the second-dimensional index within the multidimensional representation, corresponding to the number of the byte of the control command within the group of indicator bits. Considering that in Figure 10b and 10c In the STEP interconnect example shown, three bits are transmitted jointly by a single payload data symbol. Other examples may use predetermined positions within a series of transmitted symbols to insert delimiters. Using any predetermined position that depends on the position of a group of bits indicating control commands within a series of bits avoids additionally submitting data to the receiver indicating the location of the inserted delimiter. However, other examples may be implemented to additionally or alternatively insert data to the receiver indicating the location of the inserted delimiter.

[0618] Alternatively, the control symbol indicator and control symbol for control command 1024a could be inserted at a different position within line #1, not at the beginning. For example, the control symbol indicator and control symbol 1034b could be inserted after the first three bits of the second line (R1), i.e., after the first payload data symbol to be transmitted via the transmission link. Using this alternative position, spaced one payload data symbol apart (equal to 3 bits), allows it to be ensured that the control symbol indicator is always transmitted with a predetermined polarity (positive or negative) within the data signal interconnected by STEP, considering that each successive pair of 3 payload data bits is transmitted by payload data symbols with different polarities within the data signal.

[0619] In summary, control commands 1024a, 1024b, and 1024b of any communication protocol (which are transmitted, for example, via delimiters in the STEP interconnect) can be transmitted using a different modulation scheme than that used for payload data. Therefore, only modulation... Figure 10c The series of interleaved bits shown can corrupt the information in control commands 1024a, 1024b, and 1024b, which can be achieved by using... Figures 10a to 10c The method shown can be used to avoid this.

[0620] In other words, Figure 10b and 10c An example using a single matrix is ​​described. However, considering that different matrix sizes will have an impact on latency and efficiency, multiple matrix dimensions can be implemented. The matrix is ​​63×9 in size, containing 9 codewords, each with 57 information bits and 6 redundant bits (except for one codeword in column 9, which carries 56 information bits). It can hold a total of 64*8=512 application data bits of raw data, while the total data transmitted is 63*9=567, which is >90% efficiency. Data is padded column-wise. Delimiters can replace any data byte, and the minimum packet size is assumed to be no less than 3 bytes. Some STEP interconnects send data in 3-bit units because this "reserved space" at the beginning of each line is used for delimiters, and the line that sends delimiters indicates the byte where the delimiters would originally have been placed.

[0621] In the following example—512 bits represent a total of 64 bytes (0 to 63) and a total of 63 rows with space for 64 delimiters. The original data (64 bits) is placed as 57 bits in column 0 of the matrix and the remaining bits (7) are placed in the next column, followed by the next 64 bits—from this cell, 50 bits are placed in column 1 and 14 remaining bits are placed in column 2, and so on. For each 57-bit column, a 6-bit ECC code (labeled e1 to e9) is added to that column. Assume that the delimiter on the second byte of the first 64-bit data cell is “located at” “second location” (labeled L1). When the matrix is ​​full, transmission begins. If the first byte is a delimiter—this delimiter is sent first, followed by 9 bits of data in the first row of the matrix. If the second byte is a delimiter, it is sent immediately after the first row is sent, i.e., at the beginning of the second row, followed by the bits of the second row, and so on. If no delimiter is specified, no delimiter is sent.

[0622] Delimiters can have either a long "1" duration (high pulse) and a modulated "0" duration (low pulse), or a long "0" duration and a modulated "1" duration. The polarity order can be required to be fixed—as the delimiter position may need to be changed—depending on the delimiter type and the exact state of the line when the delimiter is to be transmitted. For example, suppose the second byte of the first data unit is a delimiter that requires a long "0" and a modulated "1". The first 3 bits are transmitted as a rising edge, followed by a second set of 3 bits as a modulated falling edge, followed by bits 6-8 as a modulated rising edge. Now the delimiter should be placed, but the delimiter requires a long "0" since the signal has just risen. Thus, the next 3 bits (9-11) are on the modulated falling edge, and the delimiter is transmitted after the signal has fallen to 0, and a long "0" can be applied, followed by a modulated "1". The transmitted delimiter should have a specific pattern, otherwise it may be impossible to detect whether the delimiter is "modulated" then a long level, or long then a modulated level. The transmittable delimiter should have a constant scheme of a long level followed by a modulation level (or vice versa). Alternatively, cascaded delimiters can be used, where the first delimiter has a constant format and the second is used as needed.

[0623] It can be estimated under the following assumptions Figure 10b The example shown increases the BER: the modulation additionally uses Gray coding as described above, making the probability of errors in the 3 bits of a single modulation edge low. However, errors in two triples are still possible. Utilizing... Figure 10b For example, burst errors at least 9 bits apart will result in errors distributed across more than a single data unit (57 data bits in a column) protected by ECC, which should therefore be able to correct the bits of the error.

[0624] The updated probability is estimated under the assumption that the two errors are distributed such that error correction using this matrix (the concept of interleaving) can handle them, and that the probability of a single bit is given by P. As previously described, the interleaver uses a matrix of dimension A columns × B rows. The source data fills the matrix row by row (or column by column) and adds one or more bits of error correction code to each data cell. Once the matrix is ​​full, transmission begins, but intermediate data is taken column by column (or row by row if the matrix is ​​filled column-wise) to mitigate the impact of burst errors, as burst errors will be distributed across multiple data cells protected by ECC.

[0625] Using the modulation schemes described previously (including Gray coding), it is expected that two errors will be spaced 1 to 5 bits apart. Depending on how the errors are distributed, this means that the error codes should be able to correct them. In total, up to 9 errors can be corrected using this scheme.

[0626] Bit errors will be converted into matrix error rate (MER), which is given by the following formula:

[0627] MER = 1 - P[no error] - P[single error] - P[two errors];

[0628] P[error-free] = {1-P}^[number of bits sent];

[0629] P[single error] = [number of bits!] / [1! * (bits in the matrix - 1)!] * P * (1 - P)^[bits in the matrix - 1];

[0630] P[2 errors] = [number of bits!] / [2! * (bits in the matrix - 2)!] * P^2 * (1-P)^[bits in the matrix - 2];

[0631] If we apply the above and assume P = 1e-10, and the matrix bits are 567 (= 63*9), then we can get a MER of 3.022e-20, which is a very low error rate.

[0632] Figure 10d The diagram illustrates what can be used to process by Figure 10a The flowchart describes a method for processing data signals generated by a specific method. The method includes receiving a series of symbols 1050 and identifying 1052 control symbol indicators and control symbols within the series of symbols. The method also includes sorting the bits associated with each symbol in the series along a second dimension within a multidimensional representation of the data 1054 and evaluating error correction codes along a first dimension of the multidimensional representation 1056. Additionally, the method includes interpreting the positions of the control symbol indicators and control symbols within the series of symbols, depending on their location within the multidimensional representation, as control commands along a bit group in the first dimension.

[0633] Examples of the usage method allow for the correction of errors in the received data signal, while also allowing for the use of special and robust modulation schemes for the transmission of control commands.

[0634] Figure 10e and 11a This schematically illustrates the implementation of [something] on the transmitting or receiving side of a data communication link or interconnect. Figure 10a and 10d The apparatus for the method. Figure 10e The illustration depicts an apparatus for generating a data signal to transmit a predetermined number of bits in a serial sequence, including groups of bits indicating control commands. Apparatus 1060 includes a code generation circuit 1062 configured to generate at least one error correction bit for data bits within each of a plurality of subgroups of bits.

[0635] The interleaving circuit 1064 is configured to sort the bits of each subgroup and their associated error correction bits along a first dimension of the multidimensional representation of the data; and to read data bits from the multidimensional representation along a second dimension to determine a series of transmit bits.

[0636] The modulator circuit 1066 is configured to modulate the series of transmit bits into a series of transmit symbols; and to insert control symbol indicators and control symbols into the series of transmit symbols at positions that depend on the group of bits within the series of bits that indicate control commands.

[0637] Based on some examples, Figure 10e The modulator circuit of the device is configured to insert control symbol indicators and control symbols into transmit symbols generated from bits identified by an index of the second dimension in a multidimensional representation corresponding to the number of the byte of the control command within the group of indicator bits.

[0638] According to some examples, the device may optionally further include processing circuitry configured to generate a data signal comprising a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type, the first and second signal edges being separated by a first time period corresponding to a first transmitted symbol, and the second and third signal edges being separated by a second time period corresponding to a second transmitted symbol; and output interface circuitry configured to output the data signal.

[0639] Figure 11a The illustration shows an apparatus 1070 for processing data signals. The apparatus 1070 includes a demodulation circuit 1072 configured to receive a series of symbols, identify control symbol indicators and control symbols within the series of symbols, and demodulate each symbol into associated bits.

[0640] Additionally, device 1070 includes deinterleaving circuitry 1074, which is configured to sort the bits associated with each symbol of the series along a second dimension within the multidimensional representation of the data; and read out the bits of the multidimensional representation along a first dimension.

[0641] The device 1070 also includes a code evaluation circuit 1076 configured to evaluate error correction codes for bits read along the first dimension to determine corrected bits; and to interpret groups of bits along the first dimension as control commands at positions within the multidimensional representation that depend on the positions of control symbol indicators and control symbols within the series of symbols.

[0642] According to another example, the device 1070 may optionally further include an input interface configured to receive a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type in a data signal; wherein the demodulation circuitry is configured to determine a first associated bit based on a first time period between the first signal edge and the second signal edge, and to determine a second associated bit based on a second time period between the second signal edge and the third signal edge.

[0643] The preceding paragraphs described fundamental aspects of the STEP interconnect, such as the STEP protocol and its physical layer. The following paragraphs focus on the Media Access Control (MAC) layer of the STEP protocol. Note that the circuitry and techniques described below can be used in transmitters, receivers, or transceivers to enable communication according to the STEP protocol. However, the circuitry and techniques described below can also be used with communication protocols other than STEP.

[0644] When using (high-speed) communication interfaces between electronic devices, it may be necessary to define a set of controls between the transmitting, receiving, or transceiver circuits on both sides of the interconnect. For example, controls may be used for synchronization, power management, flow control, signaling, and so on. These controls should not be confused with any other data transmissions and should have a minimal impact on overall data throughput.

[0645] Next about Figures 12a to 12q Describes a technology that enables controllable (highly) reliable transmission. Figure 12a An example of an apparatus 1200 for generating a data signal 1201 is illustrated. The apparatus 1200 includes a processing circuit 1205 (e.g., DTC) configured to generate the data signal 1201. The processing circuit 1205 generates the data signal 1201 as a sequence including a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type. For example, the first type may be a rising edge and the second type may be a falling edge, or the second type may be a rising edge and the first type may be a falling edge.

[0646] Additionally, device 1200 includes output interface circuit 1210 configured to output data signal 1201 to a transmission link (not shown).

[0647] The processing circuit 1205 generates a data signal 1201 such that the first signal edge and the second signal edge are separated by a first time period corresponding to the payload data symbols to be transmitted according to a communication protocol (e.g., the STEP protocol).

[0648] exist Figure 12b The diagram illustrates an overview of exemplary possible time periods for encoding payload data symbols into a data signal. Figure 12b In the left portion, the first pulse 1202 is illustrated. Pulse 1202 begins at a rising signal edge 1203 and ends at a falling signal edge 1204. As shown, the position of the falling signal edge 1204 is adjustable by the processing circuit 1205 based on the payload data symbols to be encoded into the data signal 1201. Figure 12b The example illustrates ten different possible positions (labeled 0 to 9) of the falling signal edge 1204. Position 0 defines the minimum pulse length of pulse 1202. Accordingly, ten different time periods between the rising signal edge 1203 and the falling signal edge 1204 can be adjusted. In other words, ten different pulse lengths can be adjusted.

[0649] exist Figure 12b In the example, assume positions 0 through 7 are used to encode payload data symbols into pulse 1202 (e.g., according to the STEP protocol). That is, eight different payload data symbols, or 3 bits, can be encoded into pulse 1202 by adjusting the position of the falling edge 1204. In other words, the different time periods between the rising edge 1203 and the falling edge 1204 indicate different payload data symbols of the communication protocol. The different time periods between the rising edge 1203 and the falling edge 1204 can be understood as the symbol width of different payload data symbols. Figure 12b As can be seen, the time periods corresponding to different payload data symbols of the communication protocol differ by (at least) a constant symbol separation time ΔT. For example, the processing circuit 1205 of device 1200 can adjust the first time period between the first signal edge and the second signal edge in the data signal 1201 to, for example, Figure 12b One of eight possible options indicated by pulse 1202 in order to encode a specific payload data symbol into data signal 1201.

[0650] The processing circuit 1205 also generates a data signal 1201 such that the second and third signal edges are separated by a second time period longer than the time period of any payload data symbol of the communication protocol. Furthermore, the processing circuit 1205 is configured to generate the data signal 1201 to include a fourth signal edge of a second type immediately following the third signal edge. The third and fourth signal edges are separated by a third time period corresponding to a control symbol of the communication protocol. In other words, the processing circuit 1205 generates out-of-band pulses in the data signal 1201 to encode control symbol indicators (e.g., out-of-band symbols) into the data signal 1201. The control symbol indicator separates the control symbol (control word) from one or more payload data symbols.

[0651] refer to Figure 12bFor example, pulse 1202 ends at position 7 at most for payload data symbols. Therefore, positions 8 and 9 can be used to send control symbol indicators.

[0652] To increase the reliability of the control symbol indicator, only position 9 can be used to encode the control symbol indicator into the data signal 1201. In other words, the time period corresponding to the (indicating) control symbol indicator can differ from the longest possible time period corresponding to the (indicating) payload data symbol of the communication protocol by more than one symbol separation time ΔT. For example, the processing circuit 1205 of device 1200 can adjust the second time period between the second and third signal edges in the data signal 1201 to be determined by... Figure 12b Position 9 in the middle indicates the time period to encode the control symbol indicator into data signal 1201.

[0653] To encode specific control symbols of the communication protocol into data signal 1201, processing circuit 1205 adjusts a third time interval between the third and fourth signal edges in data signal 1201. (See reference...) Figure 12b In the example, pulse 1202 ends at position 9 to indicate a control symbol indicator. Pulse 1202 is immediately followed by a second pulse 1206. Pulse 1206 begins at a falling signal edge 1204 at position 9. Pulse 1206 ends at a rising signal edge 1207. Three options are possible for the position of the rising signal edge 1207. Therefore, pulse 1206 can indicate three different control symbols for the communication protocol.

[0654] exist Figure 12b In the example, the time periods corresponding to different control symbols of the communication protocol differ by three symbol separation times ΔT. However, the time periods corresponding to different control symbols of the communication protocol can alternatively differ by any other integer multiple of the symbol separation time ΔT (e.g., two or four symbol separation times ΔT). In other words, the time periods corresponding to different control symbols of the communication protocol can differ by more than one symbol separation time ΔT. Making the time periods corresponding to different control symbols of the communication protocol more than one symbol separation time ΔT allows for more robust control symbol encoding due to the larger time difference between different control symbols. However, in some examples, the time periods corresponding to different control symbols of the communication protocol can alternatively differ by one symbol separation time ΔT.

[0655] For example, the processing circuit 1205 of device 1200 can adjust the third time interval between the third signal edge and the fourth signal edge in data signal 1201 to, for example... Figure 12b The pulse 1206 indicates one of three possible options for encoding a specific control symbol into the data signal 1201.

[0656] Control symbol indicators, together with control symbols, can be understood as unique delimiters used for a particular control. Because of out-of-band control symbol indicators, they cannot be misinterpreted as payload data symbols.

[0657] Control symbols can indicate various commands, states, etc., used to control data transmission and / or operation of the communication interface. For example, control symbols can indicate one of the following: start of data packet (SOP delimiter), end of data packet (EOP delimiter), idle mode (I delimiter), subsequent transmission of calibration (training) data, subsequent transmission with a more robust data packet format, and reversal of the direction of data flow on the transmission link carrying data signal 1201.

[0658] The control symbol indicating idle mode may be used, for example, when there is no data to send (sent by the MAC layer) or before entering low-power mode (see below for details on possible power modes). Figures 15a to 15d The description is encoded into a data signal.

[0659] Delimiters can also be used for power management. For example, when the MAC layer has no data to transmit until the end of at least (n bits) of the transmit data unit, a control symbol indicator, along with a control symbol indicating idle mode, can be encoded into the data signal 1201 once, twice, three times, or more. The (repeated) transmission of the delimiter indicating idle mode can be understood as a low-power mode, where the activity of device 1200 (acting as the transmitter) is low. However, simultaneously, due to the continuous transmission of the delimiter indicating idle mode, the transmission link (line) is kept "hot" by device 1200. Therefore, waking / powering up device 1200 (and / or the receiver of data signal 1201) from idle mode to full throughput mode can be very fast. In other words, delimiters can increase system efficiency by allowing entry and exit from full operation (full throughput) mode with very low latency.

[0660] Furthermore, the long pulse used to indicate the idle mode delimiter can be stretched. For example, the processing circuit 1205 of device 1200 can adjust the second time interval between the second and third signal edges in the data signal 1201 to a length greater than... Figure 12b The longer time period indicated by position 9 in the data signal 1201. For example, processing circuit 1205 can adjust the second time period in data signal 1201 to be the minimum time period (e.g., ...). Figure 12bThe second time period in the data signal 1201 (indicated by position 0) is a sum of 20, 50, 100, or more times the symbol separation time ΔT. In other words, the processing circuit 1205 can adjust the second time period in the data signal 1201 so that it is a multiple of the longest possible time period corresponding to the payload data symbol of the communication protocol. Therefore, the data signal 1201 can be generated by the processing circuit 1205 at a low rate. The burst mode using a long idle delimiter keeps the line hot without (essentially) flipping, and thus keeps the amount of energy per transmitted bit low (e.g., approximately 1 picojoule per bit).

[0661] Alternatively, two consecutive long pulses (out-of-band pulses) can be used to encode control symbols into data signal 1201. That is, processing circuit 1205 can be configured to generate data signal 1201 such that a second time period between the second and third signal edges, and a third time period between the third and fourth signal edges, are longer than the time period of any payload data symbol in the communication protocol. In other words, processing circuit 1205 can encode two consecutive control symbol indicators (delimiters) into data signal 1201 to effectively encode a specific control symbol into data signal 1201. Processing circuit 1205 of device 1200 can, for example, adjust the second and third time periods in data signal 1201 to... Figure 12b The time period indicated by position 9 in the middle.

[0662] For example, for power management delimiters, both high and low pulses can be out-of-band to create a balanced duty cycle for the data signal. Two consecutive out-of-band pulses in the data signal 1201 can, for example, be used to indicate different power modes (power state, operating mode).

[0663] Payload data is encoded into data signal 1201 by adjusting the time intervals between consecutive signal edges in data signal 1201. Therefore, processing circuitry 1205 can be configured to generate data signal 1201 to further include at least a fifth signal edge of a second type preceding (immediately adjacent to) the first signal edge. The fifth signal edge and the first signal edge are separated by a fourth time interval corresponding to another payload data symbol. As mentioned above, device 1200 can be used for communication according to the STEP protocol, among other time-encoded communication protocols. The sum of the first and fourth time intervals can be less than 10 according to the STEP protocol. -7 s, 10 -8 s, 10 -9 s, 10 -10 s, 10 -11 s or 10 -12 s.

[0664] Although the sequence of signal edges representing payload data symbols in data signal 1201 was described above before the signal edges representing control symbol indicators and control symbols, it should be noted that the above example for encoding payload data symbols into data signal 1201 is for illustrative purposes only. Any kind of data (e.g., another delimiter, training data symbols, etc.) may precede or follow the delimiters encoded into the data signal. Therefore, it should be noted that payload data symbols do not necessarily precede or immediately follow the sequence of signal edges representing control symbol indicators and control symbols in data signal 1201. In other words, the sequence of signal edges representing one, two, or more payload data symbols may be encoded into data signal 1201 at any position before or after the sequence of signal edges representing control symbol indicators and control symbols in data signal 1201.

[0665] The processing circuit 1205 of device 1200 can also be configured to generate self-balancing delimiters in terms of frequency and DC level (common-mode voltage). Therefore, processing circuit 1205 can be configured to generate one or more pulses before or after a long pulse of the delimiter to be short (e.g., shorter than the average time interval between successive signal edges in data signal 1201). For example, processing circuit 1205 can be configured to generate data signal 1201 such that the sum of the first time interval and the fourth time interval is lower than the average time interval between successive signal edges of the same type in data signal 1201. Therefore, the long pulse of the delimiter can be compensated by one or more shorter preceding pulses to balance data signal 1201 in terms of frequency and DC level.

[0666] Signal balancing for delimiters can be achieved, for example, via data rearrangement when moving from the MAC layer to the physical layer. See below for reference. Figures 12c to 12i Describe some exemplary data rearrangements. For example, some bits of the delimiter data provided by the MAC layer for delimiters indicating the start or end of a data packet may be redundant in the physical layer. These bits can be used to balance line frequency and duty cycle.

[0667] Assuming the MAC layer operates at an eight-bit resolution and the physical layer operates at a six-bit resolution (e.g., two 3-bit symbols), the delimiter can be sent on a single byte, with only six bits needed to represent the delimiter. Therefore, two of the eight bits representing the delimiter are redundant. This is in... Figure 12c A demonstrative map of China.

[0668] exist Figure 12cThe upper part of the diagram illustrates the sequence of bits b0 to b23 in the MAC layer. Bits b0 to b7 represent delimiters, while bits b8 to b15 and bits b16 to b23 represent payload data. That is, the delimiters are located at the end of the 3-byte set. Only bits b0 to b5 are needed to represent the delimiters. Therefore, bits b6 and b7 are zero.

[0669] like Figure 12c As shown in the lower part, the bits are rearranged across four clock cycles in the physical layer. Redundant bits b6 and b7 are placed as the Most Significant Bit (MSB) of the next low pulse symbol (zero bits b6 and b7 are placed between bits b8 and b9). Therefore, the payload data symbol defined by the three bits b6, b7, and b8 has a short duration. For example, refer to... Figure 12b The pulse lengths shown represent the pulses of the payload data symbols defined by the three bits b6, b7, and b8, which can end at bit 1 or bit 0 depending on the value of bit b8. Assuming the data signal is balanced, the average pulse length (the time interval between consecutive signal edges) will be between bits 3 and 4. Since the low pulse preceding the pulse of the delimiter (defined by bits b0 to b5) is shorter than the average pulse length, the long high pulse of the delimiter is compensated to keep the data signal balanced. In other words, the average symbol is balanced by data rearrangement between the MAC layer and the physical layer.

[0670] Figure 12d A similar scenario is illustrated, where the bits representing the delimiters are arranged between the bits representing the payload data. Bits b8 to b15 represent the delimiters, while bits b0 to b7 and bits b16 to b23 represent the payload data. Only bits b8 to b13 are needed to represent the delimiters. Therefore, bits b14 and b15 are zero.

[0671] These bits are then rearranged across four clock cycles in the physical layer. Bits b6 and b7 are moved to the next high-pulse symbol and the next low-pulse symbol, respectively. Redundant bits b14 and b15 are again placed as the MSB of the next low-pulse symbol. Once again, the low pulse preceding the delimiter pulse (defined by bits b8 to b13) is shorter than the average pulse length, thus compensating for the long delimiter pulse and maintaining a balanced data signal.

[0672] Figure 12e A similar scenario is illustrated, where the bits representing the delimiters are arranged before the bits representing the payload data. Bits b16 to b23 represent the delimiters, while bits b8 to b15 and bits b0 to b7 represent the payload data. Only bits b16 to b21 are needed to represent the delimiters. Therefore, bits b22 and b23 are zero.

[0673] These bits are then rearranged across four clock cycles in the physical layer. Redundant bits b22 and b23 are placed as the MSB of the next low pulse symbol. The low pulse following the delimiter (defined by bits b16 to b21) is shorter than the average pulse length, thus compensating for the long pulse of the delimiter and keeping the data signal balanced.

[0674] Figure 12f The diagram illustrates a scenario where the bits representing two consecutive free delimiters are located at the end of a 3-byte set. Bits b0 to b7 represent the first free delimiter, and bits b8 to b15 represent the second free delimiter, while bits b16 to b23 represent the payload data. Only bits b8 to b13 are needed to represent the second free delimiter. Therefore, bits b14 and b15 are zero.

[0675] These bits are then rearranged across four clock cycles in the physical layer. Bits b6 and b7 of the first idle delimiter are moved to the next high and low pulse symbols, respectively, representing the payload data. Redundant bits b14 and b15 are again placed as the MSB of the next low pulse symbol representing the payload data. Once again, the low pulse preceding the pulse of the second idle delimiter (defined by bits b8 to b13) is shorter than the average pulse length, thus compensating for the long pulses of the delimiter and maintaining a balanced data signal.

[0676] Figure 12g The diagram illustrates a scenario where a three-byte set represents three consecutive free delimiters. Bits b0 to b7 represent the first free delimiter, bits b8 to b15 represent the second free delimiter, and bits b16 to b23 represent the third free delimiter. Only bits b8 to b13 are needed to represent the second free delimiter, and only bits b16 to b21 are needed to represent the third free delimiter. Therefore, bits b14 and b15, and bits b22 and b23, are zero.

[0677] These bits are then rearranged across four clock cycles in the physical layer. Bits b1 to b5, bits b8 to b13, and bits b16 to b21 are used in the physical layer to represent the first, second, and third idle delimiters. Bits b6 and b7 of the first idle delimiter are moved to the next high-pulse symbol and the next low-pulse symbol, respectively, to represent payload data. Redundant bits b14 and b15, and redundant bits b22 and b23, are placed as the MSBs of the next low-pulse symbol and the next high-pulse symbol, respectively, representing payload data. The low and high pulses representing payload data are both shorter than the average pulse length, thus compensating for the long pulses of the delimiters and maintaining a balanced data signal.

[0678] Figure 12hThe illustration shows another scenario where the set of bytes representing the payload data is arranged between two sets of bytes representing delimiters. Bits b0 to b7 represent the first delimiter, and bits b16 to b23 represent the second delimiter, while bits b8 to b15 represent the payload data. Only bits b1 to b5 and bits b16 to b21 are needed to represent the first and second delimiters. Therefore, bits b6 and b7, and bits b22 and b23, are zero.

[0679] These bits are then rearranged across four clock cycles in the physical layer. Bits b1 through b5 and bits b16 through b21 are used to represent the first and second delimiters. Redundant bits b6 and b7 of the first delimiter are placed as the MSB of the next low pulse symbol representing the payload data. Additionally, redundant bits b22 and b23 of the second delimiter are placed as the MSB of the previous low pulse symbol representing the payload data. Both low pulses representing the payload data are shorter than the average pulse length, thus compensating for the long pulses of the delimiters and maintaining a balanced data signal.

[0680] Device 1200 can allow the generation of single-ended data signals or differential signal pairs as described above. That is, in some examples, processing circuitry 1205 can also be configured to generate a second data signal, wherein the second data signal is inverted relative to data signal 1201. Therefore, output interface circuitry 1210 can be configured to also output the second data signal to the transmission link.

[0681] exist Figure 12i The diagram illustrates another exemplary data signal 1215 according to the above aspects. Data signal 1215 includes a plurality of pulses 1215-n-(m+3),...,1215-n-2, which exhibit different pulse lengths to encode different payload data symbols into data signal 1215. Additionally, pulses 1215-n-1 and 1215-n encode idle delimiters into data signal 1215. Pulse 1215-n-1, representing a control symbol indicator, is extended as described above. For example, device 1200 may generate data signal 1215.

[0682] In the example above, the control symbol indicator precedes the control symbol in time. However, in some examples, the control symbol may alternatively precede the control symbol indicator. Figure 12j The diagram shows a device 1220 for generating the corresponding data signal 1221.

[0683] Apparatus 1200 includes processing circuitry 1225 (e.g., DTC) configured to generate a data signal 1221. Processing circuitry 1225 is configured to generate the data signal 1221 as a sequence including a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type. The first and second signal edges are separated by a first time period corresponding to control symbols of a communication protocol (e.g., the STEP protocol). The second and third signal edges are separated by a second time period longer than the time period of any payload data symbol of the communication protocol for encoding control symbol indicators into the data signal 1221. Again, the first type can be a rising edge and the second type can be a falling edge, or the second type can be a rising edge and the first type can be a falling edge.

[0684] Device 1200 includes output interface circuitry 1230 configured to output data signal 1221 to a transmission link (not shown).

[0685] Related to the above Figure 12a and 12b Similarly, in data signal 1221, the time periods corresponding to different payload data symbols of the communication protocol may differ by at least the symbol separation time ΔT, and the time periods corresponding to different control symbols of the communication protocol may differ by more than the symbol separation time ΔT. For example, the time periods corresponding to different control symbols may differ by an integer multiple of the symbol separation time ΔT. Furthermore, the time period corresponding to the (indication) control symbol indicator may differ from the longest possible time period corresponding to the (indication) payload data symbol of the communication protocol by more than one symbol separation time ΔT.

[0686] Control symbols can also indicate various commands, states, etc., used to control data transmission and / or operation of the communication interface. For example, control symbols can indicate one of the following: the start of a data packet, the end of a data packet, idle mode, subsequent transmission of calibration data, subsequent transmission with a more robust data packet format, and reversal of the direction of the data flow on the transmission link carrying data signals.

[0687] Furthermore, by adjusting the time intervals between consecutive signal edges in data signal 1221, payload data can be encoded into data signal 1221. Therefore, processing circuit 1225 can be configured to generate data signal 1221 to further include a fourth signal edge of the second type, wherein the third and fourth signal edges are separated by a third time interval corresponding to a payload data symbol of the communication protocol. Additionally, processing circuit 1225 can be configured to generate data signal 1221 to further include a fifth signal edge of the first type, wherein the fourth and fifth signal edges are separated by a fourth time interval corresponding to another payload data symbol of the communication protocol. As mentioned above, in addition to other time-encoded communication protocols, device 1200 can also be used for communication according to the STEP protocol. The sum of the third and fourth time intervals can be less than 10 according to the STEP protocol. -7 s, 10 -8 s, 10 -9 s, 10 -10 s, 10 -11 s or 10 -12 s.

[0688] Although the sequence of signal edges representing payload data symbols in data signal 1211 was described above as following the signal edges representing control symbols and control symbol indicators, it should also be noted that the above example for encoding payload data symbols into data signal 1221 is for illustrative purposes only. Any kind of data (e.g., another delimiter, training data symbols, etc.) may precede or follow the delimiters encoded into the data signal. Therefore, it should be noted that payload data symbols do not necessarily precede or immediately follow the sequence of signal edges representing control symbols and control symbol indicators in data signal 1221. In other words, the sequence of signal edges representing one, two, or more payload data symbols may be encoded into data signal 1221 at any position before or after the sequence of signal edges representing control symbols and control symbol indicators in data signal 1221.

[0689] The processing circuitry 1225 of device 1220 can also be enabled to generate self-balancing delimiters in terms of frequency and DC level (common-mode voltage). Therefore, processing circuitry 1225 can be configured to generate one or more pulses before or after a long pulse of the delimiter as short (e.g., shorter than the average time interval between successive signal edges in data signal 1221). For example, processing circuitry 1205 can be configured to generate data signal 1201 such that the sum of the third and fourth time intervals is lower than the average time interval between successive signal edges of the same type in data signal 1221.

[0690] Similar to device 1200, device 1220 can allow the generation of single-ended data signals or differential signal pairs as described above. That is, in some examples, processing circuitry 1225 can also be configured to generate a second data signal, wherein the second data signal is inverted relative to data signal 1221. Therefore, output interface circuitry 1230 can also be configured to output the second data signal to the transmission link.

[0691] In some examples, device 1220, or at least the circuitry of device 1220, may be configured to also perform the corresponding adaptive changes described above in connection with device 1200 (e.g., adapting to the interchange of control symbol indicator positions and control symbol positions in data signals).

[0692] As mentioned above, the STEP protocol is based on pulse width modulation, where pulse width modulation is based on the transmitted data. To avoid wasting one or more payload data symbols on delimiters, the proposed technique uses unique out-of-band control symbols for delimiters, which allows the receiver to detect them (easily) without any overhead penalty.

[0693] Additionally, delimiters can be mapped to specific clock periods at the physical layer, which balance them out to optimize line dynamics. This eliminates the need for specialized processing from the MAC or physical layers. Furthermore, this mapping protects delimiters from false detections caused by errors.

[0694] For example, as mentioned above. Figure 12b As described, the STEP protocol modulates each pulse of the data signal into one of several options (e.g., creating an n-bit symbol). Reference Figure 12b For example, three bits can be used for each symbol, allowing eight different phases of the pulse to be used. In other words, eight different possible phases of the pulse can be used to encode data.

[0695] To enable easy and protected / reliable reception of delimiters, out-of-band high and low pulses can be used. Each delimiter is represented by two pulses. For example, seven delimiters can be used—each with a long high pulse followed by a short low pulse, a long low pulse followed by a short high pulse, or both high and low pulses being long. If only one of the two pulses is long, the next pulse holds the delimiter type (control symbol). As mentioned above, the mapping from delimiter type to short pulses can be separated by, for example, three or more phases to avoid reception errors.

[0696] The aforementioned Figures 12a to 12j The description focuses on the generation of data (transmission) signals, including delimiters. See below for further details. Figure 12k and 12l Describe the relevant aspects regarding the detection of delimiters in data (received) signals.

[0697] Figure 12k An example of an apparatus 1240 for decoding data signal 1241 is illustrated. Apparatus 1240 includes processing circuitry 1245 (e.g., TDC) configured to determine a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type in the data signal. Again, the first type can be a rising edge and the second type can be a falling edge, or vice versa. For example, data signal 1241 may be received from a transmission link by an interface circuitry (not shown) of apparatus 1240.

[0698] Additionally, the apparatus 1240 for decoding the data signal 1241 includes a demodulation circuit 1250 configured to determine a payload data symbol based on a first time period when the time period between the first signal edge and the second signal edge is shorter than a payload data threshold. The demodulation circuit 1250 is also configured to determine a control symbol indicator when the second time period between the second signal edge and the third signal edge is longer than the payload data threshold.

[0699] As described above, there exists a longest possible time interval between the immediate signal edge corresponding to the payload data symbol of the communication protocol (e.g., STEP protocol) in the data signal. Therefore, the payload data threshold is a reference time interval used as a decision criterion for determining whether the data encoded into the pulse is payload data or a control symbol indicator for delimiters. Reference Figure 12b For example, the payload data threshold could be, for instance, any pulse width between positions 7 and 9 of the falling signal edge 1204. In other words, the payload data threshold is longer than the longest possible time interval between successive signal edges in the data signal corresponding to the payload data symbol of the communication protocol, and shorter than the time interval defined for the control symbol indicator in the communication protocol. For example, the payload data threshold could be determined by… Figure 12b The pulse width indicated by position 8 of the falling signal edge 1204 in the example.

[0700] The start of a delimiter can be detected relatively easily by comparing the time interval between consecutive signal edges in the data signal 1241 with a payload data threshold. Therefore, the processing circuit 1245 can also be configured to determine a fourth signal edge of a second type immediately following the third signal edge in the data signal 1241, and the demodulation circuit 1250 can be configured to determine the corresponding control symbol of the communication protocol based on a third time interval between the third and fourth signal edges.

[0701] As mentioned above, control symbols can also indicate various commands, states, etc., for controlling data transmission and / or operation of the communication interface. For example, control symbols can indicate one of the following: the start of a data packet, the end of a data packet, idle mode, subsequent transmission of calibration data, subsequent transmission with a more robust data packet format, and reversal of the direction of the data flow on the transmission link carrying data signals.

[0702] Contact as mentioned above Figure 12a and 12b For the signal generation described, the time periods corresponding to different payload data symbols of the communication protocol may differ by at least the symbol separation time ΔT, and the time periods corresponding to different control symbols of the communication protocol may differ by more than the symbol separation time ΔT. For example, the time periods corresponding to different control symbols may differ by an integer multiple of the symbol separation time ΔT. Therefore, the demodulation circuit 1250 can be configured to determine the payload data symbols and control symbols based on information about the time periods corresponding to different payload data symbols of the communication protocol and information about the time periods corresponding to different control symbols of the communication protocol.

[0703] Payload data is encoded into data signal 1241 via the time interval between consecutive signal edges. Therefore, processing circuitry 1245 can also be configured to determine a fifth signal edge of a second type in data signal 1241 that is temporally adjacent to the first signal edge. Therefore, demodulation circuitry 1250 can be configured to determine another payload data symbol based on the fourth time interval if the fourth time interval between the fifth signal edge and the first signal edge is shorter than a payload data threshold. As described above, the sum of the first and fourth time intervals can be less than 10 according to the STEP protocol. -7 s, 10 -8 s, 10 -9 s, 10 -10 s, 10 -11 s or 10 -12 s.

[0704] The above example for decoding payload data symbols in data signal 1241 is for illustrative purposes only. Any kind of data (e.g., another delimiter, training data symbols, etc.) may be encoded before or after the delimiters in the data signal. Therefore, it should be noted that payload data symbols do not necessarily precede or immediately follow the sequence of signal edges representing control symbol indicators along with control symbols in data signal 1241. In other words, the sequence of signal edges representing one, two, or more payload data symbols may be encoded anywhere in data signal 1241 before or after the sequence of signal edges representing control symbol indicators along with control symbols.

[0705] In some examples, differential signal pairs may be received by device 1240. That is, processing circuitry 1245 may also be configured to receive a second data signal that is inverted relative to data signal 1241. Therefore, processing circuitry 1245 may also be configured to determine a first signal edge, a second signal edge, and a third signal edge based on the second data signal. In other words, processing circuitry 1245 may determine signal edges based on differential pairs of the data signals.

[0706] As described above regarding signal generation, control symbols in data signals may alternatively precede control symbol indicators. Figure 12l The diagram shows a device 1260 for decoding the corresponding data signal 1261.

[0707] Apparatus 1260 includes processing circuitry 1265 (e.g., TDC) configured to determine a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type in a data signal. Again, the first type can be a rising edge and the second type can be a falling edge, or the second type can be a rising edge and the first type can be a falling edge. For example, data signal 1261 may be received from a transmission link by interface circuitry (not shown) of apparatus 1260.

[0708] Additionally, the apparatus 1260 for decoding the data signal 1261 includes a demodulation circuit 1270 configured to determine control symbols for a communication protocol (e.g., the STEP protocol) based on a first time period between a first signal edge and a second signal edge. Furthermore, the demodulation circuit 1270 is configured to determine control symbol indicators for the communication protocol if a second time period between the second and third signal edges is longer than a payload data threshold.

[0709] Unlike device 1240, device 1260 compares the time interval of consecutive signal edges in data signal 1261 with a payload data threshold to detect the end of a delimiter. However, delimiters can also be detected relatively easily.

[0710] In data signal 1261, payload data is also encoded into the signal via time intervals between consecutive signal edges. Therefore, processing circuit 1265 can also be configured to determine a second type of fourth signal edge immediately following the third signal edge in the data signal, and to determine a first type of fifth signal edge immediately following the fourth signal edge in the data signal. Therefore, demodulation circuit 1270 can be configured to determine the payload data symbol of a communication protocol (e.g., the STEP protocol) based on the third time interval if the third time interval between the third and fourth signal edges is shorter than a payload data threshold. Similarly, demodulation circuit 1270 can be configured to determine another payload data symbol of the communication protocol based on the fourth time interval between the fourth and fifth signal edges if the third time interval is shorter than a payload data threshold. As described above, the sum of the first and second time intervals can be less than 10 according to the STEP protocol. -7 s, 10 -8 s, 10 -9 s, 10 -10 s, 10 -11 s or 10 -12 s.

[0711] Similarly, the above examples for decoding payload data symbols in data signal 1261 are for illustrative purposes only. Any kind of data (e.g., another delimiter, training data symbols, etc.) may precede or follow the delimiters encoded into the data signal. Therefore, it should be noted that payload data symbols do not necessarily precede or follow the sequence of signal edges representing control symbols along with control symbol indicators in data signal 1261. In other words, the sequence of signal edges representing one, two, or more payload data symbols may be encoded into data signal 1241 at any position before or after the sequence of signal edges representing control symbols along with control symbol indicators in data signal 1241.

[0712] The demodulation circuit 1270 can also be configured to determine the payload data symbols and control symbols based on information about the time periods corresponding to different payload data symbols of the communication protocol and information about the time periods corresponding to different control symbols of the communication protocol. The information about the different time periods can be as described above for device 1240.

[0713] In some examples, the processing circuit 1265 may also be configured to receive a second data signal that is inverted relative to the data signal 1261. Therefore, the processing circuit 1265 may also be configured to determine a first signal edge, a second signal edge, and a third signal edge based on the second data signal. That is, the processing circuit 1265 may determine the signal edges based on differential pairs of the data signals.

[0714] The device 1260 or at least its circuit components may be configured to also perform the corresponding adaptive change features described above in connection with the device 1240 (e.g., adapting to the interchange of the control symbol indicator position and the control symbol position in the data signal).

[0715] To summarize some of the above aspects regarding delimiters, by... Figure 12m The flowchart illustrates an example of method 1200m for generating a data signal. Method 1200m includes generating a 1202m data signal. The data signal includes a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type. The first and second signal edges are separated by a first time period corresponding to a payload data symbol to be transmitted according to the communication protocol, and the second and third signal edges are separated by a second time period longer than the time period of any payload data symbol in the communication protocol. Additionally, method 1200m includes outputting a 1204m data signal.

[0716] Optionally, the data signal may also include a fourth signal edge of a second type, wherein the third signal edge and the fourth signal edge are separated by a third time period corresponding to the control symbols of the communication protocol.

[0717] For more details and aspects of method 1200m, please refer to the proposed technology or one or more examples described above (e.g. Figures 12a to 12i The method may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples described above.

[0718] By Figure 12n The flowchart illustrates another example of a method 1200n for generating a data signal. Method 1200n includes generating a 1202n data signal. This data signal includes a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type. The first and second signal edges are separated by a first time period corresponding to control symbols of a communication protocol, and the second and third signal edges are separated by a second time period longer than the time period of any payload data symbol of the communication protocol. Additionally, method 1200n includes outputting a 1204n data signal.

[0719] Optionally, the data signal may also include a fourth signal edge of a second type, wherein the third signal edge and the fourth signal edge are separated by a third time period corresponding to the payload data symbols of the communication protocol.

[0720] For more details and aspects of method 1200n, please refer to the proposed technology or one or more examples described above (e.g. Figure 12jThe method may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples described above.

[0721] By Figure 12o The flowchart illustrates an example of method 1200o for decoding a data signal. Method 1200o includes determining a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type in the data signal. Additionally, method 1200o includes determining payload data symbols of a communication protocol based on a first time period if the time period between the first and second signal edges is shorter than a payload data threshold. Method 1200o further includes determining control symbol indicators of the communication protocol if a second time period between the second and third signal edges is longer than the payload data threshold.

[0722] Optionally, method 1200o may further include determining a fourth signal edge of a second type in the data signal 1208o, and determining a control symbol of the communication protocol 1210o based on a third time period between the third signal edge and the fourth signal edge.

[0723] For more details and aspects of method 1200o, please refer to the proposed technology or one or more examples described above (e.g. Figure 12k The method may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples described above.

[0724] By Figure 12p The flowchart illustrates another example of method 1200p for decoding data signals. Method 1200p includes determining a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type in the 1202p data signal. Additionally, method 1200p includes determining control symbols for a 1204p communication protocol based on a first time period between the first and second signal edges. Method 1200p further includes determining control symbol indicators for a 1206p communication protocol if a second time period between the second and third signal edges is longer than a payload data threshold.

[0725] Optionally, method 1200p may further include determining a fourth signal edge of a second type in the 1208p data signal, and determining the payload data symbol of the 1210p communication protocol based on the third time period if the third time period between the third signal edge and the fourth signal edge is shorter than the payload data threshold.

[0726] For more details and aspects of method 1200p, please contact the proposed technique or one or more examples described above (e.g. Figure 12l The method may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples described above.

[0727] The above example of delimiters uses a combination of a control symbol indicator and a control symbol in a communication protocol. To increase the number of delimiters, more than one control symbol can follow the control symbol indicator. In other words, delimiters can be cascaded. Some exemplary circuits for generating or decoding corresponding data signals are referenced below. Figures 12q to 12s To describe.

[0728] Figure 12q Another example of an apparatus 1275 for generating data signal 1276 is illustrated. Apparatus 1275 includes processing circuitry 1277 (e.g., DTC) configured to generate data signal 1276. Processing circuitry 1277 is configured to generate data signal 1276 to include a sequence of at least a first signal edge of a first type, a second signal edge of a second type, a third signal edge of a first type, and a fourth signal edge of a second type.

[0729] Processing circuitry 1277 generates data signal 1276 such that the first and second signal edges are separated by a first time period longer than the time period of any payload data symbol of the communication protocol (e.g., the STEP protocol). Additionally, the second and third signal edges are separated by a second time period corresponding to a first control symbol of the communication protocol, which indicates the successor to at least one other control symbol of the communication protocol. The third and fourth signal edges are separated by a third time period corresponding to a second control symbol of the communication protocol. Similarly, the first type can be a rising edge and the second type can be a falling edge, or the second type can be a rising edge and the first type can be a falling edge.

[0730] Additionally, data signal 1276 may include a fifth signal edge of a first type immediately following the fourth signal edge. The fourth and fifth signal edges are separated by a fourth time period corresponding to the third control symbol of the communication protocol.

[0731] Device 1275 also includes output interface circuitry 1278 configured to output data signal 1276 to a transmission link (not shown).

[0732] The number of possible controls can be expanded by using multiple consecutive control symbols. Each control symbol can control or indicate a specific attribute / feature if it is encoded into a data signal along with a control symbol indicator. Furthermore, combinations of consecutive control symbols following a control symbol indicator in the data signal can allow additional control or indication of specific attributes / features to be encoded into the data signal. For example, a sequence of control symbols can be assigned to a specific command.

[0733] In other words, an escape (ESC) delimiter (which can be any delimiter of choice) can be followed by one or more semi-legacy delimiters. Semi-legacy delimiters can still be very compact and very reliable. For example, as mentioned above, an ESC delimiter can be followed by two control symbols. (See above for more details.) Figure 12b Similarly, the time intervals used for different control symbols can be separated by more than one symbol separation time ΔT. For example, if both control symbols can represent three different time intervals (e.g., arbitrary lengths of 0, 3, and 6), then combining these two control symbols enables 3. 2 =9 additional controls.

[0734] In some examples, the first control symbol may indicate the exact number of subsequent control symbols. In other examples, the number of subsequent control symbols may be defined by the communication protocol (e.g., the communication protocol may define that the first control symbol is always followed by two, three, four or more additional control symbols).

[0735] Alternatively, if the number of subsequent control symbols is defined by the communication protocol, the first control symbol may be omitted. For example, the communication protocol may define a control symbol indicator always followed by two, three, four, or more control symbols. Therefore, the second and third signal edges in data signal 1276 may be separated by a second time period corresponding to the second control symbol of the communication protocol, and the third and fourth signal edges in data signal 1276 may be separated by a third time period corresponding to the third control symbol of the communication protocol.

[0736] Furthermore, by adjusting the time intervals between consecutive signal edges in data signal 1276, payload data can be encoded into data signal 1276. Therefore, processing circuit 1277 can be configured to generate data signal 1276 to further include a sequence of a sixth signal edge of a first type, a seventh signal edge of a second type, and an eighth signal edge of a first type. Processing circuit 1277 generates data signal 1276 such that the sixth and seventh signal edges are separated by a fifth time interval corresponding to a first payload data symbol of the communication protocol, and the seventh and eighth signal edges are separated by a sixth time interval corresponding to a second payload data symbol of the communication protocol. As mentioned above, in addition to other time-encoded communication protocols, device 1275 can also be used for communication according to the STEP protocol. The sum of the fifth and sixth time intervals can be less than 10 according to the STEP protocol. -7 s, 10 -8 s, 10 -9 s, 10 -10 s, 10 -11 s or 10 -12 s.

[0737] Similar to device 1200, device 1275 can allow the generation of single-ended data signals or differential signal pairs as described above. That is, in some examples, processing circuitry 1277 can also be configured to generate a second data signal, wherein the second data signal is inverted relative to data signal 1276. Therefore, output interface circuitry 1278 can be configured to also output the second data signal to the transmission link.

[0738] The device 1275 or at least its circuit components may also be configured to perform other corresponding adaptive changes to the features described above in connection with device 1200.

[0739] In some examples, control symbols may precede control symbol indicators. Figure 12rThe diagram illustrates an apparatus 1280 for generating a corresponding data signal 1281. The apparatus 1280 includes a processing circuit 1282 (e.g., DTC) configured to generate the data signal 1281. The processing circuit 1282 is configured to generate the data signal 1281 to include a sequence of at least a first signal edge of a first type, a second signal edge of a second type, a third signal edge of a first type, and a fourth signal edge of a second type. The first and second signal edges are separated by a first time period corresponding to a first control symbol of a communication protocol (e.g., the STEP protocol). The second and third signal edges are separated by a second time period corresponding to a second control symbol of the communication protocol, which indicates at least one preceding control symbol of the communication protocol. Additionally, the third and fourth signal edges are separated by a third time period longer than the time period of any payload data symbol of the communication protocol. Similarly, the first type can be a rising edge and the second type can be a falling edge, or the second type can be a rising edge and the first type can be a falling edge.

[0740] Additionally, data signal 1281 may include a fifth signal edge of a second type immediately preceding the first signal edge. The first signal edge and the fifth signal edge are separated by a fourth time period corresponding to the third control symbol of the communication protocol.

[0741] The device 1280 also includes an output interface circuit 1283 configured to output a data signal 1281 to a transmission link (not shown).

[0742] By using multiple consecutive control symbols, the number of possible controls can be expanded, as described above for device 1275. Unlike device 1275, device 1280 uses control symbol indicators to indicate the end of the cascade delimiter.

[0743] In some examples, the second control symbol may indicate the exact number of preceding control symbols. In other examples, the number of preceding control symbols may be defined by the communication protocol (e.g., the communication protocol may define that there are always two, three, four or more additional control symbols before the second control symbol).

[0744] Alternatively, if the number of preceding control symbols is defined by the communication protocol, the second control symbol can also be omitted. For example, the communication protocol may define that there are always two, three, four, or more control symbols before the control symbol indicator. Therefore, the first and second signal edges in data signal 1281 may be separated by a first time period corresponding to the third control symbol of the communication protocol, and the second and third signal edges in data signal 1281 may be separated by a second time period corresponding to the first control symbol of the communication protocol.

[0745] Furthermore, by adjusting the time intervals between consecutive signal edges in data signal 1281, payload data can be encoded into data signal 1281. Therefore, processing circuitry 1282 can be configured to generate data signal 1281 as a sequence including a sixth signal edge of a first type, a seventh signal edge of a second type, and an eighth signal edge of a first type. The sixth and seventh signal edges are separated by a fifth time interval corresponding to the first payload data symbol, and the seventh and eighth signal edges are separated by a sixth time interval corresponding to the second payload data symbol. As mentioned above, in addition to other time-encoded communication protocols, device 1280 can also be used for communication according to the STEP protocol. The sum of the fifth and sixth time intervals can be less than 10 according to the STEP protocol. -7 s, 10 -8 s, 10 -9 s, 10 -10 s, 10 -11 s or 10 -12 s.

[0746] Similar to device 1275, device 1280 can allow the generation of single-ended data signals or differential signal pairs as described above. That is, in some examples, processing circuitry 1282 can also be configured to generate a second data signal, wherein the second data signal is inverted relative to data signal 1281. Therefore, output interface circuitry 1283 can be configured to also output the second data signal to the transmission link.

[0747] The circuitry of device 1280, or at least device 1280, may also be configured to perform other corresponding adaptive changes to the features described above in connection with devices 1200, 1220, and 1275.

[0748] The aforementioned Figures 12q to 12r The description focuses on the generation of data (transmission) signals, including cascaded delimiters. Below, we will discuss... Figure 12s and 12t Describes the relevant aspects of detecting cascaded delimiters in the received data signal.

[0749] Figure 12sAn example of an apparatus 1285 for decoding a data signal 1286 is illustrated. The apparatus 1285 includes processing circuitry 1286 (e.g., a TDC) configured to determine a sequence of first signal edges of a first type, second signal edges of a second type, third signal edges of a first type, and fourth signal edges of a second type in the data signal 1286. Similarly, the first type may be a rising edge and the second type may be a falling edge, or vice versa. For example, the data signal 1286 may be received from a transmission link by an interface circuitry (not shown) of the apparatus 1285.

[0750] Additionally, the apparatus 1285 for decoding the data signal 1286 includes a demodulation circuit 1287 configured to determine a control symbol indicator if a first time period between the first and second signal edges is longer than a payload data threshold defined in the communication protocol. Furthermore, the demodulation circuit 1287 is configured to determine a first control symbol of the communication protocol, indicating a successor to at least one additional control symbol of the communication protocol, if a second time period between the second and third signal edges corresponds to a predetermined time period defined in the communication protocol. The demodulation circuit 1287 is also configured to determine a second control symbol of the communication protocol based on a third time period between the third and fourth signal edges.

[0751] The processing circuit 1287 can also be configured to determine a fifth signal edge of a first type immediately following the fourth signal edge in the data signal 1286. Therefore, the demodulation circuit 1288 can also be configured to determine a third control symbol of the communication protocol based on a fourth time period between the fourth and fifth signal edges.

[0752] The start of a concatenated delimiter can be detected relatively easily by comparing the time interval between consecutive signal edges in the data signal 1286 with a payload data threshold. For example, demodulation circuit 1288 or additional circuitry of the means 1285 for decoding the data signal 1286 can analyze the sequence / combination of the second and third control symbols in the data signal 1286 to determine the type of (control) command encoded into the data signal 1286.

[0753] In some examples, the first control symbol may indicate the exact number of subsequent control symbols. In other examples, the number of subsequent control symbols may be defined by the communication protocol (e.g., the communication protocol may define that the first control symbol is always followed by two, three, four or more additional control symbols).

[0754] Alternatively, if the number of subsequent control symbols is defined by the communication protocol, the first control symbol may be omitted. For example, the communication protocol may define a control symbol indicator always followed by two, three, four, or more control symbols. Therefore, the demodulation circuit 1288 may be configured to determine the second control symbol of the communication protocol based on a second time period between the second and third signal edges in the data signal 1286, and to determine the third control symbol of the communication protocol based on a third time period between the third and fourth signal edges in the data signal 1286.

[0755] Payload data is encoded into data signal 1286 via the time interval between consecutive signal edges. Therefore, processing circuit 1287 can also be configured to determine the sequence of a first type of sixth signal edge, a second type of seventh signal edge, and a first type of eighth signal edge in data signal 1286. Additionally, demodulation circuit 1288 can be configured to determine a first payload data symbol of the communication protocol based on a fifth time interval if the fifth time interval between the sixth and seventh signal edges is shorter than a payload data threshold. Therefore, demodulation circuit 1288 can be configured to determine a second payload data symbol of the communication protocol based on a sixth time interval if the sixth signal edge between the seventh and eighth signal edges is shorter than a payload data threshold. As described above, the sum of the fifth and sixth time intervals can be less than 10 according to the STEP protocol. -7 s, 10 -8 s, 10 -9 s, 10 -10 s, 10 -11 s or 10 -12 s.

[0756] Similarly, demodulation circuit 1288 can be configured to determine payload data symbols and control symbols based on information about time periods corresponding to different payload data symbols of the communication protocol and information about time periods corresponding to different control symbols of the communication protocol. The information about the different time periods can be as described above for device 1240.

[0757] In some examples, the processing circuit 1287 may also be configured to receive a second data signal that is inverted relative to the data signal 1286. Therefore, the processing circuit 1287 may be configured to further determine at least a first signal edge, a second signal edge, a third signal edge, and a fourth signal edge based on the second data signal. That is, the processing circuit 1287 may determine the signal edges based on differential pairs of the data signal.

[0758] Device 1285, or at least the circuitry of device 1285, may also be configured to perform other corresponding adaptive modifications of the features described above in connection with devices 1240 and 1260.

[0759] As described above regarding signal generation, control symbols in data signals may alternatively precede control symbol indicators. Figure 12t The diagram shows a device 1290 for decoding the corresponding data signal 1291.

[0760] Device 1290 includes processing circuitry 1292 (e.g., TDC) configured to determine a sequence of first signal edges of a first type, second signal edges of a second type, third signal edges of a first type, and fourth signal edges of a second type in data signal 1291. Similarly, the first type may be a rising edge and the second type may be a falling edge, or vice versa. For example, data signal 1291 may be received from a transmission link by interface circuitry (not shown) of device 1290.

[0761] Additionally, the apparatus 1290 for decoding the data signal 1291 includes a demodulation circuit 1293 configured to determine a first control symbol of a communication protocol (e.g., the STEP protocol) based on a first time period between a first signal edge and a second signal edge. Furthermore, the demodulation circuit 1293 is configured to determine a second control symbol of the communication protocol, indicating at least one preceding control symbol, if a second time period between the second and third signal edges corresponds to a predetermined time period defined in the communication protocol. The demodulation circuit 1293 is configured to determine a control symbol indicator if a third time period between the third and fourth signal edges is longer than a payload data threshold defined in the communication protocol.

[0762] Additionally, the processing circuit 1292 can be configured to determine a fifth signal edge of a second type immediately preceding the first signal edge in the data signal 1291. Therefore, the demodulation circuit 1293 can also be configured to determine a third control symbol of the communication protocol based on a fourth time period between the fifth signal edge and the first signal edge.

[0763] Unlike device 1285, device 1290 compares the time interval of consecutive signal edges in data signal 1291 with a payload data threshold to detect the end of a concatenation delimiter. However, concatenation delimiters can also be detected relatively easily. For example, demodulation circuit 1293 or additional circuitry of device 1290 for decoding data signal 1291 can analyze the sequence / combination of the first and third control symbols in data signal 1291 to determine the type of (control) command encoded into data signal 1291.

[0764] In some examples, the second control symbol may indicate the exact number of preceding control symbols. In other examples, the number of preceding control symbols may be defined by the communication protocol (e.g., the communication protocol may define that there are always two, three, four or more additional control symbols before the first control symbol).

[0765] Similar to the description of device 1285 above, if the number of subsequent control symbols is defined by the communication protocol, the second control symbol can be omitted. For example, the communication protocol may define that there are always two, three, four, or more control symbols before the control symbol indicator. Therefore, demodulation circuit 1293 can be configured to determine the third control symbol of the communication protocol based on a first time period between the first and second signal edges in data signal 1291, and to determine the first control symbol of the communication protocol based on a second time period between the second and third signal edges in data signal 1291.

[0766] Similarly, in data signal 1291, payload data is encoded into the signal via time intervals between consecutive signal edges. Therefore, processing circuit 1292 can also be configured to determine a sequence of a first type of sixth signal edge, a second type of seventh signal edge, and a first type of eighth signal edge in data signal 1291. Therefore, demodulation circuit 1293 can be configured to determine a first payload data symbol of a communication protocol (e.g., STEP protocol) based on a fifth time interval if the fifth time interval between the sixth and seventh signal edges is shorter than a payload data threshold, and to determine a second payload data symbol based on a sixth time interval if the sixth time interval between the seventh and eighth signal edges is shorter than a payload data threshold. As described above, the sum of the fifth and sixth time intervals can be less than 10 according to the STEP protocol. -7 s, 10 -8 s, 10 -9 s, 10 -10 s, 10 -11 s or 10 -12 s.

[0767] Similarly, demodulation circuit 1293 can be configured to determine payload data symbols and control symbols based on information about time periods corresponding to different payload data symbols of the communication protocol and information about time periods corresponding to different control symbols of the communication protocol. The information about the different time periods can be as described above for device 1240.

[0768] In some examples, the processing circuit 1292 may also be configured to receive a second data signal that is inverted relative to the data signal 1291. Therefore, the processing circuit 1292 may be configured to further determine at least a first signal edge, a second signal edge, a third signal edge, and a fourth signal edge based on the second data signal. That is, the processing circuit 1292 may determine the signal edges based on differential pairs of the data signal.

[0769] Device 1290, or at least its circuitry, may be configured to also perform the corresponding adaptive changes described above in connection with device 1285 (e.g., adapting to the interchange of control symbol indicator positions and control symbol positions in data signals).

[0770] To summarize some of the above aspects regarding cascade delimiters, by... Figure 12u The flowchart illustrates an example of method 1200u for generating a data signal. Method 1200u includes generating a data signal 1202u. This data signal includes a sequence of first signal edges of a first type, second signal edges of a second type, third signal edges of a first type, and fourth signal edges of a second type. The first and second signal edges are separated by a first time period longer than the time period of any payload data symbol of the communication protocol. The second and third signal edges are separated by a second time period corresponding to a first control symbol of the communication protocol, which indicates the successor of at least one other control symbol of the communication protocol. The third and fourth signal edges are separated by a third time period corresponding to a second control symbol of the communication protocol. Additionally, method 1200u includes outputting a data signal 1204u.

[0771] Optionally, the data signal may also include a fifth signal edge of a second type immediately preceding the first signal edge. The first signal edge and the fifth signal edge are separated by a fourth time period corresponding to the third control symbol of the communication protocol.

[0772] Contact the proposed technology or one or more examples described above (e.g.) Figure 12q Further details and aspects of method 1200u are mentioned. This method may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples described above.

[0773] By Figure 12vThe flowchart illustrates another example of method 1200v for generating a data signal. Method 1200v includes generating a 1202v data signal. This data signal includes a sequence of first signal edges of a first type, second signal edges of a second type, third signal edges of a first type, and fourth signal edges of a second type. The first and second signal edges are separated by a first time period corresponding to a first control symbol of a communication protocol. The second and third signal edges are separated by a second time period corresponding to a second control symbol of the communication protocol, which indicates at least one preceding control symbol of the communication protocol. The third and fourth signal edges are separated by a third time period longer than the time period of any payload data symbol of the communication protocol. Additionally, method 1200v includes outputting a 1204v data signal.

[0774] Optionally, the data signal may also include a fifth signal edge of a second type immediately following the fourth signal edge. The first and fifth signal edges are separated by a fourth time period corresponding to the third control symbol of the communication protocol.

[0775] Contact the proposed technology or one or more examples described above (e.g.) Figure 12r Further details and aspects of method 1200v are mentioned. This method may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples described above.

[0776] By Figure 12w The flowchart illustrates an example of method 1200w for decoding a data signal. Method 1200w includes determining a sequence of first signal edges of a first type, second signal edges of a second type, third signal edges of a first type, and fourth signal edges of a second type in the data signal 1202w. Additionally, method 1200w includes determining a control symbol indicator 1204w if a first time period between the first and second signal edges is longer than a payload data threshold defined in the communication protocol. Method 1200w further includes determining a first control symbol 1206w, indicating a communication protocol successor to at least one additional control symbol, if a second time period between the second and third signal edges corresponds to a predetermined time period defined in the communication protocol. Furthermore, method 1200w includes determining a second control symbol 1208w for the communication protocol based on a third time period between the third and fourth signal edges.

[0777] Optionally, method 1200w may further include determining a fifth signal edge of a first type immediately following a fourth signal edge in the data signal, and determining a third control symbol of the communication protocol 1212w based on a fourth time period between the fourth signal edge and the fifth signal edge.

[0778] Contact the proposed technology or one or more examples described above (e.g.) Figure 12s Further details and aspects of method 1200w are mentioned. This method may include one or more additional optional features corresponding to one or more aspects of the proposed technique or one or more examples described above.

[0779] By Figure 12x The flowchart illustrates another example of method 1200x for decoding data signals. Method 1200x includes determining a sequence of first signal edges of a first type, second signal edges of a second type, third signal edges of a first type, and fourth signal edges of a second type in a 1202x data signal. Additionally, method 1200x includes determining a first control symbol of a communication protocol based on a first time period between the first and second signal edges. Method 1200x further includes determining a second control symbol of a communication protocol, indicating at least one preceding control symbol, if a second time period between the second and third signal edges corresponds to a predetermined time period defined in the communication protocol. Furthermore, method 1200x includes determining a 1208x control symbol indicator if a third time period between the third and fourth signal edges is longer than a payload data threshold defined in the communication protocol.

[0780] Optionally, method 1200w may further include determining a fifth signal edge of a second type immediately preceding the first signal edge in the data signal, and determining a third control symbol of the 1212x communication protocol based on a fourth time period between the fifth signal edge and the first signal edge.

[0781] Contact the proposed technology or one or more examples described above (e.g.) Figure 12t Further details and aspects of method 1200x are mentioned. This method may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples described above.

[0782] Communication interfaces (e.g., according to the STEP protocol) can transmit data for different types of services over a medium. For example, some services may be latency-sensitive, while others may require very low bitrate (BER). The STEP protocol can be, for example, in 1.10... -12 The default BER supports bit rates of several gigabits per second. While this default BER may be sufficient for some services, others may require a better BER.

[0783] Additionally, in some cases, the service may exhibit fairly deterministic behavior (e.g., data is generated at fairly deterministic timing and the data size may have a known length). In other cases, the opposite may be true, where data generation may instead have random instantaneous bandwidth. Furthermore, the bits to be transmitted may in some cases be control or status bits, and are therefore sensitive to latency and / or error rates (e.g., low BER may be required).

[0784] In the following text, contact Figure 13a The apparatus 1300 is described for generating data signal 1301, which enables efficient data transport for different types of services.

[0785] The device 1300 includes a processing circuit 1302 (e.g., DTC) configured to generate a data signal 1301. The processing circuit 1302 generates the data signal 1301 as a sequence including a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type. For example, the first type may be a rising edge and the second type may be a falling edge, or the second type may be a rising edge and the first type may be a falling edge.

[0786] Additionally, device 1300 includes output interface circuit 1303 configured to output data signal 1301 to a transmission link (not shown).

[0787] Processing circuit 1302 generates data signal 1301 such that the first signal edge and the second signal edge are separated by a first time period longer than the time period of any payload data symbol of the c...

Claims

1. An apparatus for generating a data signal, comprising: An input interface circuit, wherein the input interface circuit is used to receive payload data; A processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type, wherein the first signal edge and the second signal edge are separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge are separated by a second time period corresponding to second data to be transmitted, wherein when payload data is received at the input interface, the first time period is determined based on a first payload data symbol of the payload data and the second time period is determined based on a second payload data symbol of the payload data, and when no payload data is received at the input interface, the first time period is determined based on a first predetermined clock cycle time and the second time period is determined based on a second predetermined clock cycle time; as well as An output interface circuit configured to output the data signal.

2. The apparatus of claim 1, wherein the first type is a rising edge and the second type is a falling edge, or wherein the second type is a rising edge and the first type is a falling edge.

3. The apparatus of claim 1, wherein a sum of the first time period and the second time period is less than 10 -7 s.

4. The apparatus of claim 1, wherein the processing circuitry is further configured to generate a second data signal that is out of phase with respect to the data signal.

5. The apparatus of claim 1, wherein the first data is represented by a first data symbol and the second data is represented by a second data symbol, and the first data symbol and the second data symbol are transmitted according to a data communication protocol.

6. The apparatus of claim 1, further comprising at least one digital-to-time converter configured to generate the data signal.

7. The apparatus of claim 1, wherein the output interface circuit is configured to output the data signal to a wired transmission link, the wired transmission link comprising one or more transmission lines.

8. An apparatus for receiving data signals, comprising: A processing circuit configured to determine a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type in the data signal; A demodulation circuit configured to determine first data based on a first time period between the first signal edge and the second signal edge; and to determine second data based on a second time period between the second signal edge and the third signal edge; A detection circuit configured to identify a payload data symbol within the first data or the second data, and to generate a trigger signal when no payload data symbol is identified within the first data or the second data; as well as An oscillator circuit configured to generate a clock signal in response to the trigger signal.

9. The apparatus of claim 8, wherein the first type is a rising edge and the second type is a falling edge, or wherein the second type is a rising edge and the first type is a falling edge.

10. The apparatus of claim 8, wherein a sum of the first time period and the second time period is less than 10 -7 s or 10 -8 s.

11. The apparatus of claim 8, wherein the processing circuitry is further configured to: receive a second data signal, the second data signal being out of phase with respect to the data signal; and further determine the first signal edge, the second signal edge, and the third signal edge based on the second data signal.

12. The apparatus of claim 8, wherein the time interval between the two signal edges corresponds to the data symbol of the communication protocol.

13. The apparatus of claim 8, further comprising at least one time-to-digital converter configured to determine the first time period and the second time period.

14. An apparatus for generating a data signal, comprising processing circuitry configured to generate the data signal, the data signal comprising alternating signal edges of a first type and a second type, wherein a time period between each successive pair of signal edges corresponds to a respective payload data symbol of payload data to be transmitted, wherein a number of time periods per second is higher than 1*10 7 or 1*10 8 wherein, When the payload data is available, the time interval between each successive pair of signal edges is determined based on the corresponding payload data symbols to be transmitted, while when the payload data is unavailable, the time interval between each successive pair of signal edges is determined based on a predetermined clock cycle time.

15. The apparatus of claim 14, wherein the time interval between the two signal edges corresponds to the data symbol of the communication protocol.

16. The apparatus of claim 14 or 15, wherein the data signal is a digital signal transmitted using a wired transmission link.

17. An apparatus for generating a data signal, comprising: The apparatus for generating the data signal includes a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type, wherein the first signal edges and the second signal edges are separated by a first time period corresponding to first data to be transmitted, and the second signal edges and the third signal edges are separated by a second time period corresponding to second data to be transmitted, wherein when payload data is available, the first time period is determined based on a first payload data symbol of the payload data and the second time period is determined based on a second payload data symbol of the payload data, and when payload data is unavailable, the first time period is determined based on a first predetermined clock cycle time and the second time period is determined based on a second predetermined clock cycle time; and the apparatus for outputting the data signal.

18. The apparatus of claim 17, wherein the first type is a rising edge and the second type is a falling edge, or the second type is a rising edge and the first type is a falling edge.

19. An apparatus for receiving data signals, comprising: A means for determining a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of a first type in the data signal; A device for performing the following operations: determining first data based on a first time period between the first signal edge and the second signal edge; and determining second data based on a second time period between the second signal edge and the third signal edge; A device for performing the following operations: identifying a payload data symbol within the first data or the second data, and generating a trigger signal when no payload data symbol is identified within the first data or the second data; as well as A means for generating a clock signal in response to the trigger signal.

20. The apparatus of claim 19, wherein the first type is a rising edge and the second type is a falling edge, or wherein the second type is a rising edge and the first type is a falling edge.

21. An apparatus for generating a data signal, comprising means for generating the data signal, the data signal including alternating signal edges of a first type and a second type, wherein the time interval between each successive pair of signal edges corresponds to a corresponding payload data symbol of payload data to be transmitted, wherein the number of time intervals per second is greater than 1*102. 7 Or 1*10 8 ,in, When payload data is available, the time interval between each successive pair of signal edges is determined based on the corresponding payload data symbols to be transmitted, while when payload data is unavailable, the time interval between each successive pair of signal edges is determined based on a predetermined clock cycle time.

22. An apparatus for generating a data signal, comprising processing circuitry configured to generate the data signal, the data signal including a sequence of first signal edges of a first type, second signal edges of a second type, and third signal edges of a first type, wherein the first signal edges and the second signal edges are separated by a first time period corresponding to first data to be transmitted, and the second signal edges and the third signal edges are separated by a second time period corresponding to second data to be transmitted, wherein... When payload data is available, the first time period is determined based on a first payload data symbol of the payload data and the second time period is determined based on a second payload data symbol of the payload data. When payload data is unavailable, the first time period is determined based on a first predetermined clock cycle time and the second time period is determined based on a second predetermined clock cycle time.

23. The apparatus of claim 22, further comprising an output interface for the data signal.

24. An apparatus for generating a data signal, comprising processing circuitry configured to generate the data signal, wherein the processing circuitry is configured to adjust time intervals between successive signal edges of the data signal based on data portions of payload data to be transmitted, wherein... When payload data is available, the time interval between successive signal edges of the data signal is determined based on the various data portions of the payload data; while when payload data is unavailable, the time interval between successive signal edges of the data signal is determined based on a predetermined clock cycle time.

25. The apparatus of claim 24, further comprising an output interface for the data signal.

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