Non-volatile storage devices and their erasure methods

Abstract

A non-volatile memory device and its erasure method are provided. The non-volatile memory device includes: a memory cell array comprising a plurality of cell strings, each of the plurality of cell strings including a gate-induced drain-leak (GIDL) transistor and a group of memory cells; and control logic for applying a voltage to each of the plurality of cell strings. The control logic performs: a first erase operation, which erases the group of memory cells in each of the plurality of cell strings; a first verification operation, which detects a first erase result of the first erase operation erasing the group of memory cells in each of the plurality of cell strings; and a programming operation, which programs the GIDL transistors in some of the plurality of cell strings.

Description

[0001] Cross-references to related applications

[0002] The entire contents of Korean Patent Application No. 10-2019-0032270, entitled "Nonvolatile Memory Device and Erase Method Thereof", filed with the Korean Intellectual Property Office on March 21, 2019, are incorporated herein by reference. Technical Field

[0003] The embodiments relate to non-volatile memory devices and methods for erasing non-volatile memory devices. More specifically, the embodiments relate to non-volatile memory devices and methods of operating thereof that reduce or suppress the occurrence of deep erase cells. Background Technology

[0004] Semiconductor memory devices can be broadly classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. Non-volatile memory devices can include ROM (Read-Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory, PRAM (Phase-Change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), etc. Recently, with the increasing demand for high integration of memory devices, multi-bit flash memory devices that store multiple bits in a single memory cell have become widespread. Summary of the Invention

[0005] According to some embodiments, a non-volatile memory device includes: a memory cell array comprising a plurality of cell strings, each of the plurality of cell strings including a gate-sensed drain-leak (GIDL) transistor and a group of memory cells; and control logic configured to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation that erases the group of memory cells in each of the plurality of cell strings; a first verification operation that detects a first erase result of the first erase operation erasing the group of memory cells in each of the plurality of cell strings; and a programming operation that programs the GIDL transistors in some of the plurality of cell strings.

[0006] According to some embodiments, a non-volatile memory device includes: a first cell string connected to a first bit line and including a first memory cell group and a first gate-sensed drain-leak (GIDL) transistor; and control logic configured to apply a voltage to the first bit line. The control logic performs a programming operation to program the first GIDL transistor and an erasure operation to erase the first memory cell group using the programmed first GIDL transistor.

[0007] According to some embodiments, a non-volatile memory device includes: a first cell string connected to a first bit line and including a first memory cell group and a first gate-sensed drain-leak (GIDL) transistor; a second cell string connected to a second bit line and including a second memory cell group and a second GIDL transistor; and control logic configured to apply voltages to the first bit line and the second bit line. The control logic programs the second GIDL transistor at a first level, programs the first GIDL transistor at a second level greater than the first level, and erases the first memory cell group and the second memory cell group using the first GIDL transistor and the second GIDL transistor. Attached Figure Description

[0008] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 A storage system according to some embodiments is shown.

[0010] Figure 2 It shows Figure 1 Storage devices of the storage system.

[0011] Figure 3 It shows Figure 2 A perspective view of the storage blocks of the storage cell array.

[0012] Figure 4 It shows Figure 3 The circuit diagram of the memory block.

[0013] Figure 5 It shows the connection to Figure 4 A circuit diagram of a string of cells for a single string selection line in a memory block.

[0014] Figure 6 It shows that it includes Figure 5 A unit string within a unit string.

[0015] Figure 7It shows that it includes Figure 6 GIDL transistors in the unit string.

[0016] Figure 8a It shows Figure 7 The operation of GIDL transistors.

[0017] Figure 8b It shows Figure 8a A magnified view of region A.

[0018] Figure 9a and Figure 9b This is a diagram showing the threshold voltage to illustrate... Figure 2 Erasure operation of storage devices.

[0019] Figure 10 It is used to show by Figure 2 A diagram illustrating the beneficial effects of erasure operations performed on storage devices.

[0020] Figure 11 One side of a memory block in a memory cell array of a memory device according to some embodiments is shown.

[0021] Figure 12 A flowchart illustrating an erasure method for a storage device according to some embodiments is shown.

[0022] Figure 13 A flowchart illustrating an erasure method for a storage device according to some embodiments is shown. Detailed Implementation

[0023] Figure 1 A storage system according to some embodiments is illustrated. (Refer to...) Figure 1 The storage system may include a storage controller 10 and a non-volatile storage device 20.

[0024] The memory controller 10 can control the operation of the non-volatile memory device 20. Specifically, the memory controller 10 can provide commands CMD, addresses ADDR, and control signals CTRL along the input / output lines connected to the non-volatile memory device 20. In addition, the memory controller 10 can provide or receive data DATA along the input / output lines connected to the non-volatile memory device 20.

[0025] The CMD commands provided by the storage controller 10 to the non-volatile storage device 100 may include read, write, erase, etc.

[0026] The non-volatile storage device 20 can store or provide stored data based on the address ADDR, command CMD, and control signal CTRL provided from the storage controller 10.

[0027] The non-volatile memory device 20 may include, for example, NAND flash memory, vertical NAND flash memory (VNAND), NOR flash memory, resistive RAM (RRAM), phase-change memory (RRAM), magnetoresistive memory (MRAM), ferroelectric memory (FRAM), spin-injected magnetization inversion memory (STT-RAM), etc. In the following description, embodiments will be illustrated by using a vertical NAND flash memory (VNAND) as an example of the non-volatile memory device 20, but this can be applied to other types of memory.

[0028] Figure 2 It shows Figure 1 Storage devices in a storage system. (Refer to...) Figure 1 and Figure 2 The non-volatile storage device 20 may include a voltage generator 110, a row decoder 120, a data input / output (I / O) circuit 130, a page buffer circuit 140, control logic 150, and a memory cell array 160.

[0029] Voltage generator 110 can use the power supply voltage to generate the operating voltage required for the operation of non-volatile memory device 20. The operating voltage may include, for example, programming voltage, disable voltage, read voltage, read skip voltage, bit line voltage, common source line voltage, and various combinations thereof.

[0030] Row decoder 120 can be connected to memory cell array 160 via gate-sensed drain-leak (GIDL) line GL, serial select line SSL, word line WL, ground select line GSL, and common source line CSL. Row decoder 120 can receive operation signals from control logic 150. Row decoder 120 can operate in response to operation signals received from control logic.

[0031] Data input / output circuitry 130 can be connected to control logic 150. Data input / output circuitry 130 can perform operations, such as inputs and outputs, based on operation signals from control logic 150. Data input / output circuitry 130 can provide address ADDR, command CMD, control signal CTRL, etc., received from memory controller 10 to control logic 150.

[0032] The data input / output circuit 130 can provide input data to the page buffer circuit 140 via the data line DL. The data input / output circuit 130 can output the data DATA received from the page buffer circuit 140 to the outside.

[0033] Page buffer circuit 140 can receive operation signals from control logic 150. Page buffer circuit 140 can perform operations such as erasing, verification, and programming based on the operation signals from control logic 150.

[0034] Page buffer circuit 140 can be connected to memory cell array 160 via bit line BL. During an erase operation, page buffer circuit 140 can provide the same voltage to each bit line BL. During a verification operation, page buffer circuit 140 can apply a read voltage to bit line BL to detect the erase result of the memory cell. During a programming operation, page buffer circuit 140 can apply a programming voltage or a disable voltage to bit line BL to program the memory cell connected to the bit line BL to which the programming voltage is applied.

[0035] Control logic 150 can generate operation signals, such as erase, verify, and program, based on commands CMD or control signals CTRL from memory controller 10. Control logic 150 can provide the generated operation signals to voltage generator 110, row decoder 120, page buffer circuit 140, or data input / output circuit 130.

[0036] The following will refer to Figures 2 to 4 Describes storage cell array 160. Figure 3 It shows Figure 2 A perspective view of the storage blocks of the storage cell array. Figure 4 It shows Figure 3 The circuit diagram of the memory block.

[0037] Reference Figure 2 The memory cell array 160 can be connected to the row decoder 120 via the GIDL line GL, the serial select line SSL, the word line WL, the ground select line GSL, and the common source line CSL. The memory cell array 160 can be connected to the page buffer circuit 140 via the bit line BL.

[0038] The memory cell array 160 may include multiple memory blocks BLK1 to BLKa. Each of the multiple memory blocks BLK1 to BLKa can be connected to the row decoder 120 via the GIDL line GL, multiple word lines WL, at least one serial select line SSL, at least one ground select line GSL, and a common source line CSL. Additionally, each of the multiple memory blocks BLK1 to BLKa can be connected to the page buffer circuit 140 via multiple bit lines BL.

[0039] Reference Figure 3 Each of the multiple memory blocks BLK1 to BLKa may include a substrate SUB, a ground select line GSL, multiple word lines WL1 to WL7, a serial select line SSL, a GIDL line GL, and multiple bit lines BL.

[0040] The ground select line GSL, multiple word lines WL1 to WL7, the serial select line SSL, and the GIDL line GL can extend on the substrate SUB along the first direction X. Additionally, multiple bit lines BL can extend on the substrate SUB along the second direction Y.

[0041] Ground select line GSL, multiple word lines WL1 to WL7, serial select line SSL, GIDL line GL, and multiple bit lines BL can be stacked sequentially on substrate SUB along the third direction Z.

[0042] Reference Figure 4 The storage block includes multiple cell strings NS11 to NS33 arranged along a first direction X and a second direction Y. Each of the multiple cell strings NS11 to NS33 may include a GIDL transistor GT, a string select transistor SST, multiple storage cells MC1 to MC7, and a ground select transistor GST. The GIDL transistor GT, the string select transistor SST, the multiple storage cells MC1 to MC7, and the ground select transistor GST may be connected in series along a third direction.

[0043] exist Figure 4 In the diagram, the number of cell strings, bit lines, string select lines, and ground select lines included in the memory block are shown as 9, 3, 3, and 3, respectively. However, this is only for ease of description.

[0044] Multiple unit strings NS11 to NS33 can be connected to one of the multiple bit lines BL1 to BL3 extending along the second direction Y. For example, the first unit string NS11, the fourth unit string NS21, and the seventh unit string NS31 can be connected to the first bit line BL1. The second unit string NS12, the fifth unit string NS22, and the eighth unit string NS32 can be connected to the second bit line BL2. The third unit string NS13, the sixth unit string NS23, and the ninth unit string NS33 can be connected to the third bit line BL3.

[0045] In some embodiments, multiple bit lines BL1 to BL3 can be connected to the GIDL transistor GT of the corresponding cell string in multiple cell strings NS11 to NS33. Figure 4 In this diagram, multiple bit lines BL are shown connected to the GIDL transistor GT. In one embodiment, the GIDL transistor GT can be located below the ground select transistor GST. In this case, multiple bit lines BL can be connected to the series select transistor SST.

[0046] Refer again Figure 2 and Figure 4 The page buffer circuit 140 can apply voltage to each of the multiple bit lines BL. For example, during a programming operation, the page buffer circuit 140 can apply a programming voltage to the first bit line BL1 and can apply a disable voltage to the second bit line BL2 and the third bit line BL3.

[0047] The GIDL transistor GT of each of the multiple unit strings NS11 to NS33 can be connected to the GIDL line. Figure 4In the diagram, the GIDL transistor GT of each of the multiple cell strings NS11 to NS33 is shown connected to a GIDL line GL.

[0048] The GIDL transistor GT can be used for an erase operation to erase at least some of the memory cells MC1 to MC7. For example, the GIDL transistor GT can generate a voltage for erasing at least some of the memory cells MC1 to MC7 based on the voltage difference applied to bit line BL and GIDL line GL.

[0049] The string selection transistor SST of each of the multiple unit strings NS11 to NS33 can be connected to one of the multiple string selection lines SSL1 to SSL3 extending along the first direction X. For example, the string selection transistor SST of the first unit string NS11, the second unit string NS12, and the third unit string NS13 can be connected to the first string selection line SSL1. The string selection transistor SST of the fourth unit string NS21, the fifth unit string NS22, and the sixth unit string NS23 can be connected to the second string selection line SSL2, and the string selection transistor SST of the seventh unit string NS31, the eighth unit string NS32, and the ninth unit string NS33 can be connected to the third string selection line SSL3.

[0050] Refer again Figure 2 and Figure 4 The line decoder 120 can select some of the multiple string select lines SSL1 to SSL3. For example, the line decoder 120 can apply a select voltage to the first string select line SSL1 and can apply a non-select voltage to the second and third string select lines SSL.

[0051] At this time, the string selection transistors SST connected to the first string selection line SSL1 in the first unit string NS11, the second unit string NS12, and the third unit string NS13 can be activated. On the other hand, the string selection transistors SST connected to the second and third string selection lines SSL in the fourth unit string NS21 to the ninth unit string NS33 can be deactivated.

[0052] Multiple unit strings NS11 to NS33 can be arranged in multiple rows and columns by connecting to multiple bit lines BL and multiple string select lines SSL. For example, the first unit string NS11, the fourth unit string NS21, and the seventh unit string NS31 connected to the first bit line BL1 can be arranged in a single column along the second direction Y. The first unit string NS11, the second unit string NS12, and the third unit string NS13 connected to the first string select line SSL1 can be arranged in a single row along the first direction X.

[0053] Each of the multiple unit strings NS11 to NS33 has multiple storage units MC1 to MC7 that can be connected to multiple word lines WL. For example, the first storage unit MC1 of the multiple unit strings NS11 to NS33 can be connected to a single first word line WL1. Similarly, the second storage units MC2 to the seventh storage unit MC7 of the storage block can be connected to the second word line WL2 to the seventh word line WL7, respectively. All of the multiple storage units MC1 to MC7 can be used to store data. In some embodiments, all of the multiple storage units MC1 to MC7 can be used to store multiple bits of data.

[0054] The ground selection transistor GST of each of the multiple cell strings NS11 to NS33 can be connected to the common source line CSL. Additionally, the ground selection transistor GST of the multiple cell strings NS11 to NS33 can be connected to one of the multiple ground selection lines GSL1 to GSL3 extending along a first direction. For example, the ground selection transistor GST of the first cell string NS11, the second cell string NS12, and the third cell string NS13 can be connected to the first ground selection line GSL1.

[0055] Refer again Figure 2 and Figure 4 The row decoder 120 can select some of the multiple ground selection lines GSL1 to GSL3. For example, the row decoder 120 can apply a selection voltage to the first ground selection line GSL1 and a non-selection voltage to the second ground selection line GSL2 and the third ground selection line GSL3.

[0056] Reference Figures 2 to 7 The description includes the cell string in the storage cell array 160. Figure 5 It shows the connection to Figure 4 A circuit diagram of a string of cells for a single string selection line in a memory block. Figure 6 It shows Figure 5 A unit string within a unit string.

[0057] Reference Figure 4 and Figure 5 The storage block may include multiple unit strings NS11 to NS1n connected to the first selection line SSL1. Although Figure 5 Only the multiple unit strings NS11 to NS1n connected to the first string select line SSL1 are shown, but the multiple unit strings connected to the other string select lines are similar.

[0058] Reference Figure 5Multiple cell strings NS11 to NS1n can be connected to multiple bit lines BL1 to BLn respectively. The GIDL transistor GT of each cell string NS11 to NS1n can be connected to the GIDL line GL. The string select transistor SST of each cell string NS11 to NS1n can be connected to the first string select line SSL1. Multiple memory cells MC1 to MC7 of each cell string NS11 to NS1n can be connected to the corresponding word line WL among multiple word lines WL. The ground select transistor GST of each cell string NS11 to NS1n can be connected to the first ground select line GSL1.

[0059] Multiple unit strings NS11 to NS1n may each include a group of storage cells having at least one storage cell. For example, the first unit string NS11 may include a first storage cell group MCG1a having five storage cells MC1 to MC5. Additionally, the second unit strings NS12 to the nth unit string NS1n may each include a first storage cell group MCG2a to MCGna, each having five storage cells MC1 to MC5. As another example, the first unit string NS11 may include a first storage cell group MCG1a having five storage cells MC1 to MC5 and a second storage cell group MCG1b having two storage cells MC6 and MC7. Furthermore, the second unit strings NS12 to the nth unit string NS1n may each include a first storage cell group MCG2a to MCGna, each having five storage cells MC1 to MC5, and a second storage cell group MCG2b to MCGnb, each having two storage cells MC6 and MC7.

[0060] exist Figure 5 In the example, although the first unit string NS11 to the nth unit string NS1n are shown as including a group of storage cells with five storage cells and a group of storage cells with two storage cells respectively, any number of storage cell groups and any number of storage cells in a group of storage cells can be used.

[0061] Reference Figure 6 The first unit string NS11 may include a substrate SUB, a common source line CSL, a gate electrode 161, an insulating layer 162, a charge trapping layer 163, a core wire 164, a core layer 165, and a series drain 166.

[0062] The common source line (CSL) is formed on the substrate (SUB) and can be connected to adjacent cell strings.

[0063] Gate electrode 161 and insulating layer 162 may be alternately stacked on substrate SUB. The stacked gate electrode 161 may be used as ground select line GSL, multiple word line WL, serial select line SSL, and GIDL line GL. In the following text, for ease of description, gate electrode 161 may be referred to as ground select line GSL, multiple word line WL, serial select line SSL, and GIDL line GL, respectively.

[0064] The charge trapping layer 163 can be located between the gate electrode 161 and the insulating layer 162, and between the gate electrode 161 and the core wire 164. Although Figure 6 The charge trapping layer 163 is shown to include a single membrane, but this is for ease of description, and the charge trapping layer 163 may include multiple layers.

[0065] The charge trapping layer 163 can store introduced electrons. For example, electrons present in the core wire 164 can flow into the charge trapping layer 163 through tunneling effects, etc. The electrons introduced into the charge trapping layer 163 can be fixed to the charge trapping layer 163. The electrons introduced into the charge trapping layer 163 will not move along the charge trapping layer 163. For example, the first portion of the charge trapping layer 163 formed between the first word line WL and the core wire 164 may include introduced electrons. In this case, the second portion of the charge trapping layer 163 formed between the second word line WL and the core wire 164 may not include electrons.

[0066] The number of electrons stored in the charge trapping layer 163 can be represented as an electron level. For example, a first portion of the charge trapping layer 163 can be programmed to have a first electron level. Alternatively, a second portion of the charge trapping layer 163 can be programmed to have a second electron level different from the first electron level.

[0067] Core wire 164 can be connected to bit line BL via series drain 166. Core wire 164 can be connected to common source line CSL via substrate SUB.

[0068] The ground selection line GSL can be used as the gate of the ground selection transistor GST. For example, the ground selection line GSL, the portion of the charge trapping layer 163 located between the ground selection line GSL and the core line 164, and the portion of the core line 164 at the same height as the ground selection line GSL can form the ground selection transistor GST.

[0069] Similarly, each word line in the multiple word lines WL can be used as the gate of each of the multiple memory cells MC1 to MC7. The string select line SSL and the GIDL line GL can also be used as the gate of the string select transistor SST and the gate of the GIDL transistor, respectively.

[0070] The core wire 164 may be located between the series drain 166 and the substrate SUB, and may surround the core layer 165. That is, the core wire 164 may be a trench filled with the core layer 165. The core layer 165 may include an insulating material. For example, the core layer 165 may include silicon oxide.

[0071] Core wire 164 can be used as a channel through which current flows between the series drain 166 and the common source line CSL. For example, core wire 164 can be controlled by voltages applied to the ground select line GSL, multiple word lines WL, series select line SSL, and GIDL line GL located between the common source line CSL and the series drain 166.

[0072] For example, when performing a read operation on the first memory cell MC1, a bit line read voltage can be applied to the first bit line BL1. A select voltage can be applied to the GIDL line GL, the serial select line SSL, and the ground select line GSL. A read skip voltage can be applied to the second through seventh word lines WL. A word line read voltage can be applied to the first word line WL. A source voltage (e.g., 0V) can be applied to the common source line CSL. At this time, all the remaining transistors except the first memory cell MC1 can be activated.

[0073] When the first memory cell MC1 is not programmed, it can be activated by the word line read voltage. When the first memory cell MC1 is programmed, it will not be activated by the word line read voltage.

[0074] In this way, core wire 164 can be activated only when the first memory cell MC1 is not programmed. Therefore, the first memory cell MC1 can be read by the presence or absence of activation of core wire 164.

[0075] The following will refer to Figure 5 , Figure 6 , Figure 7 , Figure 8a and Figure 8b Describe the operation of GIDL transistors included in the cell string. Figure 7 It shows that it includes Figure 6 GIDL transistors in the unit string. Figure 8a It shows Figure 7 The operation of GIDL transistors. Figure 8b yes Figure 8a A magnified view of region A.

[0076] exist Figure 7 In this configuration, the GIDL transistor GT can be formed as a portion of a gate electrode 161, a charge trapping layer 163, and a core wire 164. The core wire 164 can be connected to a series drain 166 and a common source line CSL. The gate electrode 161 of the GIDL transistor GT can be... Figure 6 It is part of the GIDL line GL. The charge trapping layer 163 may include a first silicon oxide layer 163b, a silicon nitride layer 163a, and a second silicon oxide layer 163c stacked sequentially.

[0077] The silicon nitride layer 163a may include introduced electrons. The first silicon oxide layer 163b may block the emission of electrons introduced into the silicon nitride layer 163a to the core wire 164. The second silicon oxide layer 163c may block the emission of electrons introduced into the silicon nitride layer 163a to the gate electrode 161.

[0078] exist Figure 7 For ease of illustration, the GIDL transistor GT is shown as including a drain D and a source S formed on the core wire 164. In one embodiment, in Figure 7 The drain D and source S shown in the figure can be in Figure 6 The series drain 166 and common source line CSL are shown in the figure. That is, the drain D and source S may not be formed on the core line 164.

[0079] The GIDL transistor GT can be programmed to have a predetermined electron level. For example, electrons at the predetermined electron level can flow into the charge trapping layer 163 of the GIDL transistor, and the charge trapping layer 163 of the GIDL transistor can store the incoming electrons.

[0080] Reference Figure 8a and Figure 8b The GIDL transistor GT can generate a gate-induced drain leakage current, i.e., a GIDL current. The GIDL current can be generated by the difference between the gate voltage VG applied to the gate electrode 161 and the drain voltage VD applied to the drain electrode. For example, a GIDL current can be generated when the gate voltage VG is less than the drain voltage VD.

[0081] When the gate voltage VG is less than the drain voltage VD, the defect region formed in the drain D can be reduced. For example, when the gate voltage VG is less than the drain voltage VD, the defect region of the drain D' can be smaller than the defect region of the drain D in other cases.

[0082] When the defect region of the drain D decreases, hole-electron pairs can be generated. These pairs can then separate into holes and electrons. The separated electrons can be discharged through the drain D to the outside of the GIDL transistor GT (e.g., a bit line).

[0083] The separated holes flow into core wire 164. The number of holes flowing into core wire 164 can be represented as a hole level. For example, core wire 164 can include a predetermined hole level. The holes included in core wire 164 can form a core wire voltage.

[0084] The number of holes generated by the GIDL transistor GT can be determined by the number of electrons contained in the charge trapping layer 163 of the GIDL transistor GT. For example, if the GIDL transistor GT is programmed at a first electron level, the number of holes generated by the GIDL transistor GT can be determined by the gate voltage VG, the drain voltage, and the voltage formed by the electrons at the first electron level of the charge trapping layer 163. Specifically, when the GIDL transistor GT is programmed at a higher electron level, the number of holes generated in the GIDL transistor GT increases. In this way, by programming the GIDL transistor GT, the amplitude of the core voltage of the core wire 164 increases.

[0085] Multiple memory cells MC1 to MC7 included in the cell string may be affected by the core line voltage generated by the GIDL transistor GT. For example, some of the memory cells MC1 to MC7 can be erased by the difference between the word line erase voltage applied to at least some of the word lines WL and the core line voltage of the core line 164. For example, due to the difference between the word line erase voltage and the core line voltage, electrons included in the charge trapping layer 163 of the first memory cell group MCG1a can be discharged to the core line 164.

[0086] Refer again Figure 2 and Figure 5 When control logic 150 receives an erase command, it can perform an erase operation on at least one of the multiple memory blocks in memory cell array 160. For example, control logic 150 can perform erase, verification, GIDL programming, and GIDL recovery operations on some memory blocks in memory cell array 160.

[0087] Control logic 150 may include a GIDL programming controller 154. The GIDL programming controller 154 may execute GIDL programming operations and GIDL recovery operations included in an erase cycle. For example, the GIDL programming controller 154 may perform erase operations, verification operations, GIDL programming operations, and GIDL recovery operations on some memory blocks of the memory cell array 160.

[0088] exist Figure 5 In this configuration, multiple storage cells MC1 to MC7 may include a first storage cell region MCR1 and a second storage cell region MCR2. For example, the first storage cell region may include a first storage cell group MCG1a to MCGna. The second storage cell region may include a second storage cell group MCG1b to MCGnb.

[0089] In some embodiments, the erase operation may include a first erase operation of a first storage cell region MCR1 and a second erase operation of a second storage cell region MCR2 among a plurality of storage cells MC1 to MC7. For example, after the first erase operation of the first storage cell region MCR1 is completed, the erase operation may perform the second erase operation of the second storage cell region MCR2.

[0090] An erase operation may include multiple erase cycles. For example, an erase operation may include a first erase cycle and a second erase cycle. The first erase cycle may include an erase operation, a verification operation, and a GIDL programming operation. The second erase cycle may include an erase operation, a verification operation, and a GIDL recovery operation.

[0091] An erase operation can restore multiple memory cells MC1 to MC7 included in each of the multiple cell strings NS11 to NS33 to their state before being programmed. For example, when an erase operation is performed, electrons stored in the charge trapping layer 163 can be emitted to the core wire 164. At this time, the electron level in the charge trapping layer 163 of the memory cell MC is reduced.

[0092] In an erase operation according to some embodiments, the same bit-line erase voltage (e.g., 18V) can be applied to each of the multiple bit lines BL. In some embodiments, non-volatile memory devices can save resources by applying the same voltage to each of the multiple bit lines BL during an erase operation. This is because applying a different erase voltage to each bit line during an erase operation requires additional resources.

[0093] During the erase operation, a GIDL line voltage (e.g., 10V) less than the bit line erase voltage can be applied to the GIDL line GL. If the GIDL line voltage (e.g., 10V) is less than the bit line voltage (e.g., 18V) connected to the drain D of the GIDL transistor GT, the GIDL transistor GT can generate holes. The holes generated by the GIDL transistor GT can be applied to the core line 164, thereby forming the core line voltage.

[0094] During the erase operation, a word line erase voltage (e.g., 0.6V) less than the core line voltage formed by the GIDL transistor GT can be applied to the word line WL, which is connected to multiple cell strings NS11 to NS33. Due to the difference between the word line erase voltage and the core line voltage, multiple memory cells MC1 to MC7, including those in the multiple cell strings NS11 to NS33, can be erased.

[0095] In some embodiments, the erase operation may erase only some of the memory cells MC1 to MC7. For example, the erase operation may erase the first memory cell region MCR1, but may not erase the second memory cell region MCR2. In this case, an erase voltage (e.g., 0.6V) may be applied to the word line WL connected to the first memory cell region MCR1. Alternatively, an erase skip voltage (e.g., 12V) may be applied to the word line WL connected to the second memory cell region MCR2.

[0096] The verification operation can detect the erase results of multiple memory cells MC1 to MC7 included in each of the multiple cell strings NS11 to NS33.

[0097] The erasure result can be determined by the electron level contained in the charge trapping layer 163 of the memory cell. If the electron level contained in the charge trapping layer 163 of the memory cell is less than a predetermined verification electron level, the erasure can be considered complete.

[0098] The threshold voltage of a memory cell can be determined by the electron level in the charge trapping layer 163 contained in the memory cell MC. Therefore, when the threshold voltage of the memory cell is less than a predetermined verification voltage, the erasure result can be determined as erasure complete.

[0099] When performing a verification operation, the page buffer circuit 140 can receive the erase results of the memory cells MC included in each of the multiple cell strings NS11 to NS33 via the bit line BL.

[0100] As an example, if the erasure of multiple memory cells MC1 to MC7 included in the first cell string NS11 is completed, the page buffer circuit 140 can receive an erase success (PASS) signal through the first bit line BL1.

[0101] As another example, when the erasure of at least one of the multiple memory cells MC1 to MC7 included in the first cell string NS11 is not completed, the page buffer circuit 140 can receive an erase failure (FAIL) signal through the first bit line BL1.

[0102] During the verification operation, a verification voltage (e.g., 0.5V) can be applied to multiple word lines WL of multiple memory cells MC1 to MC7 connected to multiple cell strings NS11 to NS33.

[0103] In some embodiments, the verification operation may verify only the erased memory cells among a plurality of memory cells MC1 to MC7. For example, the verification operation may verify the erased first memory cell region MCR1, but may not verify the unerased second memory cell region MCR2. In this case, a verification voltage (e.g., 0.5V) may be applied to the word line WL connected to the first memory cell region MCR1. Alternatively, a verification skip voltage (e.g., 6V) may be applied to the word line WL connected to the second memory cell region MCR2.

[0104] GIDL programming operations can program GIDL transistors in some of the multiple cell strings NS11 to NS33. For example, a programming voltage can be applied to the first bit line BL1 to program the GIDL transistors in the first cell string NS11, and an inhibit voltage can be applied to the remaining bit lines BL to prevent programming of the GIDL transistors GT in the remaining cell strings.

[0105] When a GIDL programming operation is performed, the charge trapping layer 163 of the GIDL transistors GT in some of the multiple cell strings NS11 to NS33 may have an increased electron level. When the first erase cycle is repeated, a higher erase voltage can be applied to the cell string by programming the GIDL transistors GT of the cell string that includes the unerased memory cells MC.

[0106] The programming level of a GIDL transistor GT can be represented by a voltage level. For example, the voltage level of a programmed GIDL transistor GT will increase. Furthermore, when a GIDL transistor GT is programmed at a high voltage level, the electron level contained in the charge trapping layer of the GIDL transistor GT is high.

[0107] When the first erase cycle is repeated, each GIDL transistor GT in some of the multiple cell strings can be programmed at different voltage levels. For example, the GIDL transistor GT of the first cell string NS11 can be programmed at a first voltage level. The GIDL transistor GT of the second cell string NS12 can be programmed at a second voltage level lower than the first voltage level. In this case, the first and second voltage levels can be determined based on the number of times each GIDL transistor is programmed.

[0108] GIDL programming operations can program GIDL transistors GT included in some of the multiple cell strings NS11 to NS33 based on the erase result detected by the verification operation (also known as the erase result of the verification operation). For example, the GIDL programming operation can program GIDL transistors GT included in the first cell string NS11 that are determined to have not been erased completely. At the same time, the GIDL programming operation may not perform programming on GIDL transistors GT included in the second cell string NS12 that are determined to have been erased completely.

[0109] According to some embodiments, the GIDL programming operation can program the GIDL transistor GT of the first cell string NS11, and may not program the GIDL transistor GT of the second cell string NS12. In this case, a programming voltage (e.g., 0V) can be applied to the first bit line BL1 connected to the first cell string NS11. Alternatively, a disable voltage (e.g., 2V) different from the programming voltage can be applied to the second bit line BL1 connected to the second cell string NS12. In one embodiment, the programming voltage may be less than the disable voltage. In this case, during the GIDL programming operation, a GIDL programming voltage (e.g., 18V) may also be applied to the GIDL lines connected to the plurality of cell strings NS11 to NS33.

[0110] The GIDL recovery operation can restore all GIDL transistors included in multiple cell strings NS11 to NS33. For example, the GIDL programming controller 154 can apply a GIDL erase voltage to each bit line in multiple bit lines BL to restore all GIDL transistors GT included in multiple cell strings NS11 to NS33 to their state before being programmed.

[0111] When a GIDL recovery operation is performed, electrons stored in the charge trapping layer 163 of all GIDL transistors GT in multiple cell strings NS11 to NS33 can be discharged to the core wire 164.

[0112] In some embodiments, the GIDL recovery operation can set the charge trapping layer 163 of all GIDL transistors GT to the initial electron level. That is, the GIDL recovery operation can restore the electron level of the GIDL transistors GT, which has been increased by the first erase cycle, to its initial value.

[0113] The verification operation determines which erase cycle, either the first or the second, should be executed. For example, if all memory cells to be verified have been erased, the erase result can be "PASS". If the erasure of at least one of the memory cells to be verified has not been completed, the erase result can be "FAIL".

[0114] If the erase operation fails (FAIL), a GIDL programming operation can be performed after the verification operation. At this point, the GIDL programming operation can program the GIDL transistors included in the cell string where the erase was incomplete.

[0115] If the erase operation is successful (PASS), a GIDL recovery operation can be performed after the verification operation. At this point, the GIDL transistors included in all cell strings can be restored to their state before they were programmed.

[0116] An erase operation can include multiple first erase cycles and a single second erase cycle. For example, a first erase cycle can be executed repeatedly until the erase result is successful (PASS). If the erase result is successful (PASS), a second erase cycle can be executed once to complete the erase operation.

[0117] The following will refer to Figure 2 , Figure 5 , Figure 9a and Figure 9b Specifically, the erase operation performed by control logic 150 and GIDL programming controller 154 is described. Figure 9a and Figure 9b This is a diagram showing the threshold voltage to illustrate... Figure 2 Erasing operations on storage devices. For reference, Figure 9a and Figure 9b It shows Figure 5 A diagram showing the GIDL transistor GT of the first unit string NS11 and the second unit string NS12, and the threshold voltage V_th of one of the multiple memory cells MC.

[0118] exist Figure 9a and Figure 9b In this configuration, the threshold voltages of the GIDL transistors GT in the first cell string NS11 and the second cell string NS12, and the memory cell MC, can be determined by the electron level in the charge trapping layer of each transistor. For example, if the GIDL transistor GT has a high electron level, the gate voltage used to activate the GIDL transistor GT can increase the voltage generated by the electrons in the charge trapping layer of the GIDL transistor GT. The same applies to the memory cell MC.

[0119] Reference Figure 9a The first erase loop LOOP1 can include erase operations, verification operations, and GIDL programming operations.

[0120] During the erase operation, the GIDL transistor GT in each of the first unit string NS11 and the second unit string NS12 can have threshold voltages V_GT1 and V_GT2, respectively. At this time, the threshold voltages V_GT1 and V_GT2 can refer to the unprogrammed threshold voltages.

[0121] During the erase operation, the memory cell MC of each cell string in the first cell string NS11 and the second cell string NS12 can be erased. For example, the threshold voltage of the memory cell MC of the first cell string NS11 can be V_MC1, which is greater than the verification voltage. Conversely, the threshold voltage of the memory cell MC of the second cell string NS12 can be V_MC2, which is less than the verification voltage.

[0122] During the verification operation, the threshold voltage of the GIDL transistor GT in each of the first and second cell strings NS11 and NS12 remains unchanged. The erase result of the memory cell MC in each of the first and second cell strings NS11 and NS12 can be detected during the verification operation.

[0123] For example, the threshold voltage V_MC1 of the memory cell MC in the first cell string NS11 can be greater than the verification voltage V_verify. That is, the memory cell MC in the first cell string NS11 can be determined to have been erased incompletely.

[0124] Furthermore, the threshold voltage V_MC2 of the memory cell MC in the second cell string NS12 can be less than the verification voltage V_verify. That is, the memory cell MC in the second cell string NS12 can be determined to have been erased.

[0125] The verification operation can determine that the erasure of at least one memory cell MC in each of the first and second cell strings was incomplete. Therefore, the erasure result of the verification operation can be determined as a failure (FAIL).

[0126] In GIDL programming operations, the GIDL transistors of the first unit string NS11 can be programmed. For example, the threshold voltage of the GIDL transistors of the first unit string NS11 can be changed from V_GT1 to V_GT1'.

[0127] In GIDL programming operations, the GIDL transistors in the second unit string NS12 do not need to be programmed. For example, the threshold voltage of the GIDL transistors in the second unit string NS12 can be maintained at V_GT2.

[0128] Reference Figure 9b The second erase cycle LOOP2 can include erase operations, verification operations, and GIDL recovery operations.

[0129] During the erase operation, the GIDL transistor GT of each cell string in the first cell string NS11 and the second cell string NS12 can have threshold voltages V_GT1' and V_GT2, respectively. During the erase operation, the memory cell MC of each cell string in the first cell string NS11 and the second cell string NS12 can be erased.

[0130] For example, the memory cell MC of the first cell string NS11 can be erased at a voltage higher than the erase voltage in the first erase cycle LOOP1. Therefore, the threshold voltage of the memory cell MC of the first cell string NS11 can be changed to be less than the verification voltage V_MC1'.

[0131] The memory cells MC of the second cell string NS12 can be erased using the same voltage as the erase voltage in the first erase cycle LOOP1. Therefore, the threshold voltage of the memory cells MC of the second cell string NS12 can be maintained at V_MC2.

[0132] In addition, for ease of explanation, Figure 9b This illustrates a scenario where the threshold voltage of the memory cell MC in the second cell string NS12 does not change due to the erase operation. In one embodiment, the threshold voltage of the memory cell MC in the second cell string NS12 can be further reduced when the erase operation of the second erase cycle is performed.

[0133] During the verification operation, the threshold voltage of the GIDL transistor GT in each of the first and second cell strings NS11 and NS12 remains unchanged. The erase result of the memory cell MC in each of the first and second cell strings NS11 and NS12 can be detected during the verification operation.

[0134] For example, the threshold voltage V_MC1' of the memory cell MC in the first cell string NS11 can be less than the verification voltage V_verify. That is, the memory cell MC in the first cell string NS11 can be determined to have been erased.

[0135] Furthermore, the threshold voltage V_MC2 of the memory cell MC in the second cell string NS12 can be less than the verification voltage V_verify. That is, the memory cell MC in the second cell string NS12 can be determined to have been erased.

[0136] All memory cells (MC) in each of the first unit string NS11 and the second unit string NS12 can be determined to have been erased through a verification operation. Therefore, the erase result of the verification operation can be determined as successful (PASS).

[0137] In the GIDL recovery operation, the GIDL transistors GT of the first unit string NS11 and the second unit string NS12 can be restored to their state before being programmed. For example, the threshold voltage of the GIDL transistor in the first unit string NS11 can be changed from V_GT1' back to V_GT1.

[0138] In the following text, reference will be made to Figure 2 , Figure 9a , Figure 9b and Figure 10 Describe the effects of a non-volatile storage system according to some embodiments. Figure 10 It shows the result of Figure 2 The effect of an erase operation performed on a storage device. For reference, Figure 10 The threshold voltage distribution of multiple memory cells is shown, as detected by the verification operations of the first erase cycle LOOP1 and the second erase cycle LOOP2.

[0139] Reference Figure 10 In the verification operation of the first erase cycle LOOP1, the memory cells of multiple cell strings included in a specific memory block of the memory cell array 160 may have a first distributed threshold voltage. For example, the multiple cell strings may include a first cell string group NSG1 and a second cell string group NSG2.

[0140] The threshold voltage of the memory cell in the first cell group NSG1 can be less than the verification voltage V_verify. The first cell group NSG1 can be determined to have been erased.

[0141] The threshold voltage of the memory cells in the second cell group NSG2 can be greater than the verification voltage V_verify. That is, the second cell group NSG2 can be determined to have been erased incompletely.

[0142] In the verification operation of the second erase cycle LOOP2, the storage cells included in the storage block of multiple cell strings may have a second distributed threshold voltage.

[0143] For example, in the GIDL programming operation of the first erase cycle LOOP1, the GIDL transistor GT of the second unit group NSG2 is programmed, and the threshold voltage of the second unit group NSG2 can be changed to the verification voltage or less.

[0144] In this way, because only the threshold voltage of the second unit string NSG2 decreases, the second distribution can have a narrower range than the first distribution.

[0145] Therefore, by programming the GIDL transistors in each cell string, the erasure operation of the entire memory cell can be performed precisely. The erasure operation can suppress or reduce the occurrence of memory cells that would result in deep erasures leading to excessive holes. Thus, the reliability of non-volatile memory devices can be improved.

[0146] The following will refer to Figure 2 and Figure 11 Describes a storage device according to some embodiments. Figure 11 One side of a memory block in a memory cell array of a memory device according to some embodiments is shown.

[0147] Reference Figure 11 The GIDL transistor GT can be located below the ground select transistor GST. In this case, the bit line BL can be connected to the string select transistors SST of multiple cell strings NS11 to NS33.

[0148] The GIDL transistor GT can be directly connected to the common source line CSL. The GIDL transistor GT can generate holes based on the difference between the source voltage applied to the common source line CSL and the gate voltage applied to the GIDL line. The generated holes can flow into the core line 164 to form the core line voltage. For example, in an erase operation, the source voltage applied to the common source line CSL (e.g., 18V) can be greater than the voltage applied to the GIDL line (e.g., 10V).

[0149] In the following text, reference will be made to Figure 2 , Figure 5 and Figure 12 This describes an erasure method for a storage device according to some embodiments. Figure 12 This is a flowchart illustrating an erasure method for a storage device according to some embodiments.

[0150] Reference Figure 12 The erasure method includes erasure operation (S110), verification operation (S120), GIDL transistor programming operation (S130) and GIDL transistor recovery operation (S140).

[0151] In the erase operation (S110), multiple memory cells MC1 to MC7 included in multiple cell strings NS11 to NS33 can be erased. In the verification operation (S120), the erase results of the multiple memory cells MC1 to MC7 included in multiple cell strings NS11 to NS33 can be verified.

[0152] If the erasure result is determined to be FAIL in the verification operation (S120), the GIDL transistor programming operation (S130) can be performed. In the GIDL transistor programming operation (S130), some GIDL transistors GT of multiple cell strings NS11 to NS33 can be programmed.

[0153] If the erasure result is determined to be successful (PASS) in the verification operation (S120), the GIDL transistor recovery operation (S140) can be performed. In the GIDL transistor recovery operation (S140), the GIDL transistors GT of multiple cell strings NS11 to NS33 can be restored to their state before being programmed.

[0154] Refer to this application Figure 2 , Figure 5 , Figure 12 and Figure 13 This describes an erasure method for a storage device according to some embodiments. Figure 13 This is a flowchart illustrating an erasure method for a storage device according to some embodiments.

[0155] Reference Figure 13 The erasure method includes a first area erasure operation (S200) and a second area erasure operation (S300).

[0156] The first region erasure operation (S200) includes an erasure operation (S210) that erases the storage cells of the first storage cell region MCR1 and a verification operation (S220) that detects the erasure result of the storage cells of the first storage cell region MCR1.

[0157] In addition, the first region erasure operation (S200) includes a GIDL transistor programming operation (S230) and a GIDL transistor recovery operation (S240) performed based on the erasure result of the verification operation (S220) to program the GIDL transistors in some of the multiple cell strings NS11 to NS33.

[0158] The second region erasure operation (S300) includes an erasure operation (S310) that erases the storage cells of the second storage cell region MCR2 and a verification operation (S320) that detects the erasure result of the storage cells of the second storage cell region MCR2.

[0159] Additionally, the second region erasure operation S300 includes a GIDL transistor programming operation (S330) and a GIDL transistor recovery operation (S340) performed based on the erasure result of the verification operation (S320) to program GIDL transistors in some of the multiple cell strings NS11 to NS33.

[0160] By summarizing and reviewing, one or more embodiments can provide highly reliable non-volatile memory devices by reducing or suppressing the occurrence of deep erase cells. One or more embodiments can provide a highly reliable erasure method for non-volatile memory devices by reducing or suppressing the occurrence of deep erase cells.

[0161] Embodiments are described and illustrated in the accompanying drawings according to functional blocks, unit modules, and / or methods. Those skilled in the art will understand that these blocks, units, modules, and / or methods are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, storage elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units, modules, and / or methods implemented by microprocessors or similar devices, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Optionally, each block, unit, module, and / or method may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing certain functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing other functions. Furthermore, without departing from the scope of this disclosure, each block, unit, and / or module of the embodiments may be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of this disclosure, the blocks, units, and / or modules of the embodiments may be physically combined into more complex blocks, units, and / or modules.

[0162] Example embodiments have been disclosed herein. Although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated at the time of filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A non-volatile storage device, the non-volatile storage device comprising: A memory cell array, the memory cell array comprising a plurality of cell strings, the plurality of cell strings comprising a first cell string and a second cell string, each of the plurality of cell strings comprising a gate-sensing drain-leaking transistor and a group of memory cells; as well as Control logic, wherein the control logic is used to apply voltage to each of the plurality of cell strings, wherein the control logic performs: A first erase operation is performed, wherein the same first erase voltage is used to erase the memory cell group of each of the plurality of cell strings, wherein the gate-sensor-drain transistor of the first cell string and the gate-sensor-drain transistor of the second cell string are both programmed to the same first level. A first verification operation detects the first erasure result of the first erasure operation erasing the storage cell group of each of the plurality of cell strings. The programming operation programs the gate-sensing drain-leaking transistor of the first cell string to a second level higher than the first level, and A second erase operation is performed using the programmed gate-sensing drain-leaking transistors of the first cell string and the programmed gate-sensing drain-leaking transistors of the second cell string to erase the memory cell group of each of the plurality of cell strings.

2. The non-volatile storage device as claimed in claim 1, wherein, The control logic further performs a second verification operation, which detects the second erase result of the second erase operation erasing the storage cell group of each of the plurality of cell strings, and... The control logic also performs a recovery operation to restore the gate-sensing drain-leaking transistor of each of the plurality of cell strings based on the second erase result.

3. The non-volatile storage device as described in claim 2, wherein, If the second erase result of the second verification operation indicates that all the memory cell groups of the plurality of cell strings have been completely erased, then the control logic performs the recovery operation.

4. The non-volatile storage device as claimed in claim 1, wherein: The storage cell array includes a first bit line connected to the first cell string and a second bit line connected to the second cell string, and The first erase operation includes applying the same first erase voltage to each of the first bit line and the second bit line.

5. The non-volatile storage device as claimed in claim 4, wherein: The programming operation includes: applying a programming voltage to the first bit line, and A disable voltage, different from the programming voltage, is applied to the second bit line.

6. The non-volatile storage device as claimed in claim 1, wherein, The first verification operation further includes: identifying, based on the first erasure result, a first cell string including storage cell groups in which erasure is incomplete and a second cell string including storage cell groups in which erasure is complete.

7. The non-volatile storage device as claimed in claim 6, wherein, During programming operations, the gate-sensing drain-leaking transistor of the second unit string is maintained at the first level.

8. A non-volatile storage device, the non-volatile storage device comprising: The first unit string is connected to the first bit line and includes a first memory cell group, a first gate-sensing drain-leakage transistor, and a first core line connected to the first memory cell group and the first gate-sensing drain-leakage transistor. The second unit string is connected to the second bit line and includes a second memory cell group, a second gate-sensing drain-leakage transistor, and a second core line connected to the second memory cell group and the second gate-sensing drain-leakage transistor. as well as Control logic, configured to apply a voltage to the first bit line, wherein the control logic performs: The programming operation for programming the first gate-sensing drain-leakage transistor, and The erase operation is performed on the first memory cell group using a programmed first gate-sensor drain-leakage transistor. Specifically, when the control logic performs the erase operation, the first gate-sensing drain-leaking transistor generates a hole at a first hole level and provides the hole to the first core wire, and the second gate-sensing drain-leaking transistor generates a hole at a second hole level lower than the first hole level and provides the hole to the second core wire.

9. The non-volatile storage device of claim 8, wherein, The control logic applies voltage to the second bit line, and The programming operation includes: applying a programming voltage to the first bit line to program the first gate-sensor-drain transistor, and applying a disable voltage higher than the programming voltage to the second bit line to prevent programming of the second gate-sensor-drain transistor. The erasure operation also includes erasing the second memory cell group using the second gate-sensing drain-leakage transistor.

10. The non-volatile storage device of claim 9, wherein: The first gate-sensing drain-leakage transistor includes a first charge-trapping layer that stores electrons introduced therein. The second gate-sensing drain-leakage transistor includes a second charge-trapping layer that stores electrons introduced therein, and The programming operation includes: increasing the electron level of the first charge-trapping layer and not increasing the electron level of the second charge-trapping layer.

11. The non-volatile memory device of claim 10, further comprising: A gate-sensing drain leakage line is provided, which is connected to the gate of the first gate-sensing drain leakage transistor and the gate of the second gate-sensing drain leakage transistor. The programming operation includes applying a gate-induced drain leakage voltage greater than the programming voltage and the disable voltage to the gate-induced drain leakage line.

12. The non-volatile storage device of claim 10, wherein: The first hole level is determined based on the electron level of the first charge-trapping layer, and The second hole level is determined based on the electron level of the second charge-trapping layer.

13. The non-volatile storage device of claim 8, further comprising: A gate-sensing drain leakage line is connected to the first gate-sensing drain leakage transistor. The erase operation further includes applying a gate-induced drain leakage voltage, which is less than the voltage applied to the first bit line, to the gate-induced drain leakage line.

14. A non-volatile storage device, the non-volatile storage device comprising: The first cell string is connected to the first bit line and includes a first memory cell group and a first gate-sensing drain-leaking transistor. The second cell string is connected to the second bit line and includes a second memory cell group and a second gate-sensing drain-leak transistor. as well as Control logic, wherein the control logic is used to apply voltage to the first bit line and the second bit line, wherein the control logic performs the following operations: The second gate-sensor-drain transistor is programmed at the first level. The first gate-sensing drain-leakage transistor is programmed at a second level greater than the first level, and The first gate-sensing drain-leakage transistor and the second gate-sensing drain-leakage transistor are used to erase the first memory cell group and the second memory cell group.

15. The non-volatile storage device of claim 14, wherein: The first unit string includes a third storage unit group that is different from the first storage unit group. The second cell string includes a fourth cell group that is different from the second cell group, and When erasing the first and second storage cell groups, the control logic does not erase any of the storage cells in the third and fourth storage cell groups.

16. The non-volatile memory device of claim 15, further comprising: The first word line group includes multiple word lines connecting the memory cells of the first memory cell group and the second memory cell group; as well as The second word line group includes multiple word lines connecting the memory cells of the third and fourth memory cell groups, wherein... The control logic applies a first word line voltage to each word line of the first word line group, thereby erasing each memory cell of the first memory cell group and the second memory cell group. The control logic applies a second word line voltage greater than the first word line voltage to each word line of the second word line group, thereby preventing any memory cells in the third and fourth memory cell groups from being erased.

17. The non-volatile storage device of claim 14, wherein: The first memory cell group is located between the first gate-sensing drain-leaking transistor and the first bit line, and The second memory cell group is located between the second gate-sensing drain-leakage transistor and the second bit line.

18. The non-volatile memory device of claim 17, further comprising: A ground source electrode line is connected to the first cell string and the second cell string, and the first gate-sensing drain-leaking transistor and the second gate-sensing drain-leaking transistor are directly connected to the ground source electrode line.

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