Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate and a fin protruding from the substrate; forming a gate across the fin, the gate exposing a portion of the top of the fin; forming a first sidewall on the sidewall of the gate, the first sidewall covering the top of the fin exposed by the gate; forming a second sidewall on the sidewall of the first sidewall and the sidewall of the fin, the second sidewall covering the top of the substrate; etching and removing a portion of the thickness of the substrate at the bottom of the second sidewall to form a groove in the substrate; forming a buffer diffusion layer filling the groove; removing the second sidewall; forming a source-drain doping layer on the buffer diffusion layer, the source-drain doping layer covering the sidewall of the fin. The present invention can effectively suppress leakage current and improve the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the development of VLSI, the feature size of integrated circuits continues to decrease. In order to adapt to the reduction of feature size, the channel length of MOSFET is also shortened in semiconductor structure manufacturing. However, as the channel length of MOSFET shortens, the distance between the source and the drain also shortens, resulting in the gate's ability to control the channel becoming worse, making short-channel effects (SCE) more likely to occur.

[0003] Therefore, in order to better adapt to the reduction of feature size, semiconductor manufacturing processes have gradually begun to transition from planar MOSFET to more efficient three-dimensional transistors, such as fin field effect transistors (FinFET). In FinFET, the gate can control the fin from at least two sides. Compared with planar MOSFET, the gate has stronger control over the channel and can reduce the occurrence of short channel effect.

[0004] However, the electrical performance of semiconductor structures manufactured using existing technologies still needs to be improved. Summary of the invention

[0005] The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to reduce the leakage current of the semiconductor structure and thus improve the electrical performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate and a fin protruding from the substrate; forming a gate across the fin, the gate exposing a portion of the top of the fin; forming a first sidewall on the sidewall of the gate, the first sidewall covering the top of the fin exposed by the gate; forming a second sidewall on the sidewall of the first sidewall and the sidewall of the fin, the second sidewall covering the top of the substrate; etching away a portion of the thickness of the substrate located at the bottom of the second sidewall to form a groove in the substrate; forming a buffer diffusion layer filling the groove; removing the second sidewall; forming a source-drain doping layer on the buffer diffusion layer, the source-drain doping layer covering the sidewall of the fin.

[0007] Optionally, the second sidewall exposes a portion of the top of the substrate; and the process of forming the groove further includes: etching and removing a portion of the substrate exposed by the second sidewall.

[0008] Optionally, the depth of the groove is 5nm to 10nm.

[0009] Optionally, the process of forming the groove further includes: forming a hole between the bottom and sidewall of the fin, wherein the hole is connected to the groove.

[0010] Optionally, in a direction parallel to the extension direction of the fin, a width of the hole is 2 to 2.5 times the thickness of the second sidewall.

[0011] Optionally, after removing the second sidewall and before forming the source / drain doping layer, the method further includes: etching and removing the fin located at the bottom of the first sidewall.

[0012] Optionally, the buffer diffusion layer includes a base material layer and suppression ions located in the base material layer.

[0013] Optionally, the base material layer is made of silicon or germanium.

[0014] Optionally, the suppressor ions are germanium ions, carbon ions or nitrogen ions.

[0015] Optionally, when the inhibitory ions are germanium ions, the concentration of the germanium ions is 0.5E22atoms / cm 3 ~2.5E22atoms / cm 3 .

[0016] Optionally, when the inhibitory ions are carbon ions, the concentration of the carbon ions is 0.5E21atoms / cm 3 ~5E21atoms / cm 3 .

[0017] Optionally, when the inhibitory ions are nitrogen ions, the concentration of the nitrogen ions is 0.25E22atoms / cm 3 ~1E22atoms / cm 3 .

[0018] Optionally, the buffer diffusion layer further includes first doping ions, and the first doping ions are P-type ions or N-type ions.

[0019] Optionally, the source-drain doping layer has second doping ions, the second doping ions are P-type ions or N-type ions, and the type of the second doping ions is the same as the type of the first doping ions.

[0020] Optionally, the first doping ion concentration is less than the second doping ion concentration.

[0021] Optionally, the buffer diffusion layer is formed by a selective epitaxial process.

[0022] Optionally, the process of forming the buffer diffusion layer includes: forming a base material layer; and doping the suppression ions into the base material layer to form the buffer diffusion layer.

[0023] Optionally, the inhibitory ions are doped into the base material layer using an ion implantation process.

[0024] Optionally, the dielectric constant of the second spacer material is greater than the dielectric constant of the first spacer material.

[0025] Correspondingly, the present invention also provides a semiconductor structure, including: a substrate and a fin protruding from the substrate; a gate, spanning the fin, the gate covering the top of the fin; a first side wall, located on the side wall of the gate; a groove, located in the substrate on both sides of the fin; a buffer diffusion layer, filling the groove; a source-drain doping layer, located on the buffer diffusion layer, the source-drain doping layer covering the side wall of the fin.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] The substrate at the bottom of the second sidewall is partially removed by etching to form a groove in the substrate; the buffer diffusion layer fills the groove. Therefore, the buffer diffusion layer is located at the bottom corner of the fin, and the buffer diffusion layer is formed on both sides of the bottom of the fin. After the buffer diffusion layer is formed, the second sidewall is removed, and a source-drain doping layer is formed on the buffer diffusion layer. The buffer diffusion layer can prevent the doped ions in the source-drain doping layer from diffusing in opposite directions along the bottom surface of the fin to form leakage current, thereby suppressing the leakage current of the semiconductor structure and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 10 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0029] As can be seen from the background technology, the electrical performance of existing semiconductor structures still needs to be improved.

[0030] A method for forming a semiconductor structure is now analyzed. The process steps for forming the semiconductor structure mainly include: providing a substrate and a fin protruding from the substrate; forming a gate across the fin; and forming a source-drain doping layer in the fin on both sides of the gate.

[0031] The electrical performance of the semiconductor structure formed by the above method is poor, and the reasons are analyzed as follows:

[0032] Since the gate has a weak control capability over the bottom of the fin, leakage current is easily generated on the bottom surface of the fin between the source and drain doping layers, resulting in poor electrical performance of the formed semiconductor structure.

[0033] In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same. The method comprises: forming a first sidewall on the gate sidewall; forming a second sidewall on the first sidewall and the fin sidewall; etching and removing a portion of the thickness of the substrate at the bottom of the second sidewall to form a groove in the substrate; forming a buffer diffusion layer that fills the groove; removing the second sidewall; and forming a source-drain doping layer on the buffer diffusion layer.

[0034] Due to the existence of the buffer diffusion layer, it is difficult for the doped ions in the source-drain doping layer to diffuse along the bottom surface of the fin to form a path, thereby effectively preventing the generation of leakage current and improving the performance of the semiconductor structure.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] refer to Figure 1 , providing a substrate 100 and an initial fin 110 covering the top of the substrate 100 .

[0037] The material of the substrate 100 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In this embodiment, the substrate 100 is a silicon substrate.

[0038] The material of the initial fin 110 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In this embodiment, the material of the initial fin 110 is germanium.

[0039] refer to Figure 2 , forming a gate 200 covering a portion of the top of the initial fin 110 .

[0040] The gate 200 is made of polysilicon or polycrystalline germanium. In addition, the gate 200 may also be made of a metal material, such as Cu, W, Ag or Al. In this embodiment, the gate 200 is made of polysilicon.

[0041] In this embodiment, the gate 200 is a surrounding gate structure.

[0042] In this embodiment, after the gate 200 is formed, the method further includes: forming a hard mask layer 210 covering the top of the gate 200 .

[0043] The material of the hard mask layer 210 is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride oxynitride, boron nitride or boron carbonitride. In this embodiment, the material of the hard mask layer 210 is silicon nitride.

[0044] After forming the hard mask layer 210 , the method further includes: forming a first spacer 310 on the sidewall of the gate 200 , wherein the first spacer 310 covers a portion of the top of the fin 111 .

[0045] In this embodiment, the first spacer 310 covers the sidewalls of the gate 200 and the sidewalls of the hard mask layer 210 .

[0046] The material of the first sidewall spacer 310 is silicon carbonitride, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride oxycarbonitride, boron nitride or boron carbonitride. In this embodiment, the material of the first sidewall spacer 310 is silicon carbonitride.

[0047] refer to Figure 3 , remove the initial fins 110 located on both sides of the gate 200 (refer to Figure 2 ) until the top of the substrate 100 is exposed, forming a fin 111.

[0048] In this embodiment, the initial fin 110 is etched using a dry etching process.

[0049] In this embodiment, the gate 200 exposes a portion of the top of the fin 111 , and the first sidewall spacer 310 covers the exposed top of the fin 111 .

[0050] Subsequently, a second sidewall is formed on the sidewall of the first sidewall 310 and the sidewall of the fin 111, and the second sidewall covers the top of the substrate 100. Figure 4 and Figure 5 , the formation process of the second side wall 320 is introduced in detail.

[0051] refer to Figure 4 , forming a second spacer film 321 on the top of the substrate 100 exposed by the first spacer 310 , the sidewall of the fin 111 located at the bottom of the first spacer 310 , the top and sidewall of the first spacer 310 , and the top of the hard mask layer 210 ;

[0052] The material of the second spacer 321 is silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride or boron carbonitride. In this embodiment, the material of the second spacer 321 is silicon nitride.

[0053] In this embodiment, the dielectric constant of the material of the second spacer film 321 is greater than the dielectric constant of the first spacer 310 .

[0054] The second sidewall film 321 is subsequently etched to form the second sidewall 320 . The dielectric constant of the second sidewall 320 is greater than that of the first sidewall 310 . In the subsequent process of etching and removing the second sidewall 320 , it helps to prevent the first sidewall 310 from being etched.

[0055] refer to Figure 5 , remove the second spacer film 321 located on the top of the hard mask layer 210, the top of the first spacer 310 and the top of part of the substrate 100 (refer to Figure 4 ), the remaining second sidewall film 321 forms a second sidewall 320 .

[0056] The material of the second sidewall 320 is the same as that of the second sidewall film 321, so the dielectric constant of the material of the second sidewall 320 is greater than the dielectric constant of the first sidewall 310. When the second sidewall 320 is subsequently removed, the etching process has a high selectivity for the second sidewall 320 and the first sidewall 310, which helps to protect the first sidewall 310 and prevent the etching process from damaging the first sidewall 310.

[0057] refer to Figure 6 , a portion of the thickness of the substrate 100 located at the bottom of the second sidewall 320 is etched away to form a groove 331 in the substrate 100.

[0058] In this embodiment, the process of forming the groove 331 further includes: etching the exposed portion of the substrate 100 by etching the second sidewall 320 .

[0059] In this embodiment, the depth H1 of the groove 331 is 5nm to 10nm. If the depth H1 of the groove 331 is less than 5nm, a buffer diffusion layer is subsequently formed in the groove 331. The thickness of the buffer diffusion layer is too thin, and avalanche breakdown is likely to occur. If the depth H1 of the groove 331 is greater than 10nm, the remaining thickness of the substrate 100 is too thin.

[0060] The process of forming the groove 331 further includes: forming a hole 332 between the bottom and the side wall of the fin 111 , wherein the hole 332 is connected to the groove 331 .

[0061] In this embodiment, in the direction parallel to the extension of the fin 111, the width of the hole 332 is 2 to 2.5 times the thickness of the second sidewall 320. If the width of the hole 332 is greater than 2.5 times the thickness of the second sidewall 320, the width of the remaining fin 111 is too narrow, affecting the electrical performance of the formed semiconductor structure. If the width of the hole 332 is less than 2 times the thickness of the second sidewall 320, the buffer diffusion layer 410 has a poor effect on improving the leakage current along the bottom surface of the fin 111.

[0062] In this embodiment, a dry etching process is used to etch the substrate 100 on both sides of the gate 300 to form a pre-groove (not shown in the figure) and a pre-hole (not shown in the figure) in the substrate 100; a wet etching process is used to etch the surface of the pre-groove to form the groove 600 and the hole 332.

[0063] In other embodiments, tetramethylammonium hydroxide (TMAH) etching solution may be used to etch and remove the substrate 100 to form the groove 331 and the hole 332 .

[0064] refer to Figure 7 , forming a buffer diffusion layer 410 that fills the groove 331 .

[0065] Subsequently, a source-drain doping layer is formed on the buffer diffusion layer 410 . The buffer diffusion layer 410 can prevent lateral diffusion of doped ions in the source-drain doping layer, help suppress lateral short channel effects, reduce junction capacitance and junction leakage current, and thus improve the performance of the semiconductor structure.

[0066] The buffer diffusion layer 410 includes a base material layer and suppression ions in the base material layer.

[0067] In this embodiment, the buffer diffusion layer 410 is formed by a selective epitaxial process, and the base material layer and the suppression ion are formed in the same process step.

[0068] In this embodiment, the base material layer is made of silicon or germanium. In other embodiments, the base material layer may also be made of germanium.

[0069] In this embodiment, the inhibitory ions are carbon ions, and the material of the buffer diffusion layer 410 is silicon carbide. In other embodiments, the doping ions may also be nitrogen ions or germanium ions.

[0070] In this embodiment, the concentration of carbon ions is 0.5E21atoms / cm 3 ~5E21atoms / cm 3 .

[0071] In other embodiments, the inhibitory ions are germanium ions, and the concentration of the germanium ions is 0.5E22 atoms / cm 3 ~2.5E22atoms / cm 3 .

[0072] In another embodiment, when the inhibitory ions are nitrogen ions, the concentration of the nitrogen ions is 0.25E22 atoms / cm 3 ~1E22atoms / cm 3 .

[0073] In other embodiments, the process for forming the buffer diffusion layer includes: forming a base material layer; and doping the inhibitory ions into the base material layer to form the buffer diffusion layer. That is, the base material layer and the inhibitory ions are formed in different process steps.

[0074] Specifically, the base material layer is formed by a selective epitaxial process; and the inhibitory ions are doped into the base material layer by an ion implantation process.

[0075] In this embodiment, the buffer diffusion layer 410 further includes first doping ions, and the first doping ions are P-type ions. In other embodiments, the first doping ions may also be N-type ions.

[0076] The concentration of the first doping ion is 1E18 atoms / cm 3 ~1E19atoms / cm 3 .

[0077] When the semiconductor structure formed subsequently is under high voltage, the first doping ions can prevent the formation of an overly steep electric field, thereby avoiding the occurrence of avalanche breakdown.

[0078] In other embodiments, the buffer diffusion layer 410 may also only include the base material layer and the suppression ions.

[0079] refer to Figure 8 , remove the second sidewall 320 (reference Figure 7 ).

[0080] In this embodiment, a dry etching process is used to remove the second sidewall spacer 320. In other embodiments, a wet etching process may also be used to remove the second sidewall spacer 320.

[0081] refer to Fig. 9 , the fin 111 at the bottom of the first sidewall 310 is removed by etching. An opening 333 is formed at the bottom of the first sidewall 310 , and the opening 333 exposes the remaining sidewall of the fin 111 .

[0082] In this embodiment, a wet etching process is used to remove the second sidewall spacer 320. In other embodiments, a dry etching process may also be used to remove the second sidewall spacer 320.

[0083] refer to Fig.10 , forming a layer on the top of the first source / drain doping layer 420 to fill the opening 333 (refer to Fig. 9 The second source / drain doped layer 420 covers a portion of the sidewall of the first spacer 310 .

[0084] In this embodiment, the material of the second source / drain doping layer 420 is silicon. In other embodiments, the material of the second source / drain doping layer 420 can also be germanium or silicon germanium.

[0085] In this embodiment, the second source-drain doped layer 420 is formed by a selective epitaxial process.

[0086] The process parameters of the selective epitaxial process include: a process temperature of 650° C. to 850° C., a chamber pressure of 10 Torr to 600 Torr, and process gases including hydrogen, hydrogen chloride, dichlorosilane and phosphine, wherein the gas flow rate of hydrogen is 2000 sccm to 20000 sccm, the gas flow rate of hydrogen chloride is 30 sccm to 150 sccm, the gas flow rate of dichlorosilane is 50 sccm to 1000 sccm, and the gas flow rate of phosphine is 10 sccm to 2000 sccm.

[0087] The source-drain doping layer 420 has second doping ions therein, the second doping ions are P-type ions or N-type ions, and the type of the second doping ions is the same as the type of the first doping ions. In this embodiment, the second doping ions are P-type ions.

[0088] Since the buffer diffusion layer 410 is located at the bottom corner of the fin 111 and the buffer diffusion layer 410 is formed on both sides of the bottom of the fin 111 , it is difficult for the second doping ions to diffuse laterally along the bottom surface of the fin 111 , thereby reducing leakage current.

[0089] The second doping ion concentration is greater than the first doping ion concentration, which helps to reduce the resistance of the source-drain doping layer 420. On the other hand, the first doping ion concentration is low, so the inhibitory ions can effectively inhibit the lateral diffusion of the first doping ions, thereby reducing leakage current.

[0090] Specifically, the concentration of the second doping ion is 5E19atoms / cm 3 ~1.5E21atoms / cm 3 .

[0091] Reference Fig.10 The present invention also provides a semiconductor structure obtained by the above-mentioned formation method, wherein the semiconductor structure comprises: a substrate 100 and a fin 111 protruding from the substrate 100; a gate 200 spanning the fin 111, and the gate 200 covers the top of the fin 111; a first sidewall 310 located on the sidewall of the gate 200; a groove located in the substrate 100 on both sides of the fin 111; a buffer diffusion layer 410 filling the groove; a source-drain doping layer 420 located on the buffer diffusion layer 410, and the source-drain doping layer 420 covers the sidewall of the fin 111.

[0092] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate and a fin protruding from the substrate; forming a gate across the fin, wherein the gate exposes a portion of the top of the fin; Forming a first sidewall spacer on the sidewall of the gate, wherein the first sidewall spacer covers the top of the fin portion exposed by the gate; Forming a second sidewall spacer on the first sidewall spacer and the fin sidewall, wherein the second sidewall spacer covers the top of the substrate; Etching away a portion of the thickness of the substrate at the bottom of the second sidewall to form a groove in the substrate; forming a buffer diffusion layer filling the groove; removing the second side wall; A source-drain doping layer is formed on the buffer diffusion layer, and the source-drain doping layer covers the sidewall of the fin.

2. The method for forming a semiconductor structure according to claim 1, wherein: The second sidewall exposes a portion of the top of the substrate; The process of forming the groove further includes: etching and removing a portion of the substrate to expose the second sidewall.

3. The method for forming a semiconductor structure according to claim 1, wherein: The depth of the groove is 5nm-10nm.

4. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the groove further includes: forming a hole between the bottom and the side wall of the fin, wherein the hole is connected to the groove.

5. The method for forming a semiconductor structure according to claim 4, wherein: In a direction parallel to the extension direction of the fin, the width of the hole is 2 to 2.5 times the thickness of the second sidewall.

6. The method for forming a semiconductor structure according to claim 4, wherein: After removing the second sidewall spacer and before forming the source / drain doping layer, the method further includes: etching and removing the fin located at the bottom of the first sidewall spacer.

7. The method for forming a semiconductor structure according to claim 1, wherein: The buffer diffusion layer includes a base material layer and suppression ions located in the base material layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The base material layer is made of silicon or germanium.

9. The method for forming a semiconductor structure according to claim 7, wherein: The inhibitory ions are germanium ions, carbon ions or nitrogen ions.

10. The method for forming a semiconductor structure according to claim 9, wherein: When the inhibitory ion is germanium ion, the concentration of the germanium ion is 0.5E22atoms / cm 3 ~2.5E22atoms / cm 3 .

11. The method for forming a semiconductor structure according to claim 9, wherein: When the inhibitory ions are carbon ions, the concentration of the carbon ions is 0.5E21atoms / cm 3 ~5E21atoms / cm 3 .

12. The method for forming a semiconductor structure according to claim 9, wherein: When the inhibitory ions are nitrogen ions, the concentration of the nitrogen ions is 0.25E22atoms / cm 3 ~1E22atoms / cm 3 .

13. The method for forming a semiconductor structure according to claim 7, wherein: The buffer diffusion layer further includes first doping ions, which are P-type ions or N-type ions.

14. The method for forming a semiconductor structure according to claim 13, wherein: The source-drain doping layer has second doping ions therein, the second doping ions are P-type ions or N-type ions, and the type of the second doping ions is the same as the type of the first doping ions.

15. The method for forming a semiconductor structure according to claim 14, wherein: The first doping ion concentration is less than the second doping ion concentration.

16. The method for forming a semiconductor structure according to claim 7, wherein: The buffer diffusion layer is formed by a selective epitaxial process.

17. The method for forming a semiconductor structure according to claim 7, wherein: The process of forming the buffer diffusion layer includes: forming a base material layer; doping the suppression ions into the base material layer to form the buffer diffusion layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The suppressor ions are doped into the base material layer by an ion implantation process.

19. The method for forming a semiconductor structure according to claim 1, wherein: The dielectric constant of the second spacer material is greater than the dielectric constant of the first spacer material.

20. A semiconductor structure, characterized in that: include: A substrate and a fin protruding from the substrate; A gate, spanning across the fin, the gate covering the top of the fin; A first spacer, located on the side wall of the gate; grooves located in the substrate on both sides of the fin; A hole is located between the bottom and the side wall of the fin, and the hole is connected with the groove; A buffer diffusion layer, filling the grooves and holes; The source-drain doped layer is located on the buffer diffusion layer, and the source-drain doped layer covers the sidewall of the fin.

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