Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package includes a first electronic device and a second electronic device. The first electronic device includes a first redistribution layer including a circuit layer. The second electronic device is disposed on the first redistribution layer of the first electronic device. The second electronic device includes an encapsulant and a patterned conductive layer. The encapsulant has a first surface facing the first redistribution layer of the first electronic device and a second surface opposite the first surface. The patterned conductive layer is disposed at the second surface of the encapsulant and is configured to electrically couple to the circuit layer of the first redistribution layer of the first electronic device.

Description

Technical Field

[0001] This invention relates to semiconductor device packaging and manufacturing methods thereof, and to semiconductor device packaging comprising two or more stacked molding structures and manufacturing methods thereof. Background Technology

[0002] Stacked semiconductor device packages may contain two or more stacked electronic devices. The electronic devices are formed on a substrate (e.g., a wafer). Each of the electronic devices can be molded during manufacturing, and therefore at least two molding operations can be performed on at least one of the electronic devices. During the two or more molding operations, the substrate and one or more overlays may suffer bending due to a mismatch in the coefficient of thermal expansion (CTE) of the molding materials, which may occur at high temperatures. Bending can cause poor alignment between the electronic devices. Therefore, bending can be a problem in stacked semiconductor device packages. Summary of the Invention

[0003] In some embodiments, a semiconductor device package includes a first electronic device and a second electronic device. The first electronic device includes a first redistribution layer (RDL) that includes a circuit layer. The second electronic device is disposed on the first RDL of the first electronic device. The second electronic device includes an encapsulant and a patterned conductive layer. The encapsulant has a first surface facing the first RDL of the first electronic device and a second surface opposite to the first surface. The patterned conductive layer is disposed on the second surface of the encapsulant and is configured to be electrically coupled to the circuit layer of the first RDL of the first electronic device.

[0004] In some embodiments, a semiconductor device package includes a first electronic device, a second electronic device, and an intermediate layer. The first electronic device includes an RDL (Receptive Distributor Layer), which includes a circuit layer and an upper dielectric layer covering the circuit layer. The second electronic device is disposed on the first electronic device. The second electronic device includes an encapsulant and a patterned conductive layer. The encapsulant has a first surface and a second surface opposite to the first surface. The patterned conductive layer is disposed on the first surface of the encapsulant. The intermediate layer is disposed between the upper dielectric layer of the RDL of the first electronic device and the second surface of the encapsulant, and is configured to bond the first electronic device and the second electronic device.

[0005] In some embodiments, a method for manufacturing a semiconductor device package includes the following operations: forming a first molding structure. The first molding structure includes a first carrier, a patterned conductive layer disposed on the first carrier, and a first encapsulant disposed on the first carrier and encapsulating the patterned conductive layer. Forming a second molding structure. The second molding structure includes a second carrier, a semiconductor chip, a second encapsulant, and an RDL. Disposing the semiconductor chip on the second carrier. Disposing the second encapsulant on the second carrier and encapsulating the semiconductor chip. Disposing the RDL on the second encapsulant. The first molding structure is bonded to the second molding structure by an adhesive layer, wherein the first encapsulant faces the RDL. Attached Figure Description

[0006] Some aspects of embodiments of the invention will be readily understood from the following detailed description when read in conjunction with the accompanying drawings. Various structures may not be drawn to scale, and the dimensions of various structures may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present invention.

[0008] Figure 1A According to some embodiments of the present invention Figure 1 A top view of the upper dielectric layer of the first RDL.

[0009] Figure 1B According to some embodiments of the present invention Figure 1 Cross-sectional view of the upper dielectric layer and the middle layer.

[0010] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J and Figure 2K The operation of manufacturing a semiconductor device package according to some embodiments of the present invention is described.

[0011] Figure 3 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present invention.

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H and Figure 4IThe operation of manufacturing a semiconductor device package according to some embodiments of the present invention is described. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of the invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed or arranged in direct contact, and may also include embodiments in which an additional feature is formed or arranged between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. This repetition is for the purpose of simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations discussed.

[0014] As used herein, spatial relative terms such as “below,” “below,” “lower,” “above,” “upper,” “lower,” “left,” “right,” and similar terms may be used for the sake of simplicity in describing the relationship between one element or feature and another element or feature as illustrated in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to said other element, or there may be an intermediate element.

[0015] This invention provides a semiconductor device package and a method for manufacturing the same. The semiconductor device package includes two or more stacked electronic devices. The electronic devices can be molded structures, which are individually molded before being joined, and thus each of the molded structures can undergo one molding operation. Therefore, subjecting the electronic devices to two or more high-temperature molding operations can be avoided. Consequently, bending problems can be mitigated or avoided, and the electronic devices can be aligned well with each other accordingly.

[0016] Figure 1 This is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present invention. Figure 1As shown, the semiconductor device package 1 includes a first electronic device 10 and a second electronic device 30 stacked on the first electronic device 10. The first electronic device 10 includes an RDL 12 (also referred to as a first RDL). The first RDL 12 includes a circuit layer 12C and a dielectric layer, such as an upper dielectric layer 12D disposed on the circuit layer 12C and a bottom dielectric layer 12B disposed below the circuit layer 12C. The circuit layer 12C may be a single layer or multiple layers, and the material of the circuit layer 12C may include a metal such as copper, an alloy, or other suitable conductive material. The upper dielectric layer 12D and the bottom dielectric layer 12B may each include an inorganic dielectric layer or an organic dielectric layer. In some embodiments, the upper dielectric layer 12D may (but not necessarily) substantially completely cover the circuit layer 12C.

[0017] In some embodiments, the first electronic device 10 may further include another RDL 14 (also referred to as a second RDL), a semiconductor chip 16, and an encapsulant 18 (also referred to as a second encapsulant). The second RDL 14 is disposed below and electrically connected to the first RDL 12. In some embodiments, the surface roughness of the second RDL 14 is less than that of the first RDL 12 (e.g., by a factor of about 0.9 or less, about 0.8 or less, or about 0.7 or less). The second RDL 14 includes, for example, a dielectric layer 14D and a circuit layer 14C, wherein the circuit layer 14C is disposed on, adjacent to, or embedded in the dielectric layer 14D and exposed through the dielectric layer 14D. The second RDL 14 may include a plurality of stacked circuit layers 14C and dielectric layers 14D. The material of the circuit layer 14C may include, for example, a metal, an alloy, or other suitable conductive material such as copper. The dielectric layer 14D may contain an inorganic dielectric layer or an organic dielectric layer.

[0018] A semiconductor chip 16 is disposed between a first RDL 12 and a second RDL 14. The semiconductor chip 16 comprises, for example, an active chip, a passive chip, or a combination thereof. A second encapsulation 18 is disposed between the first RDL 12 and the second RDL 14, and the second encapsulation 18 encapsulates the semiconductor chip 16. In some embodiments, the semiconductor chip 16 may be attached to or contact the first RDL 12, and the semiconductor chip 16 includes connection elements 16C facing and electrically connected to the second RDL 14, such as conductive pillars, conductive studs, or conductive bumps. The second encapsulation 18 comprises, for example, a molding compound, which may be less expensive than other insulating materials. For example, the molding compound may comprise, for example, a polymeric resin of polyimide, an epoxy resin, or the like. The second encapsulation 18 may further comprise, for example, fillers or particles (e.g., silicon oxide or the like). The filler or particles embedded in the second encapsulation 18 can alleviate the bending of the second encapsulation 18. The second encapsulation 18 can be substantially opaque (e.g., blocking about 80% or more of the transmission of light, about 90% or more of the transmission of light, or about 95% or more of the transmission of light). The opaque second encapsulation 18 can block light such as ultraviolet light, thereby protecting the semiconductor chip 16 from ultraviolet damage.

[0019] The first electronic device 10 may further include a conductive structure 18C, such as a conductive post disposed in the second encapsulation 18, and electrically connected to the first RDL 12 and the second RDL 14 via the conductive structure 18C. The first electronic device 10 may further include a connector 19 (e.g., a solder bump) electrically connected to the second RDL 14 via a conductive pad 15 (e.g., under bump metallurgies, UBM), and said connector 19 is configured for external connection. The conductive pad 15 may be proximate to, adjacent to, or embedded in the second RDL 14 and exposed through the second RDL 14.

[0020] A second electronic device 30 is disposed on a first RDL 12 of a first electronic device 10. The second electronic device 30 includes an encapsulation 32 (also referred to as a first encapsulation) and a patterned conductive layer 34. The first encapsulation 32 has a first surface 321 facing the first RDL 12 of the first electronic device 10 and a second surface 322 opposite to the first surface 321. The first encapsulation 32 includes, for example, a molding material, which may be less expensive than other insulating materials. For example, the molding material may include, for example, a polymeric resin of polyimide, an epoxy resin, or the like. The first encapsulation 32 may further include, for example, fillers or particles (e.g., silicon oxide or the like). Fillers or particles embedded in the first encapsulation 32 can alleviate bending of the first encapsulation 32. The first encapsulation 32 may be opaque (e.g., blocking about 80% or more of light transmission, about 90% or more of light transmission, or about 95% or more of light transmission). The opaque first encapsulation 32 can block light such as ultraviolet light, thus protecting the semiconductor chip 16 from ultraviolet damage.

[0021] A patterned conductive layer 34 is disposed on the second surface 322 of the first encapsulation 32 (e.g., on, adjacent to, or embedded in and exposed on the second surface 322 of the first encapsulation 32). In some embodiments, the second electronic device 30 may further include a passivation layer 36 disposed on the patterned conductive layer 34. The material of the passivation layer 36 includes, for example, an organic material, such as polyimide or the like.

[0022] In some embodiments, the first electronic device 10 may include (but is not limited to) a fan-out package, and the second electronic device 30 may include (but is not limited to) an antenna-in package (AIP). The first electronic device 10 and the second electronic device 30 may be other types of electronic devices, chips, semiconductor dies, interposers, or the like.

[0023] In some embodiments, circuit layer 12C may include or have an antenna pattern. In some embodiments, circuit layer 12C of the first electronic device 10 and patterned conductive layer 34 of the second electronic device 30 may jointly form at least a portion of an antenna. For example, patterned conductive layer 34 of the second electronic device 30 may be electrically coupled to circuit layer 12C of the first electronic device 10. As used herein, the term “electrically coupled to” means a state in which an electrical signal can be capacitively propagated from one conductor to another while the conductors are physically isolated from each other by an insulator or dielectric layer. In some embodiments, the patterns of circuit layer 12C and patterned conductive layer 34 are aligned (e.g., a portion of conductive layer 12C is correspondingly disposed over a portion of patterned conductive layer 34). For example, circuit layer 12C of the first RDL 12 includes one or more first electrodes 12E, and patterned conductive layer 34 includes one or more second electrodes 34E substantially aligned with (e.g., correspondingly disposed over first electrodes 12E). In some embodiments, the offset of the edge of the first electrode 12E from the corresponding edge of the second electrode 34E is less than a predetermined value, for example, about 25 micrometers (or, for example, about 20 micrometers, about 17.5 micrometers, about 15 micrometers or less), such that electrical signals can propagate via coupling from the circuit layer 12C to the patterned conductive layer 34, or vice versa. In some embodiments, the offset of the imaginary center line of the first electrode 12E from the imaginary center line of the second electrode 34E is less than a predetermined value, for example, about 25 micrometers (or, for example, about 20 micrometers, about 17.5 micrometers, about 15 micrometers or less). In some embodiments, the dielectric constant (Dk) and dissipation factor (Df) of the first encapsulation 32 and the second encapsulation 18 can be selected individually based on different considerations. For example, the dielectric constant (Dk) and / or dissipation factor (Df) of the first encapsulant 32 disposed between the patterned conductive layer 34 and the circuit layer 12C is lower than that of the second encapsulant 18 (e.g., by a factor of about 0.9 or less, about 0.8 or less, or about 0.7 or less) to reduce transmission loss.

[0024] In some embodiments, the semiconductor device package 1 further includes an intermediate layer 40 disposed between the upper dielectric layer 12D of the first RDL 12 and the first surface 321 of the first encapsulation 32. The intermediate layer 40 may also be referred to as an adhesive layer, configured to bond the first electronic device 10 and the second electronic device 30 (e.g., during manufacturing). The adhesive layer may comprise glue, double-sided tape, or the like. The dielectric constant (Dk) and / or dissipation factor (Df) of the intermediate layer 40, which may be disposed between the patterned conductive layer 34 and the circuit layer 12C, may substantially match the dielectric constant (Dk) and / or dissipation factor (Df) of the first encapsulation 32 to reduce transmission losses (e.g., transmission between the patterned conductive layer 34 and the circuit layer 12C).

[0025] Figure 1A This is a top view of the upper dielectric layer 12D of the first RDL12 according to some embodiments of the present invention, and Figure 1B This is a cross-sectional view of the upper dielectric layer 12D and the intermediate layer 40 according to some embodiments of the present invention. Figure 1A and Figure 1B As shown, the upper dielectric layer 12D may include a plurality of first protrusions 12P, and the intermediate layer 40 may include a plurality of second protrusions 40P that engage with the first protrusions 12P of the upper dielectric layer 12D. In some embodiments, the height of the first protrusions 12P may be, for example, greater than about 1 micrometer (e.g., about 1.5 micrometers or greater, about 2 micrometers or greater, or about 2.5 micrometers or greater). The engaging first protrusions 12P and second protrusions 40P help to enhance the adhesion between the upper dielectric layer 12D and the intermediate layer 40, thereby enhancing alignment and reliability.

[0026] In some embodiments, the patterned conductive layer 34 of the second electronic device 30 may be electrically connected to the circuit layer 12C of the first electronic device 10 (for example, the patterned conductive layer 34 of the second electronic device 30 may be electrically connected to the circuit layer 12C of the first electronic device 10 through a conductive via or the like, the conductive via or the like penetrating the first encapsulation 32).

[0027] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J and Figure 2K This describes operations for manufacturing semiconductor device packages according to some embodiments of the present invention. (Reference) Figure 2AA carrier 50 (also referred to as a first carrier) is provided. The carrier 50 may comprise, for example, a light-transmitting carrier (e.g., that is, a light transmittance of about 80% or more, about 90% or more, or about 95% or more), such as a glass carrier. A patterned conductive layer 34 (e.g., having one or more second electrodes 34E) is formed on the carrier 50. In some embodiments, a passivation layer 36 may be formed on the carrier 50 prior to the formation of the patterned conductive layer 34, and the patterned conductive layer 34 may be formed on the passivation layer 36.

[0028] refer to Figure 2B Encapsulation 32 (also referred to as the first encapsulation) is formed on the carrier 50 to encapsulate the patterned conductive layer 34. Therefore, multiple second electronic devices 30 (also referred to as second molded structures) can be formed. Although in Figure 2B A second electronic device 30 is shown, but the second molding structure may include multiple second electronic devices 30. In some embodiments, the first encapsulation 32 is substantially opaque (e.g., blocking about 80% or more of light transmission, about 90% or more of light transmission, or about 95% or more of light transmission). In some embodiments, the second molding structure may include a flange molding structure, wherein the size (e.g., length) of the first encapsulation 32 may be smaller than the size (e.g., length) of the carrier 50 (e.g., it may be about 95% or less, about 90% or less, or about 85% or less), such that light can penetrate the periphery of the carrier 50 not covered by the first encapsulation 32 to facilitate alignment operations in continuous operation. In some embodiments, alignment marks (not shown) may be formed in the periphery of the carrier 50 not covered by the first encapsulation 32 to facilitate alignment operations.

[0029] refer to Figure 2C A third carrier 52 is provided. The carrier 52 may comprise, for example, a light-transmitting carrier (e.g., that is, a light transmittance of about 80% or more, about 90% or more, or about 95% or more), such as a glass carrier. An RDL 12 (also referred to as a first RDL) is formed on the carrier 52. In some embodiments, the first RDL 12 comprises, for example, a circuit layer 12C and a dielectric layer 12D (also referred to as an upper dielectric layer). In some embodiments, other circuit layers and / or dielectric layers may be formed.

[0030] refer to Figure 2DAnother dielectric layer 12B (also referred to as the bottom dielectric layer) may be formed on the circuit layer 12C, and the bottom dielectric layer 12B partially exposes the circuit layer 12C. A conductive structure 18C is formed on and electrically connected to the circuit layer 12C, which is exposed from the bottom dielectric layer 12B. The conductive structure 18C may be formed by electroplating, deposition, or other suitable techniques. In some embodiments, another alignment mark (not shown) may be formed together with the first RDL 12 to facilitate continuous alignment operations.

[0031] refer to Figure 2E A semiconductor chip 16 is disposed on a first RDL 12. In some embodiments, the semiconductor chip 16 is attached to the first RDL 12, for example, via a die attach film 17, and the semiconductor chip 16 includes a plurality of connection elements 16C. (See reference...) Figure 2F Encapsulation 18 (also referred to as second encapsulation) is formed on the first RDL 12 to encapsulate the semiconductor chip 16 and the conductive structure 18C. In some embodiments, the second encapsulation 18 may be partially removed, for example by grinding, to expose the ends of the conductive structure 18C and the connecting element 16C.

[0032] refer to Figure 2G Another RDL 14 (also referred to as the second RDL) is formed on the second encapsulation 18 and electrically connected to the conductive structure 18C and the connecting element 16C. The second RDL 14 includes, for example, a dielectric layer 14D and a circuit layer 14C, wherein the circuit layer 14C is disposed on, adjacent to, or embedded in the dielectric layer 14D and exposed through the dielectric layer 14D. The second RDL 14 may include multiple stacked circuit layers 14C and dielectric layers 14D. In some embodiments, a conductive pad 15 (e.g., a UBM) may be formed on the second RDL 14 and electrically connected to the second RDL 14 for receiving other electrical components.

[0033] refer to Figure 2H The second RDL 14 is bonded to another carrier 54 (also referred to as the second carrier), and the carrier 52 is removed from the first RDL 12 to expose the upper dielectric layer 12D. The carrier 54 may comprise, for example, a light-transmitting carrier (e.g., that is, a transmittance of about 80% or more, about 90% or more, or about 95% or more), such as a glass carrier. In some embodiments, the upper dielectric layer 12D is patterned to form a first protrusion (e.g., as shown in the image). Figure 1A and Figure 1B(As shown in the diagram). Thus, one or more first electronic devices 10 (also referred to as first molding structures) are formed. In some embodiments, the first molding structure may comprise a full molding structure, wherein the dimensions of the second encapsulation 18 may be substantially the same as the dimensions of the carrier 54. Although one first electronic device 10 has been described, the first molding structure may comprise multiple first electronic devices 10.

[0034] refer to Figure 2I The first molded structure is bonded to the second molded structure via an adhesive layer (also referred to as an intermediate layer) 40, wherein the first encapsulant 32 faces the first RDL 12. The adhesive layer 40 may be softer or more malleable relative to the upper dielectric layer 12D, and thus the second protrusion may be formed to connect with the first protrusion of the upper dielectric layer 12D (e.g., ...). Figure 1B (As shown) engagement to enhance adhesion when the first molded structure is bonded to the second molded structure. In some embodiments, the upper dielectric layer 12D is at least partially recessed to form a plurality of protrusions 12P and corresponding recesses, and (e.g., during bonding operations) the adhesive layer 40 at least partially fills the recesses of the upper dielectric layer 12D, thus forming a plurality of protrusions 40P in the adhesive layer 40 that engages with the protrusions 12P of the upper dielectric layer 12D.

[0035] In some embodiments, the adhesive layer 40 can be cured, for example by thermosetting to harden the adhesive layer 40 and enhance the adhesion between the first molded structure and the second molded structure. In some embodiments, alignment operations, such as optical alignment operations, can be performed using alignment marks (not shown) formed in the carrier 50 and alignment marks (not shown) formed together with the first RDL 12, such that the first molded structure and the second molded structure can be well aligned. Therefore, the first electrode 12E and the second electrode 34E can be well aligned, and the offset of the edge of at least one of the first electrodes 12E from the corresponding edge of the corresponding second electrode 34E (or the offset of the imaginary center line of the first electrode 12E from the imaginary center line of the second electrode 34E) can be controlled to be less than a predetermined value, for example, about 25 micrometers (or, for example, about 20 micrometers, about 17.5 micrometers, about 15 micrometers, or less). Therefore, electrical signals can be transmitted from the circuit layer 12C to the patterned conductive layer 34, or vice versa.

[0036] refer to Figure 2J The carrier 54 is removed from the second RDL 14. A connector 19 (e.g., a solder bump) is formed on the second RDL 14 and electrically connected to the second RDL 14 via a conductive pad 15. The second RDL 14 is attached to a support 56, such as a cutting tape, in which the connector 19 is covered.

[0037] refer to Figure 2K The first and second molding structures are then flipped, and the carrier 50 is removed from the second molding structure. A singulation operation is performed, and the support 56 is removed to form as shown. Figure 1 The semiconductor device package 1 described herein.

[0038] The semiconductor device packaging and manufacturing method of the present invention is not limited to the embodiments described above, and may be implemented according to other embodiments. For the sake of simplicity and ease of comparison between various embodiments of the present invention, similar components in the following embodiments are labeled with the same reference numerals and may not be described in great detail.

[0039] Figure 3 This is a cross-sectional view of a semiconductor device package 2 according to some embodiments of the present invention. (Reference) Figure 3 ,and Figure 1 Compared to the semiconductor device package 1, the second electronic device 30 is disposed on the first electronic device 10 and the intermediate layer is omitted. For example, the upper dielectric layer 12D may contact the first encapsulation 32. In some embodiments, the circuit layer 12C of the first electronic device 10 and the patterned conductive layer 34 of the second electronic device 30 may jointly form an antenna. For example, the patterned conductive layer 34 of the second electronic device 30 may be electrically coupled to the circuit layer 12C of the first electronic device 10. In some embodiments, the patterns of the circuit layer 12C and the patterned conductive layer 34 are substantially aligned. For example, the circuit layer 12C of the first RDL 12 includes a first electrode 12E, and the patterned conductive layer 34 includes a second electrode 34E substantially aligned with the first electrode 12E. In some embodiments, the offset of the edge of the first electrode 12E from the corresponding edge of the second electrode 34E (or the offset of the imaginary center line of the first electrode 12E from the imaginary center line of the second electrode 34E) is less than a predetermined value, for example, about 25 micrometers (or, for example, about 20 micrometers, about 17.5 micrometers, about 15 micrometers or less), such that electrical signals can propagate via coupling from the circuit layer 12C to the patterned conductive layer 34, or vice versa. In some embodiments, the dielectric constant (Dk) and dissipation factor (Df) of the first encapsulation 32 and the second encapsulation 18 can be selected individually based on different considerations. For example, the dielectric constant (Dk) and / or dissipation factor (Df) of the first encapsulant 32 disposed between the patterned conductive layer 34 and the circuit layer 12C is lower than that of the second encapsulant 18 (e.g., by a factor of about 0.9 or less, about 0.8 or less, or about 0.7 or less) to reduce transmission loss.

[0040] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H and Figure 4I This describes the operations for manufacturing a semiconductor device package according to some embodiments of the present invention. (See reference...) Figure 4A A carrier 60 is provided. In some embodiments, the carrier 60 may include a substrate 60A (e.g., a glass substrate or the like) and a releasing layer 60B (e.g., a polymer layer or the like). A passivation layer 36 may be formed on the carrier 60. A patterned conductive layer 34 is formed on the passivation layer 36.

[0041] refer to Figure 4B Encapsulation 32 (also referred to as a first encapsulation) is formed on the carrier 60 to encapsulate the patterned conductive layer 34. Thus, one or more second electronic devices 30 (also referred to as a second molding structure) are formed. Although one second electronic device 30 is described, the second molding structure may contain multiple second electronic devices 30.

[0042] refer to Figure 4C RDL12 (also referred to as the first RDL) is formed on the first encapsulation 32. In some embodiments, the first RDL12 includes, for example, a dielectric layer 12D (also referred to as the upper dielectric layer) and a circuit layer 12C, the circuit layer 12C being disposed on, adjacent to, or embedded in the dielectric layer 12D and exposed through the dielectric layer 12D. Reference Figure 4D Another dielectric layer 12B (also referred to as the bottom dielectric layer) may be formed on the circuit layer 12C, and the bottom dielectric layer 12B partially exposes the circuit layer 12C. A conductive structure 18C is formed on and electrically connected to the circuit layer 12C, which is exposed from the bottom dielectric layer 12B. The conductive structure 18C may be formed by electroplating, deposition, or other suitable techniques.

[0043] refer to Figure 4E A semiconductor chip 16 is disposed on a first RDL 12. In some embodiments, the semiconductor chip 16 is attached to the first RDL 12, for example, via a die attachment film 17, and the semiconductor chip 16 includes a plurality of connection elements 16C. (See reference...) Figure 4F Encapsulation 18 (also referred to as second encapsulation) is formed on the first RDL 12 to encapsulate the semiconductor chip 16 and the conductive structure 18C. In some embodiments, the second encapsulation 18 may be partially removed, for example by grinding, to expose the ends of the conductive structure 18C and the connecting element 16C.

[0044] refer to Figure 4GAnother RDL 14 (also referred to as the second RDL) is formed on the second encapsulation 18 and electrically connected to the conductive structure 18C and the connecting element 16C. The second RDL 14 includes, for example, a dielectric layer 14D and a circuit layer 14C, which is disposed on, embedded in, or exposed through or adjacent to the dielectric layer 14D. In some embodiments, the second RDL 14 includes a plurality of stacked circuit layers 14C and dielectric layers 14D. In some embodiments, a conductive pad 15 (e.g., a UBM) may be formed on and electrically connected to the second RDL 14 for receiving other electrical components.

[0045] refer to Figure 4H Connector 19 (e.g., solder bump) is formed on the second RDL14 and electrically connected to the second RDL14 via conductive pad 15. Reference Figure 4I The second RDL14 is attached to, for example, a support 56 for cutting tape, wherein the connector 19 is covered, and the carrier 60 is removed from the passivation layer 36. Monomerization is performed, and the support 56 is removed to form, as... Figure 3 Semiconductor device package 2 as described in the document.

[0046] In some embodiments of the invention, the semiconductor device package includes two or more stacked electronic devices. The electronic devices may include, but are not limited to, molded structures that are individually molded before being joined, and thus each of the molded structures can undergo a single molding operation. Therefore, bending problems can be mitigated, and thus the electronic devices can be well aligned with each other when joined.

[0047] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple references.

[0048] As used herein, the terms “approximately,” “substantially,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred precisely or where it occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two numerical values ​​may be considered “substantially” the same or equal. For example, "essentially parallel" can refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "essentially perpendicular" can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0049] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values ​​explicitly defined as the limits of the range, but also all individual numerical values ​​or subranges covered within that range, just as each numerical value and subrange is explicitly defined.

[0050] Although the invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not intended to limit the invention. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Artistic representations of the invention may differ from actual devices due to manufacturing processes and tolerances. Other embodiments of the invention may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein are described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of operations are not limitations of the invention.

Claims

1. A semiconductor device package comprising: A first electronic device includes a first redistribution layer, the first redistribution layer comprising a circuit layer and an upper dielectric layer covering the circuit layer; A second electronic device, disposed on the first redistribution layer of the first electronic device, the second electronic device comprising: An encapsulation having a first surface facing the first redistribution layer of the first electronic device and a second surface opposite to the first surface; and A patterned conductive layer, disposed on the second surface of the encapsulation and connected via a circuit layer to the first redistribution layer of the first electronic device, wherein the top surface of the patterned conductive layer is substantially coplanar with the second surface of the encapsulation; and An adhesive layer is disposed between the upper dielectric layer of the first redistribution layer of the first electronic device and the first surface of the encapsulation and is configured to bond the first electronic device and the second electronic device. The first electronic device further includes: a second redistribution layer disposed below the first redistribution layer; a conductive structure electrically connecting the first redistribution layer and the second redistribution layer; wherein the circuit layer of the first redistribution layer includes a first electrode, the conductive structure contacts the first electrode, and the number of conductive structures in contact with the first electrode is at least two. The upper dielectric layer of the first redistribution layer includes a plurality of first protrusions, and the adhesive layer includes a plurality of second protrusions that engage with the first protrusions of the upper dielectric layer of the first redistribution layer.

2. The semiconductor device package of claim 1, wherein the circuit layer of the first redistribution layer is physically isolated from the patterned conductive layer by the encapsulant, a first surface of the first electrode contacts the conductive structure, and a second surface of the first electrode opposite to the first surface is physically isolated from the second surface of the encapsulant by the adhesive layer.

3. The semiconductor device package of claim 2, wherein the patterned conductive layer includes a second electrode aligned with the first electrode.

4. The semiconductor device package of claim 3, wherein the edge of the first electrode is offset from the corresponding edge of the second electrode by less than 25 micrometers, and the second surface of the first electrode is closer to the interface between the adhesive layer and the encapsulant than the second electrode.

5. The semiconductor device package of claim 1, wherein the conductive structure extends from the top surface of the second redistribution layer to the bottom surface of the first electrode, the conductive structure including a first portion contacting the first electrode and a second portion contacting the second redistribution layer, the width of the first portion being smaller than the width of the second portion, and the width of the first portion gradually narrowing toward the upper dielectric layer.

6. The semiconductor device package of claim 5, wherein the first electronic device further comprises: A semiconductor chip disposed between the first redistribution layer and the second redistribution layer; A bare die attachment film is used to attach the semiconductor chip to the first redistribution layer; as well as A second encapsulant is disposed between the first redistribution layer and the second redistribution layer, and encapsulates the semiconductor chip and the die attachment film. The first portion of the conductive structure does not horizontally overlap the semiconductor chip, the die attachment film, and the encapsulation.

7. The semiconductor device package of claim 6, wherein the surface roughness of the second redistribution layer is less than the surface roughness of the first redistribution layer.

8. The semiconductor device package of claim 1, further comprising a passivation layer disposed on the patterned conductive layer.

9. The semiconductor device package of claim 1, wherein the encapsulant blocks more than 80% of the transmission of light.

10. The semiconductor device package of claim 1, wherein the plurality of first protrusions of the upper dielectric layer are elongated protrusions extending in one direction, and the plurality of first protrusions are arranged in a regular array, wherein the plurality of second protrusions of the adhesive layer engage with the plurality of elongated protrusions.

11. The semiconductor device package of claim 1, wherein a recess is formed between a plurality of first protrusions of the upper dielectric layer, and at least a portion of the second protrusions of the adhesive layer fills the recess of the upper dielectric layer and interlocks with each other.

12. The semiconductor device package of claim 1, wherein the first electronic device further comprises: A semiconductor chip comprising a connection component facing and electrically connected to the second redistribution layer; A die attachment film that attaches the semiconductor chip to the first redistribution layer; as well as The second encapsulation material encapsulates the semiconductor chip and the die attachment film.

13. A semiconductor device package comprising: A first electronic device includes a first redistribution layer, the first redistribution layer comprising a circuit layer and an upper dielectric layer covering the circuit layer; A second electronic device, disposed on the first electronic device, the second electronic device comprising: An encapsulation having a first surface and a second surface opposite to the first surface; and A patterned conductive layer is disposed on the first surface of the encapsulation; and An adhesive layer is disposed between the upper dielectric layer of the first redistribution layer of the first electronic device and the second surface of the encapsulation, and is configured to bond the first electronic device and the second electronic device, wherein the dissipation factor of the adhesive layer matches the dissipation factor of the encapsulation. The first electronic device further includes: a second redistribution layer disposed below the first redistribution layer; a conductive structure electrically connecting the first redistribution layer and the second redistribution layer; wherein the first redistribution layer further includes a bottom dielectric layer supporting the circuit layer, and a first portion of the conductive structure penetrates the bottom dielectric layer of the first redistribution layer. The upper dielectric layer of the first redistribution layer includes a plurality of first protrusions, and the adhesive layer includes a plurality of second protrusions that engage with the first protrusions of the upper dielectric layer of the first redistribution layer.

14. The semiconductor device package of claim 13, wherein the circuit layer is physically isolated from the patterned conductive layer via the upper dielectric layer of the adhesive layer and the first redistribution layer.

15. The semiconductor device package of claim 13, wherein the circuit layer of the first redistribution layer includes a first electrode, the patterned conductive layer includes a second electrode aligned with the first electrode, the first portion of the conductive structure gradually narrows toward the first electrode and contacts the first electrode, and the second portion of the conductive structure is wider than the first portion and contacts the encapsulation.

16. The semiconductor device package of claim 13, wherein the second electronic device further includes a passivation layer disposed on the patterned conductive layer, the patterned conductive layer comprising an antenna pattern and embedded in the encapsulation, the top surface of the patterned conductive layer protruding from the encapsulation and coplanar with the interface between the passivation layer and the encapsulation.

17. The semiconductor device package of claim 16, wherein the material of the passivation layer comprises an organic material.

18. A method for manufacturing a semiconductor device package, comprising: Forming a first molding structure, the first molding structure comprising: First carrier; A patterned conductive layer is disposed on the first carrier; A first encapsulant, disposed on the first carrier and encapsulating the patterned conductive layer; and Alignment marks are formed on the periphery of the first carrier that is not covered by the first encapsulation. Forming a second molding structure, the second molding structure comprising: Second carrier; A first redistribution layer is formed on the second carrier, the first redistribution layer comprising a circuit layer and an upper dielectric layer covering the circuit layer; A semiconductor chip, which is disposed on the first redistribution layer; A second encapsulant, formed on the first redistribution layer and encapsulating the semiconductor chip; and A second redistribution layer is formed on the second encapsulation; Optical alignment is performed via the alignment marks, and the first molded structure is bonded to the second molded structure via an adhesive layer, wherein the first encapsulation faces the first redistribution layer; and A conductive structure is formed through the second encapsulation to electrically connect the first redistribution layer and the second redistribution layer; wherein the circuit layer of the first redistribution layer includes a first electrode, the conductive structure contacts the first electrode, and the number of conductive structures in contact with the first electrode is at least two. The upper dielectric layer of the first redistribution layer includes a plurality of first protrusions, and the adhesive layer includes a plurality of second protrusions that engage with the first protrusions of the upper dielectric layer of the first redistribution layer.

19. The method of claim 18, wherein the first carrier comprises a light-transmitting carrier, and the first encapsulant comprises an opaque encapsulant.

20. The method of claim 18, wherein forming the second molded structure comprises: Remove the second carrier to expose the upper dielectric layer of the first redistribution layer.

21. The method of claim 18, wherein forming the second molded structure further comprises forming another alignment mark together with the first redistribution layer; and using the alignment mark formed in the first carrier and the other alignment mark formed together with the first redistribution layer to perform the optical alignment operation to precisely align the first molded structure with the second molded structure.

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