Determine the superposition of memory array characteristics

Abstract

Methods, apparatus, and systems are described that relate to determining an overlay of features of a memory array. An example method includes: forming a plurality of contacts on a working surface; and selectively forming a first portion of a conductive line layer in contact with the contacts and a second portion of the conductive line layer. The first portion of the conductive line layer formed above the working surface is separated from the second portion of the conductive line layer formed above the working surface by a gap. The method includes determining an overlay of at least one of the contacts formed above the working surface in the gap relative to one of the conductive lines formed above the working surface.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices and methods, and more particularly to determining superposition of characteristics of a memory array. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), and flash memory, among others. Some types of memory devices may be non-volatile memory (e.g., ReRAM) and may be used in a wide range of electronic applications that require high memory density, high reliability, and low power consumption. Compared to non-volatile memory cells (e.g., flash memory cells) that can also maintain their storage state in the absence of power, volatile memory cells (e.g., DRAM cells) require power to maintain their storage data state (e.g., via a refresh process). However, various volatile memory cells (e.g., DRAM cells) may operate (e.g., program, read, erase, etc.) faster than various non-volatile memory cells (e.g., flash memory cells). Summary of the invention

[0003] One embodiment of the present application provides a method, comprising: forming a plurality of contact elements (102, 104; 202, 204; 402, 404) on a working surface (313); selectively forming a first portion (630; 730; 830) of a conductive line layer (520; 620) in contact with the plurality of contact elements (102, 104; 202, 204; 402, 404) and a second portion (632; 732; 832) of the conductive line layer (520; 620), wherein the conductive line layer (520; 620) formed above the working surface (313) 20) is separated from the second portion (632; 732; 832) of the conductive line layer (520; 620) formed above the working surface (313) by a gap (728; 828); and determining the superposition of at least one of the multiple contact members (102, 104; 202, 204; 402, 404) formed above the working surface (313) in the gap (728; 828) relative to one of the conductive lines (734; 834) formed above the working surface (313).

[0004] Another embodiment of the present application provides a method, comprising: selectively forming a first portion (214; 314; 414; 514; 614; 714; 1058) of a contact layer (100; 200; 300; 400; 1065) and a second portion (216; 416; 516; 616; 716; 1060) of the contact layer (100; 200; 300; 400; 1065) on a working surface (313), wherein The first portion (214; 314; 414; 514; 614; 714; 1058) of the contact layer (100; 200; 300; 400; 1065) formed above the working surface (313) is connected to the second portion (216; 416; 514; 614; 714; 1058) of the contact layer (100; 200; 300; 400; 1065) formed above the working surface (313) through a gap (312; 412; 712). 16; 616; 716; 1060) separation; selectively forming a conductive line layer (214; 314; 414; 514; 614; 714; 1058) and a conductive line layer (216; 416; 516; 616; 716; 1060) on the working surface (313) in contact with the first portion (214; 314; 414; 514; 614; 714; 1058) and the second portion (216; 416; 516; 616; 716; 1060) of the contact layer (100; 200; 300; 400; 1065) formed above the working surface (313) 520; 620) and a first portion (630; 730; 830) of the conductive line layer (520; 620) and a second portion (632; 732; 832) of the conductive line layer (520; 620); and determining an overlap of at least one of the conductive lines (734; 834) formed above the working surface (313) in the gap (312; 412; 712) relative to one of the contact members (736; 836) formed above the working surface (313).

[0005] Another embodiment of the present application provides a method comprising: forming features of a first feature layer (100) in an active region of a memory array (1056); and applying a cleavage mask (210; 310; 626) to a second feature layer (520) of the memory array (1056) to: form features of a first portion (514) of the second feature layer (520) in the active region of the memory array (1056); and form features of a second portion (516) of the second feature layer (520) outside the active region of the memory array (1056).

[0006] Another embodiment of the present application provides a memory device, comprising: a first plurality of contacts (102; 202; 402; 940) formed above a first portion (950) of a working surface (313) corresponding to an active area of ​​a memory array (1056); a plurality of conductive lines (942, 944) of the memory array (1056) formed to contact the first plurality of contacts (102; 202; 402; 940); and a second plurality of the contacts (102; 202; 402; 940) formed above a second portion (946) of the working surface (313) such that the second plurality of contacts (102; 202; 402; 940) are separated from the plurality of conductive lines (942, 944).

[0007] Another embodiment of the present application provides a method comprising: determining an overlap of contacts (940, 945) of the memory array (1056) and the conductive lines (942, 944) of the memory array (1056) by determining an overlap of one of the conductive lines (942, 944) of the memory array (1056) and a reference contact formed above a chip and outside the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Shown are plan views of contact layers according to several embodiments of the present invention.

[0009] Figure 2 Several embodiments of the present invention are shown in FIG. Figure 1 A plan view of the chopping mask for the contact layer.

[0010] Figure 3 FIG. 1 is a diagram showing how a cleavage mask is applied to a substrate according to several embodiments of the present invention. Figure 1 Cross-sectional view on the contact layer.

[0011] Figure 4 FIG. 1 shows a plurality of embodiments of the present invention formed on a working surface. Figure 1 A plan view of a portion of the contact layer.

[0012] Figure 5 FIG. 4 is a plan view of a conductive line layer according to several embodiments of the present invention.

[0013] Figure 6 Several embodiments of the present invention are shown in FIG. Figure 4 FIG. 1 is a plan view of a chopping mask for a conductive line layer.

[0014] Figure 7 Several embodiments of the present invention are shown in FIG. Figure 4A plan view of a portion of a conductive line layer.

[0015] Figure 8 Several embodiments of the present invention are shown in FIG. Figure 1 The contact layer above Figure 4 A plan view of a portion of a conductive line layer.

[0016] Fig. 9 A plan view of a plurality of conductive lines and a plurality of contact elements formed according to several embodiments of the present invention is shown.

[0017] Figures 10A to 10C A plan view of a plurality of contacts formed outside a memory array according to several embodiments of the present invention is shown.

[0018] Figures 11A to 11E Example processing steps for pitch multiplication are shown according to several embodiments of the present invention.

[0019] Figures 12 to 15 is a flow chart of an example method for determining an overlay of characteristics of a memory array according to several embodiments of the invention. DETAILED DESCRIPTION

[0020] Various types of memory devices, including arrays of volatile and / or nonvolatile memory cells (e.g., memory arrays), may include multiple contacts and multiple lines that can couple memory cells. The lines of the memory array may be formed to contact the contacts. In at least one embodiment of the present invention, the lines of the memory array may be conductive lines. In some previous methods, during the manufacture of the memory device, a die (e.g., a wafer) may include a scribing target. The scribing target may include an overlay target and structural and / or engineering marks that can be used to determine where the pattern is on the wafer. The scribing target may be removed from the die so that the completed memory device does not include a scribing target on the die. As used herein, "overlay" refers to the offset between two or more patterns (e.g., photolithographic patterns) after the patterns are placed. During the manufacture of the memory device, the scribing target may be used to determine the overlay (e.g., offset) of a first feature (e.g., a contact) relative to a second feature (e.g., a conductive line). For example, the scribing target may be used to determine whether the contact of the memory array is in line with the conductive line of the memory array. However, as the pitch of the memory array decreases, the size of the contact also decreases. As used herein, "pitch" refers to the distance between two adjacent conductive lines of a memory array. The size of the contact is reduced so that two corresponding conductive lines (and two adjacent memory cells) are formed closer together. In some examples, the size of the contact is reduced so much that the width of the contact is less than the width of the conductive line formed to contact the contact. Therefore, the superposition of the contact and another feature (e.g., the conductive line formed to contact the contact) may be blocked and / or obscured by the other feature.

[0021] In order to form features (such as contacts and conductive lines) of the memory array, a mask material (e.g., a photoresist material) may be applied to the feature layer to selectively transfer the pattern to the wafer. That is, the mask material may be used to control where the pattern is transferred to the wafer and which portion or portions of the pattern are transferred to the wafer. The mask material may also be referred to herein as a chop mask. The pattern may extend beyond the region of the wafer associated with the operation of the memory array to reduce effects from pattern termination, such as cycle end, OPC, and etch loading effects. The mask material may be used to remove excess patterns (patterns extending beyond the region of the wafer associated with the operation of the memory array). Removal of the excess pattern may be achieved using photolithography techniques (e.g., including krypton fluoride (KrF) or argon fluoride (ArF) excimer lasers) to form mask material over the excess pattern.

[0022] To overcome difficulties associated with previous methods of determining overlays of features of a memory array, embodiments in accordance with the present invention utilize masking materials to selectively transfer portions of a pattern (eg, a feature layer) that may serve as reference features to a wafer.

[0023] The present invention includes methods, apparatus, and systems related to determining an overlay of features of a memory array. Examples of the examples described herein include: forming a plurality of contacts on a working surface; and selectively forming a first portion of a conductive line layer in contact with the contacts and a second portion of the conductive line layer. The first portion of the conductive line layer formed above the working surface is separated from the second portion of the conductive line layer formed above the working surface by a gap. The example method further includes determining an overlay of at least one of the contacts formed above the working surface in the gap relative to one of the conductive lines formed above the working surface.

[0024] In the following detailed description of the invention, reference is made to the accompanying drawings which form part of the invention and in which one or more embodiments of the invention are shown in illustrative form how they may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the invention, and it is understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the invention. As used herein, "several" things may refer to one or more such things. For example, several capacitors may refer to at least one capacitor.

[0025] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the drawing and the remaining digits identify the element or component in the drawing. Similar elements or components between different figures may be identified by using similar numerals. For example, reference numeral 104 may refer to Figure 1Component "04" in, and similar components can be found in Figure 2 It is referred to as 204 in Chinese.

[0026] Figure 1 FIG. 1 is a plan view of a contact layer 100 according to several embodiments of the present invention. The contact layer 100 may be a first feature layer. The contact layer 100 may include a first plurality of contacts 102 and a second plurality of contacts 104. Figure 1 As shown in FIG. 1 , the second plurality of contacts 104 may overlap with the first plurality of contacts (eg, at the corners of the contacts). However, embodiments of the present invention are not limited thereto. Figure 1 The contact layer 100 is depicted as including contacts in a rectangular arrangement, but embodiments of the invention are not limited thereto. Although the contacts may initially be rectangular (as depicted in the contact layer 100), the shape of the contacts may be altered during photolithography. For example, after a chopped mask is applied to the contact layer 100, the shape of the contacts of the contact layer 100 may be circular or elliptical. The contacts of the layer 100 may be in a non-rectangular arrangement, such as a hexagonal arrangement.

[0027] Figure 2 A plan view of a cleaving mask 210 applied to a contact layer 200 according to several embodiments of the present invention is shown. The cleaving mask 210 may be used to selectively form (eg, transfer) a portion or portions of the contact layer 200 onto a working surface ( Figure 2 In at least one embodiment, the working surface may be a wafer (eg, a silicon wafer). Figure 2 As shown in FIG. 1 , a chop mask 210 may be applied to the contact layer 200 to selectively form a subset (dashed lines) of contacts 202 and 204 that are in contact with the chop mask 210 on a working surface. A first portion 206 of the chop mask 210 may be used to form a first portion 214 of the contact layer 200 on the working surface and a second portion 208 of the chop mask 210 may be used to form a second portion 216 of the contact layer 200 on the working surface. Figure 2 As shown in FIG. 2 , there may be a gap 212 between the first portion 206 and the second portion 208 of the chop mask 210 so that the third portion of the contact layer 200 between the first portion 206 and the second portion 208 of the chop mask 210 is not formed to the working surface.

[0028] Figure 3 A cross-sectional view showing a chopping mask 310 being applied to contacts of a contact layer 300 is shown. Figure 3A first portion 306 of a chop mask 310, a first portion 314 of the contact layer 300, and a gap 312 are shown. The chop mask 310 may be a photoresist material. The first portion of the chop mask 310 may cause the first portion 314 of the contact layer 300 to be formed on the working surface 313 in response to exposure to the excimer laser. In contrast, the portion of the contact layer 300 in the gap 312 to which the chop mask 310 is not applied will not be formed on the working surface 313.

[0029] Although not specifically shown, the chopping mask 310 is applied to Figure 3 The contact layer 300 shown in FIG. 1 may be combined with the following Figure 6 The described application of the chopped mask 626 to the conductive line layer 620 is similar. Although the contact layer 300 may be formed by doubling the pitch, embodiments of the present invention are not limited thereto. The contact layer 300 may be formed by doubling the pitch of the conductive line layer 620 (e.g., in combination with the contact layer 300 below). Figure 5 Any pitch of contacts at the intersections of the spaces between the lines of the described line layer 520 is formed by multiplying the pitch.

[0030] Figure 4 A plan view of a portion of a contact layer 400 (including contacts 402 and 404) formed above a working surface is shown according to several embodiments of the present invention. A first portion 414 of the contact layer formed above the working surface and a second portion 416 of the contact layer formed above the working surface are separated by a gap 412.

[0031] Figure 5 A conductive line layer 520 according to several embodiments of the present invention is depicted. The conductive line layer 520 may be a second feature layer. In at least one embodiment, a line layer may be used to replace the conductive line layer 520, wherein at least one line of the line layer is non-conductive. The conductive line layer 520 may be referred to as a line space layer 520. The conductive line layer 520 includes a plurality of horizontally arranged conductive lines. However, embodiments of the present invention are not limited thereto. For example, a plurality of conductive lines may be arranged vertically or diagonally. The first portion 514 and the second portion 516 of the contact layer formed above the working surface are shown as dashed lines to indicate that the first portion 514 and the second portion 516 may be below the conductive line layer 520.

[0032] Figure 6 FIG. 6 is a diagram showing a cleavage mask 626 applied to a conductive line layer 620 according to several embodiments of the present invention. In at least one embodiment, the cleavage mask 626 may be Figure 2 The first portion 614 and the second portion 616 of the contact layer 620 formed above the working surface are shown as dashed lines to indicate that the first portion 614 and the second portion 616 may be below the conductive line layer 620.

[0033] The cleavage mask 626 may be used to selectively form (eg, transfer) a portion or portions of the conductive line layer 620 onto a working surface. Figure 6 As shown in FIG. 1 , a chopping mask 626 can be applied to the conductive wire layer 620 to selectively form a subset of conductive wires (dashed lines) on the working surface that are in contact with the chopping mask 626. A first portion 622 of the chopping mask 626 can be used to form a first portion 630 of the conductive wire layer 620 on the working surface and a second portion 624 of the chopping mask 626 can be used to form a second portion 632 of the conductive wire layer 620 on the working surface. Figure 6 As shown in FIG. 6 , a gap 628 may exist between the first portion 622 of the chopping mask 626 and the second portion 624 of the chopping mask 626 so that a third portion of the conductive line layer 620 between the first portion 622 and the second portion 624 of the chopping mask 626 is not formed over the working surface.

[0034] Figure 7 Portions of a conductive line layer 720 formed according to several embodiments of the present invention are shown. A first portion 730 of the conductive line layer can be formed on the working surface and the first portion 714 of the contact layer. A second portion 732 of the conductive line layer can be formed on the working surface and the second portion 716 of the contact layer. The first portion 730 and the second portion 732 of the conductive line layer are separated by a gap 728.

[0035] The gap 712 between the first portion and the second portion of the contact layer may partially overlap with the gap 728 between the first portion 730 and the second portion 732 of the conductive line layer. Figure 7 , portions of the first portion 730 of the conductive line layer are formed above the working surface and not in contact with the first portion 714 of the contact layer, and portions of the second portion 716 of the contact layer are formed above the working surface and not in contact with the second portion 732 of the conductive line layer. This allows for a more unobstructed superposition of portions of the first portion 730 of the conductive line layer and portions of the second portion 716 of the contact layer than some previous approaches.

[0036] Some previous methods may include determining the superposition of a conductive line relative to a contact on which the conductive line is formed. As described above, a contact may be blocked or obscured by a conductive line making it difficult, if not impossible, to determine the offset of a conductive line relative to the contact on which the conductive line is formed. In contrast, embodiments of the present invention may utilize the less obstructed superposition of portions of the first portion 730 of the conductive line layer formed in gap 728 and portions of the second portion 716 of the contact layer formed in gap 712 to determine the superposition of the first portion 730 and the second portion 732 of the conductive line layer relative to the first portion 714 and the second portion 716 of the contact layer. For example, the offset of the conductive line 734 relative to the contact 736 may be determined. For example, it may be determined whether the conductive line 734 is in line with the contact 736.

[0037] Figure 8 A portion of a conductive line layer 800 formed above a contact layer according to several embodiments of the present invention is shown. In at least one embodiment, a mask material (e.g. Figure 6 ) can be used to form a first portion 830 of the conductive line layer and a second portion 832 of the conductive line layer on the non-interrupted contact layer. This embodiment provides a less obstructed view of the contact 836 formed above the working surface within the gap 828. For example, if the size of the contact is slightly larger than the width of the conductive line 834, providing a more unobstructed overlay of portions of the contact can facilitate determining the overlay of the first portion 830 and the second portion 832 of the conductive line layer relative to the contact layer.

[0038] Fig. 9 A plurality of conductive lines and a plurality of contact elements formed according to several embodiments of the present invention are shown. Fig. 9 In the example, dots are formed on a working surface (e.g., a wafer) by a first feature layer (e.g., Figure 1 The contacts formed by the contact layer 100 shown in FIG. 1 and the horizontal lines are the conductive lines formed above the working surface and the contacts from the second feature layer (eg, Figure 5 5. A contact of the conductive line layer 520 shown in FIG.

[0039] Fig. 9 Depicted are: a first portion 950 of the working surface, wherein the conductive wire is formed to contact the contact member; a second portion 946 of the working surface, wherein the conductive wire is formed above the working surface but not on the contact member; a third portion 948 of the working surface, wherein the contact member is formed above the working surface but the conductive wire is not formed above the contact member; and a fourth portion 952 of the working surface, wherein the conductive wire is formed to contact the contact member. Fig. 9 The arrangement of the contacts and conductive wires shown in FIG. Figure 7 The arrangement of the contacts and conductive lines shown in FIG. 5 is similar.

[0040] like Fig. 9 , in the first portion 950 and the fourth portion 952 of the working surface, it may be difficult to distinguish between contacts and conductive lines. For example, in the first portion 950 of the working surface, contact 940 and conductive line 942 may be distinguished, and conductive line 942 is formed to contact contact 940. Thus, the offset of contact 940 and conductive line 942 may be determined. However, conductive line 944 obscures and hides the contact on which conductive line 944 is formed. Thus, it is difficult, if not impossible, to determine the offset between conductive line 944 and the contact on which conductive line 944 is formed.

[0041] In contrast, the above combination Figures 1 to 4 The contact described above and in combination Figures 5 to 7 The described conductive lines can provide improved (e.g., less obstructed) superposition of the conductive lines in the second portion 946 of the working surface and the contacts in the third portion 948 of the working surface. For example, to determine the offset between the conductive line 944 and the contacts on which the conductive line 944 is formed, the contacts (e.g., contacts 945) in the third portion 948 of the working surface can be used. The offset between the contacts 945 in the second portion 946 of the working surface and the conductive line 944 can indicate the offset between the conductive line 944 and the contacts on which the conductive line 944 is formed.

[0042] Figures 10A to 10C A plurality of contacts are shown formed external to the memory array 1056 in accordance with several embodiments of the present invention. Fig. 10A A memory device 1054 is shown including multiple memory arrays. Fig. 10B An enlarged view of a memory array 1056 of a memory device 1054 is depicted. An inner rectangle 1055 represents an active area of ​​the memory array 1056. As used herein, the "active area of ​​the memory array" refers to the portion of the memory array that includes features (e.g., contacts and / or conductive lines) that are functional during operation of the memory array 1056. In contrast, an outer rectangle 1057 represents an outer boundary of the memory array 1056. Features (e.g., contacts and / or conductive lines) formed within the outer boundary of the memory array 1056 but outside the active area of ​​the memory array are inactive during operation of the memory array 1056.

[0043] Fig. 10C An enlarged view of a portion of the memory array 1056 is shown. Figure 2 As described, a chopped mask can be used to selectively form portions of a feature layer (eg, a contact layer) onto a working surface. FIG. 10 illustrates a contact layer 1065 including a first portion 1058 and a second portion 1060. The contact layer 1065 can be formed with Figure 21056. The first portion 1058 of the contact layer 1065 can be positioned on a portion of the working surface corresponding to the active area of ​​the memory array 1056. The first portion 1062 of the chopped mask 1063 can be applied to the first portion 1058 of the contact layer 1065 to form contacts for the active area of ​​the memory array 1056.

[0044] The second portion 1060 of the contact layer 1065 may be positioned over a different portion of the working surface outside the active area of ​​the memory array 1056. In some previous approaches, no features may be formed outside the active area of ​​the memory array. In contrast, at least one embodiment may include using a chop mask to form features on the portion of the working surface outside the active area of ​​the memory array. As depicted in FIG. 10 , a second portion 1064 of the chop mask 1063 may be applied to at least a portion of the second portion 1060 of the contact layer 1065 to form contacts on the portion of the working surface outside the active area of ​​the memory array 1056. The second portion 1064 of the chop mask 1063 may be considered an extension of the first portion 1062 of the chop mask 1063. Thus, the second portion 1064 of the chop mask 1063 may extend the formation of contacts of the contact layer 1065 beyond the active area of ​​the memory array 1056. The contacts formed outside the active area of ​​the memory array 1056 may be referred to as reference contacts.

[0045] Forming contacts outside the active region of the memory array may provide a more unimpeded overlap of contacts formed outside the active region of the memory array 1056 because other features (e.g., conductive lines) are not formed over contacts formed outside the active region of the memory array 1056. One or more contacts formed outside the active region of the memory array 1056 may be used to determine overlap of another feature (e.g., conductive lines) formed in the active region of the memory array 1056 relative to contacts formed outside the active region of the memory array 1056. This may be beneficial, for example, when contacts of the active region of the memory array are blocked or obscured by conductive lines of the active region such that it is difficult, if not impossible, to determine the offset of the conductive lines of the active region relative to the contacts of the active region. Overlap of a reference contact relative to the conductive lines of the active region of the memory array 1056 may indicate overlap of contacts of the active region of the memory array 1056 relative to the conductive lines of the active region of the memory array 1056.

[0046] Figures 11A to 11E Example processing steps for pitch multiplication are shown according to several embodiments of the present invention. Figures 11A to 11E The processing steps shown in Figure 2 The contact layer 200 and / or Figure 5 The conductive line layer 520 is shown in FIG.

[0047] Fig.11A A photoresist material 1170 is depicted formed over a substrate material 1172. The photoresist material 1170 has a first width 1171. Each instance of the photoresist material 1170 is separated from another instance of the photoresist material 1170 by a first distance (eg, a first pitch) 1174.

[0048] Fig. 11B The photoresist material 1170 is depicted after subsequent processing steps, wherein the photoresist material 1170 is trimmed from a first width 1171 to a second width 1175 .

[0049] Fig. 11C The trimmed photoresist material 1170 is depicted after subsequent processing steps in which a spacer material 1176 is formed (eg, deposited) over the trimmed photoresist material 1170 and the substrate material 1172 .

[0050] Fig.11D The spacer material 1176 is depicted after a subsequent processing step in which portions of the spacer material 1176 are removed (eg, etched). The spacer material 1176 may be removed from the top of the trimmed photoresist material 1170. For example, Fig.11D As shown in , the top of the trimmed photoresist material 1170 can be coplanar with the top of the adjacent spacer material 1176.

[0051] Fig.11E The spacer material 1176 is depicted after a subsequent processing step in which the photoresist material 1170 is removed. Thus, each instance of the spacer material 1176 is separated from another instance of the spacer material 1176 by a second distance (e.g., a second pitch) 1177. The second distance 1177 can be half of the first distance 1174.

[0052] Fig.12 1 is a flow chart of an example method 1280 for determining an overlay of features of a memory array according to several embodiments of the present invention. Unless explicitly stated, the elements of the methods described herein are not limited to a particular order or sequence. In addition, several method embodiments described herein or elements thereof may be performed at the same or substantially the same time point.

[0053] At block 1281 , method 1280 may include forming a plurality of contacts on a working surface.

[0054] At block 1282, method 1280 may include selectively forming a first portion of the conductive wire layer in contact with the contact and a second portion of the conductive wire layer. The first portion of the conductive wire layer formed above the working surface may be separated from the second portion of the conductive wire layer formed above the working surface by a gap. Selectively forming the first portion and the second portion of the conductive wire layer may include applying a chopping mask to the first portion and the second portion of the conductive wire layer.

[0055] At block 1283, method 1280 may include determining an overlay of at least one of the contacts formed in the gap above the working surface relative to one of the conductive lines formed above the working surface. Determining the overlay of at least one of the contacts may include determining an offset between at least one of the contacts and one of the conductive lines in line with the contact formed above the working surface.

[0056] Forming a plurality of contacts may include selectively forming a first portion of a contact layer on the working surface and a second portion of a contact layer on the working surface. The first portion of the contact layer may be formed above the working surface in a gap. The second portion of the conductive line layer may be formed in another gap that separates the first portion of the contact layer formed above the working surface from the second portion of the contact layer formed above the working surface. In several embodiments, method 1280 may further include determining an overlay of at least one of the contacts formed above the working surface in a gap relative to a conductive line formed above the working surface in another gap. In several embodiments, method 1280 may further include determining an overlay of at least one of the contacts formed above the working surface in a gap relative to a conductive line formed above the working surface in another gap and in line with the contact formed in the gap.

[0057] Fig.13 1384 is a flow chart of an example method 1384 for determining an overlay of features of a memory array according to several embodiments of the present invention. Unless explicitly stated, the elements of the methods described herein are not limited to a particular order or sequence. In addition, several method embodiments described herein or elements thereof may be performed at the same or substantially the same time point.

[0058] At block 1385, method 1384 may include selectively forming a first portion of a contact layer and a second portion of a contact layer on the working surface. The first portion of the contact layer formed over the working surface is separated from the second portion of the contact layer formed over the working surface by a gap.

[0059] At block 1386, the method 1384 may include selectively forming a first portion of a conductive wire layer and a second portion of the conductive wire layer on the working surface in contact with the first portion and the second portion of the contact layer formed over the working surface. Selectively forming the first portion and the second portion of the conductive wire layer may include applying a chop mask to the first portion and the second portion of the conductive wire layer.

[0060] At block 1387, the method 1384 may include determining an overlay of at least one of the conductive lines formed in the gap above the working surface relative to one of the contacts formed above the working surface. Determining the overlay of at least one of the conductive lines may include determining an offset between at least one of the conductive lines relative to one of the contacts formed above the working surface in line with the conductive line.

[0061] Fig.14 1488 is a flow chart of an example method 1488 for determining an overlay of features of a memory array according to several embodiments of the present invention. Unless explicitly stated, the elements of the methods described herein are not limited to a particular order or sequence. In addition, several method embodiments described herein or elements thereof may be performed at the same or substantially the same time point.

[0062] At block 1489, method 1488 may include forming features of a first feature layer of an active region of the memory array.

[0063] At block 1490, method 1488 may include applying a chopping mask to a second feature layer of the memory array to form features of a first portion of the second feature layer in an active region of the memory array and to form features of a second portion of the second feature layer outside of the active region of the memory array.

[0064] In a number of embodiments, method 1488 may further include determining an overlay of one of the formed features of the first feature layer of the active region relative to one of the formed features of a second portion of the second feature layer outside of the active region of the memory array.

[0065] In several embodiments, method 1488 may further include orienting the features of the second portion of the second feature layer to be collinear with the features of the first feature layer. Orienting the features of the second portion of the second feature layer may include rotating the features of the second portion of the second feature layer based on a translation of the features of the second portion of the second feature layer relative to the features of the first feature layer. The translation of the features may include a horizontal (e.g., x-direction) component and / or a vertical (e.g., y-direction) component.

[0066] In several embodiments, method 1488 may further include, before forming features of the first feature layer, forming a photoresist material having a first pitch on the working surface and trimming the photoresist material. A spacer material may be formed over the trimmed photoresist material. A portion of the spacer material in contact with a top surface of the trimmed photoresist material may be removed. The trimmed photoresist material may be removed so that the spacer material has a second pitch that is approximately half of the first pitch.

[0067] Fig.15 1 is a flow chart of an example method 1591 for determining an overlay of features of a memory array according to several embodiments of the present invention. Unless explicitly stated, the elements of the methods described herein are not limited to a particular order or sequence. In addition, several method embodiments described herein or elements thereof may be performed at the same or substantially the same time point.

[0068] At block 1592, method 1591 may include determining an overlay of a contact of the memory array with a conductive line of the memory array by determining an overlay of one of the conductive lines of the memory array with a reference contact formed over the chip and external to the memory array.

[0069] In several embodiments, method 1591 may further include, before determining the overlay, forming contacts of the memory array on the working surface and forming a reference contact on a portion of the working surface outside of an active area of ​​the memory array. Method 1591 may further include extending an application region of the chop mask to the contact layer to simultaneously form the contacts and the reference contact.

[0070] In the above detailed description of the invention, reference is made to the accompanying drawings which form a part of the invention and in which is shown by way of illustration how one or more embodiments of the invention may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the invention, and it is to be understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the invention.

[0071] It should be understood that the terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" include singular and plural referents, unless the context clearly dictates otherwise, as do "several", "at least one", and "one or more" (e.g., several memory arrays may refer to one or more memory arrays), and "multiple" is intended to refer to more than one such thing. In addition, throughout this application, the words "may" and "can" are used in a permissive sense (i.e., it is possible, can) rather than a mandatory sense (i.e., must). The term "including" and its derivatives mean "including but not limited to". The term "coupled" and "coupling" means physically connected directly or indirectly, and unless otherwise stated, may include wireless connections for accessing and / or for moving (transmitting) instructions (e.g., control signals, address signals, etc.) and data (as the case may be).

[0072] Although example embodiments have been depicted and described herein (including various combinations and configurations of semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, nitride materials, buffer materials, etching chemistries, etching processes, solvents, memory devices, memory cells, sidewalls of openings and / or trenches, and other materials and / or components associated with the overlay determining features of a memory array), embodiments of the invention are not limited to the combinations explicitly recited herein. Combinations and configurations of semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, nitride materials, buffer materials, etching chemistries, etching processes, solvents, memory devices, memory cells, sidewalls of openings and / or trenches associated with the overlay determining features of a memory array other than those disclosed herein are expressly included within the scope of the invention.

[0073] Although specific embodiments have been depicted and described herein, it will be understood by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present invention is intended to cover adaptations or changes to one or more embodiments of the present invention. It should be understood that the above description has been made in an illustrative manner and not in a restrictive manner. Upon reviewing the above description, the combinations described above and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of one or more embodiments of the present invention includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present invention should be determined with reference to the appended claims together with the full scope of equivalents enjoyed by such claims.

[0074] In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of simplifying the invention. The inventive method should not be interpreted as reflecting an intention that the disclosed embodiments of the invention must use more features than those explicitly recited in each claim. On the contrary, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment.

Claims

1. A method for memory operation, comprising: forming a plurality of contacts on the working surface; selectively forming a first portion of the conductive line layer and a second portion of the conductive line layer in contact with the plurality of contact elements, wherein the first portion of the conductive line layer formed above the working surface is separated from the second portion of the conductive line layer formed above the working surface by a gap, such that the conductive line layer is not formed above the working surface in the gap; and An overlay of at least one of the plurality of contacts formed above the working surface in the gap relative to one of the conductive lines formed above the working surface is determined. 2 . The method of claim 1 , wherein selectively forming the first and second portions of the conductive line layer comprises applying a chop mask to the first and second portions of the conductive line layer.

3. The method of claim 1 , wherein determining the superposition of the at least one of the contacts comprises determining an offset between the at least one of the contacts and one of the conductive lines formed above the working surface in line with the contact.

4. The method according to claim 1, wherein: Forming the plurality of contacts includes selectively forming a first portion of a contact layer on the working surface and forming a second portion of the contact layer on the working surface such that: The first portion of the contact layer is formed in the gap over the working surface; and The second portion of the conductive line layer is formed in another gap that separates the first portion of the contact layer formed over the working surface from the second portion of the contact layer formed over the working surface.

5. The method of claim 4, further comprising determining an overlay of at least one of the contacts formed in the gap above the working surface relative to a conductive line formed in the other gap above the working surface.

6. The method of claim 4 further comprising determining an overlay of at least one of the contacts formed in the gap above the working surface relative to the conductive line formed in the other gap above the working surface and in line with the contact formed in the gap.

7. A method for memory operation, comprising: selectively forming a first portion of a contact layer and a second portion of the contact layer on a working surface, wherein the first portion of the contact layer formed above the working surface is separated from the second portion of the contact layer formed above the working surface by a gap, such that the contact layer is not formed above the working surface in the gap; selectively forming a first portion of a conductive line layer and a second portion of the conductive line layer on the working surface in contact with the first portion and the second portion of the contact layer formed above the working surface; and An overlay of at least one of the conductive lines formed above the working surface in the gap relative to one of the contacts formed above the working surface is determined. 8 . The method of claim 7 , wherein selectively forming the first and second portions of the conductive line layer comprises applying a chopping mask to the first and second portions of the conductive line layer.

9. The method of claim 7, wherein determining the superposition of the at least one of the conductive lines comprises determining an offset of the at least one of the conductive lines relative to one of the contacts formed above the working surface in line with the conductive line.

10. A method for memory operation, comprising: Features of a first feature layer forming an active region of a memory array; Applying a chopping mask to a second feature layer of the memory array to: features of a first portion of the second feature layer forming the active region of the memory array; and forming features of a second portion of the second feature layer outside the active area of ​​the memory array; and An overlay of one of the formed features of the first feature layer of the active region relative to one of the formed features of the second portion of the second feature layer outside of the active region of the memory array is determined. 11 . The method of claim 10 , further comprising orienting features of the second portion of the second feature layer to be collinear with features of the first feature layer.

12. The method of claim 11, wherein orienting the features of the second portion of the second feature layer comprises rotating the features of the second portion of the second feature layer based on a translation of the features of the second portion of the second feature layer relative to the features of the first feature layer.

13. The method of claim 10, further comprising, before forming the features of the first feature layer: forming a photoresist material having a first pitch on the working surface; trimming the photoresist material; forming a spacer material on the trimmed photoresist material; removing portions of the spacer material in contact with a top surface of the trimmed photoresist material; and The trimmed photoresist material is removed such that the spacer material has a second pitch that is approximately half of the first pitch.

14. A memory device comprising: a first plurality of contacts formed over a first portion of the working surface corresponding to an active area of ​​the memory array; a plurality of conductive lines of the memory array formed to contact the first plurality of contacts; and A second plurality of contacts is formed over a second portion of the working surface such that the second plurality of contacts are separated from the plurality of conductive lines.

15. The memory device of claim 14, wherein the second portion of the working surface is outside the active area of ​​the memory array.

16. The memory device of claim 14, wherein a width of the contact is at most equal to a width of the conductive line.

17. A method for memory operation, comprising: An overlap of a contact of the memory array with the conductive line of the memory array is determined by determining an overlap of one of the conductive lines of the memory array with a reference contact formed above a chip and external to the memory array.

18. The method of claim 17, further comprising, before determining the superposition: forming the contacts of the memory array on a working surface; and The reference contact is formed on a portion of the working surface outside of an active area of ​​the memory array.

19. The method of claim 18, further comprising extending an application region of a chop mask to a contact layer to simultaneously form the contact and the reference contact.

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