Device for electrostatic discharge protection

Abstract

Embodiments of the present disclosure relate to devices for electrostatic discharge protection. A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed at an interface between the semiconductor substrate and the semiconductor layer. A first well and a second well of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconductor layer, the second well, and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well, and the second region form a second lateral thyristor. The buried region and the semiconductor substrate form a Zener diode that sets a trigger voltage of the lateral thyristors.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. 1903659, filed on April 5, 2019, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates generally to electronic circuits, and more specifically to a device for protecting electronic circuits from electrostatic discharge. Background Technology

[0004] Devices that protect electronic circuits from electrostatic discharge are known in the art, including lateral thyristors to dissipate overvoltages caused by electrostatic discharge.

[0005] However, known structures of electrostatic discharge protection devices based on lateral thyristors have various drawbacks.

[0006] The goal is to at least partially overcome some of these shortcomings. Summary of the Invention

[0007] To achieve this objective, an embodiment provides a device for electrostatic discharge protection, comprising: a semiconductor substrate of a first conductivity type coated with a semiconductor layer of a second conductivity type; a first buried region of the second conductivity type, the first buried region having a doping level greater than that of the semiconductor layer at the interface between the substrate and the semiconductor layer; a first well and a second well of the first conductivity type formed in the semiconductor layer on one side of the semiconductor layer opposite to the substrate surface; a second region of the second conductivity type formed in the first well on one side of the first well opposite to the substrate surface; and a third region of the second conductivity type formed in the second well on one side of the second well opposite to the substrate surface, wherein the first well and the second region are connected to a first connection terminal of the device, and the second well and the third region are connected to a second connection terminal of the device, the first well, the semiconductor layer, the second well, and the third region form a first lateral thyristor, and the second well, the semiconductor layer, the first well, and the second region form a second lateral thyristor.

[0008] According to one embodiment, the first well and the second well are laterally separated from each other only by a portion of the semiconductor layer.

[0009] According to one embodiment, the device further includes a stop channel region of a second conductivity type having a doping level greater than that of the semiconductor layer. The stop channel region is formed in the semiconductor layer on one side of the surface opposite to the substrate and laterally separates the first well and the second well.

[0010] According to one embodiment, viewed from above, the stop channel region completely surrounds each of the first and second wells.

[0011] According to one embodiment, the device includes a first vertical insulating wall that, when viewed from top, surrounds a first well and a second well, the first insulating wall extending across the entire thickness of the semiconductor layer and across the entire thickness of the buried layer.

[0012] According to one embodiment, the device further includes a second vertical insulating wall and a third vertical insulating wall in a portion of the device excluding the buried region, the second vertical insulating wall and the third vertical insulating wall laterally defining the first diode and the second diode, respectively, which are defined by a junction between the substrate and the semiconductor layer.

[0013] According to one embodiment, a portion of the semiconductor layer laterally defined by a second vertical insulating wall is connected to a second connection terminal of the device via a contact area, and a portion of the semiconductor layer laterally defined by a third vertical insulating wall is connected to a first connection terminal of the device via a contact area.

[0014] According to one embodiment, a first buried region forms a PN junction together with a substrate, the PN junction defining a Zener diode, and the avalanche voltage of the first Zener diode determines the trigger threshold of the protection device.

[0015] According to one embodiment, the trigger threshold is between 5 volts and 20 volts.

[0016] According to one embodiment, the first conductivity type and the second conductivity type are P-type and N-type, respectively. Attached Figure Description

[0017] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments, taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 This is a simplified cross-sectional view of an example of a device for electrostatic discharge protection;

[0019] Figure 2 This is a simplified cross-sectional view of an example of a device for electrostatic discharge protection according to the first embodiment;

[0020] Figure 3 This is a simplified cross-sectional view of an example of a device for electrostatic discharge protection according to the second embodiment;

[0021] Figure 4 yes Figure 3 A simplified top view of a variant of the device;

[0022] Figure 5 yes Figure 3A simplified top view of another variant of the device;

[0023] Figure 6 This is a simplified cross-sectional view of an example of a device for electrostatic discharge protection according to the third embodiment; and

[0024] Figure 7 This is a simplified cross-sectional view of an example of a device for electrostatic discharge protection according to the fourth embodiment. Detailed Implementation

[0025] In different figures, the same elements are designated by the same reference numerals. In particular, structural and / or functional elements common to different embodiments can be designated by the same reference numerals and can have the same structure, dimensions, and material properties.

[0026] For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, electronic circuits that can be protected by the described protective devices are not described in detail; the described embodiments are compatible with common electronic circuits that require protection against electrostatic discharge.

[0027] Throughout this disclosure, the term "connection" is used to specify a direct electrical connection between circuit elements, wherein there are no intermediate elements other than conductors, while the term "coupling" is used to specify an electrical connection between circuit elements, which may be direct or may be via one or more intermediate elements.

[0028] In the following description, when terms that define absolute position (such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc.) or relative position (such as the terms “above”, “below”, “up”, “down”, etc.) or terms that define direction (such as the terms “horizontal”, “vertical”, etc.) are used, they refer to the orientation of the figures unless otherwise specified. It should be understood that in practice, the described devices may be oriented differently.

[0029] The terms “approximately,” “substantially,” and “approximately” are used herein to indicate a tolerance of plus or minus 10%, preferably plus or minus 5%, for the value under discussion.

[0030] Figure 1 This is a simplified cross-sectional view of an example of an electronic circuit (not shown) for electrostatic discharge protection device 100.

[0031] Device 100 is, for example, a discrete integral component different from the circuit to be protected. Device 100 includes at least two connection terminals configured to be connected to two different connection terminals of the circuit to be protected, respectively.

[0032] exist Figure 1 In the example, device 100 includes two connection terminals IO1 and IO2, which are configured to be connected to two different connection terminals of the circuit to be protected. Figure 1 The device 100 is a bidirectional protection device, that is, the device 100 is capable of eliminating positive and negative overvoltages that may occur between its terminals IO1 and IO2, and the device 100 is configured to receive positive and negative voltages between its terminals IO1 and IO2 under normal operation (in the absence of overvoltage).

[0033] Device 100 includes a p-type doped semiconductor substrate 101, such as a silicon substrate.

[0034] Device 100 also includes a lightly doped N-type layer 103, such as an epitaxial layer, which coats the upper surface of substrate 101. Layer 103 extends over, for example, the entire upper surface of substrate 101.

[0035] Device 100 also includes a heavily doped N-type buried region 105 disposed at the interface between substrate 101 and layer 103. In this example, region 105 extends in the upper portion of substrate 101 and the lower portion of layer 103. For example, region 105 is formed prior to the epitaxial growth step of layer 103 by implanting N-type dopant elements on the front surface side of substrate 101. In the example shown, region 105 is laterally positioned, i.e., region 105 does not extend over the entire surface of substrate 101. In the example shown, region 105 is located in the central portion of the device.

[0036] Device 100 also includes a first lateral thyristor SCR1, which includes two local P-type wells 107 and 109 formed in the upper portion of layer 103, and a local N-type region 111 formed in the upper portion of well 109. In this example, wells 107 and 109 are separated. Each well extends vertically from the upper surface of layer 103 across a thickness less than the thickness of layer 103. For example, wells 107 and 109 have substantially the same depth and the same doping level. In this example, wells 107 and 109 are arranged opposite to buried region 105 (vertically corresponding to buried region 105). Region 111 extends laterally over only a portion of the surface of well 109, and region 111 extends vertically from the upper surface of well 109 across a thickness less than the thickness of well 109. The transverse thyristor SCR1 is a PNPN type thyristor, which is formed by a P-type well 107, a layer 103, a P-type well 109, and an N-type region 111. The anode region of the thyristor SCR1 corresponds to the P-type well 107, and the cathode region of the thyristor SCR1 corresponds to the N-type region 111.

[0037] Device 100 also includes a second lateral thyristor SCR2, which includes two local P-type wells 113 and 115 formed in the upper portion of layer 103, and a local N-type region 117 formed in the upper portion of well 115. In this example, wells 113 and 115 are separate from and distinct from wells 107 and 109. Each of wells 113 and 115 extends vertically from the upper surface of layer 103 across a thickness less than the thickness of layer 103. For example, wells 113 and 115 have substantially the same depth and the same doping level as wells 107 and 109. In this example, wells 113 and 115 are arranged opposite to buried region 105 (vertically corresponding to buried region 105). Region 117 extends laterally over only a portion of the surface of well 115, and extends vertically from the upper surface of well 115 across a thickness less than the thickness of well 115. For example, region 117 has essentially the same depth and doping level as region 111. The lateral thyristor SCR2 is a PNPN type thyristor, formed by a P-type well 113, layer 103, a P-type well 115, and an N-type region 117. The anode region of thyristor SCR2 corresponds to the P-type well 113, and the cathode region of thyristor SCR2 corresponds to the N-type region 117.

[0038] In this example, thyristor SCR1 is completely laterally surrounded by a first vertical insulating wall 119, and thyristor SCR2 is completely laterally surrounded by a second vertical insulating wall 121. Each of the insulating walls 119 and 121 laterally separates thyristor SCR1 and thyristor SCR2. Insulating walls 119 and 121 are made of, for example, silicon oxide. In this example, each of the insulating walls 119 and 121 extends vertically from the upper surface of layer 103, across the entire thickness of layer 103 and the entire thickness of region 105, and terminates in substrate 101. In this example, buried region 105 extends laterally below the entire lower surface of the portion of layer 103 laterally defined by insulating wall 119, and laterally across the entire lower surface of the portion of layer 103 defined by insulating wall 121.

[0039] A portion of buried region 105 laterally defined by insulating wall 119 forms a PN junction together with substrate 101, defining a first Zener diode DZ1. The anode region of Zener diode DZ1 is formed by substrate 101, and the cathode region of Zener diode DZ1 is formed by the portion of region 105 laterally defined by insulating wall 119. Similarly, a portion of buried region 105 laterally defined by insulating wall 121 forms a PN junction together with substrate 101, defining a second Zener diode DZ2. The anode region of Zener diode DZ2 is formed by substrate 101, and the cathode region of Zener diode DZ2 is formed by the portion of region 105 laterally surrounded by insulating wall 121.

[0040] Device 100 also includes a first diode D1, which is located in the peripheral region where the buried region 105 is absent. The first diode D1 is defined by a PN junction between substrate 101 and layer 103. Diode D1 is laterally surrounded by a vertical insulating wall 123, which has the same properties as insulating walls 119 and 121. Wall 123 laterally separates diode D1 from thyristors SCR1 and SCR2. In this example, insulating wall 123 extends vertically from the upper surface of layer 103, across the entire thickness of layer 103, and terminates in substrate 101. The anode region of diode D1 is formed by substrate 101, and the cathode region of diode D1 is formed by the portion of layer 103 laterally surrounded by insulating wall 123.

[0041] Device 100 also includes a second diode D2, which is located in the peripheral region where the buried region 105 is absent. The second diode D2 is defined by a PN junction between substrate 101 and layer 103. Diode D2 is laterally surrounded by a vertical insulating wall 125, which has the same properties as insulating walls 119, 121, and 123. Wall 125 laterally separates diode D2 from thyristors SCR1 and SCR2, as well as diode D1. In this example, insulating wall 125 extends vertically from the upper surface of layer 103, across the entire thickness of layer 103, and terminates in substrate 101. The anode region of diode D2 is formed by substrate 101, and the cathode region of diode D2 is formed by the portion of layer 103 laterally surrounded by insulating wall 125.

[0042] In the example shown, device 100 also includes a heavily doped N-type contact region 127 above the cathode region of diode D1, and device 100 also includes a heavily doped N-type contact region 129 above the cathode region of diode D2. Each of regions 127 and 129 extends vertically from the upper surface of layer 103 across a thickness less than the thickness of layer 103. For example, regions 127 and 129 have substantially the same depth and the same doping level.

[0043] Figure 1 The device 100 also includes an insulating passivation layer 131, which is made of, for example, silicon oxide, and is coated on the upper surface of layer 103. In this example, the passivation layer is disposed on top of and in contact with the upper surface of layer 103, and is disposed on top of and in contact with the upper surfaces of insulating walls 119, 121, 123, and 125. The passivation layer 131 includes a plurality of locally through-holes that allow restoration of electrical contacts in different semiconductor regions of the device. More specifically, layer 131 includes: an opening positioned relative to a portion of the upper surface of contact area 127; an opening positioned relative to a portion of the upper surface of contact area 129; an opening positioned relative to a portion of the upper surface of well 107; an opening positioned relative to a portion of the upper surface of well 113; an opening positioned relative to a portion of the upper surface of region 111 and a portion of the upper surface of well 109 not occupied by region 111; and an opening positioned relative to a portion of the upper surface of region 117 and a portion of the upper surface of well 115 not occupied by region 117.

[0044] The device 100 further includes, on the upper surface side of the passivation layer 131: a first metallization 133, which contacts the exposed portions of the upper surface of the P-type well 107 and the exposed portions of the upper surface of the N-type region 129; a second metallization 135, which contacts the exposed portions of the upper surface of the P-type well 109 and the exposed portions of the upper surface of the N-type region 111; a third metallization 137, which contacts the exposed portions of the upper surface of the P-type well 115 and the exposed portions of the upper surface of the N-type region 117; and a fourth metallization 139, which contacts the exposed portions of the upper surface of the P-type well 113 and the exposed portions of the upper surface of the N-type region 127. Metallizations 133 and 137 are connected to the device's connection terminal IO1, and metallizations 135 and 139 are connected to the device's connection terminal IO2.

[0045] The p-type doping level of substrate 101 is, for example, from 9 × 10⁻⁶. 18 atoms / cm 3 Up to 5×10 19 atoms / cm 3 Within the range. The N-type doping level of layer 103 is, for example, from 5 × 10⁻⁶. 13 atoms / cm 3 Up to 2×10 14 atoms / cm 3 Within the range. The N-type doping level of the buried region 105 is, for example, from 1 × 10⁻⁶. 18 atoms / cm 3 Up to 1×1019 atoms / cm 3 Within this range. The p-type doping levels of wells 107, 109, 113, and 115 are, for example, from 1 × 10⁻⁶. 18 atoms / cm 3 Up to 1×10 19 atoms / cm 3 Within the range. The N-type doping levels in regions 111 and 117 are, for example, from 5 × 10⁻⁶. 18 atoms / cm 3 Up to 5×10 19 atoms / cm 3 The thickness of substrate 101 is, for example, in the range of 40 μm to 300 μm. The thickness of layer 103 is, for example, in the range of 5 μm to 15 μm. The thickness of buried region 105 is, for example, in the range of 2 μm to 5 μm. The thickness of wells 107, 109, 113, and 115 is, for example, in the range of 1 μm to 3 μm. The thickness of regions 111, 117, 129, and 127 is, for example, in the range of 0.5 μm to 2.5 μm.

[0046] Now will describe Figure 1 The operation of device 100.

[0047] This section considers electrostatic discharge (ESD) that results in a positive overvoltage peak between terminals IO1 and IO2 of device 100, such as ESD as defined in Part 4-2 or Part 4-5 of standard IEC 61000, or ESD defined by one of the following models: HBM (Human Body Model), MM (Machine Model), and CDM (Charging Device Model).

[0048] Once the overvoltage reaches the avalanche threshold of the Zener diode DZ1 (e.g., in the range of 5V to 20V, such as approximately 7V), current flows from terminal IO1 to terminal IO2 through the following: metallization 133, P-well 107, Zener diode DZ1, substrate 101, diode D1, contact region 127, and metallization 139. This conduction path, also known as the startup path, in... Figure 1 The diagram is illustrated by arrow 141. The starting current turns on thyristor SCR1, which then dissipates all current due to overvoltage.

[0049] In the event of a negative overvoltage between terminals IO1 and IO2 of device 100, the operation is similar, except that the startup path passes through metallization 139, P-well 113, Zener diode DZ2, substrate 101, diode D2, contact region 129, and metallization 133. The startup current turns on thyristor SCR2, which then dissipates all current due to the overvoltage.

[0050] Figure 1 The limitation of device 100 is that, during the conduction phase of thyristor SCR1 or thyristor SCR2, parasitic current flows through terminals IO1 and IO2, but not through Zener diode DZ1 or Zener diode DZ2. Under positive overvoltage, this current corresponds to the leakage current of the lateral PNP transistor formed by well 107, layer 103, and well 109, and under negative overvoltage, this current corresponds to the leakage current of the lateral PNP transistor formed by well 113, layer 103, and well 115. This parasitic conduction path (under positive overvoltage) in... Figure 1 The diagram is illustrated by arrow 143. Parasitic current causes Zener diode DZ1 or DZ2 to cross the avalanche threshold delay, thus delaying the turn-on of thyristor SCR1 or SCR2. In other words, in the event of an overvoltage, parasitic current increases the time required for the turn-on protection device to operate.

[0051] Figure 2 This is a simplified cross-sectional view of an example of a device 200 for electrostatic discharge protection according to the first embodiment.

[0052] Figure 2 The device 200 includes with Figure 1 The devices 100 share common elements. These common elements will not be described in detail below. In the remainder of the description, only elements related to... Figure 1 The difference between the devices 100.

[0053] Figure 2 Device 200 and Figure 1 The main difference between device 100 and device 200 is that device 200 also includes a first heavily doped N-type stop channel region 201, which is located above the portion of layer 103 laterally defined by insulating walls 119, separating the P-type well 107 of thyristor SCR1 from the P-type well 109 of the same thyristor SCR1. The stop channel region extends vertically downward from the upper surface of layer 103 to a depth less than the thickness of layer 103, for example, less than the depth of wells 107 and 109. The doping level of the stop channel region 201 is, for example, from 5 × 10⁻⁶. 18 atoms / cm 3 Up to 5×10 19 atoms / cm 3 Within a certain range. The depth of the stop channel region 201 is, for example, in the range of 10% to 80% of the depth of the P-type wells 107 and 109. As an example, the stop channel region 201 has essentially the same depth and the same doping level as the N-type regions 111 and 117 and / or the N-type regions 127 and 129.

[0054] The stopping channel region 201 is separated from, for example, P-type wells 107 and 109. As an example, viewed from above, the stopping channel region 201 has the shape of two adjacent rings that completely surround wells 107 and 109, respectively. Thus, viewed from above, the stopping channel region 201 not only laterally separates wells 107 from wells 109, but also laterally separates each of wells 107 and 109 from the vertical insulating wall 119.

[0055] The stop channel region 201 remains floating, i.e., not connected to the connection metallization of the device. In the example shown, the upper surface of the stop channel region 201 contacts the lower surface of the passivation layer 131 over the entire upper surface of the stop channel region 201.

[0056] Figure 2 The device 200 also includes a second heavily doped N-type stop channel region 203, which is located in the upper portion of the layer 103 laterally defined by the insulating wall 121, separating the P-type well 113 of the thyristor SCR2 from the P-type well 115 of the same thyristor SCR2. For example, the stop channel region 203 has substantially the same depth and the same doping level as the stop channel region 201.

[0057] The stopping channel region 203 is separated from, for example, P-type wells 113 and 115. As an example, viewed from above, the stopping channel region 203 has the shape of two adjacent rings that completely surround wells 113 and 115, respectively. Thus, viewed from above, the stopping channel region 203 not only laterally separates wells 113 and 115, but also laterally separates each of wells 113 and 115 from the vertical insulating wall 121.

[0058] The stop channel region 203 remains floating, i.e., not connected to the connection metallization of the device. In the example shown, the upper surface of the stop channel region 203 contacts the lower surface of the passivation layer 131 over the entire upper surface of the stop channel region 203.

[0059] and Figure 1 Compared to device 100, the stop channel region 201 enables a reduction in the gain of the lateral PNP transistor formed between well 107, layer 103, and well 109. Under the condition of a positive overvoltage between terminals IO1 and IO2 of the device, during the device startup phase, the parasitic current flowing in the transistor ( Figure 1 The parasitic conduction path 143 is thus reduced. The conduction threshold of the Zener diode DZ1 is therefore reached more quickly. Relative to Figure 1 This device allows for a reduction in the time required for protection to be triggered.

[0060] Similarly, the stop channel region 203 enables the reduction of the gain of the lateral PNP transistors formed between well 113, layer 103 and well 115, and thus reduces the protection trigger time when a negative overvoltage occurs between the device's connection terminals IO1 and IO2.

[0061] Figure 3 This is a simplified cross-sectional view of an example of a device 300 for electrostatic discharge protection according to the second embodiment.

[0062] Figure 3 Device 300 includes and Figure 2 The devices 200 share common elements. These common elements will not be described in detail below. In the remainder of this description, only those relative to... Figure 2 The difference between the devices 200.

[0063] Figure 3 Device 300 and Figure 2 The main difference between device 200 and device 300 is that, in device 300, the P-type wells of thyristors SCR1 and SCR2 are shared, which makes it possible to eliminate Figure 2 Two of the four P-type wells in the structure.

[0064] More specifically, in Figure 3 Among the 300 devices, Figure 2 The P-type wells 107, 109, 113, and 115 and the N-type regions 111 and 117 of the device are replaced by two local P-type wells 301 and 303 and two local N-type regions 305 and 307. The two local P-type wells 301 and 303 are formed in the upper portion of layer 103, and the two local N-type regions 305 and 307 are formed in the upper portions of wells 301 and 303, respectively. The P-type wells 301 and 303 are separate. Each well extends vertically from the upper surface of layer 103 across a thickness less than the thickness of layer 103. For example, wells 301 and 303 substantially have the same... Figure 2 Device 200 has wells 107, 109, 113, and 115 with the same depth and the same doping level. Wells 301 and 303 are arranged opposite to buried region 105 (vertically corresponding to buried region 105). N-type region 305 extends laterally over only a portion of the surface of well 301, and extends vertically from the upper surface of well 301 across a thickness less than the thickness of well 301. Similarly, N-type region 307 extends laterally over only a portion of the surface of well 303, and extends vertically from the upper surface of well 303 across a thickness less than the thickness of well 303. For example, regions 305 and 307 have substantially the same depth and the same doping level as regions 111 and 117.

[0065] The transverse thyristor SCR1 is a PNPN type thyristor, which is formed by a P-type well 301, a layer 103, a P-type well 303, and an N-type region 307. The anode region of the thyristor SCR1 corresponds to the P-type well 301, and the cathode region of the thyristor SCR1 corresponds to the N-type region 307.

[0066] The transverse thyristor SCR2 is a PNPN type thyristor, which is formed by a P-type well 303, a layer 103, a P-type well 301, and an N-type region 305. The anode region of the thyristor SCR2 corresponds to the P-type well 303, and the cathode region of the thyristor SCR2 corresponds to the N-type region 305.

[0067] In this example, thyristors SCR1 and SCR2 are not laterally separated from each other by a vertical insulating wall. In other words, no vertical insulating wall extends between wells 301 and 303 of the device. However, the assembly including thyristors SCR1 and SCR2 is completely laterally surrounded by a vertical insulating wall 309, which replaces... Figure 2 The device has insulating walls 119 and 121. Insulating wall 309 is made of silicon oxide, for example. In this example, insulating wall 309 extends vertically from the upper surface of layer 103, across the entire thickness of layer 103 and the entire thickness of region 105, and terminates in substrate 101. In this example, region 105 extends laterally beneath the entire surface of the portion of layer 103 laterally defined by insulating wall 309.

[0068] A portion of the buried region 105, laterally defined by the insulating wall 309, forms a PN junction together with the substrate 101, which defines the Zener diode DZ. The anode region of the Zener diode DZ is formed by the substrate 101, and the cathode region of the Zener diode DZ is formed by the portion of region 105 laterally defined by the insulating wall 309.

[0069] picture Figure 2 The device is the same as 200. Figure 3 The device 300 also includes two diodes D1 and D2 defined by a PN junction between substrate 101 and layer 103, the two diodes D1 and D2 being located in the peripheral region where the buried region 105 is absent. Figure 2 As in the example, diode D1 is laterally defined by a vertical insulating wall 123, and diode D2 is laterally defined by a vertical insulating wall 125. Wall 123 laterally separates diode D1 from thyristors SCR1 and SCR2 and diode D2, and wall 125 laterally separates diode D2 from thyristors SCR1 and SCR2 and diode D1. In the example shown, compared with... Figure 2As in the example, device 300 also includes a heavily doped N-type contact region 127 above the cathode region of diode D1, and a heavily doped N-type contact region 129 above the cathode region of diode D2.

[0070] With Figure 2 The same as in the example, Figure 3 The device 300 also includes an insulating passivation layer 131, which is made of, for example, silicon oxide, and is coated on the upper surface of layer 103. In this example, the passivation layer 131 is disposed on top of and in contact with the upper surface of layer 103, and is disposed on top of and in contact with the upper surfaces of insulating walls 309, 121, 123, and 125. The passivation layer 131 includes a plurality of partially through-holes that allow the restoration of electrical contacts on different semiconductor regions of the device. More specifically, layer 131 includes: an opening positioned relative to a portion of the upper surface of contact region 127; an opening positioned relative to a portion of the upper surface of contact region 129; an opening positioned relative to a portion of the upper surface of region 305 and a portion of the upper surface of well 301 not occupied by region 305; and an opening positioned relative to a portion of the upper surface of region 307 and a portion of the upper surface of well 303 not occupied by region 307.

[0071] On the upper surface side of the passivation layer 131, Figure 3 The device 300 further includes: a first metallization 311, which contacts the exposed portions of the upper surfaces of the P-type well 301, the N-type region 305, and the N-type region 129; and a second metallization 313, which contacts the exposed portions of the upper surfaces of the P-type well 303, the N-type region 307, and the N-type region 127. The metallizations 311 and 313 are respectively connected to the device's connection terminals IO1 and IO2.

[0072] Figure 3 The device 300 also includes a heavily doped N-type stop channel region 315, which is located in the upper portion of the layer 103 laterally defined by the insulating wall 309, replacing the... Figure 2 The device 200 has stop channel regions 201 and 203. Viewed from the top, stop channel region 315 laterally separates P-type well 301 from P-type well 303. Stop channel region 315 extends vertically downward from the upper surface of layer 103 to a depth less than the thickness of layer 103, for example, extending downward to a depth less than the depth of wells 301 and 303. For example, stop channel region 315 substantially has the same characteristics as... Figure 2The stop channel regions 201 and 203 of device 200 have the same depth and the same doping level.

[0073] The stopping channel region 315 is separated from, for example, P-type traps 301 and 303. As an example, viewed from above, the stopping channel region 315 has the shape of two adjacent rings that completely surround traps 301 and 303, respectively. Thus, viewed from above, the stopping channel region 315 not only laterally separates traps 301 and 303, but also laterally separates each of traps 301 and 303 from the vertical insulating wall 309.

[0074] The stop channel region 315 remains floating, i.e., it is not connected to the connection metallization of the device. In the example shown, the upper surface of the stop channel region 315 contacts the lower surface of the passivation layer 131 over the entire upper surface of the stop channel region 315.

[0075] Figure 3 The operation of device 300 is similar to Figure 2 The operation of device 200.

[0076] More specifically, in the event of an electrostatic discharge that causes a positive overvoltage peak between terminals IO1 and IO2 of device 300, once the overvoltage reaches the avalanche threshold of the Zener diode DZ, current flows from terminal IO1 to terminal IO2 through: metallization 311, P-well 301, Zener diode DZ, substrate 101, diode D1, contact region 127, and metallization 313. This initiation current turns on thyristor SCR1, which then dissipates all current due to the overvoltage. In the case of a negative overvoltage between terminals IO1 and IO2, the operation is similar, except that the initiation path passes through metallization 313, P-well 303, Zener diode DZ, substrate 101, diode D2, contact region 129, and metallization 311. The initiation current turns on thyristor SCR2, which then dissipates all current due to the overvoltage.

[0077] With already about Figure 2 Similarly, as described, the stop channel region 315 enables the limiting of the gain of the lateral PNP transistor formed between the well 301, layer 103, and well 303, which enables the reduction of the protection trigger time in the event of a positive or negative overvoltage between the device's connection terminals IO1 and IO2.

[0078] and Figure 2 Compared to device 200, Figure 3 The device 300 also has the advantage of being more compact, due to the suppression of two P-type wells and a lateral insulating wall.

[0079] exist Figure 3 In the example, device 300 includes a unique P-type well 301 and a unique N-type region 305 connected to terminal IO1, and a unique P-type well 303 and a unique N-type region 307 connected to terminal IO2. Viewed from above, wells 301 and 303, as well as regions 305 and 307, have the shape of elongated strips (e.g., rectangles) parallel to each other. Well 301 and region 305 together form a first finger connected to terminal IO1 via metallization 311, and well 303 and region 307 together form a second finger connected to metallization 313.

[0080] To improve robustness, facilitate triggering, and / or symmetrize the behavior of the protection, the device may include, for example, as shown in... Figure 4 The diagram above shows several interlaced first fingers and / or several second fingers.

[0081] Figure 4 This is a top view illustrating an example of an interdigitated device, comprising alternating first and second fingers (three first fingers and two second fingers in the example shown), with the first fingers connected to terminal IO1 and the second fingers connected to terminal IO2. For clarity, in... Figure 4 Metallized bodies 311 and 313, diodes D1 and D2, insulating walls 123 and 125, and passivation layer 131 are not shown above.

[0082] exist Figure 4 In the example, viewed from above, the stop channel region 315 completely surrounds the P-type traps 301 and 303, and laterally separates the traps 301 and 303 from each other. The insulating outer wall 309 completely surrounds the P-type traps 301 and 303 and the stop channel region 315, but does not laterally separate the traps 301 and 303 from each other.

[0083] exist Figure 4 In the example, each finger of the protection device includes an emitter short-circuit strip 401, which is formed by a portion of the finger's P-type well 301 (correspondingly, P-type well 303) not covered by the N-type region 305 (correspondingly, N-type region 307), and the emitter short-circuit strip is connected to the metallization 311 (correspondingly, metallization 313) of the connection between the finger and terminal IO1 (correspondingly, terminal IO2). Figure 4 (Not shown above). Viewed from above, the emitter short-circuit strip 401 is parallel to the strip formed by the P-type traps 301 and 303 and the N-type regions 305 and 307. Each emitter short-circuit strip 401 extends substantially along the entire length of the traps 301 and 303, along the long side of the traps. Figure 4In the device, the emitter short-circuit strip 401 is entirely positioned on the same side of the wells 301 and 303, for example in Figure 4 The left side of the orientation.

[0084] Figure 5 It is a diagram. Figure 4 A top view of a variant of the device. Figure 5 The variant is designed to further equalize the behavior of the protection and to increase the semiconductor surface area actually used for surge protection.

[0085] exist Figure 5 In the device, each finger of the protection device includes two separate emitter short-circuit strips 501A and 501B, which replace... Figure 4 Emitter short-circuit strip 401, emitter short-circuit strips 501A and 501B each extend approximately half the length of the P-type traps 301 and 303 of the finger, respectively. Strip 501A extends along the first side of the P-type trap of the finger. Figure 5 It is positioned on the right side of the orientation, and in the first half of the length of the trap ( Figure 5 It extends in the upper half of the orientation. Strip 501B runs along the opposite side of the finger's P-well ( Figure 5 The left side of the orientation is located, and in the second half of the length of the trap ( Figure 5 It extends into the lower half of the orientation.

[0086] Figure 6 This is a simplified cross-sectional view of an example of a device 600 for electrostatic discharge protection according to the third embodiment.

[0087] Device 600 includes and Figure 2 The devices 200 share common elements. These common elements will not be described in detail below. In the remainder of this description, only those relative to... Figure 2 The difference between the devices 200.

[0088] Figure 6 Device 600 and Figure 2 The main difference between device 200 and device 600 is that device 600 is unidirectional. That is, device 600 can dissipate positive and negative overvoltages that may occur between its terminals IO1 and IO2, but device 600 is configured to receive only the positive voltage between its terminals IO1 and IO2 during normal operation (in the absence of overvoltage).

[0089] More specifically, Figure 6 The device 600 includes: corresponding to Figure 2 The device 200 has a single thyristor SCR1, corresponding to Figure 2 The single Zener diode DZ of device 200, and corresponding to the Zener diode DZ1. Figure 2 The device 200 has a single diode D2. Specifically, Figure 6 Device 600 does not include Figure 2 The device 200 includes P-type wells 113 and 115, N-type regions 117 and 127, a stop channel region 203, lateral insulating walls 121 and 123, and metallizations 137 and 139. However, Figure 6 The device 600 includes a connection metallization 601, which is disposed on top of and in contact with the rear surface of the substrate 101, and is connected to the same connection terminal IO2 as the metallization 135.

[0090] In the event of an electrostatic discharge that causes a positive overvoltage peak between terminals IO1 and IO2 of device 600, once the overvoltage reaches the avalanche threshold of the Zener diode DZ, current flows from terminal IO1 to terminal IO2 through: metallization 133, P-well 107, Zener diode DZ, substrate 101, and metallization 601. This initiation current turns on the thyristor SCR, which then dissipates all current due to the overvoltage.

[0091] When a negative overvoltage occurs between terminals IO1 and IO2 of device 600, the overvoltage is directly dissipated by diode D.

[0092] With Figure 2 As in the example, the stop channel region 201 enables the reduction of the gain of the lateral PNP transistor formed between well 107, layer 103 and well 109 when a positive overvoltage occurs, and thus reduces the protection trigger time.

[0093] Figure 7 This is a simplified cross-sectional view of an example of a device 700 for electrostatic discharge protection according to the fourth embodiment.

[0094] Figure 7 The device 700 includes and Figure 3 The devices 300 share common elements. These common elements will not be described in detail below. In the remainder of the description, only those relative to... Figure 3 The difference between the 300 devices.

[0095] With Figure 3 Like in device 300, thyristor SCR1 and thyristor SCR2 in device 700 share the same two P-type wells 301 and 303. However, Figure 7 Device 700 and Figure 3 The difference between device 300 and other devices is that, Figure 7 Among the 700 devices, Figure 3The stop channel region 315 of device 300 is absent. Therefore, in device 700, P-type well 301 and P-type well 303 are laterally separated only through a portion of layer 103.

[0096] and Figure 3 Compared to the 300 device, Figure 7 The device 700 does not have the advantage of improved triggering provided by the stop channel region 315. However, compared with Figure 1 Compared to device 100, Figure 7 The device 700 has the advantage of being more compact due to the suppression of two P-type wells and a lateral insulating wall.

[0097] Figure 7 The embodiments may be adapted Figure 4 and Figure 5 A variation of. In other words, Figure 4 and 5 The stop channel region 315 of device 300 can be omitted.

[0098] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. In particular, the described embodiments are not limited to the examples of sizes and doping levels mentioned in this disclosure.

[0099] Furthermore, in the above example of the protective device, all conductivity types can be reversed.

Claims

1. A protective device for electrostatic discharge, comprising: Semiconductor substrate of the first conductivity type; A semiconductor layer of a second conductivity type, wherein the semiconductor layer is coated on the semiconductor substrate; The buried region of the second conductivity type has a doping level greater than that of the semiconductor layer at the interface between the semiconductor substrate and the semiconductor layer. The first well and the second well of the first conductivity type are formed in the semiconductor layer at a surface away from the semiconductor substrate; A second region of the second conductivity type is formed in the first well at the surface remote from the semiconductor substrate; A third region of the second conductivity type is formed in the second well at the surface remote from the semiconductor substrate; The first connection terminal of the device is connected to the first well and the second region; The second connection terminal of the device is connected to the second well and the third region; The third well connected to the first connection terminal, the semiconductor layer, the second well connected to the second connection terminal, and the third region form a first lateral thyristor. The third well is formed in the semiconductor layer at the surface away from the semiconductor substrate and is spaced apart from the second well. The fourth well connected to the second connection terminal, the semiconductor layer, the first well connected to the first connection terminal, and the second region form a second lateral thyristor. The fourth well is formed in the semiconductor layer at a surface remote from the semiconductor substrate and is spaced apart from the first well. The buried region forms a PN junction with the semiconductor substrate for a Zener diode, the Zener diode being connected to the semiconductor layer of the first lateral thyristor and the semiconductor layer of the second lateral thyristor, and the Zener diode being configured to trigger the switching on of at least one of the first and second lateral thyristors when the avalanche voltage of the Zener diode is exceeded, thereby forming a discharge path between the first connection terminal and the second connection terminal.

2. The device of claim 1, wherein the first well and the second well are laterally separated from each other only by a portion of the semiconductor layer.

3. The device according to claim 1, further comprising: A stop channel region having a doping level greater than that of the semiconductor layer, the stop channel region being formed in the semiconductor layer at the surface remote from the semiconductor substrate and being positioned to laterally separate the first well from the second well.

4. The device of claim 3, wherein, viewed from above, the stop channel region completely surrounds each of the first and second wells.

5. The device of claim 1, further comprising a first vertical insulating wall, viewed from top, surrounding the first well and the second well, the first vertical insulating wall extending across the entire thickness of the semiconductor layer and across the entire thickness of the buried region.

6. The device of claim 1, further comprising a second vertical insulating wall and a third vertical insulating wall, the second vertical insulating wall and the third vertical insulating wall being located in a portion of the interface between the semiconductor substrate and the semiconductor layer excluding the buried region, the second vertical insulating wall and the third vertical insulating wall laterally defining a first diode and a second diode, the first diode and the second diode being defined by a first junction and a second junction between the semiconductor substrate and the semiconductor layer, respectively.

7. The device of claim 6, wherein a portion of the semiconductor layer laterally defined by the second vertical insulating wall is connected to the second connection terminal via a contact area, and wherein a portion of the semiconductor layer laterally defined by the third vertical insulating wall is connected to the first connection terminal via a contact area.

8. The device of claim 1, wherein the avalanche voltage is determined by a trigger threshold ranging from 5 volts to 20 volts.

9. The device according to claim 1, wherein the first conductivity type and the second conductivity type are P-type and N-type, respectively.

Images