Display device

Abstract

This disclosure provides a display device comprising: a substrate having a display area, a peripheral area, and a pad area having a plurality of pixels; a plurality of fan-out wirings for transmitting image signals to the plurality of pixels; a first metal layer covering at least a portion of the plurality of fan-out wirings in the peripheral area; a second metal layer overlapping the first metal layer with at least a portion thereof; a third metal layer disposed on the second metal layer in the peripheral area; a first insulating layer disposed between the first metal layer and the second metal layer and having a first contact hole; a second insulating layer disposed between the second metal layer and the third metal layer and having a second contact hole; and a third insulating layer disposed between the plurality of fan-out wirings and the first metal layer, wherein the first metal layer and the second metal layer are in contact with each other in the first contact hole, and the second metal layer and the third metal layer are in contact with each other in the second contact hole, and the second contact hole is disposed between adjacent first contact holes.

Description

Technical Field

[0001] Embodiments of this disclosure relate to display devices. Background Technology

[0002] An organic light-emitting display device is an organic light-emitting element comprising a hole injection electrode and an electron injection electrode, and an organic light-emitting layer formed between them. The exciton generated by the recombination of holes injected by the hole injection electrode and electrons injected by the electron injection electrode in the organic light-emitting layer decreases from the excited state to the ground state and generates light.

[0003] Organic light-emitting displays (OLEDs), as self-emissive display devices, do not require a separate light source. Therefore, they can be driven with low voltage and can be configured as lightweight and thin devices. Due to their high-quality characteristics such as wide viewing angle, high contrast, and fast response speed, they have attracted much attention as display devices.

[0004] On the other hand, a recent key issue in display devices is expanding the display area, which serves as the region for user identification images. This has led to a tendency to shrink the peripheral area outside the display area. However, as the peripheral area shrinks, the spacing of the wiring within that area also decreases, potentially causing problems such as wire breakage or overheating. Summary of the Invention

[0005] The purpose of this disclosure is to provide a display device capable of preventing defects such as broken wiring in the peripheral area outside the display area. However, this problem is merely illustrative, and the scope of this disclosure is not limited thereto.

[0006] According to one aspect of this disclosure, a display device is provided, comprising: a substrate having a display area having a plurality of pixels, a peripheral area surrounding the display area, and a pad area outside the peripheral area; a plurality of fan-out wirings extending from the pad area across the peripheral area toward the display area and transmitting image signals to the plurality of pixels; a first metal layer covering at least a portion of the plurality of fan-out wirings in the peripheral area; a second metal layer overlapping at least a portion of the first metal layer on the first metal layer; a third metal layer disposed on the second metal layer in the peripheral area; a first insulating layer disposed between the first metal layer and the second metal layer and having a first contact hole; a second insulating layer disposed between the second metal layer and the third metal layer and having a second contact hole; and a third insulating layer disposed between the plurality of fan-out wirings and the first metal layer, wherein the first metal layer and the second metal layer are in contact with each other in the first contact hole, and the second metal layer and the third metal layer are in contact with each other in the second contact hole, and the second contact hole is disposed between adjacent first contact holes.

[0007] Alternatively, the third insulating layer may have a groove corresponding to the intermediate region between adjacent fan-out wirings, with the first contact hole disposed between the grooves.

[0008] Alternatively, the third insulating layer may have a groove corresponding to the intermediate region between adjacent fan-out wirings, in which the first metal layer and the second metal layer are in contact with each other.

[0009] Alternatively, at least one of the first insulating layer and the second insulating layer may contain an organic insulating material.

[0010] Alternatively, the second metal layer may have a plurality of holes spaced apart from the first contact hole, the second contact hole being configured to be spaced apart from the first contact hole and each of the plurality of holes.

[0011] It is possible that the size of the plurality of holes is larger than the size of the first contact hole and the size of the second contact hole.

[0012] It is possible that the area of ​​the first contact hole is larger than the area of ​​the second contact hole.

[0013] The plurality of pixels may include: a thin-film transistor; a pixel electrode electrically connected to at least one of the source electrode and the drain electrode of the thin-film transistor; a counter electrode on the pixel electrode; and a light-emitting layer disposed between the pixel electrode and the counter electrode.

[0014] Alternatively, the third metal layer may be integral with the opposing electrode.

[0015] Alternatively, the first metal layer may be disposed on the same layer as the source electrode and the drain electrode of the thin-film transistor.

[0016] Alternatively, at least a portion of the plurality of fan-out wirings may be disposed on the same layer as the gate electrode of the thin-film transistor.

[0017] Alternatively, the display device may further include: an auxiliary electrode, at least one of the source electrode and drain electrode of the thin-film transistor connected to the pixel electrode, and the second metal layer disposed on the same layer as the auxiliary electrode.

[0018] It is possible that the plurality of fan-out routes include a first fan-out route and a second fan-out route, wherein the first fan-out route and the second fan-out route are configured on different layers, and the first fan-out route and the second fan-out route are adjacent to each other.

[0019] According to another aspect of this disclosure, a display device is provided, comprising: a substrate having a display area having a plurality of pixels, a peripheral area surrounding the display area, and a pad area outside the peripheral area; a plurality of fan-out wirings extending from the pad area across the peripheral area toward the display area and arranged to be spaced apart from each other in a first direction in the peripheral area; a first metal layer covering at least a portion of the plurality of fan-out wirings in the peripheral area; a second metal layer overlapping at least a portion of the first metal layer on the first metal layer in the peripheral area; a counter electrode disposed on the second metal layer along with the plurality of pixels; a first insulating layer disposed between the first metal layer and the second metal layer and having a first contact hole; a second insulating layer disposed between the second metal layer and the counter electrode and having a second contact hole; and a third insulating layer disposed between the plurality of fan-out wirings and the first metal layer and having a groove corresponding to an intermediate region between adjacent fan-out wirings, wherein the spacing distance between the first contact hole and the groove in the first direction is different from the spacing distance between the second contact hole and the groove in the first direction.

[0020] Alternatively, the second metal layer may have a plurality of holes spaced apart from each other, wherein the distance between the first contact hole and the hole in the first direction is different from the distance between the second contact hole and the hole in the first direction.

[0021] The plurality of pixels may include: a thin-film transistor; a pixel electrode electrically connected to at least one of the source electrode and the drain electrode of the thin-film transistor; and a light-emitting layer disposed between the pixel electrode and the opposing electrode.

[0022] Alternatively, the first metal layer may be disposed on the same layer as the source electrode and the drain electrode of the thin-film transistor.

[0023] Alternatively, at least a portion of the plurality of fan-out wirings may be disposed on the same layer as the gate electrode of the thin-film transistor.

[0024] Alternatively, the display device may further include: an auxiliary electrode, at least one of the source electrode and drain electrode of the thin-film transistor connected to the pixel electrode, and the second metal layer disposed on the same layer as the auxiliary electrode.

[0025] Alternatively, the plurality of fan-out cabling may include a first fan-out cabling and a second fan-out cabling, wherein the first fan-out cabling and the second fan-out cabling are configured on different layers from each other.

[0026] (The effect of public disclosure)

[0027] According to an embodiment of the present disclosure configured as described above, it is possible to prevent wiring breaks or poor contact.

[0028] Furthermore, by reducing the peripheral area outside the display area, the proportion of the display area can be increased.

[0029] However, the scope of this disclosure is not limited by these effects. Attached Figure Description

[0030] Figure 1 This is a top view that briefly illustrates a display device according to an embodiment of the present disclosure.

[0031] Figure 2 It includes Figure 1 The equivalent circuit diagram of a pixel in a display device.

[0032] Figure 3 It is shown in magnification Figure 1 A top view of an example of the W section.

[0033] Figure 4a It is along Figure 1 AA′ line and Figure 3 A cross-sectional view of the BB′ line.

[0034] Figure 4b It is along Figure 3 A cross-sectional view of the CC′ line.

[0035] Figure 5 This is a cross-sectional view that briefly shows a portion of a display device according to another embodiment of the present disclosure.

[0036] Figure 6 This is a simplified cross-sectional view of a portion of a display device according to yet another embodiment of the present disclosure.

[0037] Figure 7 This is a top view that briefly shows a portion of the display device according to the comparative example.

[0038] Figure 8 It is shown in magnification Figure 1 A top view of another example of the W section.

[0039] Figure 9a It is along Figure 8 A cross-sectional view of the DD′ line.

[0040] Figure 9b It is along Figure 8 A cross-sectional view of the EE′ line.

[0041] Explanation of reference numerals in the attached figures

[0042] 100: Substrate

[0043] 111: Buffer layer

[0044] 112: Gate insulating layer

[0045] 113: First interlayer insulation layer

[0046] 115: Second interlayer insulation layer

[0047] 117: First planarization layer

[0048] 119: Second planarization layer

[0049] M1: First metal layer

[0050] M2: Second metal layer

[0051] M3: Third Metal Layer

[0052] CNT1: First contact hole

[0053] CNT2: Second contact hole

[0054] G: Groove Detailed Implementation

[0055] This disclosure can be modified in various ways and has many embodiments, specific embodiments of which are illustrated in the accompanying drawings and described in detail in the accompanying description. However, this is not intended to limit this disclosure to specific implementations, and it should be understood to include all modifications, equivalents, and substitutions encompassing the concept and technical scope of this disclosure. In describing this disclosure, detailed descriptions of relevant prior art are omitted where it is determined that such detailed descriptions may obscure the spirit of this disclosure.

[0056] The terms "first," "second," etc., used in this specification may be used to describe multiple constituent elements, but the constituent elements cannot be limited by the terms. The terms are only used to distinguish one constituent element from other constituent elements.

[0057] In this specification, when a layer, film, region, plate, or other part is described as being "on" or "above" other parts, this includes not only cases where it is "directly" "on" another part, but also cases where there are other parts in between.

[0058] The x-axis, y-axis, and z-axis used in this specification are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0059] Hereinafter, embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. In the description with reference to the drawings, substantially the same or corresponding constituent elements are given the same reference numerals, and repeated descriptions thereof are omitted. In the drawings, the thickness is shown enlarged to clearly illustrate each layer and region. Furthermore, the thickness of some layers and regions is exaggerated in the drawings for ease of explanation.

[0060] Figure 1 This is a simplified top view illustrating a display device according to an embodiment of the present disclosure. Figure 2 It includes Figure 1 The equivalent circuit diagram of a pixel in a display device.

[0061] Reference Figure 1 and Figure 2 According to an embodiment of the present disclosure, a display device 1000 includes a substrate 100 having a display area DA, a peripheral area PA, and a pad area PADA.

[0062] The display area DA is the area that enables the user to recognize the image. The peripheral area PA is the area surrounding the display area DA as a non-display area. The pad area PADA is the area located outside the display area DA and the peripheral area PA.

[0063] Multiple pixels P are configured in the display area DA. Figure 2 An example of the equivalent circuit diagram for a pixel P is shown. (Refer to...) Figure 2 Pixel P may include a pixel circuit PC connected to scan line SL and data line DL, and a display element connected to pixel circuit PC. For example, the display element may be an organic light-emitting diode (OLED).

[0064] Each pixel P includes a pixel circuit PC connected to the scan line SL and the data line DL, and an organic light-emitting diode (OLED) connected to the pixel circuit PC.

[0065] The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and transmits the scan signal Sn input through the scan line SL and the data signal Dm input through the data line DL to the driving thin-film transistor T1.

[0066] The storage capacitor Cst is connected to the switching thin-film transistor T2 and the drive voltage line PL, and stores the voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the first power supply voltage (or drive voltage) ELVDD supplied to the drive voltage line PL.

[0067] The driving thin-film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL through the organic light-emitting diode (OLED) according to the voltage value stored in the storage capacitor Cst. The OLED can emit light with a predetermined brightness through the driving current.

[0068] exist Figure 2 The description indicates that a pixel P includes two thin-film transistors and a storage capacitor, but this disclosure is not limited thereto. As other embodiments, the pixel circuit PC of pixel P may include three or more thin-film transistors or two or more storage capacitors, and various modifications can be made.

[0069] Refer to Figure 1 In the peripheral area PA, various wirings connecting multiple pixels P to the display area DA can pass through and be used to encapsulate the display area DA, forming an encapsulation component (not shown). The encapsulation component can be a sealing component surrounding the display area DA.

[0070] The peripheral area PA can be configured with display elements for driving pixel P (e.g., Figure 2 The first voltage line 10 and the second voltage line 20 of the power supply for the OLED.

[0071] The first voltage line 10 can be a driving voltage ELVDD line, and the second voltage line 20 can be a common voltage ELVSS line. Alternatively, the first voltage line 10 can be disposed in the display area DA and connected to the subordinate voltage line 15 that supplies driving voltage to pixel P, and the second voltage line 20 can be directly or via other wiring connected to the opposing electrode described later. Figure 4a 223) connection.

[0072] As an example, the first voltage line 10 can be configured between one edge of the display area DA and the pad area PADA, and the second voltage line 20 can be configured to correspond to other edges of the display area DA besides the one edge where the first voltage line 10 is configured. As an example, the second voltage line 20 can surround the remaining edges of the display area DA other than the one edge where the first voltage line 10 is configured.

[0073] The first voltage line 10 may include: a main voltage line extending in a first direction (x direction) in a manner corresponding to an edge of the display area DA and having two ends 11; and a first connection portion 12 connected to the main voltage line. In this case, the edge may be an edge adjacent to the pad area PADA of the display area DA.

[0074] The first connection portion 12 can protrude from the main voltage line of the first voltage line 10 and extend along a second direction (y-direction). The second direction (y-direction) refers to the direction from the display area DA towards the pad area PADA, for example, a direction approximately perpendicular to the first direction (x-direction). The first connection portion 12 can connect to the pad 430 located in the pad area PADA to electrically connect the first voltage line 10 and the driver IC 410. Referring to the description below, the pad 430 and the driver IC 410 are discussed later.

[0075] The second voltage line 20 may include: a main voltage line configured to surround the edge of the display area DA; and a second connecting portion 22 bent from the end 21 of the main voltage line. As an example, the end 21 of the main voltage line of the second voltage line 20 may extend in a first direction (x direction) corresponding to the main voltage line of the first voltage line 10, and the second connecting portion 22 of the second voltage line 20 may extend in a second direction (y direction) corresponding to the first connecting portion 12 of the first voltage line 10.

[0076] The second connection part 22 is similar to the first connection part 12 and can be connected to the pad 430 located in the pad area PADA to electrically connect the second voltage line 20 and the driver IC 410.

[0077] The pad area PADA is an area equipped with a power supply device (not shown) or a signal generation device (not shown) for transmitting various electrical signals and voltages to multiple pixels P of the display area DA.

[0078] A driver IC 410 can be configured in the pad area of ​​the PADA. The driver IC 410 may include a data driving unit for supplying data signals, and may also include pixel circuitry. Figure 2The driver IC 410 is mounted on the substrate 100 as a chip-on-glass (COG) type, and includes various functional components required for driving the PC. The driver IC 410 has a contact terminal (not shown) on one side that is electrically connected to a pad 430 formed on the substrate 100. A conductive ball may be included between the pad 430 and the contact terminal (not shown) to bond the pad 430 and the contact terminal (not shown) together with an electrically conductive adhesive material. Such an adhesive material may be, for example, anisotropic conductive film, self-organizing conductive film, etc.

[0079] Furthermore, the pad area PADA can be configured with pads 430 that connect various voltage lines 10, 20 configured in the surrounding area PA to the driver IC 410. For this purpose, pad 430 can have pad connection wiring 420. The pad 430 can be formed as a single layer or multiple layers from a material selected from at least one of molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), and titanium (Ti).

[0080] Multiple fan-out traces 30 are configured in the pad area PADA and the surrounding PA area. These fan-out traces 30 are connected to the driver IC 410 and extend from the driver IC 410 across the pad area PADA and the surrounding PA area towards the display area DA. Although Figure 1 Although not shown in the diagram, the multiple fan-out lines 30 can also be connected to the driver IC 410 via pads 430, similar to the aforementioned voltage lines 10 and 20. Thus, the multiple fan-out lines 30 connect the driver IC 410 and the pixel circuitry (…). Figure 2 (PC) connection.

[0081] Multiple fan-out lines 30 are configured to be spaced apart from each other to transmit data signals to each of the multiple pixels P disposed in the display area DA. For this purpose, the multiple fan-out lines 30 can be connected to data lines that transmit data signals to each of the multiple pixels P. Figure 2 DL).

[0082] Multiple fan-out routing lines 30 can be configured on different layers from the second voltage line 20, overlapping a portion of the second voltage line 20. In this case, the overlapping portion of the multiple fan-out routing lines 30 and the second voltage line 20 can be located between the display area DA and the pad area PADA of the peripheral area PA.

[0083] exist Figure 1The diagram shows that multiple fan-out wirings 30 overlap with the ends 21 of the main voltage line of the second voltage line 20, but it is not necessarily limited to this. It is also possible that multiple fan-out wirings 30 overlap with at least a portion of the second connection portion 22 of the second voltage line 20.

[0084] The specific positional relationship (including the stacking structure) between the multiple fan-out wirings 30 and the second voltage line 20 is referenced. Figures 3 to 5 To be discussed later.

[0085] Figure 3 It is shown in magnification Figure 1 A top view of an example of the W section. Figure 4a It is along Figure 1 AA′ line and Figure 3 Cross-sectional view of the BB′ line. Figure 4b It is along Figure 3 A cross-sectional view of the CC′ line.

[0086] Figure 3 The one shown Figure 1 The W part is configured with multiple fan-out cabling ( Figure 1 30) and the second voltage line ( Figure 1 20) overlapping surrounding areas ( Figure 1 It is part of PA.

[0087] Reference Figure 3 and Figure 4a Multiple fan-out cabling ( Figure 1 Each of the 30) can be configured to be spaced apart from each other on the substrate 100. Multiple fan-out wirings ( Figure 1 The first fan-out wiring 30a and the second fan-out wiring 30b can be configured as a first fan-out wiring 30a and a second fan-out wiring 30b, which can be configured on different layers. However, it is not necessary to limit it to this; the first fan-out wiring 30a and the second fan-out wiring 30b can also be configured on the same layer.

[0088] First, refer to Figure 4a The line shown in the middle Figure 1 The cross section of line AA′ shows that the display area DA has a reference. Figure 2 The driving thin-film transistor T1 and storage capacitor Cst in the pixel circuit PC of each pixel P are described. For ease of explanation, they are configured in... Figure 4a The structure of the display area DA is explained in the order of layer stacking.

[0089] The substrate 100 may comprise glass, ceramic, metallic, or other materials with flexible or bendable properties. When the substrate 100 has flexible or bendable properties, it may comprise a polymer resin. The substrate 100 may have a single-layer or multi-layer structure of polymer resin; in the case of a multi-layer structure, it may also include an inorganic layer. In some embodiments, the substrate 100 may have an organic / inorganic / organic structure.

[0090] A semiconductor layer A1 may be disposed on the buffer layer 111. The semiconductor layer A1 may comprise amorphous silicon or polycrystalline silicon. As another embodiment, the semiconductor layer A1 may comprise an oxide semiconductor or an organic semiconductor. The semiconductor layer A1 may include a channel region and source and drain regions disposed on both sides of the channel region. The semiconductor layer A1 may be configured as a single layer or multiple layers.

[0091] A gate electrode G1 is disposed on the semiconductor layer A1, with a gate insulating layer 112 placed between it and the semiconductor layer A1 in such a way that it overlaps with at least a portion of the semiconductor layer A1. The gate electrode G1 may contain molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be configured as a single layer or multiple layers. As an example, the gate electrode G1 may be a single layer of Mo. A first electrode CE1 of a storage capacitor Cst may be disposed on the same layer as the gate electrode G1. The first electrode CE1 may be formed of the same material as the gate electrode G1.

[0092] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2, with a first interlayer insulating layer 113 disposed between them and overlapping each other. The storage capacitor Cst can be overlapped with a thin-film transistor (TFT). Relatedly, Figure 4a The diagram shows that the gate electrode G1 of the driving thin-film transistor T1 is the lower electrode CE1 of the storage capacitor Cst. In another embodiment, the storage capacitor Cst may not overlap with the thin-film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer 115.

[0093] The gate insulating layer 112 and the interlayer insulating layers 113 and 115 may contain inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The gate insulating layer 112 and the interlayer insulating layers 113 and 115 may be a single layer or multiple layers containing the aforementioned materials.

[0094] An active electrode S1 and a drain electrode D1 can be disposed on the interlayer insulating layers 113 and 115.

[0095] The source electrode S1 and drain electrode D1 may contain conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be formed as a multilayer or a single layer containing the above materials. As an example, the source electrode S1 and drain electrode D1 may be configured as a Ti / Al / Ti multilayer structure. The source electrode S1 and drain electrode D1 may be connected to the source or drain region of the semiconductor layer A1 through contact holes formed in the interlayer insulating layers 113 and 115.

[0096] A first planarization layer 117 and a second planarization layer 119 may be disposed on the source electrode S1 and the drain electrode D1, and an organic light-emitting diode (OLED) may be disposed on the planarization layers 117 and 119.

[0097] An auxiliary electrode AL can be disposed between the first planarization layer 117 and the second planarization layer 119. Specifically, the auxiliary electrode AL can be disposed on the first planarization layer 117, and the second planarization layer 119 can be disposed on the auxiliary electrode AL to cover the auxiliary electrode AL. Thus, by using the auxiliary electrode AL as a medium, the pixel electrode 221 can be electrically connected to at least one of the source electrode S1 and the drain electrode D1.

[0098] The auxiliary electrode AL can be connected to at least one of the source electrode S1 and the drain electrode D1 through a contact hole formed in the first planarization layer 117, and can be connected to the pixel electrode 221 (described later) through a contact hole formed in the second planarization layer 119. The auxiliary electrode AL may contain a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc.

[0099] The planarization layers 117 and 119 can be formed as a single layer or multiple layers of an organic film, providing a flat top surface. In this case, the first planarization layer 117 and the second planarization layer 119 can be formed of the same material or different materials.

[0100] In the display area DA of the substrate 100, an organic light-emitting diode (OLED) is disposed on the second planarization layer 119. The OLED includes a pixel electrode 221, an intermediate layer 222 including an organic light-emitting layer, and a counter electrode 223.

[0101] Pixel electrode 221 can be a (semi-)transparent electrode or a reflective electrode. In some embodiments, pixel electrode 221 may include: a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and their compounds; and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include one or more of the following: indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, pixel electrode 221 may be configured as ITO / Ag / ITO.

[0102] A pixel definition film 121 containing one or more organic insulating materials may be disposed on the second planarization layer 119. The pixel definition film 121 has an opening in the display area DA corresponding to each sub-pixel, that is, an opening OP that exposes at least the central part of the pixel electrode 221, thereby defining the light-emitting area of ​​the pixel.

[0103] The intermediate layer 222 of an organic light-emitting diode (OLED) may include an organic light-emitting layer. The organic light-emitting layer may contain organic matter comprising fluorescent or phosphorescent materials that emit red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material. Selectively, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may also be disposed below and above the organic light-emitting layer.

[0104] The counter electrode 223 can be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode 223 can be a transparent or semi-transparent electrode, formed from a metal thin film with a low work function comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and their compounds. Furthermore, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 can be disposed on top of the metal thin film. The counter electrode 223 can be disposed across the display area DA and the peripheral area PA, and above the intermediate layer 222 and the pixel defining film 121. The counter electrode 223 can be integrally formed in multiple organic light-emitting diodes (OLEDs) to correspond to multiple pixel electrodes 221.

[0105] Organic light-emitting diodes (OLEDs) can be easily damaged by external factors such as moisture or oxygen, so they can be protected by covering them with a substrate or a thin film encapsulation layer.

[0106] As an example, when an organic light-emitting diode (OLED) is protected using an encapsulation substrate, a sealing member can be provided between the substrate 100 and the encapsulation substrate. This sealing member can be located in the peripheral area as described above. Figure 1 The PA is configured to surround the display area ( Figure 1 As an example, when an organic light-emitting diode (OLED) is protected using a thin-film encapsulation layer, the thin-film encapsulation layer can cover the display area (DA). Figure 1 (DA) and extends to the display area ( Figure 1 The outer side of the DA). The thin-film encapsulation layer may include at least one organic encapsulation layer and at least one inorganic encapsulation layer.

[0107] Secondly, refer to Figure 4a The line shown in the middle Figure 3 The cross-section of the BB′ line (hereinafter referred to as the "BB′ cross-section"), the first fan-out wiring 30a of the BB′ cross-section can be disposed on the same layer as the gate electrode G1 of the driving thin film transistor T1 or the lower electrode CE1 of the storage capacitor Cst. The second fan-out wiring 30b of the BB′ cross-section can be disposed between adjacent first fan-out wirings 30a, and can be disposed on an upper layer compared to the first fan-out wirings 30a. The second fan-out wiring 30b can be disposed on the same layer as the upper electrode CE2 of the storage capacitor Cst. Thus, the first fan-out wiring 30a and the second fan-out wiring 30b can be separated by a first interlayer insulating layer 113.

[0108] However, it is not limited to this. The first fan-out wiring 30a and the second fan-out wiring 30b can both be configured on the same layer. In this case, they can be configured on the same layer as the lower electrode CE1 of the gate electrode G1 or the storage capacitor Cst, or on the same layer as the upper electrode CE2 of the storage capacitor Cst.

[0109] In the BB′ section, the thickness of each of the first fan-out wiring 30a and the second fan-out wiring 30b can be approximately 3000 mm. Here, "thickness" refers to the length defined in the z-direction, which is the stacking direction, and the term "thickness" will be used in the same sense below.

[0110] A first metal layer M1 is disposed on the second fan-out wiring 30b of the BB′ cross section. The first metal layer M1 of the BB′ cross section can be disposed on the same layer as the source electrode S and the drain electrode D1 and cover the fan-out wirings 30a and 30b. Thus, a second interlayer insulating layer 115 can be interposed between the first metal layer M1 and the second fan-out wiring 30b.

[0111] In the BB′ cross section, as the first fan-out wiring 30a and the second fan-out wiring 30b are spaced apart from each other, a groove can be formed in the interlayer insulating layers 113 and 115 corresponding to the middle region MA of the BB′ cross section, which is the region between the first fan-out wiring 30a and the second fan-out wiring 30b. Therefore, a groove G can also be formed in the first metal layer M1 of the BB′ cross section disposed on the interlayer insulating layers 113 and 115.

[0112] The first metal layer M1 can be formed of the same material as the source electrode S1 and the drain electrode D1, and can have the same characteristics as the data line ( Figure 2 DL) and drive voltage lines ( Figure 2 The structure is the same as that of the PL. For example, the first metal layer M1 can be a single layer or multiple layer containing at least one of aluminum (Al), copper (Cu), titanium (Ti), and alloys thereof. As an embodiment, the first metal layer M1 can be a Ti / Al / Ti three-layer film. In the BB′ section, the thickness of the first metal layer M1 can be formed to be 4,500. Up to 9,000 Specifically, it could be approximately 6,800 .

[0113] A second metal layer M2 is disposed on the first metal layer M1 in the BB′ cross section. The second metal layer M2 in the BB′ cross section is disposed on the same layer as the auxiliary electrode AL and overlaps at least a portion of the first metal layer M1. In this case, the second metal layer M2 can also cover the fan-out wirings 30a and 30b in the same manner as the first metal layer M1. The second metal layer M2 can be formed of the same material as the auxiliary electrode AL, for example, it can contain conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. In the BB′ cross section, the thickness of the second metal layer M2 can be formed to be 4,500 mm. Up to 9,000 Specifically, it could be approximately 6,800 .

[0114] The second metal layer M2 can have the same characteristics as the second voltage line ( Figure 1 20) and / or drive voltage lines ( Figure 2 The wiring in the PL is the same structure.

[0115] A first planarization layer 117 is disposed between the first metal layer M1 and the second metal layer M2. The first planarization layer 117 can fill the grooves G of the interlayer insulating layers 113 and 115 and is formed of a thick film relatively thicker than the first metal layer M1. Thus, the region corresponding to the groove G of the second metal layer M2, i.e., the region directly above the groove G, can be planarized. In the BB′ cross-section, the thickness of the first planarization layer 117 can be formed to be 10,000 mm. Up to 20,000 Specifically, it could be approximately 16,000 .

[0116] The first planarization layer 117 has a first contact hole CNT1 in the BB′ cross section, and the second metal layer M2 is connected to the first metal layer M1 through the first contact hole CNT1. In this embodiment, the first contact hole CNT1 in the BB′ cross section can be separated from the groove G of the first metal layer M1 in the width direction of the fan-out wirings 30a and 30b. Here, "width direction" refers to the area of ​​the fan-out wirings 30a and 30b in the peripheral region of the substrate 100. Figure 1 The PAs are arranged in a direction that is separated from each other, that is, the first direction, in Figure 4a The x-direction is shown in the figure. Hereinafter, the term "width direction" will be used in the sense of the first direction, i.e., the x-direction, and the term "width" will be used in the sense of length in the x-direction.

[0117] A third metal layer M3 is disposed on the second metal layer M2 at the BB′ cross section. The third metal layer M3 at the BB′ cross section is disposed on the same layer as the opposing electrode 223 and overlaps with at least a portion of the second metal layer M2. At this time, the third metal layer M3 can also cover the fan-out wirings 30a and 30b in the same way as the first metal layer M1 and the second metal layer M2.

[0118] As one embodiment, the third metal layer M3 can be integrally formed with the opposing electrode 223. In this case, the opposing electrode 223 can be configured to cover the display area of ​​the substrate 100. Figure 1 The entire DA and its surrounding areas Figure 1 At least a portion of the PA can be formed of the same material as the counter electrode 223. Therefore, in the BB′ cross section, the third metal layer M3 can be, like the counter electrode 223, having a surface area of ​​approximately 100 mm. A thin film of a certain thickness.

[0119] In another embodiment, the third metal layer M3 may also be a metal layer connected to the counter electrode 223. In this case, a connecting metal layer for connecting the third metal layer M3 and the counter electrode 223 may also be provided.

[0120] A second planarization layer 119 is disposed between the second metal layer M2 and the third metal layer M3. The second planarization layer 119 can fill the first contact hole CNT1 of the first planarization layer 117 in the BB′ cross section and is formed by a thick film that is relatively thicker than the second metal layer M2. As a result, the region corresponding to the first contact hole CNT1 of the first planarization layer 117, that is, the region located directly above the first contact hole CNT1, can be planarized.

[0121] The second planarization layer 119 has a second contact hole CNT2 in the BB′ cross section, and the third metal layer M3 is connected to the second metal layer M2 through the second contact hole CNT2. In this embodiment, the second contact hole CNT2 in the BB′ cross section is disposed between adjacent first contact holes CNT1 in the first contact holes CNT1 of the first planarization layer 117. At the same time, the second contact hole CNT2 can also be spaced apart from the groove G in the width direction of the fan-out wiring 30a, 30b, that is, in the first direction (x direction). That is, the spacing distance in the first direction (x direction) between the first contact hole CNT1 and the groove G can be different from the spacing distance in the first direction (x direction) between the second contact hole CNT2 and the groove G.

[0122] Similar to or similar to the first planarization layer 117, the thickness of the second planarization layer 119 in the BB′ section can be formed to be 10,000 mm. Up to 20,000 Specifically, it could be approximately 16,000 .

[0123] The first planarization layer 117 and / or the second planarization layer 119 may contain organic insulating materials, and as an example, may contain a soft and dense material such as polyimide.

[0124] As described above, in the BB′ section, with the first contact hole CNT1 and the second contact hole CNT2 configured to be staggered from each other in the width direction (e.g., the first direction (x direction)) of the fan-out wiring 30a, 30b, as... Figure 3 As shown, the first contact hole CNT1 and the second contact hole CNT2 are arranged alternately to each other in a planar view (i.e., in the xy plane).

[0125] On the other hand, refer to Figure 3 and Figure 4b In the second metal layer M2 at the CC′ cross section, a plurality of spaced-apart holes OG can be configured. These holes OG facilitate the outgassing of the first planarization layer 117 containing organic matter. Therefore, the size of the holes OG can be larger than the size of the plurality of first contact holes CNT1 and the plurality of second contact holes CNT2. That is, the width w3 of the holes OG in the second metal layer M2 can be larger than the width w2 of the second contact holes CNT2 in the second planarization layer 119 and the width w1 of the first contact holes CNT1 in the first planarization layer 117.

[0126] exist Figure 3 and Figure 4b The width w2 of the second contact hole CNT2 of the second planarization layer 119 is shown to be approximately the same as the width w1 of the first contact hole CNT1 of the first planarization layer 117, but it is not necessarily limited to this.

[0127] like Figure 3 As shown, the plurality of holes OG, the first contact hole CNT1, and the second contact hole CNT2 can be formed into a quadrilateral shape. As one embodiment, the width w3 of the plurality of holes OG can be approximately 17.5 mm. The width w1 of the first contact hole CNT1 and the width w2 of the second contact hole CNT2 can each be approximately 6. However, it is not limited to this. Obviously, the multiple holes OG, the first contact hole CNT1 and the second contact hole CNT2 can be formed into various shapes other than quadrilaterals, such as polygons, (elliptical) circles, etc.

[0128] Alternatively, the plurality of holes OG in the second metal layer M2 may be configured to be separated from the first contact holes CNT1 in the first planarization layer 117, and the second contact holes CNT2 in the second planarization layer 119 may be configured to be separated from each of the first contact holes CNT1 and the plurality of holes OG. That is, the separation distance in the first direction (x direction) between the first contact holes CNT1 and the holes OG in the second metal layer M2 may be different from the separation distance in the first direction (x direction) between the second contact holes CNT2 and the holes OG in the second metal layer M2.

[0129] Therefore, from a planar viewpoint (i.e., in the xy plane), the plurality of first contact holes CNT1, the plurality of second contact holes CNT2, and the plurality of holes OG can be configured to alternate with each other.

[0130] Figure 5 This is a cross-sectional view that briefly shows a portion of a display device according to another embodiment of the present disclosure.

[0131] Figure 5 The situation of the embodiments shown in the figure is similar to that of the embodiments shown in the figure. Figure 4a The embodiment shown in [reference 1] differs only in the position defined in the first direction (x direction) of the first contact hole CNT1; otherwise, it has the same or similar structure as the embodiment shown in [reference 2]. Therefore, the following focuses on the differences between the embodiment shown in [reference 3] and the embodiment shown in [reference 4]. Figure 5 The embodiments shown are described in detail below. Furthermore, Figure 5 The structure below the first metal layer M1 shown in the figure is similar to Figure 4a The embodiments shown are the same, therefore the description thereof is based on reference. Figure 4a Replace with the description.

[0132] Reference Figure 5 A second metal layer M2 is disposed on the first metal layer M1. The second metal layer M2 is disposed in relation to the auxiliary electrode ( Figure 4a The second metal layer M2 is located on the same layer as the first metal layer M1 and overlaps at least a portion of the first metal layer M1. In this case, the second metal layer M2 may also cover the fan-out wirings 30a and 30b in the same manner as the first metal layer M1. The first metal layer M1 is disposed on the same layer as the driving thin-film transistor (AL). Figure 4a The source and drain electrodes of T1) Figure 4a On the same layer as S1 and D1, this is the same as above.

[0133] A first planarization layer 117 is disposed between a first metal layer M1 and a second metal layer M2. The first planarization layer 117 has a first contact hole CNT1, through which the second metal layer M2 is connected to the first metal layer M1. In this embodiment, the first contact hole CNT1 may be located corresponding to a groove G formed by the interlayer insulating layers 113 and 115. Therefore, the portion of the second metal layer M2 covering the inner surface of the first contact hole CNT1 can contact the portion of the first metal layer M1 covering the inner surface of the groove G. Thus, the first contact hole CNT1 of the first planarization layer 117 and the groove G of the first interlayer insulating layer 113 and the second interlayer insulating layer 115 are located in the region between the first fan-out wiring 30a and the second fan-out wiring 30b, i.e., the intermediate region MA.

[0134] A third metal layer M3 is disposed on the second metal layer M2. The third metal layer M3 is disposed at the junction with the opposing electrode ( Figure 4a (223) On the same layer and overlapping at least a portion of the second metal layer M2. At this time, the third metal layer M3 may also be configured to cover the fan-out wirings 30a and 30b in the same way as the first metal layer M1 and the second metal layer M2.

[0135] A second planarization layer 119 is disposed between the second metal layer M2 and the third metal layer M3. The second planarization layer 119 can fill the first contact hole CNT1 of the first planarization layer 117 and is formed of a thick film that is relatively thicker than the second metal layer M2. As a result, the area corresponding to the groove G of the third metal layer M3 and the first contact hole CNT1 can be planarized.

[0136] The second planarization layer 119 has a second contact hole CNT2, and the third metal layer M3 is connected to the second metal layer M2 through the second contact hole CNT2. In this embodiment, the second contact hole CNT2 is disposed between adjacent first contact holes CNT1 in the first contact holes CNT1 of the first planarization layer 117.

[0137] In this embodiment, as the first contact hole CNT1 of the first planarization layer 117 is located corresponding to the groove G of the interlayer insulating layers 113 and 115, the second contact hole CNT2 of the second planarization layer 119 can be separated from the first contact hole CNT1 and the groove G, which are configured to overlap each other, in the width direction of the fan-out wiring 30a and 30b, i.e., the first direction (x direction).

[0138] Figure 6 This is a cross-sectional view that briefly shows a portion of a display device according to yet another embodiment of the present disclosure.

[0139] Figure 6 The situation of the embodiments shown in the figure is similar to that of the embodiments shown in the figure. Figure 4aThe embodiment shown differs only in the position defined in the first direction (x direction) of the first contact hole CNT1; otherwise, it has the same characteristics as... Figure 4a The embodiments shown herein have the same or similar structures. Therefore, the following will use... Figure 4a Focusing on the differences between the embodiments shown, Figure 6 The embodiments shown are described in detail below. Furthermore, Figure 6 The structure below the first metal layer M1 shown in the figure is similar to Figure 4a The embodiments shown are the same, therefore their description is based on reference. Figure 4a Replace with the description.

[0140] Reference Figure 6 A second metal layer M2 is disposed on the first metal layer M1. The second metal layer M2 is disposed in relation to the auxiliary electrode ( Figure 4a The second metal layer M2 is located on the same layer as the first metal layer M1 and overlaps at least a portion of the first metal layer M1. In this case, the second metal layer M2 may also cover the fan-out wirings 30a and 30b in the same manner as the first metal layer M1. The first metal layer M1 is disposed on the same layer as the driving thin-film transistor (AL). Figure 4a The source and drain electrodes of T1) Figure 4a On the same layer as S1 and D1, this is the same as above.

[0141] A first planarization layer 117 is disposed between the first metal layer M1 and the second metal layer M2. The first planarization layer 117 has a first contact hole CNT1, through which the second metal layer M2 is connected to the first metal layer M1. In this embodiment, the grooves G of the plurality of interlayer insulating layers 113, 115 can be located between adjacent first contact holes CNT1. That is, with... Figure 4a Unlike the embodiment shown, the first contact holes CNT1 and the groove G are not alternately arranged in the first direction (x direction). Therefore, in this embodiment, the number of first contact holes CNT1 on the fan-out wirings 30a and 30b can be compared to... Figure 4a The embodiments shown are few. However, it is not limited to this. As other embodiments, the first contact holes CNT1 may have a wide distribution in a portion of the fan-out wirings 30a and 30b, and a compact distribution in other regions of the fan-out wirings 30a and 30b.

[0142] A third metal layer M3 is disposed on the second metal layer M2. The third metal layer M3 is disposed on the same layer as the opposing electrode 223 and overlaps with at least a portion of the second metal layer M2. At this time, the third metal layer M3 can also be configured to cover the fan-out wirings 30a and 30b in the same way as the first metal layer M1 and the second metal layer M2.

[0143] A second planarization layer 119 is disposed between the second metal layer M2 and the third metal layer M3. The second planarization layer 119 can fill the first contact hole CNT1 of the first planarization layer 117 and is formed of a thick film that is relatively thicker than the second metal layer M2. As a result, the area corresponding to the groove G of the third metal layer M3 and the first contact hole CNT1 can be planarized.

[0144] The second planarization layer 119 has a second contact hole CNT2, through which the third metal layer M3 is connected to the second metal layer M2. The second contact hole CNT2 is disposed between adjacent first contact holes CNT1 in the first planarization layer 117. As mentioned above, the spacing between adjacent first contact holes CNT1 is compared to the previous embodiment (see reference). Figure 4a , Figure 5 As the size of the first contact hole (CNT1) increases, the number of second contact holes (CNT2) disposed between adjacent first contact holes (CNT1) can also be multiple.

[0145] In the case of this embodiment, with Figure 4a Similar to the embodiment shown, the first contact hole CNT1 of the first planarization layer 117 can be configured to be spaced apart from the grooves G of the interlayer insulating layers 113 and 115 and the second contact hole CNT2 of the second planarization layer 119 in the width direction, i.e., the first direction (x direction), of the fan-out wiring 30a and 30b, respectively.

[0146] Figure 7 This is a top view that briefly shows a portion of the display device according to the comparative example.

[0147] Reference Figure 7 In the case of the display device according to the comparative example, the first contact hole CNT1 of the first planarization layer 117 and the second contact hole CNT2 of the second planarization layer 119 may be located corresponding to the groove G formed by the interlayer insulating layers 113 and 115.

[0148] In this case, the portion of the third metal layer M3 covering the inner surface of the second contact hole CNT2 may contact the portion of the second metal layer M2 covering the inner surface of the first contact hole CNT1, and the portion of the second metal layer M2 covering the inner surface of the first contact hole CNT1 may contact the portion of the first metal layer M1 covering the inner surface of the groove G. Thus, the first metal layer M1, the second metal layer M2, and the third metal layer M3 are in contact at approximately the same position.

[0149] like Figure 7As shown, in a stacked structure that includes both a first planarization layer 117 and a second planarization layer 119, which are thicker than other inorganic insulating layers (112, 113, 115, etc.), the portion CA of the third metal layer M3 in contact with the first metal layer M1 and the second metal layer M2 may become quite fragile due to the corresponding thinning. This is because, as the third metal layer M3 extends long along the inner surface of the first contact hole CNT1 formed in the first planarization layer 117 and the inner surface of the second contact hole CNT2 formed in the second planarization layer 119, it has approximately 100... The thinness of the third metal layer M3 may make it prone to breakage.

[0150] At this point, if the third metal layer M3 breaks, the layer below the third metal layer M3, namely the second metal layer M2, will be exposed, resulting in a connection that can be used as a second voltage line. Figure 2 As a result, the second metal layer M2 of (20) also fractured. Consequently, serious problems such as overheating may occur in the display device.

[0151] Figure 8 This is a simplified cross-sectional view showing a portion of a display device according to yet another embodiment of the present disclosure. Figure 9a It is along Figure 8 Cross-sectional view of the DD′ line. Figure 9b It is along Figure 8 A cross-sectional view of the EE′ line.

[0152] Figure 8 and Figure 9a The situation of the embodiments shown in the figure is similar to that of the embodiments shown in the figure. Figure 3 , Figure 4a and Figure 4b The embodiment shown differs only in the size and shape of the second contact hole CNT2, otherwise it has the same characteristics as... Figure 3 , Figure 4a and Figure 4b The structures shown in the embodiments are the same or similar. Therefore, the following uses the same or similar structures as those shown in the embodiments. Figure 3 , Figure 4a and Figure 4b Focusing on the differences between the embodiments shown, Figure 8 , Figure 9a and Figure 9b The embodiments shown in the figure will be described in detail.

[0153] Refer to together Figure 8 and Figure 9a and Figure 9b The width w2 of the second contact hole CNT2 in the second planarization layer 119 can be larger than the width w1 of the first contact hole CNT1 in the first planarization layer 117. In this case, as... Figure 9aAs shown, the first contact hole CNT1 can be disposed between adjacent second contact holes CNT2. Furthermore, the first contact hole CNT1 can also be disposed between adjacent grooves G in the grooves G of the interlayer insulating layers 113 and 115. However, it is not limited to this, as... Figure 5 As shown, the first contact hole CNT1 and the groove G can also be configured to overlap each other.

[0154] Thus, in this embodiment, the contact area between the third metal layer M3 and the second metal layer M2 is greater than that in the previous embodiment (see reference). Figure 3 , Figure 4a and Figure 4b As it grows larger, it can more stably distribute to each pixel. Figure 1 The P) transmits the initialization voltage and / or drive voltage.

[0155] exist Figure 8 and Figure 9b The diagram shows that the width w2 of the second contact hole CNT2 in the second planarization layer 119 is larger than the width w3 of the hole OG in the second metal layer M2, but this is not necessarily the case. That is, the width w2 of the second contact hole CNT2 can be a value between the width w3 of the hole OG in the second metal layer M2 and the width w1 of the first contact hole CNT1.

[0156] In this embodiment, the first contact hole CNT1 and the second contact hole CNT2 are alternately arranged in a planar view (i.e., in the xy plane), and the width w2 of the second contact hole CNT2 is larger than the width w1 of the first contact hole CNT1, thereby reducing the number of first contact holes CNT1 compared to previous embodiments. However, as another embodiment, it is also possible that, in a planar view, the distribution of first contact holes CNT1 is low in some areas but high in other areas.

[0157] On the other hand, Figure 8 The image shows the second contact hole CNT2 in a cross shape, but this is just an example and can certainly be modified into many other shapes.

[0158] Thus, this disclosure has been illustrated with reference to one embodiment shown in the accompanying drawings, but this is merely illustrative, and it will be understood by those skilled in the art that various modifications and variations of the embodiments can be made therefrom. Therefore, the true scope of protection of this disclosure should be determined by the disclosed technical concept.

Claims

1. A display device, wherein, have: The substrate has a display area configured with multiple pixels, a peripheral area surrounding the display area, and a pad area outside the peripheral area; Multiple fan-out wirings extend from the pad area across the surrounding area to the display area and transmit image signals to the multiple pixels; A first metal layer covers at least a portion of the plurality of fan-out wirings in the surrounding area; A second metal layer overlaps at least a portion of the first metal layer on the first metal layer; A third metal layer is disposed on the second metal layer in the peripheral region; A first insulating layer is disposed between the first metal layer and the second metal layer, and has a first contact hole; A second insulating layer is disposed between the second metal layer and the third metal layer, and has a second contact hole; as well as A third insulating layer is disposed between the plurality of fan-out wirings and the first metal layer. The first metal layer and the second metal layer are in contact with each other in the first contact hole, and the second metal layer and the third metal layer are in contact with each other in the second contact hole.

2. The display device according to claim 1, wherein, The second contact hole is disposed between adjacent first contact holes.

3. The display device according to claim 1, wherein, The third insulating layer has a groove corresponding to the intermediate region between the adjacent fan-out wirings. The first contact hole is disposed between the grooves.

4. The display device according to claim 1, wherein, The third insulating layer has a groove corresponding to the intermediate region between the adjacent fan-out wirings. The first metal layer and the second metal layer are in contact with each other in the groove.

5. The display device according to claim 1, wherein, At least one of the first insulating layer and the second insulating layer contains an organic insulating material.

6. The display device according to claim 1, wherein, The second metal layer has a plurality of holes spaced apart from the first contact hole. The second contact hole is configured to be spaced apart from each of the first contact hole and the plurality of holes.

7. The display device according to claim 6, wherein, The size of the plurality of holes is larger than the size of the first contact hole and the size of the second contact hole.

8. The display device according to claim 1, wherein, The area of ​​the first contact hole is larger than the area of ​​the second contact hole.

9. The display device according to claim 1, wherein, The plurality of pixels have: Thin-film transistors; The pixel electrode is electrically connected to at least one of the source electrode and the drain electrode of the thin-film transistor. The opposing electrode on the pixel electrode; as well as A light-emitting layer is disposed between the pixel electrode and the opposing electrode.

10. The display device according to claim 9, wherein, The third metal layer is integral with the opposing electrode.

11. The display device according to claim 9, wherein, The first metal layer is disposed on the same layer as the source electrode and the drain electrode of the thin-film transistor.

12. The display device according to claim 9, wherein, At least a portion of the plurality of fan-out wirings are disposed on the same layer as the gate electrode of the thin-film transistor.

13. The display device according to claim 9, wherein, The display device also includes: An auxiliary electrode is connected to at least one of the source and drain electrodes of the thin-film transistor and to the pixel electrode. The second metal layer is disposed on the same layer as the auxiliary electrode.

14. The display device according to claim 1, wherein, The plurality of fan-out cabling includes a first fan-out cabling and a second fan-out cabling. The first fan-out routing and the second fan-out routing are configured on different layers. The first fan-out wiring and the second fan-out wiring are adjacent to each other.

15. A display device, wherein, have: The substrate has a display area configured with multiple pixels, a peripheral area surrounding the display area, and a pad area outside the peripheral area; Multiple fan-out wirings extend from the pad area across the peripheral area toward the display area and are spaced apart from each other in the peripheral area in a first direction. A first metal layer covers at least a portion of the plurality of fan-out wirings in the surrounding area; A second metal layer overlaps at least a portion of the first metal layer on the first metal layer; A third metal layer is disposed on the second metal layer in the peripheral region; Opposing electrodes are configured together across the plurality of pixels and are disposed on the second metal layer; A first insulating layer is disposed between the first metal layer and the second metal layer, and has a first contact hole; A second insulating layer is disposed between the second metal layer and the third metal layer, and has a second contact hole; as well as A third insulating layer is disposed between the plurality of fan-out wirings and the first metal layer, and includes a groove corresponding to the intermediate region between adjacent plurality of fan-out wirings. The first distance between the first contact hole and the groove in the first direction is different from the first distance between the second contact hole and the groove in the first direction.

16. The display device according to claim 15, wherein, The second metal layer includes a plurality of holes spaced apart from each other. The first contact hole and the plurality of holes are spaced apart in the first direction by a distance different from the second contact hole and the plurality of holes by a distance different in the first direction.

17. The display device according to claim 15, wherein, The plurality of pixels includes: Thin-film transistors; A pixel electrode, electrically connected to at least one of the source and drain electrodes of the thin-film transistor; and The light-emitting layer is located between the pixel electrode and the opposing electrode.

18. The display device according to claim 17, wherein, The first metal layer is located on the same layer as the layer on which the source electrode and the drain electrode of the thin-film transistor are disposed.

19. The display device according to claim 17, wherein, At least a portion of the plurality of fan-out wirings are located in the same layer as the layer on which the gate electrode of the thin-film transistor is disposed.

20. The display device according to claim 17, wherein, The display device further includes: An auxiliary electrode connects the pixel electrode to at least one of the source and drain electrodes of the thin-film transistor. The second metal layer is located on the same layer as the layer on which the auxiliary electrode is disposed.

21. The display device according to claim 16, wherein, The plurality of fan-out cabling includes a first fan-out cable and a second fan-out cable. The first fan-out line and the second fan-out line are configured on different layers.

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