Display device

Abstract

The display device includes: a substrate; a plurality of unit display parts, each unit display part including a thin film transistor located on the substrate and including at least one inorganic layer, a display element electrically connected to the thin film transistor, and a planarization layer located between the thin film transistor and the display element; and an encapsulation layer for sealing each of the plurality of unit display parts, the planarization layer including a recessed portion recessed in a depth direction on one side of the display element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0041496, filed on April 9, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] An aspect of one or more embodiments relates to a display device. Background Art

[0004] According to the rapid development of the display field that visually expresses various electrical signal information, various flat display devices having extraordinary characteristics such as small thickness, light weight, and low power consumption are being introduced. Recently, with the development of display-related technologies, flexible display devices that can be bent or rolled are being studied and developed. In addition, research and development of retractable display devices that can be changed into various shapes are being actively carried out.

[0005] Meanwhile, a display device having flexibility and a small thickness may include a thin film type encapsulation layer to prevent penetration of external moisture or oxygen. Generally, the thin film encapsulation layer may have a structure in which an inorganic layer and an organic layer are alternately stacked. However, the thin film encapsulation layer formed in the entire area of ​​the display device according to the prior art may reduce the flexibility of the display device, and when the shape of the display device is changed, the thin film encapsulation layer may be damaged. Summary of the invention

[0006] According to aspects of one or more embodiments, there is provided a display device whose shape can be changed.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0008] According to one or more embodiments, a display device includes: a substrate; a plurality of unit display portions, each unit display portion including a thin film transistor on the substrate, a display element electrically connected to the thin film transistor, and a planarization layer between the thin film transistor and the display element; and an encapsulation layer for sealing each of the plurality of unit display portions, wherein the planarization layer includes a recess on one side of the display element that is recessed in a depth direction.

[0009] In an embodiment, the recess may at least partially surround the display element.

[0010] In an embodiment, each of the plurality of unit display portions may include a plurality of display elements, and the recess may surround the plurality of display elements.

[0011] In an embodiment, the encapsulation layer may include an organic encapsulation layer, a first inorganic encapsulation layer arranged below the organic encapsulation layer, and a second inorganic encapsulation layer arranged above the organic encapsulation layer, the organic encapsulation layer includes unit organic encapsulation layers corresponding to a plurality of unit display parts, respectively, and the first inorganic encapsulation layer and the second inorganic encapsulation layer may contact each other at the periphery of the unit organic encapsulation layer.

[0012] In an embodiment, the substrate includes a plurality of islands spaced apart from each other, a plurality of connection portions connecting the plurality of islands, and a plurality of penetration portions penetrating the substrate between the plurality of connection portions, and the plurality of unit display portions may be respectively arranged on the plurality of islands.

[0013] In embodiments, the first inorganic encapsulating layer and the second inorganic encapsulating layer may be in contact at the plurality of connection portions.

[0014] In the embodiment, the first inorganic encapsulation layer and the second inorganic encapsulation layer may be at least partially disposed on side surfaces of the plurality of penetration portions.

[0015] In an embodiment, the display device may further include: wirings on the plurality of connection portions, wherein the electrical signal is transmitted to the unit display portion through the wirings; and a step compensation layer disposed between the plurality of connection portions and the wirings and including an organic material.

[0016] In an embodiment, the display element may include a pixel electrode, an intermediate layer, and a counter electrode, wherein the pixel electrode may be disposed on the planarization layer, and a pixel defining layer covering an edge of the pixel electrode may be disposed on the planarization layer.

[0017] In embodiments, the pixel defining layer may expose the recess.

[0018] In an embodiment, the planarization layer may include an organic planarization layer and an inorganic planarization layer disposed on the organic planarization layer, and the recess may be provided in the inorganic planarization layer.

[0019] In an embodiment, the display device may further include: an inorganic protection layer disposed between the thin film transistor and the planarization layer and covering a source electrode or a drain electrode of the thin film transistor.

[0020] In an embodiment, the thin film transistor may include at least one inorganic layer, and a step compensation layer may be disposed on a side surface of the at least one inorganic layer, the step compensation layer including an organic material.

[0021] In an embodiment, the display device may further include: a lower planarization layer disposed between the thin film transistor and the planarization layer; and a connection metal disposed on the lower planarization layer.

[0022] According to one or more embodiments, a display device includes: a substrate including a plurality of islands separated from each other, a plurality of connecting portions connecting the plurality of islands, and a plurality of penetrating portions penetrating the substrate between the plurality of connecting portions; a plurality of unit display portions respectively arranged on the plurality of islands; and an encapsulation layer for sealing each of the plurality of unit display portions, wherein each of the plurality of unit display portions includes a thin film transistor, an organic light emitting diode electrically connected to the thin film transistor, and a planarization layer located between the thin film transistor and the organic light emitting diode, and the planarization layer includes a recess that is recessed in a depth direction on one side of the organic light emitting diode.

[0023] In an embodiment, an organic light emitting diode included in each of the plurality of unit display portions is provided in plurality, and a recess may be disposed between the plurality of organic light emitting diodes.

[0024] In an embodiment, the encapsulation layer may include an organic encapsulation layer, a first inorganic encapsulation layer arranged below the organic encapsulation layer, and a second inorganic encapsulation layer arranged above the organic encapsulation layer, wherein the organic encapsulation layer may include unit organic encapsulation layers corresponding to a plurality of unit display portions, respectively, and the first inorganic encapsulation layer and the second inorganic encapsulation layer may contact each other at the periphery of the unit organic encapsulation layer.

[0025] In embodiments, the first inorganic encapsulating layer and the second inorganic encapsulating layer may contact each other at a plurality of connection portions.

[0026] In the embodiment, the first inorganic encapsulation layer and the second inorganic encapsulation layer may be at least partially disposed on side surfaces of the plurality of penetration portions.

[0027] In an embodiment, an organic light emitting diode may include a pixel electrode, an intermediate layer including an organic emission layer, and a counter electrode, wherein the pixel electrode may be arranged on a planarization layer, and a pixel defining layer covering an edge of the pixel electrode may be arranged on an upper surface of the planarization layer and not overlap with the recess.

[0028] In an embodiment, the display device may further include: wirings on the plurality of connection portions, wherein the electrical signals are transmitted to the plurality of unit display portions through the wirings; and a step compensation layer disposed between the plurality of connection portions and the wirings and including an organic material.

[0029] Aspects, features, and effects in addition to those described herein will be understood from the following detailed description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] These and / or other aspects will become apparent and more readily understood from the following description of some embodiments in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a schematic top plan view of a display device according to an embodiment;

[0032] Figure 2 It is shown Figure 1 An enlarged schematic top plan view of an example of area "A" shown in;

[0033] Figure 3 yes Figure 1 A schematic top plan view of a portion of the unit shown in FIG.

[0034] Figure 4 is shown along Figure 3 A schematic cross-sectional view of an example of a cross section taken along line II' shown in FIG.

[0035] Figure 5 is shown along Figure 3 A schematic cross-sectional view of an example of a cross section taken along line II-II' shown in FIG.

[0036] Figure 6 is a schematic cross-sectional view showing a display device according to another embodiment;

[0037] Figure 7 is a schematic cross-sectional view showing a display device according to another embodiment; and

[0038] Figure 8 is a schematic cross-sectional view showing a display device according to another embodiment. DETAILED DESCRIPTION

[0039] Reference will now be made in further detail to some embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments described below with reference to the accompanying drawings are only used to explain the aspects of this description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. A statement such as "at least one of ...", when located after a list of elements, modifies the list of the entire element and does not modify the individual elements in the list.

[0040] It should be understood that although terms such as “first” and “second” may be used herein to describe various components, these components are not limited by these terms and the terms are used to distinguish one component from another.

[0041] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0042] It should be further understood that the terms “include” and / or “comprises” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0043] It should be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, the layer, region or component may be directly or indirectly formed on the other layer, region or component. That is, for example, one or more intermediate layers, regions or components may be present.

[0044] For the convenience of explanation, the size of the components in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings may be arbitrarily illustrated for the convenience of explanation, the following embodiments are not limited thereto.

[0045] When the embodiment can be implemented differently, a specific process may be performed in an order different from the described order. For example, two processes described successively may be performed substantially at the same time, or in an order opposite to the described order.

[0046] In the embodiments described herein, when a layer, region, or component is connected to another layer, region, or component, the layer, region, or component may be directly connected to each other, and the layer, region, or component may also be indirectly connected to each other using other layers, regions, or components between the layer, region, or component and another layer, region, or component. For example, in this specification, when a layer, region, or component is electrically connected to another layer, region, or component, the layer, region, or component and the other layer, region, or component may be directly electrically connected to each other, or the layer, region, or component and the other layer, region, or component may also be indirectly electrically connected to each other using other layers, regions, or components between the layer, region, or component and another layer, region, or component.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the exemplary embodiments of the inventive concept belong. It should be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0048] Herein, the embodiments will be described in further detail with reference to the accompanying drawings. Throughout the description, the same or corresponding components will be given the same reference numerals, and redundant descriptions of the same or corresponding components may be omitted.

[0049] Figure 1 is a schematic top plan view of a display device according to an embodiment; and Figure 2 It is shown Figure 1 An enlarged schematic top plan view of an example of area “A” is shown in FIG.

[0050] refer to Figure 1 , the display device 10 according to the embodiment may include a substrate 100 and a unit display part 200 on the substrate 100 .

[0051] The substrate 100 may include any of various materials. The substrate 100 may include any of glass, metal, organic material, and other materials.

[0052] In an embodiment, the substrate 100 may include a flexible material. For example, the substrate 100 may include a bendable, foldable, or rollable material. For example, the flexible material included in the substrate 100 may be thin glass, metal, or plastic. When the substrate 100 includes plastic, the substrate 100 may include polyimide (PI). As another embodiment, the substrate 100 may include another type of plastic material.

[0053] The substrate 100 may include a plurality of islands 101 spaced apart from each other, a plurality of connection portions 102 connecting the plurality of islands 101 , and a plurality of penetration portions V penetrating the substrate 100 between the plurality of connection portions 102 .

[0054] The plurality of islands 101 may be arranged to be spaced apart from each other. For example, the plurality of islands 101 may be repeatedly arranged in a first direction X and a second direction Y different from the first direction X, and form a planar grid pattern. For example, the first direction X and the second direction Y may be orthogonal to each other. As another example, the first direction X and the second direction Y may form an obtuse angle or an acute angle.

[0055] A plurality of unit display parts 200 may be respectively arranged on a plurality of islands 101. The unit display part 200 may include at least one display element to realize visible rays.

[0056] The connection portion 102 may connect the plurality of islands 101. In an embodiment, four connection portions 102 may be connected to each of the plurality of islands 101, and the four connection portions 102 connected to one island 101 may extend in different directions, respectively, and be arranged adjacent to the one island 101, so as to be respectively connected to four other islands 101 surrounding the one island 101. The plurality of islands 101 and the plurality of connection portions 102 may include at least a portion continuously including the same material. The plurality of islands 101 and the plurality of connection portions 102 may be integrally formed.

[0057] The penetration portion V is formed to penetrate the substrate 100. The penetration portion V can provide a separation area between the plurality of islands 101, reduce the weight of the substrate 100, and enhance the flexibility of the substrate 100. In addition, according to the change in the shape of the penetration portion V when the substrate 100 is bent or curled, the generation of stress occurring during the change in the shape of the substrate 100 can be reduced, and thus, the abnormal change in the shape of the substrate 100 can be prevented or substantially prevented, and the durability of the substrate 100 can be enhanced. Therefore, for example, the user convenience during the use of the display device 10 can be improved, and the display device 10 can be applied to wearable devices.

[0058] The through portion V may be formed by removing a portion of the substrate 100 through a method such as etching, and as another example, the through portion V may also be formed while manufacturing the substrate 100. The process of forming the through portion V in the substrate 100 may be performed by any of various examples, and the method of forming the through portion V in the substrate 100 is not limited.

[0059] Herein, a unit portion U as a basic unit for configuring the substrate 100 is defined, and the structure of the substrate 100 will be described in further detail based on the unit portion U.

[0060] The unit portion U may be repeatedly arranged in the first direction X and the second direction Y. In other words, it can be understood that a plurality of unit portions U repeatedly arranged in the first direction X and the second direction Y are combined with each other and form the substrate 100. The unit portion U may include an island 101 and at least one connection portion 102 connected to the island 101. Four connection portions 102 may be connected to one island 101.

[0061] The islands 101 of two adjacent unit parts U may be separated from each other, and the connection parts 102 of the two adjacent unit parts U may be connected to each other. Here, the connection part 102 included in the unit part U may refer to a local area of ​​the connection part 102 located in the area of ​​the unit part U or the entire connection part 102 connecting the two adjacent islands 101 between the two adjacent islands 101.

[0062] Among the plurality of unit portions U, four adjacent unit portions U form a closed curve CL therebetween, and the closed curve CL may define a through portion V that is an empty space. The through portion V formed by removing a region from the substrate 100 may enhance the flexibility of the substrate 100 and reduce stress generated when the substrate 100 is deformed. The width of the connection portion 102 may be smaller than that of the island 101, and therefore, the through portion V may also contact the island 101 among the four unit portions U.

[0063] In an embodiment, among the plurality of unit parts U, two adjacent unit parts U may be symmetrical to each other. Figure 1 As shown, a unit portion U can be symmetrical with another unit portion U arranged adjacent to the one unit portion U in the second direction Y about an axis of symmetry parallel to the first direction X, and the one unit portion U can be symmetrical with another unit portion U arranged adjacent to the one unit portion U in the first direction X about an axis of symmetry parallel to the second direction Y.

[0064] In addition, the angle (θ) formed between the direction in which the connection portion 102 extends and the side surface of the island 101 to which the connection portion 102 is connected may be an acute angle. For example, when the island 101 has a quadrilateral shape and the quadrilateral corner portion of the quadrilateral shape is arranged to face the first direction X or the second direction Y, the connection portion 102 may be connected to the island 101 in an area adjacent to the corner portion and extend in a direction parallel to the second direction Y or the first direction X. In other words, the connection portion 102 connected to the corner portion facing the first direction may face the second direction Y or the direction opposite to the second direction (-Y), and the connection portion 102 connected to the corner portion facing the second direction Y may face the first direction X or the direction opposite to the first direction (-X). Therefore, the side surfaces of two adjacent islands 101 connected to one connection portion 102 and the direction in which the one connection portion 102 extends may form acute angles, respectively. Therefore, the islands 101 may be densely arranged and the length of the connection portion 102 may be minimized or reduced, thereby maximizing or increasing the area of ​​the through portion V. In addition, as Figure 2 As shown in , the substrate 100 may be provided with elongation properties.

[0065] Figure 2 1 shows the shape of the substrate 100 when it extends in the first direction X and the second direction Y. Figure 2 , when external force is applied to the substrate 100, each angle formed by the side surfaces of the islands 101 connected to the connection portion 102 and the connection portion 102 increases (θ<θ′), and thus, the area of ​​the penetration portion V may increase. Therefore, as the intervals between the islands 101 increase, the substrate 100 may be elongated in the first direction X and the second direction Y and deformed two-dimensionally or three-dimensionally.

[0066] Since the connection portion 102 has a smaller width than that of the island 101, when an external force is applied to the substrate 100, a change in shape for increasing the angle mainly occurs in the connection portion 102, and when the substrate 100 is stretched, the shape of the island 101 may not be changed. Therefore, even when the substrate 100 is stretched, the unit display portion 200 arranged on the island 101 may be stably maintained, and therefore, for example, the display device 10 may be applied to a display device requiring flexibility, such as any of a curved display device, a flexible display device, and a retractable display device, and the like.

[0067] During the elongation of the substrate 100, stress concentrates on the connection portion of the connection portion 102 connected to the side surface of the island 101. Therefore, the connection portion of the connection portion 102 may include a curved surface to prevent or substantially prevent the connection portion 102 from being torn or the like due to the concentration of stress.

[0068] Figure 3 yes Figure 1 A schematic top plan view of a portion of the unit shown in FIG. Figure 4 is shown along Figure 3 A schematic cross-sectional view of an example of a cross section taken along line II' shown in FIG. 1 ; and Figure 5 is shown along Figure 3 Schematic cross-sectional view of an example of a cross section taken along line II-II′ shown in FIG.

[0069] refer to Figures 3 to 5 The unit display portion 200 and the encapsulation layer 300 for sealing the unit display portion 200 may be located in the island 101 of the unit portion U, and the connecting portion 102 may include a pair of first connecting portions 102a and a pair of second connecting portions 102b, the pair of first connecting portions 102a being located at two opposite sides relative to the island 101 and extending in directions parallel to the first direction X, respectively, and the pair of second connecting portions 102b being located at two opposite sides relative to the island 101 and extending in directions parallel to the second direction Y, respectively.

[0070] The unit display portion 200 is located on the island 101, and in an embodiment, at least one organic light emitting diode OLED emitting red light, blue light, green light or white light may be located in the unit display portion 200, and the organic light emitting diode OLED may be electrically connected to the thin film transistor TFT. In the present embodiment, the organic light emitting diode OLED is described as a display element. However, the embodiment is not limited thereto, and the unit display portion 200 may include any of various types of display elements such as an inorganic electroluminescent (EL) device, a quantum dot light emitting device, and a liquid crystal device.

[0071] The unit display portion 200 may include a plurality of organic light emitting diodes OLED that emit different lights, respectively. Figures 3 to 5 As shown in FIG. 1 , one unit display portion 200 may form one pixel by including an organic light emitting diode OLED emitting red (R) light, an organic light emitting diode OLED emitting green (G) light, and an organic light emitting diode OLED emitting blue (B) light.

[0072] However, the embodiment is not limited thereto. As another example, each of the unit display parts 200 may include an organic light emitting diode OLED that emits red light, blue light, green light, or white light, thereby forming a sub-pixel. As another example, each of the unit display parts 200 may include a plurality of pixels.

[0073] In addition, the organic light emitting diodes OLED in the unit display portion 200 may be variously arranged according to the efficiency of materials included in the organic emission layer, for example, arranged in any one of an RGB manner, a Pentile structure, and a honeycomb structure.

[0074] A spacer S may be formed around the unit display portion 200. The spacer S is a member for preventing or substantially preventing the mask from being imprinted, and a height of the spacer S at the upper surface of the substrate 100 may be greater than a height of the organic light emitting diode OLED. Figure 3 In the embodiment, the spacer S is provided at the outer corner portion in the perimeter of the unit display portion 200, but the embodiment is not limited thereto. For example, the spacer S may be arranged in the unit display portion 200. For example, the spacer S may be provided on the pixel defining layer 211 formed in the unit display portion 200.

[0075] refer to Figure 4 The display device 10 according to the embodiment includes a substrate 100, unit display portions 200 each including a planarization layer 209, and an encapsulation layer 300 that seals each of the unit display portions 200. The unit display portions 200 may be arranged on islands 101 of the substrate 100, and wirings may be arranged on connection portions 102 connecting the islands 101.

[0076] First, the unit display portion 200 and the encapsulation layer 300 are described according to the stacking order of the unit display portion 200 and the encapsulation layer 300 arranged in the island 101 .

[0077] A buffer layer 201 for preventing or substantially preventing foreign matter from penetrating into the semiconductor layer Act of the thin film transistor TFT may be formed on the island 101. The buffer layer 201 may include a silicon oxide (SiO x ) or silicon nitride (SiN x) of the inorganic insulating layer, and may include a single layer or multiple layers including the inorganic insulating layer.

[0078] The pixel circuit may be arranged on the buffer layer 201. The pixel circuit includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. In the present embodiment, a top gate thin film transistor in which the gate electrode GE is located on the semiconductor layer Act and the gate insulating layer 203 is between the gate electrode GE and the semiconductor layer Act is illustrated. However, according to another embodiment, the thin film transistor TFT may be a bottom gate type.

[0079] In an embodiment, the semiconductor layer Act may include polycrystalline silicon. In another embodiment, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The gate electrode GE may include a low-resistance metal material. In an embodiment, the gate electrode GE may include a conductive material including any one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), etc., and may include a multilayer or a single layer including the materials described above.

[0080] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer 203 may include a single layer or multiple layers including the above-described materials.

[0081] The source electrode SE and the drain electrode DE may include a highly conductive material. In an embodiment, the source electrode SE and the drain electrode DE may each include a material including any one of Mo, Al, Cu, and Ti, and may include a multilayer or a single layer including the materials described above. For example, the source electrode SE and the drain electrode DE may include a multilayer of Ti / Al / Ti.

[0082] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 overlapping the lower electrode CE1, and the first interlayer insulating layer 205 is between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst may overlap the thin film transistor TFT. In this regard, Figure 4 The case where the gate electrode GE of the thin film transistor TFT is the lower electrode CE1 of the storage capacitor Cst is shown. In another embodiment, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 207.

[0083] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may include an inorganic insulating material such as any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may each include a single layer or multiple layers including the materials described above.

[0084] The pixel circuit including the thin film transistor TFT and the storage capacitor Cst may be covered by the planarization layer 209 .

[0085] The planarization layer 209 may include an organic insulating material such as a general commercial polymer (such as any one of polymethyl methacrylate (PMMA) and polystyrene (PS)), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and a blend thereof. In an embodiment, the planarization layer 209 may include polyimide.

[0086] In another embodiment, the planarization layer 209 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. As another embodiment, the planarization layer 209 may include a structure in which an organic insulating layer and an inorganic insulating layer are stacked. The planarization layer 209 may include an inorganic insulating material and an organic insulating material.

[0087] In the present embodiment, the planarization layer 209 may include a plane in which the upper surface is approximately flat, and includes a recess R that is recessed in a depth direction in a local area. The recess R may be provided in an area where the pixel electrode 221 is not arranged. That is, the pixel electrode 221 may be arranged on the flat upper surface of the planarization layer 209, and the recess R may be formed in an area in which the pixel electrode 221 is not formed. The recess R may be introduced to prevent or substantially prevent a material of a unit organic encapsulation layer 320u for forming an encapsulation layer 300 to be described later from flowing down to the penetration portion V.

[0088] In order to form the planarization layer 209, after applying the liquid organic material to cover the thin film transistor TFT, a mask process and a development process may be performed so that a through hole VH for exposing the drain electrode DE of the thin film transistor TFT is formed. As described above, the planarization layer 209 is formed by curing the liquid organic material, and the upper surface of the planarization layer 209 may be formed approximately flat.

[0089] Next, after forming a photoresist so that a region in which the recess R is to be formed is exposed, the recess R may be formed through an etching process. In an embodiment, the etching process may be a dry etching process.

[0090] However, the embodiment is not limited thereto. The recess R may be formed concurrently (eg, simultaneously) with the through hole VH of the planarization layer 209. For example, when the planarization layer 209 is formed, the through hole VH and the recess R may be formed concurrently (eg, simultaneously) in a process using a half-tone mask.

[0091] In an embodiment, the depth d of the recess R may be approximately 1 μm or greater. In an embodiment, the depth d of the recess R may be approximately 20%, 30%, or 50% of the thickness t of the planarization layer 209. In some embodiments, the thickness t of the planarization layer 209 may be approximately 4 μm, and the depth d of the recess R may be from approximately 1 μm to approximately 2 μm. In this case, the depth d of the recess R may indicate the distance from the flat upper surface of the planarization layer 209 to the lower surface of the recess R, and the thickness t of the planarization layer 209 may indicate the longest distance between the upper surface of the layer (e.g., the second interlayer insulating layer 207) on which the source electrode SE or the drain electrode DE of the thin film transistor TFT is arranged to the upper surface of the planarization layer 209.

[0092] Since the recess R surrounds the organic light emitting diode OLED, when a plurality of organic light emitting diodes OLED are provided in the unit display portion 200, the recess R may also be provided between the organic light emitting diodes OLED, such as in FIG. Figure 5 as shown in .

[0093] The pixel electrode 221 may be formed on the flat upper surface of the planarization layer 209. The pixel electrode 221 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode 221 may include a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a combination thereof. In another embodiment, the pixel electrode 221 may further include a reflective film containing ITO, IZO, ZnO or In above / below the reflective film described above. 2 O 3 membrane.

[0094] The pixel defining layer 211 may be formed on the pixel electrode 221. The pixel defining layer 211 may include an opening that exposes the upper surface of the pixel electrode 221 and covers the edge of the pixel electrode 221. Therefore, the pixel defining layer 211 may define the emission area of ​​the pixel. The pixel defining layer 211 may include an organic insulating material. In an embodiment, the pixel defining layer 211 may include an organic insulating material such as SiN x , SiON or SiOx In another embodiment, the pixel defining layer 211 may include an organic insulating material and an inorganic insulating material.

[0095] In an embodiment, the thickness of the pixel defining layer 211 may be less than that of the planarization layer 209. Therefore, the pixel defining layer 211 may fill the recess R of the planarization layer 209, and a concave portion corresponding to the shape of the recess R may be formed on the upper surface of the pixel defining layer 211.

[0096] The intermediate layer 222 of the organic light emitting diode OLED may include a low molecular weight material or a polymer material. When the intermediate layer 222 includes a low molecular weight material, the intermediate layer 222 may have a single layer structure or a multilayer stacked structure of a hole injection layer (HIL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc., and the low molecular weight material may include copper phthalocyanine (CuPc), N, N'-bis (naphthalene-1-yl) -N, N'-diphenyl-benzidine (NPB) and tri-8-hydroxyquinoline aluminum (Alq 3 ) In an embodiment, such a layer may be formed by a vacuum deposition method.

[0097] In an embodiment, the intermediate layer 222 including a polymer material may have a structure including an HTL and an EML. In this case, the HTL may include poly(3,4-ethylenedioxythiophene (PEDOT)), and the EML may include a high molecular weight material such as a polyphenylene vinylene material and polyfluorene. The intermediate layer 222 may be formed by using any one of a screen printing method, an inkjet printing method, a laser induced thermal imaging (LITI) method, and the like.

[0098] However, the intermediate layer 222 is not limited thereto and may have any of various structures. In addition, the intermediate layer 222 may include a layer integrally formed above the plurality of pixel electrodes 221 and may also include a layer patterned to correspond to each of the plurality of pixel electrodes 221 .

[0099] The counter electrode 223 may include a conductive material having a small work function. For example, the counter electrode 223 may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy thereof. In an embodiment, the counter electrode 223 may further include a (semi) transparent layer such as ITO, IZO, ZnO or In on the (semi) transparent layer including the materials described above. 2 O 3The counter electrode 223 may be formed not only in the display area but also in the non-display area. In an embodiment, the intermediate layer 222 and the counter electrode 223 may be formed by a thermal deposition method. The counter electrode 223 formed on the top surface of the substrate 100 may also be partially arranged on the side surface of the penetration portion V.

[0100] A capping layer (not shown) for protecting the opposite electrode 223 may be further disposed on the opposite electrode 223. The capping layer may include lithium fluoride (LiF), an inorganic material, and / or an organic material.

[0101] The encapsulation layer 300 that seals the unit display portion 200 is formed on the opposing electrode 223. The encapsulation layer 300 may block external oxygen or moisture and include a single layer or multiple layers. The encapsulation layer 300 may include at least one of an organic encapsulation layer and an inorganic encapsulation layer.

[0102] exist Figure 4 and Figure 5 In the embodiment, the encapsulation layer 300 includes a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 and an organic encapsulation layer 320 located between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330, but the embodiment is not limited thereto. In another embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order may be changed differently.

[0103] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic insulating material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride, and may be formed by a chemical vapor deposition (CVD) method, etc. The organic encapsulation layer 320 may include a polymer material. The polymer material may include any one of acrylic resin, epoxy resin, polyimide, polyethylene, etc.

[0104] When the first inorganic encapsulation layer 310 is formed along the structure below the first inorganic encapsulation layer 310, as shown in FIG. Figure 4 and Figure 5 As shown in , in an embodiment, the upper surface of the first inorganic encapsulation layer 310 is uneven. The organic encapsulation layer 320 covers the first inorganic encapsulation layer 310, and unlike the first inorganic encapsulation layer 310, the organic encapsulation layer 320 may have an approximately flat upper surface. More specifically, the upper surface of the organic encapsulation layer 320 may be approximately flat in a portion corresponding to the organic light emitting diode OLED as a display element. In addition, the organic encapsulation layer 320 may relieve stress occurring on the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0105] The organic encapsulating layer 320 may include any one of polymethyl methacrylate (PMMA), polycarbonate (PC), polystyrene (PS), acrylic resin, epoxy resin, polyimide, polyethylene, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisilane, and the like.

[0106] In the present embodiment, the organic encapsulation layer 320 may be provided as unit organic encapsulation layers 320u to respectively correspond to the unit display portions 200. That is, the unit organic encapsulation layer 320u may be disposed on the island 101 of the substrate 100, but not on the connection portion 102. Therefore, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may contact each other at the periphery of the unit organic encapsulation layer 320u to individually encapsulate each of the unit display portions 200.

[0107] As described above, the encapsulation layer 300 includes the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330, and by using the multilayer structure, even when cracks occur in the encapsulation layer 300, connection between cracks between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320 or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330 can be prevented or substantially prevented. Therefore, the formation of a path through which external moisture or oxygen can penetrate into the unit display portion 200 can be prevented or minimized. In addition, the second inorganic encapsulation layer 330 can contact the first inorganic encapsulation layer 310 at an edge located outside the unit organic encapsulation layer 320u, thereby preventing or substantially preventing the unit organic encapsulation layer 320u from being exposed to the outside.

[0108] In an embodiment, the first and second inorganic encapsulating layers 310 and 330 may be formed with respect to the entire surface of the substrate 100 by using a CVD method and may be formed to cover side surfaces of the penetration portion V.

[0109] When forming the unit organic encapsulation layer 320u, a certain amount of liquid organic material is applied corresponding to the unit display part 200, and a curing process is performed on the applied liquid organic material. At this time, due to the characteristics of the liquid organic material, flow occurs toward the edge of the unit display part 200.

[0110] In the present embodiment, since the recess R recessed in the depth direction is formed in the upper surface of the planarization layer 209 , the liquid organic material used to form the unit organic encapsulation layer 320 u can be prevented or substantially prevented from flowing down to the edge of the unit display portion 200 .

[0111] To prevent or substantially prevent the liquid organic material from flowing down to the edge of the unit display portion 200 and overflowing the penetration portion V, a protruding dam structure may be provided at the edge of the unit display portion 200. However, when the dam structure is provided, the dam structure may be damaged during formation of the penetration portion V.

[0112] In an embodiment of the present disclosure, a recess R may be formed in the upper surface of the planarization layer 209 to surround the organic light emitting diode OLED as a display element in the unit display portion 200 to prevent or substantially prevent the formation of an edge tail of the unit organic encapsulation layer 320u.

[0113] In an embodiment, the pixel defining layer 211, the opposing electrode 223, and the first inorganic encapsulation layer 310 may fill the recess R. In this case, the pixel defining layer 211, the opposing electrode 223, and the first inorganic encapsulation layer 310 may have a small thickness, and a recessed portion corresponding to the shape of the recess R may also be formed in the upper surfaces of the pixel defining layer 211, the opposing electrode 223, and the first inorganic encapsulation layer 310. Due to the recessed portion, the unit organic encapsulation layer 320u may be prevented or substantially prevented from flowing down to the edge of the island 101.

[0114] The step compensation layer 202 may be disposed on the connection portion 102b of the substrate 100. The connection portion 102b of the substrate 100 may have a width smaller than that of the island 101, and thus may be susceptible to stress occurring when the shape of the display device 10 is changed. Therefore, at least one of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207, which are inorganic insulating layers, may not be disposed on the connection portion 102b of the substrate 100.

[0115] For example, the buffer layer 201 , the gate insulating layer 203 , the first interlayer insulating layer 205 , and the second interlayer insulating layer 207 may be removed from the connection portion 102 b by a process such as an etching process, and the step compensation layer 202 including an organic material may be formed.

[0116] Wiring W for transmitting voltage or signal to the unit display portion 200 is arranged on the step compensation layer 202. Therefore, the step compensation layer 202 can prevent or substantially prevent the height difference when the wiring W is connected to the island 101 and absorb stress that may be applied to the wiring W.

[0117] The step compensation layer 202 may include an organic insulating material such as any one of polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisilane (HMDSO), and phenolic resin. The step compensation layer 202 may include a single layer or multilayer structure including the organic insulating material described above.

[0118] In an embodiment, the wiring W disposed on the step compensation layer 202 may include the same material as the source electrode SE or the drain electrode DE of the thin film transistor TFT disposed on the island 101. In an embodiment, the wiring W disposed on the step compensation layer 202 may include the same material as the gate electrode GE of the thin film transistor TFT. The wiring W may include a wiring for transmitting a voltage or a signal to a pixel circuit.

[0119] The wiring W may be covered by the planarization layer 209. The counter electrode 223, the first inorganic encapsulation layer 310, and the second inorganic encapsulation layer 330 may be stacked on the planarization layer 209. The counter electrode 223, the first inorganic encapsulation layer 310, and the second inorganic encapsulation layer 330, which may be formed after forming the through portion V by using an open mask, may surround the side surface of the through portion V. In an embodiment, although not shown, the pixel defining layer 211 may be further arranged between the planarization layer 209 and the counter electrode 223, and the capping layer may be further arranged between the counter electrode 223 and the first inorganic encapsulation layer 310.

[0120] Figure 6 is a schematic cross-sectional view showing a display device according to another embodiment. Figure 6 Can be used with Figure 3 The line I-I' shown in Figure 6 In, with Figure 3 and Figure 4 The same reference numerals as those in the accompanying drawings denote the same components, and their repeated descriptions may be omitted.

[0121] refer to Figure 6 , the display device 10 according to the embodiment includes a substrate 100 , a unit display portion 200 including a planarization layer 209 , and an encapsulation layer 300 sealing each of the unit display portions 200 .

[0122] like Figures 1 to 3 As shown in , the substrate 100 may include a plurality of islands 101 spaced apart from each other, a plurality of connection portions 102 connecting the plurality of islands 101 , and a plurality of penetration portions V penetrating the substrate 100 between the plurality of connection portions 102 .

[0123] The unit display portions 200 are respectively arranged on a plurality of islands 101. That is, the unit display portion 200 may indicate a group of display elements arranged on one island 101. In an embodiment, the unit display portion 200 may include only one display element. In another embodiment, the unit display portion 200 may include a plurality of display elements representing red, green, and blue.

[0124] The unit display portion 200 includes a planarization layer 209, and a display element (e.g., an organic light emitting diode OLED) may be arranged on the planarization layer 209. The planarization layer 209 may provide a flat upper surface in a region in which the organic light emitting diode OLED as a display element is arranged, and may include a recess R recessed in a depth direction on one side of the display element or around the display element.

[0125] In an embodiment, the depth d of the recess R may be approximately 1 μm or greater. In an embodiment, the depth d of the recess R may be approximately 20%, 30%, or 50% of the thickness t of the planarization layer 209. In some embodiments, the thickness t of the planarization layer 209 may be approximately 4 μm, and the depth d of the recess R may be from approximately 1 μm to approximately 2 μm. In this case, the depth d of the recess R indicates the distance from the flat upper surface of the planarization layer 209 to the lower surface of the recess R, and the thickness t of the planarization layer 209 may indicate the longest distance between the upper surface of the layer (e.g., the second interlayer insulating layer 207) on which the source electrode SE or the drain electrode DE of the thin film transistor TFT is arranged to the upper surface of the planarization layer 209.

[0126] In the present embodiment, the pixel defining layer 211 may not be disposed on the recess R. That is, the pixel defining layer 211 may be formed to expose the recess R. Since the pixel defining layer 211 does not fill the inner portion of the recess R, the depth of the recessed portion formed in the first inorganic encapsulation layer 310 may be greater than the depth of the recessed portion in the case where the pixel defining layer 211 is disposed in the recess R.

[0127] As the depth of the recessed portion increases, the organic encapsulation layer 320 can be more effectively prevented from flowing down to the edge of the island 101 .

[0128] That is, in the present embodiment, since the planarization layer 209 includes the recess R, the unit organic encapsulation layer 320u included in the encapsulation layer 300 does not flow toward the penetration portion V and is arranged to correspond to the unit display portion 200, and the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 contact each other at the periphery of the unit organic encapsulation layer 320u. Therefore, the encapsulation layer 300 seals each of the unit display portions 200.

[0129] Figure 7 is a schematic cross-sectional view showing a display device according to another embodiment. Figure 7 Can be used with Figure 3 The line I-I' shown in Figure 7 In, with Figure 3 and Figure 4 The same reference numerals as those in the accompanying drawings denote the same components, and their repeated descriptions may be omitted.

[0130] refer to Figure 7 , the display device 10 according to the embodiment includes a substrate 100 , a unit display portion 200 including a planarization layer 209 , and an encapsulation layer 300 sealing each of the unit display portions 200 .

[0131] like Figures 1 to 3 As shown in , the substrate 100 may include a plurality of islands 101 spaced apart from each other, a plurality of connection portions 102 connecting the plurality of islands 101 , and a plurality of penetration portions V penetrating the substrate 100 between the plurality of connection portions 102 .

[0132] The unit display portions 200 are respectively arranged on a plurality of islands 101. That is, the unit display portion 200 may be a group of display elements arranged on one island 101. In an embodiment, the unit display portion 200 may include only one display element. In another embodiment, the unit display portion 200 may include a plurality of display elements representing red, green, and blue.

[0133] The unit display portion 200 includes a planarization layer 209, and a display element (e.g., an organic light emitting diode OLED) may be arranged on the planarization layer 209. The planarization layer 209 may provide a flat upper surface in a region in which the organic light emitting diode OLED as a display element is arranged, and may include a recess R recessed in a depth direction on one side of the display element or around the display element.

[0134] In an embodiment, the depth d of the recess R may be approximately 1 μm or greater. In an embodiment, the depth d of the recess R may be approximately 20%, 30%, or 50% of the thickness t of the planarization layer 209. In some embodiments, the thickness t of the planarization layer 209 may be approximately 4 μm, and the depth d of the recess R may be from approximately 1 μm to approximately 2 μm. In this case, the depth d of the recess R indicates the distance from the flat upper surface of the planarization layer 209 to the lower surface of the recess R, and the thickness t of the planarization layer 209 may indicate the longest distance between the upper surface of the layer (e.g., the second interlayer insulating layer 207) on which the source electrode SE or the drain electrode DE of the thin film transistor TFT is arranged to the upper surface of the planarization layer 209.

[0135] In the present embodiment, the planarization layer 209 may include an organic planarization layer 209 a and an inorganic planarization layer 209 b disposed on the organic planarization layer 209 a .

[0136] The organic planarization layer 209a may include a through hole VH exposing the drain electrode DE of the thin film transistor TFT, and may have a flat (e.g., completely flat) upper surface. The organic planarization layer 209a may include an organic insulating material such as a general commercial polymer (such as any one of PMMA and PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and a blend thereof. For example, the organic planarization layer 209a may include polyimide.

[0137] The recess R may be provided in the inorganic planarization layer 209b. The recess R may be arranged on one side or around the organic light emitting diode OLED as a display element. The inorganic planarization layer 209b arranged on the organic planarization layer 209a may have a flat upper surface in a region where the organic light emitting diode OLED is arranged.

[0138] In an embodiment, the depth d of the recess R may be approximately 1 μm or greater. In an embodiment, the depth d of the recess R may be approximately 20%, 30%, or 50% of the total thickness t of the planarization layer 209. In some embodiments, the total thickness t of the planarization layer 209 may be approximately 4 μm, and the depth d of the recess R may be from approximately 1 μm to approximately 2 μm. In this case, the depth d of the recess R indicates the distance from the flat upper surface of the planarization layer 209 to the lower surface of the recess R, and the total thickness t of the planarization layer 209 may indicate the longest distance between the upper surface of the layer (e.g., the second interlayer insulating layer 207) on which the source electrode SE or the drain electrode DE of the thin film transistor TFT is arranged to the upper surface of the planarization layer 209.

[0139] The inorganic planarization layer 209b may include SiN x 、SiO x Or inorganic insulating materials such as SiON.

[0140] exist Figure 7 , the recess R is shown as not penetrating the inorganic planarization layer 209b, but the embodiment is not limited thereto. In an embodiment, the recess R may penetrate the inorganic planarization layer 209b so that the upper surface of the organic planarization layer 209a is exposed. In an embodiment, the recess R may be formed so that the inorganic planarization layer 209b is penetrated and a portion of the organic planarization layer 209a may be removed in the depth direction. In other words, the recess R may have any of various concave shapes in the depth direction of the entire portion of the planarization layer 209.

[0141] In the present embodiment, since the planarization layer 209 includes the recess R, the unit organic encapsulation layer 320u included in the encapsulation layer 300 does not flow toward the penetration portion V and is arranged to correspond to the unit display portion 200, and the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 contact each other at the periphery of the unit organic encapsulation layer 320u. Therefore, the encapsulation layer 300 seals each of the unit display portions 200.

[0142] Figure 8 is a schematic cross-sectional view showing a display device according to another embodiment. Figure 8 Can be used with Figure 3 The line I-I' shown in Figure 8 In, with Figure 3 and Figure 4 The same reference numerals as those in the accompanying drawings denote the same components, and their repeated descriptions may be omitted.

[0143] refer to Figure 8 , the display device 10 according to the embodiment includes a substrate 100 , a unit display portion 200 including a planarization layer 209 , and an encapsulation layer 300 sealing each of the unit display portions 200 .

[0144] like Figures 1 to 3 As shown in , the substrate 100 may include a plurality of islands 101 spaced apart from each other, a plurality of connection portions 102 connecting the plurality of islands 101 , and a plurality of penetration portions V penetrating the substrate 100 between the plurality of connection portions 102 .

[0145] The unit display portions 200 are respectively arranged on a plurality of islands 101. That is, the unit display portion 200 may be a group of display elements arranged on one island 101. In an embodiment, the unit display portion 200 may include only one display element. In another embodiment, the unit display portion 200 may include a plurality of display elements representing red, green, and blue.

[0146] The unit display portion 200 includes a planarization layer 209, and a display element (e.g., an organic light emitting diode OLED) may be arranged on the planarization layer 209. The planarization layer 209 may provide a flat upper surface in a region in which the organic light emitting diode OLED as a display element is arranged, and may include a recess R recessed in a depth direction on one side of the display element or around the display element.

[0147] In the present embodiment, the inorganic protective layer PVX and the lower planarization layer 208 may be additionally disposed between the thin film transistor TFT and the planarization layer 209. In addition, the step compensation layer 202 may be disposed in a portion of the island 101 of the substrate 100.

[0148] In an embodiment, the inorganic protective layer PVX may include SiN x and SiO x The inorganic protective layer PVX may cover and protect the source electrode SE and some wiring of the thin film transistor TFT. In an embodiment, a wiring (not shown) formed together with the source electrode SE in the same process may be exposed in a local area of ​​the substrate 100. The exposed portion of the wiring may be damaged by the etchant used in the patterning of the pixel electrode 221. However, since the inorganic protective layer PVX covers at least some of the wiring in the present embodiment, the wiring may be prevented or substantially prevented from being damaged in the patterning process of the pixel electrode 221.

[0149] The lower planarization layer 208 may be disposed between the inorganic protective layer PVX and the planarization layer 209. The lower planarization layer 208 may include an organic insulating material such as a general commercial polymer such as any one of polymethyl methacrylate (PMMA) and polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend thereof.

[0150] A connection metal CM for connecting the pixel electrode 221 and the thin film transistor TFT may be arranged on the lower planarization layer 208. In an embodiment, on the lower planarization layer 208, a wiring (not shown) may be arranged on the same layer as the connection metal CM. In an embodiment, the connection metal CM may include a conductive material including any one of Mo, Al, Cu, and Ti, and may include a multilayer or a single layer including the materials described above. As described above, since the lower planarization layer 208 is provided, the wiring may also be arranged on the lower planarization layer 208, and therefore, the density of the components in the unit display portion 200 may be enhanced.

[0151] The step compensation layer 202 may be disposed in a portion of the island 101 of the substrate 100. In an embodiment, the step compensation layer 202 may be disposed to cover side surfaces of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207.

[0152] In the process of removing the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 disposed on the connection portion 102b, some of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 disposed on the island 101 are removed, and the step compensation layer 202 is filled in the portion from which some of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 are removed. Next, the planarization layer 209, the pixel defining layer 211, and the penetration portion V may be formed.

[0153] Therefore, a portion of the step compensation layer 202 may be disposed on the island 101 .

[0154] In an embodiment, the depth d of the recess R formed in the planarization layer 209 may be approximately 1 μm or greater. In an embodiment, the depth d of the recess R may be approximately 20%, 30%, or 50% of the total thickness t of the inorganic protective layer PVX, the lower planarization layer 208, and the planarization layer 209. In some embodiments, the total thickness t may be approximately 4 μm, and the depth d of the recess R may be from approximately 1 μm to approximately 2 μm. In this case, the depth d of the recess R indicates the distance from the flat upper surface of the planarization layer 209 to the lower surface of the recess R, and the total thickness t may indicate the longest distance between the upper surface of the layer (e.g., the second interlayer insulating layer 207) on which the source electrode SE or the drain electrode DE of the thin film transistor TFT is arranged to the upper surface of the planarization layer 209.

[0155] In other words, the step compensation layer 202 , the lower planarization layer 208 , and the planarization layer 209 may be disposed in the connection portion 102 b , and the additional wiring W′ may be disposed between the lower planarization layer 208 and the planarization layer 209 .

[0156] In the present embodiment, since the planarization layer 209 includes the recess R, the unit organic encapsulation layer 320u included in the encapsulation layer 300 does not flow toward the penetration portion V and is arranged to correspond to the unit display portion 200, and the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 contact each other at the periphery of the unit organic encapsulation layer 320u. Therefore, the encapsulation layer 300 seals each of the unit display portions 200.

[0157] According to the embodiment, an encapsulation layer having high reliability may be implemented in the display device 10 whose shape may be changed. However, the scope of the embodiment is not limited to the effects described above.

[0158] It should be understood that the embodiments described herein should be considered to be illustrative and not for limiting purposes. The description of the features or aspects in each embodiment should typically be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various modifications in form and detail may be made in one or more embodiments without departing from the spirit and scope as set forth in the appended claims.

Claims

1. A display device, comprising: substrate; a plurality of unit display portions, each of which includes a thin film transistor located on the substrate, a first display element and a second display element disposed on the thin film transistor, and a planarization layer located between the thin film transistor and the first display element and the second display element; and an encapsulation layer for sealing each of the plurality of unit display portions, wherein the planarization layer comprises a first recess and a second recess, each of which is recessed in a depth direction, wherein the first recess is located at least in a portion between the first display element and the second display element included in each of the unit display sections, the second recess is located at the periphery of each of the plurality of unit display sections, and The depth of the first recess is smaller than the thickness of the planarization layer.

2. The display device according to claim 1, wherein: The first recess at least partially surrounds the first and second display elements.

3. The display device according to claim 1, wherein: The encapsulation layer includes an organic encapsulation layer, a first inorganic encapsulation layer arranged below the organic encapsulation layer, and a second inorganic encapsulation layer arranged above the organic encapsulation layer. The organic encapsulation layer includes unit organic encapsulation layers respectively corresponding to the plurality of unit display parts, and The first inorganic encapsulating layer and the second inorganic encapsulating layer contact each other at a periphery of the unit organic encapsulating layer.

4. The display device according to claim 3, wherein: The substrate includes a plurality of islands spaced apart from each other, a plurality of connection portions connecting the plurality of islands, and a plurality of penetration portions penetrating the substrate between the plurality of connection portions, and The plurality of unit display portions are arranged on the plurality of islands, respectively.

5. The display device according to claim 4, wherein: The first inorganic encapsulating layer and the second inorganic encapsulating layer are at least partially disposed on side surfaces of the plurality of penetration portions.

6. The display device according to claim 4, further comprising: wirings on the plurality of connection portions, wherein electrical signals are transmitted to the unit display portion through the wirings; as well as The step compensation layer is disposed between the plurality of connection portions and the wirings and includes an organic material.

7. The display device according to claim 1, wherein: The first display element includes a pixel electrode, an intermediate layer and a counter electrode, The pixel electrode is arranged on the planarization layer, and A pixel defining layer covering an edge of the pixel electrode is disposed on the planarization layer, wherein the pixel defining layer exposes the second recess.

8. The display device according to claim 1, wherein the planarization layer comprises an organic planarization layer and an inorganic planarization layer arranged on the organic planarization layer, and The first recess is provided in the inorganic planarization layer.

9. The display device according to claim 1, further comprising: The inorganic protective layer is arranged between the thin film transistor and the planarization layer and covers the source electrode or the drain electrode of the thin film transistor.

10. A display device, comprising: a substrate including a plurality of islands spaced apart from each other, a plurality of connection portions connecting the plurality of islands, and a plurality of penetration portions penetrating the substrate between the plurality of connection portions; A plurality of unit display parts are arranged on the plurality of islands respectively; as well as an encapsulation layer for sealing each of the plurality of unit display portions, Each of the plurality of unit display sections includes a thin film transistor, a first organic light emitting diode and a second organic light emitting diode disposed on the thin film transistor, and a planarization layer located between the thin film transistor and the first organic light emitting diode and the second organic light emitting diode, wherein the planarization layer comprises a first recess and a second recess, each of which is recessed in a depth direction, wherein the first recess is located at least in a portion between the first organic light emitting diode and the second organic light emitting diode included in each of the unit display portions, the second recess is located at a periphery of each of the plurality of unit display portions, and The depth of the first recess is smaller than the thickness of the planarization layer.

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