Semiconductor devices and their manufacturing methods

Abstract

This disclosure relates to a semiconductor device and a method for manufacturing the same. In a deep trench DTC extending from a first main surface of a semiconductor substrate SUB to a predetermined depth, a plurality of columnar conductors CCBs, including plugs PUGs and field plates FP, are formed. A p-type impurity layer PIL is formed along the sidewall surface of the deep trench DTC. Between the bottom of the plugs PUGs and the bottom of the p-type impurity layer PIL, the field plate FP and the p-type impurity layer PIL are positioned facing each other via an insulating film FIF inserted therebetween. Between the bottom of the p-type impurity layer PIL and the bottom of the field plate FP, the field plate FP and an n-type drift layer NDL of the semiconductor substrate SUB are positioned facing each other via an insulating film FIF inserted therebetween.

Description

[0001] Cross-reference to related applications

[0002] The disclosure (including specification, drawings and abstract) of Japanese Patent Application No. 2019-070450, filed on April 2, 2019, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and the invention can be suitably used in semiconductor devices, for example, having a field plate structure and a superjunction structure. Background Technology

[0004] In semiconductor devices for power systems, field plate structures are used as structures to achieve low conduction resistance (on-resistance) and high withstand voltage. Patent documents 1 and 2 disclose, for example, semiconductor devices having field plate structures.

[0005] In semiconductor devices for power systems, increasing the impurity concentration of the drift layer (e.g., an n-type drift layer) is necessary to reduce on-resistance. However, increasing the impurity concentration of the drift layer leads to a decrease in breakdown voltage. In field-plate semiconductor devices, the electric field strength is increased, and the breakdown voltage of the drift layer can be improved without increasing the impurity concentration.

[0006] The following technologies have been disclosed.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2012-059943

[0008] [Patent Document 2] International Patent Publication No. P2011-512677A Summary of the Invention

[0009] In semiconductor devices for power systems, there is a need for even higher voltage withstand and lower on-resistance. Other objectives and novel features will become clear from the description and accompanying drawings in this specification.

[0010] Problem-solving methods

[0011] A semiconductor device according to one embodiment includes a semiconductor substrate of a first conductivity type, a first electrode, a second electrode, a plurality of pillared conductors, a first impurity region of a second conductivity type, a second impurity region of a second conductivity type, a third impurity region of a first conductivity type, and a gate electrode. The semiconductor substrate has a first main surface and a second main surface, and the first electrode is formed on one side of the first main surface, and the second electrode is formed on one side of the second main surface. The plurality of pillared conductors are electrically connected to the first electrode and are formed from the first main surface of the semiconductor substrate to a first depth. For each of the plurality of pillared conductors, at a second depth shallower than the first depth from the first main surface of the semiconductor substrate, the first impurity region of the second conductivity type is formed around the pillared conductor and is electrically connected to the first electrode. The second impurity region of the second conductivity type is formed from the first main surface of the semiconductor substrate to a third depth shallower than the second depth and is electrically connected to the first electrode. The third impurity region of the first conductivity type is formed from one side of the first main surface of the second impurity region to a fourth depth shallower than the third depth and is electrically connected to the first electrode. A gate electrode is formed in a gate trench via a gate dielectric film to penetrate the third impurity region and the second impurity region, the gate trench extending from the first main surface to a portion of the semiconductor substrate of the first conductivity type. First impurity regions are in contact with portions of a first conductivity type semiconductor substrate and second impurity regions, respectively. Each of the plurality of pillar conductors includes a field plate formed from a fifth depth (shallower than the second depth) to a first depth, as viewed from a first main surface of the semiconductor substrate, and formed in the first conductivity type semiconductor substrate via an insulating film. Between the fifth depth and the second depth, the field plate and the first impurity regions face each other, with the insulating film interposed between them. Between the second depth and the first depth, the field plate and the first conductivity type semiconductor substrate face each other, with the insulating film interposed between them.

[0012] A method for manufacturing a semiconductor device according to another embodiment includes the following steps.

[0013] A semiconductor substrate of a first conductivity type is prepared, having a first main surface and a second main surface. A gate trench of a predetermined depth is formed in the first main surface of the semiconductor substrate, and a gate electrode is formed by inserting a gate dielectric film into the gate trench. A deep trench of a first depth, deeper than the gate trench, is formed on the first main surface of the semiconductor substrate at a certain distance from the gate electrode. Impurities of a second conductivity type are implanted into the sidewall surfaces of the deep trench to form a first impurity region of the second conductivity type at a second depth shallower than the first depth from the first main surface of the semiconductor substrate. To fill the interior of the deep trench, a conductive film is formed to fill the deep trench via an insulating film covering the sidewall surfaces of the deep trench. A second impurity region of the second conductivity type is formed from the first main surface of the semiconductor substrate to a third depth shallower than the bottom of the gate trench, in a manner contacting the first impurity region. A third impurity region of the first conductivity type is formed from one side of the first main surface of the second impurity region to a fourth depth shallower than the third depth, in a manner reaching the sidewall surfaces of the deep trench. To expose the third and first impurity regions, a portion of the insulating film and a portion of the conductive film in the deep trench, located at a fifth depth shallower than the second depth and deeper than the third depth from one side of the first main surface, are removed, and the remaining portion of the conductive film is formed as a field plate. A plug is formed in the deep trench reaching the fifth depth and contacting the field plate and the third and first impurity regions. A first electrode electrically connected to the plug is formed on the first main surface of the semiconductor substrate. A second electrode is formed on the second main surface of the semiconductor substrate.

[0014] According to one embodiment, both high voltage withstand capability and low on-resistance of a semiconductor device can be achieved.

[0015] According to another embodiment, a semiconductor device capable of achieving both high withstand voltage and low on-resistance can be manufactured. Attached Figure Description

[0016] Figure 1 These are examples of planar patterns of semiconductor devices according to each embodiment;

[0017] Figure 2 The semiconductor device according to the first embodiment is in Figure 1 The cross-sectional view shown in section line II-II;

[0018] Figure 3 The semiconductor device of the first embodiment and Figure 1 Perspective view of the section corresponding to section line II-II shown;

[0019] Figure 4 This is a partially enlarged plan view showing an example of a planar pattern of the semiconductor device in the first embodiment;

[0020] Figure 5 The semiconductor device in the first embodiment is Figure 4 A partial cross-sectional view at section line VV shown;

[0021] Figure 6 This is a cross-sectional view showing one step of the manufacturing method of the semiconductor device in the first embodiment;

[0022] Figure 7 It is shown in Figure 6 A cross-sectional view of the steps performed after the process shown;

[0023] Figure 8 It is shown in Figure 7 A cross-sectional view of the steps performed after the process shown;

[0024] Figure 9 It is shown in Figure 8 A cross-sectional view of the steps performed after the process shown;

[0025] Figure 10 It is shown in Figure 9 A cross-sectional view of the steps performed after the process shown;

[0026] Figure 11 It is shown in Figure 10 A cross-sectional view of the steps performed after the process shown;

[0027] Figure 12 It is shown in Figure 11 A cross-sectional view of the steps performed after the process shown;

[0028] Figure 13 It is shown in Figure 12 A cross-sectional view of the steps performed after the process shown;

[0029] Figure 14 It is shown in Figure 13 A cross-sectional view of the steps performed after the process shown;

[0030] Figure 15 It is shown in Figure 14 A cross-sectional view of the steps performed after the process shown;

[0031] Figure 16 This is a partial cross-sectional view showing the initialization state, used to explain the simulation-based evaluation of the semiconductor device involving the first embodiment;

[0032] Figure 17 This is a partial cross-sectional view showing the initial state, used to explain the simulation-based evaluation of the semiconductor device based on the comparative example;

[0033] Figure 18This is a partial cross-sectional view showing the distribution of the electric field intensity, used to explain the evaluation performed by simulating the semiconductor device involved in the first embodiment;

[0034] Figure 19 This is a partial cross-sectional view showing the distribution of the electric field intensity, used to interpret the evaluation performed by simulating a semiconductor device based on a comparative example;

[0035] Figure 20 This is a graph showing the relationship between the depth direction of the n-type drift layer and the electric field strength below the gate electrode in the first embodiment;

[0036] Figure 21 This is a graph showing the relationship between the depth of the p-type impurity layer and the breakdown voltage in the first embodiment;

[0037] Figure 22 This is a graph showing the relationship between the peak concentration of the p-type impurity layer and the breakdown voltage in the first embodiment;

[0038] Figure 23 This is a cross-sectional view used to illustrate the charge balance between the p-type impurity layer and the n-type drift layer in the first embodiment;

[0039] Figure 24 It is shown Figure 23 A diagram illustrating an example of the impurity concentration distribution in the p-type impurity layer and n-type drift layer along cross-sections XXIV-XXIV;

[0040] Figure 25 It is shown Figure 23 A diagram illustrating an example of the impurity concentration distribution in the p-type impurity layer and n-type drift layer along the cross-sectional line XXV-XXV;

[0041] Figure 26 This is a partial plan view showing a modified example of the planar arrangement pattern of the gate electrodes in each embodiment;

[0042] Figure 27 This is a partial plan view illustrating a first modified example of the planar construction of the columnar conductor including the field plate in each embodiment;

[0043] Figure 28 This is a partial plan view illustrating a second modified example of the planar construction of the columnar conductor including the field plate in each embodiment;

[0044] Figure 29 This is a partial plan view illustrating a third modified example of the planar construction of the columnar conductor including the field plate in each embodiment;

[0045] Figure 30 The semiconductor device according to the second embodiment and Figure 1The cross-sectional view corresponding to section line II-II shown;

[0046] Figure 31 This is a cross-sectional view showing one step of the method for manufacturing a semiconductor device in the second embodiment;

[0047] Figure 32 It is shown in Figure 31 A cross-sectional view of the steps performed after the process shown;

[0048] Figure 33 It is shown in Figure 32 A cross-sectional view of the process performed after the process shown;

[0049] Figure 34 This is a graph showing the relationship between the depth direction of the n-type drift layer and the electric field strength below the gate electrode in the second embodiment;

[0050] Figure 35 The semiconductor device according to the third embodiment and Figure 1 The cross-sectional view corresponding to section line II-II shown;

[0051] Figure 36 This is a cross-sectional view showing one step of the method for manufacturing a semiconductor device according to the third embodiment;

[0052] Figure 37 This is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to a modified example of the third embodiment; and

[0053] Figure 38 This is a graph showing the relationship between the depth direction of the n-type drift layer and the electric field strength below the gate electrode in the third embodiment. Detailed Implementation

[0054] (Example 1)

[0055] An example of a semiconductor device according to the first embodiment will be described. The planar structure of the semiconductor device PSD will be described. For example... Figure 1 As shown, in a semiconductor device PSD, a gate electrode pad (GEP) and a source electrode pad (SEP) are formed on the first main surface of a semiconductor substrate (SUB). A drain electrode pad (DEP) is formed on the other main surface (second main surface) of the semiconductor substrate (SUB). (See Figure 1) Figure 2 ).

[0056] The planar and cross-sectional structures of semiconductor device PSDs will be described in more detail. For example... Figure 2 and 3As shown, the semiconductor substrate SUB includes an n+ type substrate NPSB and an n-type epitaxial layer NEL. The n-type epitaxial layer NEL is called an n-type drift layer NDL. A plurality of pillar-shaped conductors CCB are formed from the first main surface of the semiconductor substrate SUB to a predetermined depth in the n-type epitaxial layer NEL.

[0057] Each of the plurality of columnar conductors CCBs is formed in a deep trench DTC. Each of the plurality of columnar conductors CCBs includes a tungsten plug PUG and a field plate FP. An insulating film FIF is inserted between the field plate FP and the semiconductor substrate SUB.

[0058] For each of the plurality of columnar conductors CCB, a p-type impurity layer PIL (first impurity region) is formed at a predetermined depth (second depth) from the first main surface of the semiconductor substrate SUB, such that it surrounds the columnar conductor CCB in a plan view. The p-type impurity layer PIL is formed from the sidewall surface of the deep trench DTC toward the n-type epitaxial layer NEL, etc. The p-type impurity layer PIL is electrically connected to the source electrode pad SEP via a plug PUG.

[0059] A p-type base diffusion layer BDL (second impurity region) is formed at a predetermined depth (third depth) from the first main surface of the semiconductor substrate SUB. An n+ type source diffusion layer SDL (third impurity region) is formed from the surface of the p-type base diffusion layer BDL to a predetermined depth (fourth depth) shallower than the bottom of the p-type base diffusion layer BDL.

[0060] The gate trench GTC, extending from the first main surface of the semiconductor substrate SUB to the n-type epitaxial layer NEL, is formed to penetrate the n+ type source diffusion layer SDL and the p-type base diffusion layer BDL. A gate electrode TGEL is formed within the gate trench GTC, and a gate dielectric film GIF is inserted between the gate trench GTC and the gate electrode TGEL. The gate electrode TGEL, the n+ type source diffusion layer SDL, and the n-type drift layer NDL constitute a MOS (Metal-Oxide-Semiconductor) field-effect transistor.

[0061] An interlayer insulating film (ILF) is formed to cover the first main surface of the semiconductor substrate (SUB). A source electrode pad (SEP) is formed to contact the ILF. Each of a plurality of columnar conductors (CCBs) is electrically connected to the source electrode pad (SEP) via a plug (PUG). An n+ type source diffusion layer (SDL) and a p-type impurity layer (PIL) are formed to contact the plug (PUG). In a plan view, the shape (pattern) of the columnar conductors (CCBs) including the p-type impurity layer (PIL) is, for example, set to a square.

[0062] In the aforementioned semiconductor device PSD, a p-type impurity layer PIL is formed at a predetermined depth from the first main surface of the semiconductor substrate SUB. Between the bottom of the plug PUG (fifth depth) and the bottom of the p-type impurity layer PIL (second depth), the field plate FP and the p-type impurity layer PIL are positioned with an insulating film FIF inserted therebetween. This structure is called a semi-superjunction structure.

[0063] A field plate FP is formed from the bottom of the plug PUG (fifth depth), which is shallower than the bottom of the p-type impurity layer PIL (second depth), to the bottom of the deep trench DTC (first depth). Between the bottom of the p-type impurity layer PIL (second depth) and the bottom of the field plate FP (first depth), the field plate FP and the n-type drift layer NDL of the semiconductor substrate SUB are positioned with an insulating film FIF inserted therebetween. This structure is called a field plate structure.

[0064] The field plate FP is electrically connected to the source electrode pad SEP via a plug PUG. The n+ type source diffusion layer SDL and the p-type impurity layer PIL are electrically connected to the source electrode pad SEP via a plug PUG.

[0065] The gate electrode TGEL is wired through the gate circuit GIC (see [link]). Figure 4 Electrically connected to the gate electrode pad GEP (see...) Figure 1 ).like Figure 4 and Figure 5 As shown, the gate trench GTC, in which the gate electrode TGEL is formed, includes a portion extending in one direction and a portion extending in another direction intersecting the one direction. In a predetermined region on the first main surface of the semiconductor substrate SUB, the gate electrode TGEL is electrically connected to the gate wiring GIC via the gate contact GCN. The gate wiring GIC is connected to the gate electrode pad GEP (see...). Figure 1 ).

[0066] Next, an exemplary manufacturing method for the above-described semiconductor device will be described. First, as Figure 6 As shown, an n-type epitaxial layer NEL is formed on the surface of an n+ type substrate NPSB by epitaxial growth. The n+ type substrate NPSB and the n-type epitaxial layer NEL form a semiconductor substrate SUB.

[0067] Next, a predetermined photolithography and etching process is performed on the semiconductor substrate SUB to form a gate trench (not shown). Next, a hot acid treatment is performed to form a thermal oxide film (not shown) to serve as the gate dielectric film. Next, for example, a polycrystalline silicon film (not shown) is formed to fill the gate trench.

[0068] Next, the etch-back process is performed. The result is as follows: Figure 7As shown, portions of the polysilicon film and the thermally oxidized film located on the upper surface of the semiconductor substrate SUB are removed, and a gate electrode TGEL is formed in the gate trench GTC, wherein a gate dielectric film GIF is inserted between the gate trench GTC and the gate electrode TGEL. Note that a chemical mechanical polishing process can be performed instead of an etch-back process.

[0069] Next, a protective film IPF (see [link to IPF]) is formed to create the deep trenches. Figure 8 The semiconductor substrate SUB is covered. As a protective film, for example, a stacked film of silicon nitride and silicon oxide is formed. At this time, the silicon nitride film is the lower layer. Next, photolithography is performed to form a photoresist pattern (not shown) corresponding to the pattern of the deep trenches.

[0070] Next, using the photoresist pattern as an etching mask, the semiconductor substrate SUB (n-type epitaxial layer NEL) is etched. Then, the photoresist pattern is removed. The result is as follows: Figure 8 As shown, deep trench DTC is formed.

[0071] Next, p-type impurities were implanted into the sidewall surface of the deep trench DTC by tilted ion implantation using a protective IPF film as an implantation mask. The results are as follows: Figure 9 As shown, a p-type impurity layer PIL is formed on the sidewall surface of a deep trench DTC. The p-type impurity layer PIL is formed at a predetermined depth (second depth) starting from the first main surface of the semiconductor substrate SUB (n-type epitaxial layer NEL).

[0072] Next, a hot acid treatment is performed to form a thermal oxide film (not shown) on the sidewall surface of the deep trench DTC. Then, an insulating film is formed, for example, by a CVD (chemical vapor deposition) method to cover the thermal oxide film. Therefore, as... Figure 10 As shown, the insulating film TIF is formed as the first main surface of the semiconductor substrate SUB, which includes the sidewall surface of the deep trench DTC.

[0073] Next, as Figure 11 As shown, a polysilicon film PSF is formed to cover the first main surface of the semiconductor substrate SUB by filling a deep trench (DTC). Next, a chemical mechanical polishing process is performed to remove a portion of the polysilicon film PSF, a portion of the insulating film TIF, and the protective film IPF located on the upper surface of the semiconductor substrate SUB.

[0074] At this point, the silicon nitride film of the protective IPF is used as a stop layer in the chemical mechanical polishing process. Next, the silicon nitride film is removed by a wet etching process. Therefore, as... Figure 12As shown, the insulating film TIF and the polysilicon film PSF remain in the deep trench DTC, and the surface of the semiconductor substrate SUB (n-type epitaxial layer NEL) is exposed. Next, a protective film (not shown) is formed on the exposed surface of the semiconductor substrate SUB.

[0075] Next, p-type impurities are implanted from the first main surface of the semiconductor substrate SUB. Next, n-type impurities are implanted. The result is as follows: Figure 13 As shown, a p-type base diffusion layer BDL is formed from the first main surface of the semiconductor substrate SUB at a predetermined depth (third depth). The p-type impurity concentration of the p-type base diffusion layer BDL is, for example, about 10. 17 atoms / cm 3 An n+ type source diffusion layer SDL is formed from the surface of the p-type base diffusion layer BDL to a predetermined depth.

[0076] The n-type impurity density of the n+ type source diffusion layer SDL is, for example, about 10. 20 atoms / cm 3 At this point, by injecting impurities with a higher n-type impurity concentration, a portion of the p-type impurity layer PIL located on the first main surface of the semiconductor substrate SUB is replaced with a portion of the n+ type source diffusion layer SDL.

[0077] Next, an interlayer insulating film (ILF), such as a silicon oxide film, is formed to cover the first main surface of the semiconductor substrate (SUB). Then, predetermined photolithography and etching processes are performed to remove a portion of the polysilicon film (PSF) and a portion of the insulating film (FIF) located above a predetermined depth from the first main surface side of the deep trench DTC.

[0078] As a result, Figure 14 As shown, an opening SOP is formed to expose a portion of the deep trench DTC. The opening SOP is formed from one side of the first main surface to a position (fifth depth) that is shallower than the bottom of the p-type impurity layer PIL (second depth) and deeper than the bottom of the p-type base diffusion layer BDL (third depth).

[0079] Next, for example, a tungsten film (not shown) is formed by CVD to cover the interlayer insulating film (ILF) in a manner that fills the opening SOP. The tungsten film is then subjected to, for example, chemical mechanical polishing to remove a portion of the tungsten film located on the upper surface of the interlayer insulating film (ILF), while leaving a portion of the tungsten film located within the opening SOP.

[0080] As a result, Figure 15 As shown, a tungsten plug PUG is formed in a deep trench DTC. A portion of the polysilicon film remaining beneath the plug PUG serves as the field plate FP. The plug PUG contacts each of the n+ type source diffusion layer SDL, the p-type impurity layer PIL, and the field plate FP.

[0081] Next, an aluminum film (not shown) is formed, for example, by sputtering, to cover the interlayer insulating film (ILF). Then, predetermined photolithography and etching processes are performed. The result is as follows: Figure 15 As shown, the source electrode pad (SEP) is formed. Simultaneously with the source electrode pad (SEP), the gate wiring (GIC) and the gate electrode pad (GEP) are formed. Then, the drain electrode pad (DEP) is formed to cover the second main surface of the semiconductor substrate (SUB). This completes the main part of the semiconductor device PSD.

[0082] In the aforementioned semiconductor device PSD, a field plate structure is first provided. As a result, high breakdown voltage and low on-resistance can be achieved in the semiconductor device PSD. In addition to the field plate structure, the aforementioned semiconductor device PSD also has a semi-superjunction structure. As a result, the breakdown voltage can be further improved. The evaluation and results of simulations performed by the inventors will be described.

[0083] First, the initial conditions (initial state) of the simulation will be described. In the simulation, a region containing a MOS field-effect transistor is set between the insulating film in one deep trench and the insulating film in another deep trench in adjacent deep trenches.

[0084] As an example, Figure 16 The initialization of the aforementioned semiconductor device is shown. (As...) Figure 16 As shown, in the semiconductor device according to this embodiment, a semi-superjunction structure including a p-type impurity layer and a field plate structure are provided. Figure 16 In the diagram, the relationship between the height of n-type impurity concentration and the height of p-type impurity concentration is schematically shown using the direction and density of the shading lines.

[0085] Next, Figure 17 The initial state of the semiconductor device according to the comparative example is shown. Figure 17 As shown, in the semiconductor device according to this comparative example, no impurity layer corresponding to the p-type impurity layer is provided; instead, only a typical field plate structure is provided. Figure 17 In the diagram, the relationship between the height of n-type impurity concentration and the height of p-type impurity concentration is schematically shown using the direction and density of the shading lines.

[0086] Next, the electric field intensity distribution when a predetermined voltage used to evaluate the withstand voltage is applied to the n+ type source diffusion layer will be described. Figure 18 The diagram illustrates the electric field intensity distribution in a semiconductor device according to an embodiment, and... Figure 19 The diagram shows the electric field intensity distribution in a semiconductor device according to a comparative example. Figure 18 and 19In each of the figures, only the electric field strength contour is shown to avoid complicating the illustrations. Based on the calculated electric field strength distribution, the electric field strength in the depth direction is extracted at a position directly below the gate electrode (gate dielectric film) in the Y=0 coordinate system (see down arrow). Figure 20 The graph shows the electric field strength.

[0087] exist Figure 20 In Example 1, a graph showing the electric field strength of the semiconductor device according to this embodiment is displayed using a solid line. A graph showing the electric field strength of the semiconductor device according to a comparative example is displayed using a dashed line. Figure 20 As shown, in the semiconductor device according to this embodiment, due to the formation of a p-type impurity layer, the electric field strength is higher than that of the semiconductor device according to the comparative example when the value of X is approximately 2 μm to 6 μm. The breakdown voltage is calculated as the integral value of the electric field strength in the depth direction. The inventors concluded from the electric field strength graph that the breakdown voltage of the semiconductor device can be improved compared to the semiconductor device according to the comparative example.

[0088] Next, the inventors used simulations to evaluate the relationship between the depth of the p-type impurity layer and the withstand voltage. This graph is shown in... Figure 21 As shown in the diagram. The horizontal axis represents the distance from... Figure 16 The length d of the insulating film in the deep trench shown (i.e., from the top of the field plate to the bottom of the p-type impurity layer) is shown. The vertical axis represents the breakdown voltage. Figure 21 As shown, it was found that the withstand voltage was improved by setting the length d from the top of the field plate to the bottom of the p-type impurity layer to half the length (depth) of the field plate. Half the length of the field plate is not intended to be exactly half, but rather includes a range of error of ±10% due to manufacturing variations.

[0089] It is understandable that when the length d from the top of the field plate to the bottom of the p-type impurity layer is less than the length of the field plate, the breakdown voltage decreases rapidly. This is believed to be because when the length d is shortened, the structure of the semiconductor device is similar to that of the semiconductor device without the p-type impurity layer according to the comparative example, thus reducing the effect of improving the breakdown voltage.

[0090] On the other hand, it can be understood that the breakdown voltage gradually decreases with increasing length d from the top of the field plate to the bottom of the p-type impurity layer. For example... Figure 20 As shown, in the semiconductor device according to the comparative example, the electric field strength (electric field strength A) near the lower end of the field plate is higher than the electric field strength near the center in the depth direction of the field plate. Therefore, when the length d is set to be relatively long, the electric field strength near the lower end of the field plate FP is not much different from the electric field strength A of the semiconductor device according to the comparative example, and the effect of improving the breakdown voltage is small.

[0091] That is, in order to improve the breakdown voltage, it has been found that it is desirable to form a p-type impurity layer to a predetermined depth so that the electric field strength under relatively low electric field strength can be increased in the electric field strength distribution of the semiconductor device according to the comparative example. Here, it has been found that setting the length d to half the length (depth) of the field plate is effective for improving the breakdown voltage. As mentioned above, the length d includes an error range of ±10% as a manufacturing tolerance.

[0092] Next, the inventors used simulations to evaluate the relationship between the impurity concentration of the p-type impurity layer and the breakdown voltage. This curve is shown in... Figure 22 The diagram shows the peak concentration of the p-type impurity layer on the horizontal axis and the breakdown voltage on the vertical axis. The length d (depth) of the p-type impurity layer is set to 2 μm. Figure 22 As shown, it was found that when the impurity concentration (peak concentration) of the p-type impurity layer was approximately 2.6 × 10⁻⁶, 17 atoms / cm 3 At that time, the withstand pressure becomes the highest.

[0093] Next, the charge balance between the impurity mass of the p-type impurity layer PIL and the impurity mass of the n-type drift layer NDL will be described. Here, as Figure 23 As shown, the impurity mass in the p-type impurity layer PIL and the n-type drift layer NDL at one depth (section line XXIV-XXIV) and another depth (section line XXV-XXV) along the direction in which adjacent columnar conductors CCB are arranged will be described.

[0094] first, Figure 24 The distribution of impurity concentrations along section line XXIV-XXIV is shown. The horizontal axis represents... Figure 23 The center of the gate electrode shown is located at Y=0. The vertical axis represents the impurity concentration. Figure 24 The diagram shows the distribution of impurity concentrations at corresponding depths of a p-type impurity layer PILA on one columnar conductor CCB side, a p-type impurity layer PILB on the other columnar conductor CCB side, and an n-type drift layer NDL located between the p-type impurity layers PILA and PILB.

[0095] Here, the impurity mass based on the impurity concentration at a depth location of the p-type impurity layer PILA is defined as (Qp1) / 2. The impurity mass based on the impurity concentration at a depth location of the p-type impurity layer PILB is also defined as (Qp1) / 2. Let Qn1 be the impurity mass based on the impurity concentration at a depth location of the n-type drift layer NDL. Each impurity mass corresponds to the area of ​​the distribution of the corresponding impurity concentration.

[0096] Then, the total p-type impurity mass is (Qp1) / 2 + (Qp1) / 2 = Qp1. In the semiconductor device PSD, the impurity concentration of the p-type impurity layer PIL and the impurity concentration of the n-type drift layer NDL are set such that the total p-type impurity mass Qp1 is equal to the n-type impurity mass Qn1.

[0097] Next, Figure 25 The distribution of impurity concentration along the cross-sectional line XXV-XXV is shown. The horizontal axis represents the position when Y=0. Figure 23 The center of the gate electrode is shown. The vertical axis represents the impurity concentration. Figure 25 The distribution of impurity concentrations at other depths is shown for a p-type impurity layer PILA on one side of a columnar conductor CCB, a p-type impurity layer PILB on the other side of a columnar conductor CCB, and an n-type drift layer NDL located between the p-type impurity layers PILA and PILB.

[0098] Here, the amount of impurities based on the p-type impurity layer PILA at other depths is assumed to be (Qp2) / 2. Let the amount of impurities based on the p-type impurity layer PILB at other depths be (Qp2) / 2. Let Qn2 be the amount of impurities based on the n-type drift layer NDL at other depths. Each amount of impurities corresponds to the area of ​​the distribution of the corresponding impurity concentration.

[0099] Then, the total p-type impurity mass is (Qp2) / 2 + (Qp2) / 2 = Qp2. In the semiconductor device PSD, the impurity concentrations of the p-type impurity layer PIL and the n-type drift layer NDL are set such that the total p-type impurity mass Qp2 equals the n-type impurity mass Qn2. Note that Qp2 = Qn2 is not intended to strictly represent that Qp2 and Qn2 are equal, but rather to include a ±10% error range in terms of manufacturing tolerances.

[0100] like Figure 24 and 25 As shown, the impurity concentrations of the p-type impurity layer PIL and the n-type drift layer NDL at one depth location and at another depth location are different from each other and are not the same impurity concentration.

[0101] However, at one depth location, the total p-type impurity mass Qp1 equals the n-type impurity mass Qn1. At other depth locations, the total p-type impurity mass Qp2 equals the n-type impurity mass Qn2. Therefore, in a semiconductor device PSD, the highest breakdown voltage can be ensured through charge balance.

[0102] In the aforementioned semiconductor device, a planar pattern of gate trenches GTCs, in which gate electrodes TGELs are formed, is provided such that the spacing of the gate trenches GTCs is as follows: Figure 3 or Figure 4 Taking the offset mesh pattern shown as an example, the planar pattern of the gate trench (GTC) can be a mesh pattern with uniform spacing, such as... Figure 26 As shown. The planar shape of the cylindrical conductor CCB is illustrated using a square as an example. The planar shape of the cylindrical conductor CCB can be, for example, as shown... Figure 27 The rectangle shown. (As shown) Figure 28 As shown, the shape can be octagonal or circular, such as... Figure 29 As shown.

[0103] (Example 2)

[0104] Examples of semiconductor devices according to the second embodiment will be described. For example... Figure 30 As shown, for each of the plurality of columnar conductors CCB, a p-type impurity layer PIL is formed from the first main surface of the semiconductor substrate SUB at a predetermined depth (second depth). The p-type impurity layer PIL includes p-type impurity layer PILH, p-type impurity layer PILM, and p-type impurity layer PILL.

[0105] The impurity concentration of the p-type impurity layer (PILL) is, for example, 10. 17 atoms / cm 3 The impurity concentration of the p-type impurity layer PILM is higher than that of the p-type impurity layer PILL, for example, by about 10. 18 atoms / cm 3 The impurity concentration of the p-type impurity layer PILH is higher than that of the p-type impurity layer PILM, for example, by about 10. 19 atoms / cm 3 Due to other constructions and Figure 2 The semiconductor devices shown are constructed identically; therefore, the same components are indicated by the same reference numerals, and their descriptions will not be repeated unless necessary.

[0106] Next, an exemplary manufacturing method for the aforementioned semiconductor device will be described. First, in performing the process with... Figures 6 to 8 Following a process substantially similar to the one shown, p-type impurities are injected into the sidewall surface of the deep trench DTC at a first injection angle and a first dose, such as... Figure 31 As shown, the resulting layer will become part of the p-type impurity layer PILL.

[0107] Next, as Figure 32 As shown, p-type impurities are injected into the sidewall surface of a deep trench DTC at a second injection angle and a second dose. The second injection angle is greater than the first injection angle. The second dose is higher than the first dose. As a result, a portion of the p-type impurity layer PILM is formed, while a portion of the p-type impurity layer PILL remains.

[0108] Next, as Figure 33As shown, p-type impurities are injected into the sidewall surface of a deep trench DTC at a third injection angle and a third dose. The third injection angle is greater than the second injection angle. The third dose is higher than the second dose. Therefore, a p-type impurity layer PILH is formed, while a portion of a p-type impurity layer PILL and a portion of a p-type impurity layer PILM are left. Subsequently, by... Figures 10 to 15 The same steps as shown are completed. Figure 30 The main part of the semiconductor device shown.

[0109] In the aforementioned semiconductor device PSD, the p-type impurity layer PIL includes p-type impurity layer PILH, p-type impurity layer PILM, and p-type impurity layer PILL. The impurity concentration of p-type impurity layer PILM is higher than that of p-type impurity layer PILL. The impurity concentration of p-type impurity layer PILH is higher than that of p-type impurity layer PILM.

[0110] The inventors believe that, based on the results of an evaluation performed through simulation on a semiconductor device PSD according to the first embodiment, three peaks appeared as indicators of the semiconductor device PSD including a p-type impurity layer PIL having the three different impurity concentrations described above. Figure 20 The electric field strength described in [the text]. That is, as [the text continues with details about electric field strength]. Figure 34 As shown, in addition to the peak electric field intensity corresponding to the p-type impurity layer PILL, there are also peak electric field intensity corresponding to the p-type impurity layer PILM and peak electric field intensity corresponding to the p-type impurity layer PILH (see solid lines in the second embodiment).

[0111] The inventors believe that by summing the peak values ​​of such electric field strength, the integral value of the electric field strength in the depth direction becomes greater than the integral value of the semiconductor device described in the first embodiment (see the first embodiment), resulting in a further improvement in withstand voltage.

[0112] Furthermore, it has been found that the aforementioned semiconductor devices improve resistance to avalanche breakdown. This will be explained. Avalanche breakdown is a mode in which a spike voltage exceeds the drain rated withstand voltage of a MOS transistor and enters the breakdown region, and breaks down due to, for example, the flyback voltage generated during off-state operation in an inductive load.

[0113] When breakdown occurs at a location with a strong electric field around the gate electrode TGEL, charge carriers are generated, holes are led out to the source electrode pad SEP side, and electrons are led out to the drain electrode pad DEP side. At this time, as holes flow from the n-type drift layer NDL to the p-type base diffusion layer BDL, a potential difference is generated by the resistor, and electrons are injected from the n+ type source diffusion layer SDL to the p-type base diffusion layer BDL, activating the parasitic bipolar transistor. That is, the parasitic NPN bipolar transistor composed of the n+ type source diffusion layer SDL, the p-type base diffusion layer BDL, and the n-type drift layer NDL operates, and current flows from the drain electrode pad DEP to the source electrode pad SEP.

[0114] In the aforementioned semiconductor device PSD, a p-type impurity layer PIL is formed along the side surface of the deep trench DTC. The p-type impurity layer PIL contacts the plug PUG on the sidewall surface of the deep trench DTC and contacts the n-type drift layer NDL and the p-type base diffusion layer BDL in the depth direction. This arrangement ensures sufficient contact area between the plug PUG, which is electrically connected to the source electrode pad SEP, and the p-type impurity layer PIL. This adequately ensures sufficient contact area between the n-type drift layer NDL, the p-type base diffusion layer BDL, and the p-type impurity layer PIL. Furthermore, within the p-type impurity layer PIL, a p-type impurity layer PILH with a relatively high impurity concentration contacts the p-type base diffusion layer BDL and the plug PUG.

[0115] Therefore, when breakdown occurs, the number of holes flowing from the n-type drift layer (NDL) into the p-type base diffusion layer (BDL) and from the p-type base diffusion layer (BDL) into the PUG plug increases. Additionally, the number of holes flowing from the n-type drift layer (NDL) into the plug PUG through the p-type impurity layer (PIL) increases. As a result, the number of holes flowing near the gate electrode (TGEL) decreases. Consequently, the number of electrons injected from the n+ source diffusion layer (SDL) into the p-type base diffusion layer (BDL) decreases, and the operation of parasitic NPN bipolar transistors can be suppressed. Therefore, avalanche resistance can be improved.

[0116] (Example 3)

[0117] Examples of semiconductor devices according to the third embodiment will be described. For example... Figure 35 As shown, the semiconductor substrate SUB includes an n+ type substrate NPSB, an n-type epitaxial layer NEL, and an n-type epitaxial layer NELL. The impurity concentration of the n-type epitaxial layer NEL is, for example, about 10. 16 atoms / cm 3 The impurity concentration of the n-type epitaxial layer NELL is, for example, about 10. 15 atoms / cm 3 .

[0118] The n-type epitaxial layer NEL is transformed into an n-type drift layer NDL. The n-type epitaxial layer NELL is transformed into an n-type drift layer NDLL. Multiple pillar-shaped conductors CCB are formed from the first main surface of the semiconductor substrate SUB through the n-type epitaxial layer NELL to a predetermined depth in the n-type epitaxial layer NEL. Due to other structural features... Figure 2 The semiconductor devices shown are constructed identically; therefore, the same components are indicated by the same reference numerals, and their descriptions will not be repeated unless necessary.

[0119] Next, an exemplary manufacturing method for the above-described semiconductor device will be described. First, as Figure 36 As shown, an n-type epitaxial layer NEL is formed on the surface of an n+ type substrate NPSB through epitaxial growth. An n-type epitaxial layer NELL is then formed on the surface of the n-type epitaxial layer NEL through epitaxial growth. The impurity concentration of the n-type epitaxial layer NELL is lower than that of the n-type epitaxial layer NEL. The semiconductor substrate SUB is formed from the n+ type substrate NPSB, the n-type epitaxial layer NEL, and the n-type epitaxial layer NELL. Subsequently, through... Figures 7 to 15 The same steps as shown are completed. Figure 35 The main part of the semiconductor device shown.

[0120] Furthermore, as another exemplary manufacturing method for the aforementioned semiconductor device, it can be manufactured as follows. During the execution of... Figures 6 to 8 Following the same steps as shown, p-type impurities are injected from the sidewalls of the deep trench DTC, such as... Figure 37 As shown. Subsequently, heat treatment is performed. As a result, the n-type impurities in the n-type epitaxial layer NEL located at a predetermined depth from the surface of the n-type epitaxial layer NEL are neutralized by p-type impurities, and an n-type epitaxial layer NELL with a lower impurity concentration than the n-type epitaxial layer NEL is formed. Subsequently, by... Figures 9 to 15 The same steps as shown are completed. Figure 35 The main part of the semiconductor device shown.

[0121] In the aforementioned semiconductor device PSD, an n-type drift layer NDLL with an impurity concentration lower than that of the n-type drift layer NDL is formed. Multiple pillared conductors CCB, each including a field plate FP, are formed in the deep trench DTC. The deep trench DTC penetrates the n-type epitaxial layer NELL and extends from the first main surface of the semiconductor substrate SUB to the n-type epitaxial layer NEL. A p-type impurity layer PIL is formed along the sidewall surface of the deep trench DTC, contacting the p-type base diffusion layer BDL and the n-type drift layer NDLL (n-type epitaxial layer NELL).

[0122] Based on the evaluation results performed on the semiconductor device PSD according to the first embodiment, the inventors believe that in the above-described semiconductor device PSD including an n-type drift layer NDLL in contact with the p-type impurity layer PIL, the electric field strength increases in the depth direction of the n-type drift layer NDLL. That is, as Figure 38 As shown, the base point of the electric field intensity in the region where the n-type drift layer NDLL is located is considered to be higher than the base point of the electric field intensity of the semiconductor device PSD described in the first embodiment (refer to the solid line in the third embodiment).

[0123] The inventors believe that, compared with the integral value of the semiconductor device PSD described in the first embodiment, the increase of the base point of the electric field strength increases the integral value of the electric field strength in the depth direction, resulting in a further increase in the breakdown voltage.

[0124] Note that the semiconductor devices described in the corresponding embodiments can be combined in various ways as needed. Dependencies in the claims according to the embodiments are also contemplated.

[0125] Although the invention made by the inventors has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its spirit.

Claims

1. A semiconductor device comprising: a semiconductor substrate of a first conductivity type, having a first main surface and a second main surface opposite to the first main surface; a first electrode formed on the first main surface of the semiconductor substrate; a second electrode formed on the second main surface of the semiconductor substrate; a plurality of columnar conductors formed in the semiconductor substrate and electrically connected to the first electrode, each of the plurality of columnar conductors extending between a first depth in the semiconductor substrate and the first main surface, the first depth in the semiconductor substrate being measured from the first main surface toward the second main surface; a first impurity region of a second conductivity type formed in the semiconductor substrate and electrically connected to the first electrode, the first impurity region extending between a second depth in the semiconductor substrate and the first main surface, the second depth in the semiconductor substrate being measured from the first main surface toward the second main surface, the second depth being shallower than the first depth; a second impurity region of the second conductivity type formed in the semiconductor substrate and electrically connected to the first electrode, the second impurity region extending between a third depth in the semiconductor substrate and the first main surface, the third depth in the semiconductor substrate being measured from the first main surface toward the second main surface, the third depth being shallower than the second depth; a third impurity region of the first conductivity type formed in the semiconductor substrate and electrically connected to the first electrode, the third impurity region extending between a fourth depth in the semiconductor substrate and the first main surface, the fourth depth in the semiconductor substrate being measured from the first main surface toward the second main surface, the fourth depth being shallower than the third depth; and a gate electrode formed in a gate trench in the semiconductor substrate via a gate dielectric film so as to penetrate the third impurity region and the second impurity region; wherein the first impurity region contacts each of the semiconductor substrate of the first conductivity type and the second impurity region of the second conductivity type, wherein each of the plurality of columnar conductors includes a field plate extending from a fifth depth in the semiconductor substrate to the first depth, the fifth depth in the semiconductor substrate being measured from the first main surface toward the second main surface, the fifth depth being shallower than the first depth and the second depth and deeper than the third depth and the fourth depth, the field plate and the semiconductor substrate of the first conductivity type being disposed opposite to each other via an insulating film, wherein i) a first portion of the field plate extending between the fifth depth and the second depth in the semiconductor substrate and ii) the first impurity region are opposite to each other via the insulating film, wherein the first portion of the field plate is electrically connected to the first electrode, and wherein the second portion of the field plate is electrically connected to the second electrode. wherein in a region between the second depth and the first depth, i) a second portion of the field plate extending between the second depth and the first depth in the semiconductor substrate and ii) the semiconductor substrate of the first conductivity type via the insulating film are opposite each other, and wherein a length of a portion of the first impurity region extending from the fifth depth to the second depth in the semiconductor substrate is set to half a length of the field plate extending from the fifth depth to the first depth in the semiconductor substrate.

2. The semiconductor device of claim 1, wherein each of the plurality of columnar conductors is formed in a deep trench that reaches a portion of the semiconductor substrate of the first conductivity type from the first major surface in a manner that penetrates the third impurity region and the second impurity region.

3. The semiconductor device of claim 2, wherein each of the plurality of columnar conductors includes a plug in contact with the field plate and the first impurity region, wherein each of the plurality of columnar conductors is formed in the deep trench such that the plug extends between the first major surface and the fifth depth of the semiconductor substrate.

4. The semiconductor device of claim 1, wherein the first impurity region includes a first portion having a first impurity concentration and a second portion having a second impurity concentration higher than the first impurity concentration, and wherein the second portion of the first impurity region is located proximal to the first major surface compared to the first portion of the first impurity region.

5. The semiconductor device of claim 1, wherein the semiconductor substrate of the first conductivity type includes a first layer having a third impurity concentration and a second layer having a fourth impurity concentration lower than the third impurity concentration, wherein the second layer is closer to the first major surface than the first layer, and wherein each of the plurality of columnar conductors is formed to reach the first layer and the gate electrode is formed to reach the second layer.

6. The semiconductor device of claim 1, wherein a shape of each of the plurality of columnar conductors in a plan view is any one of a square, a circle, or an octagon.

7. A method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate of a first conductivity type having a first major surface and a second major surface; forming a gate trench of a predetermined depth on the first major surface of the semiconductor substrate; forming a gate electrode in the gate trench, wherein a gate insulating film is interposed between the gate trench and the gate electrode; forming a deep trench on the first major surface of the semiconductor substrate, the deep trench being formed at a distance from the gate electrode, the deep trench extending between a first depth in the semiconductor substrate and the first major surface, the first depth being measured from the first major surface toward the second major surface; forming a first impurity region of a second conductivity type in the first main surface of the semiconductor substrate by implanting an impurity of the second conductivity type into a sidewall surface of the deep trench, the first impurity extending between a second depth in the semiconductor substrate and the first main surface, the second depth in the semiconductor substrate being measured from the first main surface toward the second main surface, the second depth being shallower than the first depth; forming a conductive film in the deep trench to fill the deep trench via an insulating film covering the sidewall surface of the deep trench; forming a second impurity region of the second conductivity type in the first main surface of the semiconductor substrate to contact the first impurity region, the second impurity region extending between a third depth in the semiconductor substrate and the first main surface, the third depth in the semiconductor substrate being measured from the first main surface toward the second main surface, the third depth being a point in the semiconductor substrate shallower than a bottom of the gate trench; forming a third impurity region of the first conductivity type in the first main surface of the second impurity region, the third impurity region extending between a fourth depth in the semiconductor substrate and the first main surface, the fourth depth in the semiconductor substrate being measured from the first main surface toward the second main surface, the fourth depth being shallower than the third depth; removing a portion of the insulating film and a portion of the conductive film to expose a portion of the third impurity region and a portion of the first impurity region, whereby a remaining portion of the conductive film is formed as a field plate, each of the portion of the insulating film and the portion of the conductive film being in a region between the first main surface of the semiconductor substrate and a fifth depth in the semiconductor substrate, the fifth depth being measured from the first main surface toward the second main surface, the fifth depth being shallower than the first depth and the second depth and deeper than the third depth and the fourth depth; forming a plug extending to the fifth depth in the deep trench to contact the field plate, the third impurity region, and the first impurity region; forming a first electrode on the first main surface of the semiconductor substrate electrically connected to the plug; and forming a second electrode electrically connected to the second main surface of the semiconductor substrate, wherein a length of a portion of the first impurity region extending from the fifth depth in the semiconductor substrate to the second depth is set to half a length of the field plate extending from the fifth depth in the semiconductor substrate to the first depth.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming the first impurity region includes: a step of implanting a first impurity of the second conductivity type having a first impurity concentration into the sidewall surface of the deep trench at a first angle of incidence; and implanting a second dopant of a second conductivity type having a second dopant concentration higher than the first dopant concentration into the sidewall surface of the deep trench at a second angle of incidence smaller than the first angle of incidence.

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