Power amplifier packages and systems incorporating a design flexible package platform

Abstract

Embodiments of Doherty power amplifiers (PAs) and other PA packages, and systems including PA packages, are provided. In embodiments, a PA package includes a package body having a longitudinal axis, a first set of input-side leads extending from a first side of the package body and having an intra-set lead pitch, and a first set of output-side leads extending from a second side of the package body and also having the intra-set lead pitch. A first carrier input lead extends from the first package body side and is separated from the first set of input-side leads by an input-side isolation gap having a width that exceeds the intra-set lead pitch. Similarly, a first carrier output lead extends from the second package body side, is laterally aligned with the first carrier input lead, and is separated from the first set of output-side leads by an output-side isolation gap.

Description

Technical Field

[0001] Embodiments of the present invention relate generally to microelectronics, and more specifically to power amplifier packages incorporated into flexible packaging platforms, and to power amplifier systems comprising such packages.

[0002] abbreviations

[0003] Abbreviations that appear relatively infrequently in this document are defined upon their first use, while abbreviations that appear more frequently in this document are defined as follows:

[0004] FET—Field-Effect Transistor;

[0005] IC—Integrated Circuit;

[0006] IPD – Integrated Passive Device;

[0007] MN – Matching Network;

[0008] PA—Power Amplifier;

[0009] PCB—Printed Circuit Board; and

[0010] RF – Radio Frequency. Background Technology

[0011] Wireless communication systems (e.g., cellular base stations) are typically incorporated into microelectronic packages containing a Doherty PA (referred to herein as a "Doherty PA package") to enhance RF signal strength. Traditionally, a Doherty PA package includes at least one carrier transistor and at least one peak transistor arranged in a symmetrical, bidirectional, dual-path configuration. The transistors are typically provided on separate semiconductor dies attached side-by-side to a die-bonding region of a conductive flange or substrate. A carrier (or primary) signal amplification path extends from a carrier input lead through the carrier transistor and to a carrier output lead; while a parallel peak (or secondary) signal amplification path extends from a peak input lead through the peak transistor and to a peak output lead. In the case of a symmetrical Doherty PA package, the transistor die and the die-bonding region to which the transistor die is attached are given substantially equal dimensions. Similarly, the input and output leads of the transistor die are typically given equal widths, which typically correspond to the width of the die-bonding region along the longitudinal axis of the PA package.

[0012] While symmetrical bidirectional Doherty architectures remain prevalent, PA packages incorporating more complex Doherty architectures are gaining popularity. For example, tri-directional and quad-directional Doherty PA packages with symmetrical and asymmetrical layouts are now widely available for commercial use. Specifically, for Doherty PA packages with asymmetrical layouts, the share of available die-bonding region allocated to one or more peak transistor dies contained within the package is larger than the share allocated to one or more charge carrier transistor dies. This can increase the size of one or more peak transistors within the Doherty PA package relative to one or more charge carrier transistors to enhance performance characteristics; for example, increasing gain, linearity, stability, and / or power-added efficiency levels. In some cases, the corresponding widths of the input and output leads can also vary with a corresponding asymmetric relationship. Therefore, some asymmetric Doherty PA packages are manufactured to include input and output leads of different widths. Typically, wider leads are aligned with wider die-bonding regions of one or more peak transistor dies attached, while narrower leads are aligned with narrower die-bonding regions of one or more charge carrier transistor dies attached. This asymmetric Doherty PA package is well-suited for fabrication using leadframe-based methods and offers several benefits, such as increased current distribution uniformity and reduced cross-coupling between adjacent charge carriers and the signal conducted through the peak signal amplification path of the PA package. Nevertheless, further improvements to the performance characteristics and design flexibility of the Doherty PA package and PA packages are typically required. Summary of the Invention

[0013] According to a first aspect of the present invention, a power amplifier (PA) package (110) is provided, comprising:

[0014] The encapsulation body (112) has a longitudinal axis (114);

[0015] The first set of input-side leads (132-1, 134-1, 136-1) extends from the first side (115) of the package body (112) and is spaced apart by the intra-group lead spacing along the longitudinal axis (114);

[0016] The first set of output side leads (132-2, 134-2, 136-2) extends from the second side (117) of the package body (112), is separated by the lead spacing within the set, and is laterally aligned with the first set of input side leads (132-1, 134-1, 136-1).

[0017] A first carrier input lead (130-1) extends from the first side (115) of the package body (112) and is spaced from the first group of input-side leads (132-1, 134-1, 136-1) by an input-side isolation gap (137-1), the width of which exceeds the lead spacing within the group along the longitudinal axis (114); and

[0018] A first carrier output lead (130-2) extends from the second side (117) of the package body (112), is laterally aligned with the first carrier input lead (130-1), and is separated from the first set of output-side leads (132-2, 134-2, 136-2) by an output-side isolation gap (137-2), the output-side isolation gap (137-2) having the width of the isolation gap.

[0019] According to one or more embodiments, the first group of input-side leads (132-1, 134-1, 136-1) includes a plurality of peak input leads extending from the first side (115) of the package body (112) and spaced apart by the lead spacing within the group; and

[0020] The first set of output-side leads (132-2, 134-2, 136-2) includes multiple peak output leads that extend from the second side (117) of the package body (112), are spaced apart by the lead spacing within the set, and are laterally aligned with the multiple peak input leads.

[0021] According to one or more embodiments, it further includes:

[0022] A second carrier input lead (128-1) extends from the first side (115) of the package body (112), and the first carrier input lead (130-1) is located between the second carrier input lead (128-1) and the first set of input-side leads (132-1, 134-1, 136-1) along the longitudinal axis (114); and

[0023] A second carrier output lead (128-2) extends from the second side (117) of the package body (112) and is laterally aligned with the second carrier input lead (128-1). The second carrier input lead (128-1) is located between the second carrier output lead (128-2) and the first set of output side leads (132-2, 134-2, 136-2) along the longitudinal axis (114).

[0024] According to one or more embodiments, it further includes:

[0025] The second set of input-side leads (128-1, 130-1) extends from the first side (115) of the package body (112), is spaced apart by the lead spacing within the set, and includes the first carrier input lead (130-1); and

[0026] The second set of output-side leads (128-2, 130-2) extends from the second side (117) of the package body (112), is separated by the lead spacing within the set, is laterally aligned with the second set of input-side leads, and includes the first carrier output lead (130-2).

[0027] According to one or more embodiments, the first set of input-side leads (132-1, 134-1, 136-1) consists of Y carrier input leads;

[0028] The first group of output-side leads (132-2, 134-2, 136-2) consists of Y carrier output leads;

[0029] The second group of input-side leads (128-1, 130-1) consists of X peak input leads;

[0030] The second group of output-side leads (128-2, 130-2) consists of X peak output leads; and

[0031] Where Y is greater than X.

[0032] According to one or more embodiments, each of the first set of input-side leads (132-1, 134-1, 136-1), each of the first set of output-side leads (132-2, 134-2, 136-2), the first carrier input lead (130-1), and the first carrier output lead (130-2) have substantially equal maximum lead widths along the longitudinal axis (114).

[0033] According to one or more embodiments, the first set of input-side leads (132-1, 134-1, 136-1) includes a first peak input lead (134-1) that extends from the first side (115) of the package body (112);

[0034] The first set of output-side leads (132-2, 134-2, 136-2) includes a first peak output lead (134-2), which extends from the second side (117) of the package body (112) and is laterally aligned with the first peak input lead;

[0035] The PA package (110) further includes:

[0036] A peak PA die (156) is contained within the package body (112) and electrically coupled between the first peak input lead (134-1) and the first peak output lead (134-2); and

[0037] A carrier PA die (152) is contained in a package body (112) and electrically coupled between the first carrier input lead (130-1) and the first carrier output lead (130-2).

[0038] According to one or more embodiments, the PA package (110) further includes:

[0039] An input-side isolation lead (132-1) extends from the first side (115) of the package body (112);

[0040] An output-side isolation lead (132-2) extends from the second side (117) of the package body (112) and is laterally aligned with the input-side isolation lead; and

[0041] An isolation structure (266) within the packaging structure (112) is located between the peak PA die (156) and the carrier PA die (152) along the longitudinal axis (114) and is electrically coupled to at least one of the input-side isolation lead (132-1) and the output-side isolation lead (132-2).

[0042] According to one or more embodiments, the isolation gap width (W) G The spacing between the leads in the group is at least 50% larger than the spacing between the leads in the group.

[0043] According to a second aspect of the present invention, a power amplifier (PA) system (192) is provided, comprising:

[0044] PA package (110), comprising:

[0045] The encapsulation body (112) has a longitudinal axis (114);

[0046] The first set of input-side leads (132-1, 134-1, 136-1) extends from the first side (115) of the package body (112) and is spaced apart by the intra-group lead spacing along the longitudinal axis (114);

[0047] The first set of output side leads (132-2, 134-2, 136-2) extends from the second side (117) of the package body (112), is separated by the lead spacing within the set, and is laterally aligned with the first set of input side leads (132-1, 134-1, 136-1).

[0048] A first carrier input lead (130-1) extends from the first side (115) of the package body (112) and is spaced from the first group of input-side leads (132-1, 134-1, 136-1) by an input-side isolation gap (137-1), the width of which exceeds the lead spacing within the group along the longitudinal axis (114); and

[0049] A first carrier output lead (130-2) extends from the second side (117) of the package body (112), is laterally aligned with the first carrier input lead (130-1), and is separated from the first set of output side leads (132-2, 134-2, 136-2) by an output side isolation gap (137-2), the output side isolation gap (137-2) having the width of the isolation gap;

[0050] Substrate (196), comprising:

[0051] The upper surface (194) on which the PA package (110) is mounted; and

[0052] Transmission lines (198, 200, 202, 204) are formed on the upper surface of the substrate and electrically coupled to the first set of input-side leads (132-1, 134-1, 136-1), the first set of output-side leads (132-2, 134-2, 136-2), and the first carrier input lead (130-1).

[0053] According to one or more embodiments, the transmission lines (198, 200, 202, 204) include a first branch transmission line (202) having a plurality of transmission line branches (212), each of the first set of input-side leads (132-1, 134-1, 136-1) contacting a different one of the plurality of transmission line branches (212).

[0054] According to one or more embodiments, the plurality of transmission line branches include:

[0055] The first transmission line branch (212) contacts the first input side lead (132-1) included in the first set of input side leads (132-1, 134-1, 136-1);

[0056] The second transmission line branch (212) contacts the second input side lead (134-1) included in the first set of input side leads (132-1, 134-1, 136-1);

[0057] The third transmission line branch contacts the third input-side lead (136-1) included in the first set of input-side leads (132-1, 134-1, 136-1);

[0058] The second transmission line branch (212) is located between the first and third transmission line branches (212) along the longitudinal axis (114); and

[0059] The average width of the second transmission line branch (212) exceeds the average width of the first transmission line branch (212) and also exceeds the average width of the third transmission line branch (212).

[0060] According to one or more embodiments, the leads included in the first set of input-side leads (132-1, 134-1, 136-1), the leads included in the first set of output-side leads (132-2, 134-2, 136-2), the first carrier input lead (130-1), and the first carrier output lead (130-2) have substantially equal maximum lead widths along the longitudinal axis (114).

[0061] According to one or more embodiments, the PA package (110) further includes:

[0062] The second set of input-side leads (128-1, 130-1) consists of X carrier input leads (including the first carrier input lead (130-1)); and

[0063] The second set of output-side leads (128-2, 130-2) consists of X carrier output leads (including the first carrier output lead (130-2));

[0064] The first group of input-side leads (132-1, 134-1, 136-1) consists of Y peak input leads;

[0065] The first group of output-side leads (132-2, 134-2, 136-2) consists of Y peak output leads; and

[0066] Where Y is greater than X. Attached Figure Description

[0067] At least one example of the invention will be described below in conjunction with the following drawings, wherein similar numbers denote similar elements, and:

[0068] Figure 1 This is a simplified schematic diagram of a Doherty PA circuit structure that can be implemented in part or in whole within a microelectronic package, as shown according to an exemplary embodiment.

[0069] Figure 2 This is a schematic circuit diagram of a parallel amplification path appropriately included in a 2-way or N-way Doherty PA package, as shown according to an exemplary embodiment.

[0070] Figure 3 This is a top or plan view of a flexible PA package platform with a 10-lead form factor (excluding any bias leads) as illustrated in an exemplary embodiment of this disclosure.

[0071] Figure 4 and 5 It is to utilize Figure 3 The diagram shows a plan view of a 10-lead Doherty PA package manufactured using a flexible PA packaging platform and illustrated according to an exemplary embodiment of the present disclosure. The flexible PA packaging platform has a first (bidirectional, five-path, asymmetric) Doherty PA configuration, shown in various completion stages.

[0072] Figure 6 This is after electrical interconnection via wire bonding. Figure 5 A detailed plan view of the area of ​​an exemplary 10-lead Doherty PA package is shown in the figure;

[0073] Figure 7 This is after the attachment of the cap or cover of the completed Doherty PA package manufacturing. Figure 4-6 An isometric view of the 10-lead Doherty PA package is shown in the image.

[0074] Figure 8 This is a plan view of a first exemplary PA system, which includes a substrate (e.g., a PCB (partially shown)) mounted on a branch transmission line. Figure 3-7 The 10-lead Doherty PA package shown in the image;

[0075] Figure 9 This is as illustrated in an exemplary embodiment after the finger isolation device is mounted on the lead-Doherty PA package. Figure 8 The plan view of the PA system shown in the figure;

[0076] Figure 10 This is a floor plan of a second exemplary PA system, which includes... Figures 3-7 The 10-lead Doherty PA package shown in the figure includes a substrate with non-branched transmission lines;

[0077] Figures 11-13 The utilization is as shown in other exemplary embodiments of this disclosure. Figure 3 The diagram shows a plan view of a 10-lead Doherty PA package manufactured using a flexible PA packaging platform and configured with different Doherty PA configurations; and

[0078] Figure 14 and Figure 15 This is a plan view of a Doherty PA package with different form factor and lead count, as shown in further exemplary embodiments according to this disclosure.

[0079] For the sake of simplicity and clarity, descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the following detailed description. It should also be understood that, unless otherwise stated, features or elements appearing in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements or regions in the drawings may be enlarged relative to other elements or regions to improve understanding of embodiments of the invention. Detailed Implementation

[0080] definition

[0081] The following definitions apply throughout this document. Terms not explicitly defined herein or elsewhere in this document are given their general meaning in the relevant technical field.

[0082] Input-side leads – Leads located on one side of the microelectronic package (at least two input leads extend from said side).

[0083] Lateral alignment – ​​Alignment along an axis perpendicular to the longitudinal axis of the microelectronic package and parallel to the front face of one or more semiconductor dies contained in the package and / or parallel to the die bonding area of ​​the package flange or other substrate.

[0084] Output-side leads – Leads located on one side of the microelectronic package (at least two output leads extend from said side).

[0085] Power amplifier (PA) package – any type of microelectronic package containing at least one power transistor for amplifying electrical signals (e.g., RF signals).

[0086] Power amplifier (PA) packaging platform – a basic packaging structure suitable for additional processing (e.g., via die attachment, electrical interconnection, and package enclosure) to produce finished PA packages (as defined above).

[0087] Overview

[0088] The following describes PA packages manufactured using a flexible PA platform, and PA systems incorporated into such PA packages. The PA package is usefully presented in the form of a Doherty PA package and is primarily described below; however, other types of PA packages can be manufactured using the flexible PA platform, including, for example, single-package push-pull PA devices. As indicated by the term "flexible design," the PA platform described herein is capable of supporting a variety of different PA configurations. For example, a single flexible PA package platform can be processed differently to manufacture Doherty PA packages with different layout configurations or circuit topologies (determined during die attachment, electrical interconnection, and package enclosure stages of the manufacturing process). Therefore, a first manufacturing entity can produce a flexible PA package platform and then further process PA packages with the same manufacturing entity or another entity to produce Doherty (or other) PA packages with the desired circuit layout and functionality. This enhances design flexibility, allowing purchasers to easily customize PA packages to best suit the needs of a specific application or use, while minimizing manufacturing costs through the mass production of a general-purpose PA platform.

[0089] Examples of Doherty PA packages may include multi-lead arrays extending from opposite sides of the package body (input and output sides herein). As described more fully below, in embodiments the lead arrays may be grouped or clustered such that certain lead groups are separated from adjacent lead groups by an expanded isolation gap to, for example, reduce cross-coupling between adjacent peak and carrier signal amplification paths. Regardless of whether arranged in small-pitch lead groups separated by such isolation gaps, the input-side lead array and the output-side lead array may each contain at least three leads, enabling the PA package to be manufactured to include a desired number of peak and / or carrier signal amplification paths to provide an asymmetric allocation of die-bonded regions favorable to one or more peak transistors to support N-axis Doherty circuit layouts (N > 2), and / or to provide enhanced isolation thereby reducing cross-coupling between signal-carrying (e.g., peak and carrier) paths as needed. Furthermore, in contrast to asymmetric Doherty packages with leads of varying widths, embodiments of the PA package can be manufactured comprising an asymmetric Doherty layout, wherein the asymmetric Doherty layout is arranged between arrays of leads of uniform width separated along the input and output sides of the package. As will become apparent from the following description, the disclosed Doherty PA package and packaging platform can provide further additional benefits.

[0090] See the attached diagram below. Figure 3-7 This describes an exemplary Doherty PA package manufactured using a flexible PA packaging platform; the following is in conjunction with... Figure 8-10 The description mentions that it can be installed. Figure 3-7 An exemplary PA system packaged in Doherty PA; the following is combined with Figure 11-13The discussion covers a variety of other PA package configurations that can be alternatively manufactured using the same flexible PA packaging platform; the following section combines... Figure 14 and 15 Further examples of Doherty PA packages with different form factors and lead counts will be discussed. However, firstly, the following will be combined with... Figure 1 and 2 A general description of the Doherty PA circuitry and package is provided to establish an exemplary but non-limiting context in which embodiments of this disclosure can be better understood.

[0091] General discussion of exemplary Doherty PA circuits and packages containing them

[0092] Figure 1 This is a simplified schematic diagram of a Doherty PA circuit 30 as illustrated in an exemplary embodiment of this disclosure. As indicated by dashed box 28, the Doherty PA circuit 30 shown can be partially integrated into a Doherty PA package. The Doherty PA circuit 30 includes an input node 32, an output node 34, and a power divider 36 (or splitter) between nodes 32 and 34. The Doherty PA circuit 30 further includes a main or “carrier” amplifier signal path (indicated by arrow 38), an auxiliary or “peak” signal amplification path (indicated by arrow 40), and a combination node 42 where the signal amplification paths 38 and 40 converge. A load 44 can be coupled to the combination node 42, for example, via an impedance transformer (not shown), to receive amplified RF signals from the Doherty PA circuit 30. The Doherty PA circuit 30 can be advantageously incorporated into a larger PA system (not shown), such as a cellular base station or other wireless communication system.

[0093] Power divider 36 is configured to divide the power of the input RF signal received at input node 32 into carrier and peak portions (referred to herein as "carrier input signal" and "peak input signal"). The carrier input signal is provided to carrier amplification path 38 via power divider output 46, while the peak input signal is provided to peak amplification path 40 via power divider output 46. When operating in full-power mode where both carrier and peak amplifiers 50, 52 simultaneously supply current to load 44, power divider 36 distributes the input signal power between signal amplification paths 38, 40. When the illustrated circuit 30 is configured with a symmetrical Doherty PA, power divider 36 can distribute power in a substantially equal manner, such that approximately half of the input signal power is provided to each signal amplification path 38, 40. In other instances, such as when the illustrated circuit 30 is configured with an asymmetrical Doherty PA, power divider 36 can distribute power unevenly between signal amplification paths 38, 40. Essentially, the power divider 36 distributes the input RF signal provided at the input node 32, and then the distributed signal portion is amplified along the carrier (main) and peak (auxiliary) amplification paths 38 and 40, respectively.

[0094] Carrier amplifier 50 and peak amplifier 52 each include at least one power transistor IC for amplifying RF signals conducted through amplifiers 50 and 52. Each power transistor IC can be fabricated on a semiconductor die and is configured as a single stage or multiple stages. In embodiments, all amplifier stages (or the final amplifier stage) of one or both of carrier amplifier 50 and peak amplifier 52 can be implemented using one of the following: silicon-based FETs (e.g., laterally diffused metal-oxide-semiconductor FETs or LDMOS FETs) or III-V FETs (e.g., gallium nitride (GaN) FETs, gallium arsenide (GaAs) FETs, gallium phosphide (GaP) FETs, indium phosphide (InP) FETs, or indium antimonide (InSb) FETs) or another type of III-V transistor. When, for example, circuit 30 has a symmetrical Doherty configuration, the dimensions of the carrier and peak transistor ICs can be equal. Alternatively, in various asymmetric Doherty configurations, the sizes of the carrier and peak transistor ICs can be unequal; it should be understood that the term "size" in this context refers to the planar dimension or surface area occupied by the power transistor IC. Specifically, in an asymmetric Doherty configuration, one or more peak transistor ICs can be a multiple of one or more carrier transistor ICs. For example, the size of one or more peak transistor ICs can be twice the size of one or more carrier transistor ICs, such that the current carrying capacity of one or more peak transistor ICs is approximately twice that of one or more carrier transistor ICs. Peak / carrier amplifier IC size ratios other than 2:1 can also be implemented.

[0095] During circuit operation, the carrier amplifier 50 of the Doherty PA circuit 30 can be biased to operate in Class AB mode, while the peak amplifier 52 is biased to operate in Class C mode. At low power levels (e.g., when the power of the input signal at node 32 is less than the turn-on threshold level of the peak amplifier 52), the Doherty PA circuit 30 operates in low-power or backoff mode. In low-power (backoff) mode, the carrier amplifier 50 is typically the only amplifier supplying current to the load 44. However, when the power of the input signal exceeds the threshold level of the peak amplifier 52, the Doherty PA circuit 30 switches to high-power mode operation, in which both the carrier amplifier 50 and the peak amplifier 52 supply current to the load 44 simultaneously. At this time, the peak amplifier 52 provides active load modulation at the combined node 42, thereby allowing a sustained linear increase in the current of the carrier amplifier 50.

[0096] In embodiments of the Doherty PA circuit 30, input and / or output impedance matching networks 54, 56 (input MNm, output MNm) can be implemented at the input and / or output of the carrier amplifier 50. Similarly, input and / or output impedance matching networks 58, 60 (input MNp, output MNp) can be implemented at the input and / or output of the peak amplifier 52. In each case, matching networks 54, 56, 58, 60 can be used to gradually increase the circuit impedance towards the load impedance and source impedance. In some embodiments, all or part of the input and output impedance matching networks 54, 56, 58, 60 can be implemented within the power transistor package including the carrier and / or peak amplifiers 50, 52, as indicated by the dashed box representing the Doherty PA package 28. Figure 1 As indicated in the document. In other instances, the input and output impedance matching networks 54, 56, 58, and 60 can be implemented, wholly or partially, outside the Doherty PA package 28, for example, on a PCB (e.g., in conjunction with the following). Figure 8-10 The PCB 196 or PCB 228 described may be mounted on another substrate with a Doherty PA package 28.

[0097] exist Figure 1In a typical example, the Doherty PA circuit 30 has a non-inverting load network configuration. Therefore, the input-side circuitry is configured such that, at, for example, the center operating frequency of the Doherty PA circuit 30, the input signal provided to the peak amplifier 52 is delayed by 90 degrees relative to the input signal provided to the carrier amplifier 50. To ensure that the carriers and the peak input RF signal arrive at amplifiers 50, 52 with a phase shift of approximately 90 degrees, a phase delay element 62 can be incorporated into the Doherty PA circuit 30, providing approximately 90 degrees of phase shift to the peak input signal. For example, the phase delay element 62 may comprise a quarter-wavelength transmission line, or another suitable type of delay element with an electrical length of approximately 90 degrees. To compensate for the 90-degree phase delay difference between the carriers and the peak amplification paths 38, 40 at the inputs of amplifiers 50, 52, thereby ensuring that the amplified signal arrives in phase at the combination node 42, the output-side circuitry is configured to apply an approximately 90-degree phase delay to the signal between the output of the carrier amplifier 50 and the combination node 42. This can be achieved by providing an additional delay element 64, which may or may not be included in the Doherty PA package 28 itself.

[0098] Although the Doherty PA circuit 30 has a non-inverting load network configuration in the illustrated embodiment, other load network configurations are possible in other embodiments. For example, in an alternative embodiment, the Doherty PA circuit 30 may alternatively have an inverting load network configuration. In this case, the input-side circuitry can be configured such that the input signal provided to the carrier amplifier 50 at the center operating frequency of the Doherty PA circuit 30 is delayed by approximately 90 degrees relative to the input signal provided to the peak amplifier 52. Accordingly, the output-side circuitry can be configured to apply an approximately 90-degree phase delay to the signal between the output of the peak amplifier 52 and the combination node 42.

[0099] As described above, power amplifiers 50, 52 and a portion of impedance matching networks 30, 58, 56, 60 can be implemented in the form of a Doherty PA package 28. In this case, the PA package 28 can be electrically coupled to signal transmission lines (e.g., traces) provided on a substrate on which the PA package 28 is mounted; for example, Figure 8 and 9The PCB 196 is shown in the diagram. In various embodiments, power amplifiers 50 and 52 may each include single-stage or multi-stage power transistors bonded to the substrate. Input and output matching networks 54, 56, 58, 60, or portions thereof, may be implemented as additional components within the PA package 28. Furthermore, in more complex embodiments, one or both of power amplifiers 50 and 52 may be implemented using multiple parallel amplification paths (instead of a single amplification path). For example, in an exemplary asymmetric Doherty configuration, carrier amplifier 50 may be implemented using two (or more) parallel amplification paths, while peak amplifier 52 may be implemented using three (or other) parallel amplification paths. Furthermore, in the case of an N-axis Doherty amplifier (N > 2), the Doherty PA package 28 may contain multiple peak amplifiers with different configurations or levels. This will now be combined with... Figure 2 Further discussion on this topic is provided.

[0100] Go to Figure 2 A schematic diagram of an exemplary Doherty PA package 66 is shown, comprising a package body 68 through which multiple conductive signal amplification paths 70-1, 70-2, 70-3 extend. The Doherty PA package 66 provides at least two types of signal amplification paths: one or more carrier (main) signal amplification paths 70-1, and one or more peak (auxiliary) signal amplification paths 70-2, 70-3. Furthermore, when the Doherty PA package 66 is in the form of an N-way Doherty amplifier (N > 2), the Doherty PA package 66 can contain two or more different types of peak signal amplification paths 70-2, 70-3 (which are often referred to as different peak signal amplification "levels"). In this example, and as... Figure 2 As indicated illustratively, the N-way Doherty PA package 66 may include: (i) a first type (or horizontal) peak signal amplification path, which may include one or more separate signal amplification paths 70-2 extending through the Doherty PA package 66, and (ii) one or more other types (or horizontal) peak signal amplification paths, which in turn include any desired number of signal amplification paths 70-3. The peak signal amplification paths 70-2, 70-3 may be routed through different transistors, phase shifts, or otherwise differently processed to produce an N-way (e.g., 3-way or 4-way) Doherty amplifier. In other instances, the Doherty PA package 66 may take the form of a 2-way Doherty amplifier, and the peak amplification path 70-3 may be omitted.

[0101] The Doherty PA package 66 may include any actual number of carrier signal amplification paths 70-1 (labeled “X”) extending in parallel through the package 66. When the Doherty PA package 66 includes two or more carrier signal amplification paths 70-1, the illustrated circuit structure may be repeated for each instance of the carrier signal amplification paths 70-1. Similarly, the Doherty PA package 66 may include any actual number of first (and possibly only) type or level carrier signal amplification paths 70-2, 70-3. This can be expressed by stating that the Doherty PA package 66 includes a number of first type peak signal amplification paths 70-2 of “Y1”. If the Doherty PA package 66 includes one or more other (second, and possibly third) types of peak signal amplification paths 70-3, it may be further stated that the Doherty PA package includes “Y2” peak signal amplification paths 70-3 for each other signal amplification path type. When the Doherty PA package 66 is configured as an N-directional Doherty amplifier containing two or more peak signal amplification path types, the number of each type of signal amplification path can be equal, such that Y1 = Y2. Furthermore, when the N-directional Doherty amplifier has a symmetrical layout, the number of carrier signal amplification paths can be selected such that X = Y1 = Y2. Conversely, when the N-directional Doherty amplifier has an asymmetrical layout, the number of carrier signal amplification paths can be selected such that X < Y1 = Y2. In yet another instance where the Doherty PA package 66 has a bidirectional Doherty amplifier topology, the PA package 66 may lack an additional peak signal amplification path 70-3, and Y1 may be equal to X (in the case of a symmetrical Doherty circuit structure) or greater than X (in the case of an asymmetrical Doherty circuit structure).

[0102] like Figure 2 The illustration indicates that the circuit structure of each signal amplification path 70-1, 70-2, 70-3 can be substantially similar. Therefore, the following description also applies to each amplification path 70-1, 70-2, 70-3, where common reference numerals are used to denote similar elements. Continuing with the previously introduced numbering scheme, the suffix "-1" is appended to the reference numerals identifying circuit elements located in one or more carrier signal amplification paths 70-1, while the suffix "-2" is appended to the reference numerals identifying circuit elements located in one or more peak signal amplification paths 70-2. Similarly, if included in the Doherty PA package 66, the suffix "-3" is appended to the reference numerals identifying circuit elements located in any other type or level of peak signal amplification path 70-3. Furthermore, in the following description, the aforementioned suffixes are omitted when referring substantially to the same type of circuit elements (or other features) common to all amplification paths 70-1, 70-2, 70-3.

[0103] Each signal amplification path of the exemplary Doherty PA package 66 includes a package input 74 (e.g., a first conductive package terminal or lead of package 66), an input impedance matching circuit 76, at least one power transistor 78, an output impedance matching circuit 80, and a corresponding package output 82 (e.g., a second conductive package terminal or lead of package 66). First, regarding the power transistor 78, it can be the primary active component in each amplification path. Each transistor 78 includes a control terminal 83 and two conductive terminals 84, 86. The conductive terminals 84, 86 of transistor 78 are spatially and electrically separated by a variable conductivity channel. For example, each transistor 78 can be a FET including a gate (control terminal 83), a drain (first conductive terminal 84), and a source (second conductive terminal 86). In various embodiments, and utilizing the nomenclature generally applied to FETs in a non-limiting manner, the gate 82 of transistor 78 is coupled to the input impedance matching circuit 76, the drain 84 of transistor 78 is coupled to the output impedance matching circuit 80, and the source 86 of transistor 78 is coupled to ground (or another reference voltage). Then, by changing the control signal supplied to the gate of transistor 78, the current between the conductive terminals of transistor 78 can be appropriately modulated during the operation of the Doherty PA package 66.

[0104] Input impedance matching circuitry 76 is coupled between the corresponding package input 74 and the control terminal 83 (e.g., gate) of transistor 78. Input impedance matching circuitry 76 is configured to raise the impedance of the Doherty PA package 66 to a higher impedance level, for example, in the range of about 2 to about 10 ohms or higher. This allows the PBC level matching interface from the driver stage (not shown) to have an impedance achieved in high-volume manufacturing with minimal loss and variation. Figure 2 As indicated, each input impedance matching circuit 76 may have a T-matching configuration. Therefore, the input impedance matching circuit 76 may include two inductor elements 88, 90 (e.g., two bonded wires or an array of bonded wires) and a parallel capacitor 92. The first inductor element 88 is electrically coupled between the corresponding package input 74 and node 92, which is coupled to a first end of capacitor 94. The second inductor element is coupled between node 92 (or the first end of capacitor 94) and the control terminal 83 of transistor 78. Finally, the second end of capacitor 94 may be electrically coupled to a reference voltage, such as ground.

[0105] Due to the circuit arrangement described above, inductors 88 and 90 and parallel capacitor 92 together form a low-pass filter upstream of transistor 78. The inductance values ​​of inductors 88 and 90 and the capacitance value of capacitor 92 will vary between embodiments. However, as an example, in one embodiment, the series combination of inductors 88 and 90 can have an inductance value in the range of about 50 picohens (pH) to about 3 nanohenries (nH), while the parallel capacitor 94 can have an inductance value in the range of about 5 picofarads (pF) to about 120 pF. In contrast, the parallel capacitor 92 can be selected to have a relatively large capacitance, for example, exceeding about 60 pF, to provide an acceptable low RF impedance point. In other instances, the inductance values ​​of inductors 88 and 90 and / or the capacitance of the parallel capacitor 92 can be greater than or less than the ranges described above.

[0106] Discussing the output side of the Doherty PA package 66, an output impedance matching circuit 80 is coupled between a first conductive terminal 84 (e.g., drain) of transistor 78 and the corresponding package output 80. The output impedance matching circuit 80 is configured to match the output impedance of the Doherty PA package 66 to the input impedance of an external circuit or component (not shown) electrically coupled to the output 80. In an embodiment, the output impedance matching circuit 80 includes at least two inductor elements 96, 98 and a parallel capacitor 100. Inductor element 96 (e.g., a third wire-bonded array) is coupled between the first conductive terminal 84 (e.g., drain) of transistor 78 and the package output 80. Another inductor element 98 (e.g., a fourth wire-bonded array) is electrically coupled between the first conductive terminal 84 of transistor 78 and a first terminal of the parallel capacitor 100. In the illustrated embodiment, a second terminal of the parallel capacitor 100 is coupled to ground or another reference voltage. Therefore, the parallel inductor element 98 and the parallel capacitor 100 are series-coupled between the conductive terminal 84 of transistor 78 and ground. This combination of impedance matching elements serves as a first (high-pass) matching stage. As an example, the parallel inductor 98 can have an inductance value ranging from about 66 pF to about 3 nH. In contrast, the parallel capacitor 100 can have a capacitance value ranging from about 30 pF to about 500 pF. In other embodiments, these values ​​may fall outside the aforementioned ranges.

[0107] In various embodiments, portions of the input and output impedance matching circuits 76, 80 may be implemented as separate or discrete components, or may be part of other assemblies, such as PCBs or low-temperature co-fired ceramic (LTCC) devices. In other embodiments, portions of the input and / or output impedance matching circuits 76, 80 may be coupled to and / or integrated into one or more semiconductor dies carrying transistor 78. In some embodiments, some or all of the signal amplification paths 70 may also include a bias circuitry system (not shown). When present, such a bias circuitry system may be electrically connected to an external bias circuitry (not shown) via one or more bias leads. Alternatively, the external bias circuitry may be connected to package input 74 or package output 80, and one or more bias voltages may be suitably provided through input 74 and / or output 80.

[0108] Continue to refer to Figure 2 In embodiments, the Doherty PA package 66 may include any number of isolation features within the package body or housing. When present, such isolation features can be usefully positioned between conductive signal paths to reduce the likelihood of electrical and / or magnetic cross-coupling therebetween. Two such isolation features are shown in the illustrated example: (i) a first isolation feature 72-1 located between one or more carrier signal amplification paths 70-1 and one or more peak signal amplification paths 70-2 along the longitudinal axis of the package 66 (indicated by the bidirectional arrow 100); and (ii) a second isolation feature 72-2 located between one or more peak signal amplification paths 70-2 and one or more peak signal amplification paths 70-3, additionally along the longitudinal axis 100. The number and location of isolation features 72 within the Doherty PA package 66 will vary; and in many instances, the Doherty PA package 66 may lack any of these isolation features. However, when present, isolation features 72 are usefully extended between signal amplification paths prone to unwanted electrical and / or magnetic cross-coupling, as discussed further below.

[0109] According to embodiments of this disclosure, isolation features 72 (when present) may each include at least two ground isolation leads 102, 104. In some embodiments, each isolation feature 72 may not include additional structural elements other than the spacing or gap between adjacent signal amplification paths (e.g., along longitudinal axis 100). In other instances, isolation walls 106, 108 may be electrically coupled between ground leads 102, 104 to further enhance electrical and / or magnetic shielding. Each isolation wall 106, 108 may include a conductive layer, fin, or body 106 having a wall-like shape factor and extending between adjacent dies on which transistors 78 are formed. Conductors 106 may be made of a variety of different conductive materials, such as alloys (by weight) containing one or more of the following as main components: copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), and gold (Au). In some embodiments, conductors 106 may be electrically coupled between isolation leads 102, 104, or alternatively, may be free-floating. In other embodiments, the conductor 106 included in each isolation wall 106, 108 can be electrically coupled to ground (or coupled to another reference voltage) via one or both of the leads 102, 104, and thus can generally be used as a ground plane. In this way, the conductor 106 and (more generally) each conductive wall 106 can be electrically grounded via the lead pairs 102, 104 to, for example, reduce eddy current losses, hysteresis effects, and RF mismatch (where applicable). In other embodiments, the conductive wall 106 may not be electrically grounded, or may be omitted entirely from the Doherty PA package 66.

[0110] In some cases, one or more magnetic shielding layers 108 may be bonded to or otherwise contacted with one or more conductors 106 included in one or more isolation walls 106. If present, the magnetic shielding layer 108 may be composed of any magnetically permeable material with a permeability greater than that of the material constituting the conductor 106 and a conductivity less than that of the conductor 106. As used herein, when the relative permeability (μ) exceeds 1000... r When the magnetic shielding layer 108 is defined as "magnetic", the material is defined as having a relative permeability (μ). In some embodiments, the magnetic shielding layer 108 may be made of materials with a relative permeability (μ). r The material composition exceeds 10,000. Suitable materials include, but are not limited to, metallic materials, including Mu metal, Fe-based alloys (e.g., permalloy), ferrites, electrical steel, and amorphous metal alloys (e.g., Other alloys with relatively high magnetic permeability. In embodiments, composite materials containing magnetic particles, fibers, etc. may also be utilized. Further description of the isolation structures of the isolation walls 106, 108 included in embodiments suitable for use as the Doherty PA package 66 can be found in the following reference, which is incorporated herein by reference: U.S. Patent Application Serial No. 16 / 107,089 entitled “Electromagnetically Shielded Microelectronic Assemblies and Methods for the Fabrication Thereof”, filed August 21, 2018 with the United States Patent and Trademark Office (USPTO).

[0111] Examples of designing a flexible Doherty PA packaging platform and its packaging.

[0112] Next, let's talk about... Figure 3 This illustrates a flexible PA packaging platform 110 in a die-ready state; that is, in a state awaiting bonding or attachment of one or more semiconductor dies. In this particular example, the flexible PA packaging platform 110 employs a cavity package form, which is attached with a cover or cap to complete the package manufacturing, as shown below. Figure 7 The following description applies equally to all microelectronic package types suitable for manufacturing Doherty PA packages and PA packages, including, for example, capsule-shaped or overmolded packages lacking a gas-filled cavity. The flexible PA package platform 110 includes a package body 112 having a longitudinal axis 114, a first longitudinal edge portion or package side 115, and an opposing second longitudinal side edge portion or package side 117. In examples of fabricating the flexible PA package platform 110 to produce a Doherty PA package, some or all of the leads extending from package side 115 can be used as carrier and peak input leads, while some or all of the leads extending from package side 117 can be used as carrier and peak output leads. For this reason, package sides 115 and 117 are also referred to below as “input side 115” and “output side 117”, respectively.

[0113] The package body 112 of the flexible PA packaging platform 110 will have different constructions between various embodiments and can take various forms without limitation. In the example shown, the package body 112 includes a conductive substrate or base flange 116 on which a die bonding region 118 is provided. An outer package sidewall 120 extends around the outer periphery of the upper surface of the base flange 116 to surround or constrain the outer periphery of the cavity 122 and the exposed inner peripheral recess or bonding pad holder 124 within the cavity 122. The package sidewall 120 may be made of a dielectric material to provide isolation between the package leads and the conductive base flange 116, as described below. In some embodiments, the package sidewall 120 may be provided as one or more discretely manufactured structures, such as a single or multi-piece window frame, positioned on and bonded in place on the base flange 116. In other instances, the package sidewall 120 may be overmolded onto the base flange 116. In the latter case, the package sidewall 120 may or may not be formed to extend downward beyond the front of the base flange 116 to form a lower skirt region. When present, this skirt region may extend around the outer periphery of the base flange 116, while the lower main surface of the flange 116 remains exposed along the back of the package body 112.

[0114] As indicated above, the base flange 116 of the flexible PA package platform 110 has an upper surface or front surface on which a die bonding region 118 is provided for attaching one or more transistor dies and possibly other microelectronic devices mounted within the package body 112. The base flange 116 can be implemented as a material body, a layered or laminated structure, or other substrate suitable for supporting such microelectronic devices. In some embodiments, the base flange 116 can serve as a heat sink and / or conductive terminal for the subsequently manufactured PA package. As an example, in some embodiments, the base flange 116 can be in the form of a monolithic metal structure, a plate, or a block. In other embodiments, the base flange 116 can have a multilayer metal construction; for example, the base flange 116 can include multiple thermally conductive layers bonded in a stacked or laminated arrangement. Typically, the base flange 116 will be primarily composed of one or more metals (e.g., Cu) having relatively high thermal conductivity. As a more specific example, in an embodiment where the base flange 116 is a layered or laminated structure, the base flange 116 may comprise a combination of at least one Cu layer and at least one different metal layer with a coefficient of thermal expansion (CTE) less than or equal to that of the Cu layer. The different metal layers may be composed of, for example, molybdenum (Mo), a Mo-Cu alloy, or a Mo-Cu composite material. In this way, the base flange 116 can be endowed with relatively high thermal conductivity and a low effective CTE.

[0115] The flexible PA package platform 110 can be described as having a 10-lead count. As used herein, the term "lead count" refers to the number of signal-carrying leads included in the PA package (or package platform), excluding any bias leads, such as... Figure 3 The bias lead 126 is shown in the diagram. In the example shown, the flexible PA package platform 110 includes a set of five input-side leads 128-1, 130-1, 132-1, 134-1, 136-1 and a corresponding set of five output-side leads 128-2, 130-2, 132-2, 134-2, 136-2. Package leads may also be discussed below as “laterally aligned lead pairs” or more simply as “lead pairs.” Each lead pair includes two leads that are perpendicular to the longitudinal axis 114 of the package platform 110 (or the package manufactured thereon) and parallel to the [missing information]. Figure 3 The Y-axis of the coordinate graph 138 in the lower left corner is aligned horizontally. Using this terminology, the flexible PA package platform 110 can also be described as including the following lead pairs: a first laterally aligned lead pair 128 consisting of leads 128-1 and 128-2, a second laterally aligned lead pair 130 consisting of leads 130-1 and 130-2, a third laterally aligned lead pair 132 consisting of leads 132-1 and 132-2, a fourth laterally aligned lead pair 134 consisting of leads 134-1 and 134-2, and a fifth laterally aligned lead pair 136 consisting of leads 136-1 and 136-2.

[0116] Commonly, input-side leads 128-1, 130-1, 132-1, 134-1, and 136-1 form a first (input-side) lead array, while output-side leads 128-2, 130-2, 132-2, 134-2, and 136-2 form a second (output-side) lead array. In the example shown, the input-side lead array and the output-side lead array are each arranged as two clusters or groups; as used herein, the terms "group" and "set" refer to a configuration with respect to a longitudinal axis along the PA package or package platform (e.g., along...). Figure 3Two or more leads with relatively small spacing (compared to at least one other lead or lead group included in the PA package or package platform) of the PA package platform 110 are interchangeable. First, let’s talk about the input-side lead array containing package leads 128-1, 130-1, 132-1, 134-1, and 136-1, which is spatially divided into two groups: (i) a first input-side lead group containing leads 128-1 and 130-1, and (ii) a second input-side lead group containing leads 132-1, 134-2, and 136-2. In some instances, the input-side lead group containing leads 128-1 and 130-1 may be alternatively referred to as the “second input-side lead group”, while the input-side lead group containing leads 132-1, 134-1, and 136-1 may be alternatively referred to as the “first input-side lead group”, depending on the order in which these lead groups are introduced.

[0117] Continue to refer to Figure 4 The leads in the first (or second) input-side lead group (leads 128-1, 130-1) are spaced or offset by the intra-group (IG) lead spacing as described along the longitudinal axis 114 of the flexible PA package platform 110. The first IG lead spacing is determined by... Figure 3 The arrow "S" in the upper right corner IG_1 "Identification. Similarly, the leads in the second (or first) input side lead group (132-1, 134-1, 136-1) are arranged as shown along the longitudinal axis 114 and marked by the arrow "S". IG_2 The second (or first) group of internal leads are separated by a spacing. In the example shown, the first and second IG lead spacings are substantially equal, such that S IG_1 ≈S IG_2 As used herein, the term "substantially equal" is defined as a difference of less than 10%. In other embodiments, S IG_1 and S IG_2 They may be substantially unequal, making S IG_1 More than S IG_2 Or conversely, making S IG_2 More than S IG_1 .

[0118] The first input-side lead group (small-pitch leads 128-1, 130-1) and the second input-side lead group (small-pitch leads 132-1, 134-1, 136-1) are separated by an enlarged input-side isolation gap 137-1. The isolation gap 137-1 is "enlarged" in the sense that its width exceeds the IG lead pitch. Figure 3The exemplary design shown in the figure features a flexible PA packaging platform 110 sized such that the input-side isolation gap 137-1 has a longitudinal axis 114 and is marked by a double-headed arrow "W". G The predetermined width of the identifier. In various embodiments, the width of the input-side isolation gap 137-1 is greater than the first IG lead pitch (S). IG_1 ) and second IG lead spacing (S) IG_2 Furthermore, in several instances, the width of the input-side isolation gap 137-1 can be greater than the first IG lead pitch (S). IG_1 It is at least 50% larger than the second IG lead spacing (S). IG_2 At least 50% larger; again, note S IG_1 and S IG_2 They may be roughly equal, or they may be roughly unequal.

[0119] The aforementioned lead spacing scheme helps to minimize the footprint of the flexible PA package platform 110 and any PA package manufactured using it, while reducing cross-coupling between carriers and peak signal amplification paths. Furthermore, providing multiple discrete package leads 128-1, 130-1 (instead of providing a first larger single lead instead of leads 128-1, 130-1) and multiple discrete package leads 132-1, 134-1, 136-1 (instead of providing a second larger single lead instead of leads 132-1, 134-1, 136-1) advantageously enhances design flexibility, improves the uniformity of current distribution during operation of PA packages manufactured using the PA package platform 110, and provides other benefits. Despite these advantages, the flexible PA package platform 110 may not include an enlarged input-side isolation gap 137-1 in all instances. In this case, package leads 128-1, 130-1, 132-1, 134-1, and 136-1 may be separated at regular intervals along the longitudinal axis 114 of the PA package platform 110.

[0120] The foregoing description of the package leads and lead groups included in the input-side lead array also applies to the package leads and lead groups included in the output-side lead array of the PA package platform 110. Therefore, in a similar manner, the output-side leads 128-2, 130-2, 132-2, 134-2, and 136-2 forming the output-side lead array of the PA package platform 110 are divided into two groups: (i) a first (or second) output-side lead group containing leads 128-2 and 130-2, and (ii) a second (or first) lead output-side lead group containing leads 132-2, 134-2, and 136-2. The leads 128-2 and 130-2 within the first output-side lead group are spaced at the aforementioned first IG (within the group) lead spacing (S). IG_1Separated by ) and the leads 132-2, 134-2, and 136-2 in the second output side lead group are separated by the second IG lead spacing (S IG_2 The input-side lead array and the output-side lead array are separated by a spacing of 128, 132, 132, 134, and 136. As previously mentioned, this identical or left-right symmetrical lead spacing between the input-side lead array and the output-side lead array ensures lateral alignment of the leads in the lead pairs 128, 132, 132, 134, and 136. Furthermore, in a manner similar to the input-side lead groups discussed above, the first and second output-side lead groups are spaced with a gap width (W) specified above. G The enlarged output-side isolation gap 137-2 is separated or offset. Therefore, as discussed above, the dimensions of the flexible PA package platform 110 can be set such that the gap width (W) of the output-side isolation gap 137-2 is separated or offset. G ) exceeds and may exceed the first IG lead pitch (S) IG_1 ) and second IG lead spacing (S) IG_2 The first IG lead spacing is at least 50% larger than the first IG lead spacing (S). IG_1 ) and second IG lead spacing (S) IG_2 They can be easily made to be substantially equal, but they do not necessarily have to be substantially equal.

[0121] In an embodiment, leads 128-1, 130-1 in the first input-side lead group and leads 128-2, 130-2 in the first output-side lead group may have substantially equal maximum lead widths (as considered to be outside the package body 112). This can be achieved by referring to... Figure 3 The dimension "W1" appearing in the upper right area can be interpreted as indicating the corresponding maximum width of leads 128-2 and 130-2, which can be equal to the maximum width of leads 128-1 and 130-1. These maximum lead widths and all other lead widths mentioned in this document are along the longitudinal axis of the reference package or package platform (e.g., the longitudinal axis 114 of package platform 110) in the package body of the PA package or package platform (e.g., ...). Figure 3 The maximum width of each lead on the exterior of the package body 112 shown is measured. Similarly, the dimensions of the leads in lead pairs 132, 134, and 136 can be set to have the same maximum width, which is equal to the maximum width measured at the maximum width of each lead on the exterior of the package body 112 shown. Figure 3The arrow "W2" appearing in the lower right region indicates the second predetermined lead width. In other words, in embodiments, each lead 132-1, 134-1, 136-1 in the second input-side lead group and each lead 132-2, 134-2, 136-2 in the second output-side lead group can have substantially equal maximum lead widths (W2). Furthermore, in at least some embodiments, all leads in the input-side lead array and all leads in the output-side lead array (and therefore all leads in the first input-side group, the second input-side group, the first output-side group, and the second output-side group) can have substantially equal maximum lead widths (again, considered to be outside the package body 112), such that W1≈W2. In such instances, when the package leads constituting the lead arrays have equal (or substantially equal) maximum widths, the input-side lead array and the output-side lead array can be referred to as "uniform width lead arrays". In other instances, the corresponding widths of the leads included in the input-side lead array and / or the output-side lead array can differ.

[0122] In some embodiments, the flexible PA package platform 110 can be manufactured to include one or more IPDs. In the example shown, the flexible PA package platform 110 includes ten IPDs contained within the package body 112: five input-side IPDs 140-1, 142-1, 144-1, 146-1, and 148-1, and five output-side IPDs 140-2, 142-2, 144-2, 146-2, and 148-2. The input-side IPDs 140-1, 142-1, 144-1, 146-1, and 148-1 are aligned with the output-side IPDs 140-2, 142-2, 144-2, 146-2, and 148-2 in a manner similar to package leads to form five IPD pairs 140, 142, 144, 146, and 148. IPD pairs 140, 142, 144, 146, and 148 are separated along an axis parallel to the longitudinal axis 114 and laterally aligned with lead pairs 128, 130, 132, 134, and 136. In various embodiments, the IPDs in IPD pairs 140, 142, 144, 146, and 148 can take the form of integrated capacitors. When the flexible PA packaging platform 110 is fabricated to produce complete PA packages (deployed within the PA system), the integrated capacitors can be coupled to ground via the base flange 116. IPDs 140-1 and 142-1 can therefore correspond to Figure 2 The input-side capacitor 94-1 is shown, while IPDs 144-1, 146-1, and 148-1 correspond to input-side capacitor 94-2. Similarly, IPDs 140-2 and 142-2 can correspond to... Figure 2The output-side capacitor 100-1 is shown in the figure; while IPDs 144-2, 146-2, and 148-2 correspond to Figure 2 The input-side capacitor 100-2 is also shown. In other instances, one or more of IPDs 140, 142, 144, 146, and 148 may be omitted from the PA package platform 110; or they may be replaced by discrete passive devices, such as chip capacitors or other surface mount devices (SMDs).

[0123] Advance to Figure 4 This illustrates a flexible PA package platform 110 after chip attachment. Here, five power transistor IC dies 150, 152, 154, 156, and 158 (hereinafter referred to as "transistor dies 150, 152, 154, 156, and 158") have been bonded or otherwise attached to die bonding regions 118 of a base flange 116 at selected locations separated along the longitudinal axis 114. At this manufacturing juncture, the desired configuration of the PA package platform 110 has been established and used to determine the number, type, and location of the transistor dies 150, 152, 154, 156, and 158 mounted within the flexible PA package platform 110. Here, it has been determined that the flexible PA package platform 110 should be processed to produce a Doherty PA package with a bidirectional, five-path, asymmetric Doherty PA configuration. For this reason, the flexible PA package platform 110 in… Figure 4 The designation is indicated by the reference numeral "110-1" in the attached diagram, where the suffix "-1" indicates a specific package configuration. This numbering scheme is also described below. Figure 5-7 The remainder is retained. In other embodiments, the flexible PA packaging platform 110 can be used to manufacture Doherty PA packages with different configurations, as described below. Figure 11-13 Let's discuss a few other examples.

[0124] from Figure 4 From top to bottom, a first transistor die 150 can be mounted to the upper portion of the die bonding region 118 of the base flange 116. The transistor die 150 is positioned laterally aligned with the input-side lead 128-1 and the output-side lead 128-2. The width of the transistor die 150 may be substantially equal to or less than the maximum lead width of the leads included in the lead pair 128. Similarly, a second transistor die 152 is bonded to the die bonding region 118 of the base flange 116 at a location laterally aligned with the input-side lead 130-1 and the output-side lead 130-2. Again, the width of the second transistor die 152 may be substantially equal to or less than the maximum lead width of the corresponding lead pair 130. In the example shown, at least one charge-carrying transistor (similar to...) can be provided on each transistor die 150, 152. Figure 2Transistor 78-1 in the PA package is configured such that dies 150 and 152 cooperate with corresponding lead pairs 128 and 130 (and IPDs 140 and 142, when present) to form two parallel carrier signal amplification paths through PA package 110-1, as follows. Figure 5 For this reason, transistor dies 150 and 152 are referred to below as “carrier PA dies 150 and 152”, respectively. In other instances, the width or positioning of carrier PA dies 150 and 152 may vary; and / or dies 150 and 152 may be replaced by a single transistor die carrying two (or more) carrier transistors arranged side-by-side.

[0125] Continue from Figure 4 From top to bottom, the third transistor die 154 is attached to the die bonding region 118 of the base flange 116 at a position laterally aligned with the input-side lead 132-1 and the output-side lead 132-2; the fourth transistor die 156 is attached to the die bonding region 118 at a position laterally aligned with the input-side lead 134-1 and the output-side lead 134-2; and the fifth transistor die 158 is attached to the die bonding region 118 at a position laterally aligned with the input-side lead 136-1 and the output-side lead 136-2. In this embodiment, similar to... Figure 2 The transistor 78-2, schematically shown, can provide at least one peak transistor on each transistor die 154, 156, 158. Therefore, transistor dies 154, 156, 158 cooperate with corresponding lead pairs 132, 134, 136 (and IPDs 144, 146, 148, when present) to form three parallel peak signal amplification paths through the Doherty PA package 110-1, as considered to be in... Figure 7 The completion status shown is described below. For this reason, transistor dies 154, 156, and 158 are more specifically referred to below as "peak PA dies 154, 156, and 158".

[0126] In this embodiment, the widths of peak dies 154, 156, and 158 can be substantially equal to the maximum widths of the package leads in lead pairs 132, 134, and 136, respectively. In other embodiments, this may not be the case. The cumulative die bonding area attached to peak PA dies 154, 156, and 158 (i.e., the surface area of ​​the die bonding region 118 covered by PA dies 154, 156, and 158) exceeds the cumulative die bonding area occupied by carrier PA dies 150 and 152. Therefore, the cumulative size of the transistors provided on peak PA dies 154, 156, and 158 can exceed the cumulative size of the transistors provided on carrier PA dies 150 and 152. Therefore, in the illustrated embodiment, the Doherty PA package 110-1 is given an asymmetric layout to achieve performance improvements through the cumulative expansion of peak transistors within the Doherty PA package 110-1. In other instances, peak PA dies 154, 156, and 158 can be replaced by one or two transistor dies on which multiple transistors are formed. In fact, in an alternative embodiment of the Doherty PA package 110.1, all illustrated transistor dies 152, 154, 156, 156, and 158 can be replaced by a single die carrying both peak and charge carrier transistors.

[0127] Figure 5 The Doherty PA package 110-1 is shown after electrical interconnection to complete the desired package wiring structure. In this particular example, wire bonding, or “wire bonding,” is used to form the desired electrical interconnection; however, in other examples, different interconnection techniques may be used instead of wire bonding or different interconnection techniques may be combined with wire bonding. Several input-side wire bonding arrays 160-1, 162-1, 164-1, 166-1, 168-1 and corresponding numbers of output-side wire bonding arrays 160-2, 162-2, 164-2, 166-2, 168-2 have been manufactured according to the wire bonding process to electrically interconnect transistor dies 152, 154, 156, 156, 158; IPDs 140, 142, 144, 146, 148; and lead pairs 128, 130, 132, 134, 136 to complete the signal amplification path described below. Specifically, the formation of the wire-bonded array pairs 160, 162, 164, 166, and 168 completes multiple signal-carrying paths through the Doherty PA package 110-1, as indicated by arrows to pairs 170, 172, 174, 176, and 178. In this example, these paths include the first carrier signal amplification path (by... Figure 5 The arrows in the diagram represent the following paths: the first peak signal amplification path (represented by arrow 170), the second peak signal amplification path (represented by arrow 172), the first peak signal amplification path (represented by arrow 174), the second peak signal amplification path (represented by arrow 176), and the third peak signal amplification path (represented by arrow 178).

[0128] Carrier signal amplification paths 170 and 172 extend in parallel through the Doherty PA package 110-1. Carrier PA dies 150 and 152 are located in paths 170 and 172, respectively, to provide the above combination. Figure 1 and 2 The signal amplification function is discussed. Similarly, carrier amplification paths 170 and 172 extend parallel through the Doherty PA package 110-1, with peak PA dies 154, 156, and 158 located in paths 174, 176, and 178, respectively, to provide the required signal amplification function. Combined with... Figure 5 For a brief reference again Figure 2 During operation of the Doherty PA package 110-1, the wire bonding arrays 160 and 162 provide inductances corresponding to symbols 88-1, 90-1, 98-1, and 96-1. Therefore, the combination of lead pairs 128 and 130; wire bonding arrays 160 and 162; IPDs 140 and 142; and transistor dies 150 and 152 forms what is typically associated with carrier signal amplification path 70-1. Figure 2 Two examples of corresponding circuit structures. Similarly, wire bonding arrays 164, 166, and 168 provide circuits using symbols 88-2, 90-2, 98-2, and 96-2 ( Figure 2 The inductance is represented by ). Therefore, the combination of lead pairs 132, 134, 136; wire bonding arrays 164, 166, 168; IPDs 144, 146, 148; and transistor dies 154, 156, 158 forms an inductance with Figure 2 Three examples of circuit structures corresponding to the peak amplification path 70-2 in the diagram.

[0129] Figure 6 This shows a limited area of ​​the Doherty PA package 110-1, which corresponds to Figure 5 The details are in bubble frames 180 and include wire bonding arrays 160-1 and 160-2. See also: Figure 3-6 Selected wire bonds in the input-side wire bond array 160-1 are formed between the inner edge 182 (exposed along the bonding pad holder 124) of the carrier signal input lead 128-1 and the input-side IPD 140-1. Additional wire bonds are formed between IPD 140-1 and bonding pads provided along the front edge of the carrier PA die 150. Similarly, selected wire bonds in the output-side wire bond array 160-2 extend from the bonding pads provided on the carrier PA die 150 to the output-side IPD 140-2. Other wire bonds extend from the carrier PA die 150 to the inner edge 186 of the carrier signal output lead 128-2 exposed along the bonding pad holder 124 to complete the carrier signal amplification path 170. Figure 5Ultimately, some bonding pads (or possibly other bias circuitry) on the carrier PA die 150 shown can also be bonded to... Figure 3-5 The exposed inner edge 188 of the bias lead 126 is shown in the upper part. Similar wire bonds or electrical interconnects are also formed to appropriately complete other signal amplification paths 172, 174, 176, 178.

[0130] After the bonding wires are formed, a cap or cover 190 is attached to the upper peripheral edge of the peripheral wall 120 to surround the transistor dies 150, 152, 154, 156, 158; the wire bonding arrays 160, 162, 164, 166, 168; and other internal features of the Doherty PA package 110-1. The cap attachment can be performed under pressure, temperature, and atmospheric conditions and using bonding materials (e.g., sintering materials, epoxy resins, or chip attachment materials) suitable for trapping the desired pressure and atmosphere within the cavity package. The cap attachment completes the fabrication of the Doherty PA package 110-1 to produce… Figure 7 The final package is shown in the figure. The finished Doherty PA package 110-1 has an asymmetric, bidirectional, five-path circuit topology or configuration, which can improve gain, linearity, stability, and power-added efficiency levels; and / or other performance benefits. Furthermore, compared to conventional Doherty PA packages with fewer (e.g., variable width) leads (each dedicated to transmitting a specific signal type), embodiments of the Doherty PA package 110-1 reduce the likelihood of cross-coupling or crosstalk between signal paths, for example, by keeping the total combined current applied to the PA package 110-1 away from the power devices therein. These benefits can be enhanced when the Doherty PA package 110-1 is mounted to a substrate with corresponding forked or branched interconnect features (e.g., branched traces or transmission lines); and / or when used with finger-shaped isolation devices fitted over and around the PA package 110-1, as combined below. Figure 8 and 9 A more comprehensive discussion is needed.

[0131] Figure 8This is a plan view of an exemplary Doherty PA system 192, wherein an exemplary 10-lead Doherty PA package 110-1 is suitably deployed. The Doherty PA package 110-1 is soldered or otherwise mounted to the upper surface 194 of a PCB 196 or another substrate having certain electrical wiring features for electrical interconnection with the package leads. Specifically, a network of conductive interconnect features (here, a plurality of signal transmission lines 198, 200, 202, 204, 206, 208) is formed on the upper surface 194 of the PCB 196. When the Doherty PA package 110-1 is suitably positioned on the PCB 196, the transmission lines 198, 200, 202, 204 can be formed relatively close together and extend to lead pairs 128, 130, 132, 134, 136. Electrical isolation between adjacent transmission lines 198, 200 is maintained by a spacing or clearance 218 along the longitudinal axis of PA package 110-1. Transmission lines 206, 208 additionally contact bias lead 126, which extends from opposite ends of the Doherty PA package 110-1 when the PA package 110-1 is mounted to PCB 196. In other embodiments, bias lead 126 and transmission lines 206, 208 may be omitted.

[0132] exist Figure 8 In the example, transmission lines 198, 200, 202, and 204 are given finger-like, forked, or branching shape factors. Specifically, each transmission line 198, 200, 202, and 204 includes an elongated body 210 (only a limited portion of which is shown) that divides into multiple transmission line branches 212 and terminates at these branches (more commonly referred to as "interconnect branches 212"). The transmission line branches 212 are separated by isolation gaps or notches 214, which are distributed throughout the transmission line branches 212 and extend to the Doherty PA package 110-1 when mounted to the PCB 196. The width of the isolation gaps 214 can vary, as can the size and geometry of the transmission line branches 212; however, in one embodiment, the width of each isolation gap 214 can be smaller than the gap width of the package lead isolation gap 137 (W). G In other embodiments, the isolation notch 214 extends between leads 128-1, 128-2, 130-1, and 130-2, and its length may be substantially equal to the first IG lead pitch (S). IG_1 The width of the isolation gap 214 extending to leads 132-1, 132-2, 134-1, 134-2, 136-1, and 136-2 can be substantially equal to the second IG lead pitch (S). IG_2 And it is likely to be roughly equal to the first IG lead pitch (S). IG_1 ).

[0133] Assigning to transmission lines 198, 200, 202, and 204 Figure 8 The similar or identical branch geometries shown can provide certain benefits, such as improving the uniformity of current distribution and / or reducing internal coupling within the Doherty PA package 110-1 by moving the location where charge carriers and peak signals merge away from the location of the PA package 110-1 itself. In some instances (e.g., when at least some branch transmission lines contain three or more branches), this benefit can be enhanced by varying the corresponding width of some branches (e.g., outer transmission line branch 212) relative to one or more other branches (e.g., central or intermediate transmission line branch 212). (See reference...) Figure 8 This can be understood more fully by examining the branch transmission lines 202 and 204 that appear in the lower portion. The outer branch 212 of transmission line 204 is given increased thickness near leads 132-1, 132-2, 136-1, and 136-2; for example, the outer branch 212 may be patterned or otherwise produced to include a widened or “spread” area near leads 132-1, 132-2, 136-1, and 136-2 and opposite the isolation notch 214. Therefore, in the illustrated embodiment, the average width of the upper and lower transmission line branches 212 exceeds the average width of the intermediate branch 212 included in the branch transmission line 202 (located between the upper and lower branches 212). The average width of the upper and lower transmission line branches 212 also exceeds the average width of the intermediate transmission line branches 212 included in the branch transmission line 204 that contact the package leads 132-2, 134-2, and 136-2. When present, this variable width geometry of the branch transmission line group can help reduce the impedance toward the outer edges of the branch transmission lines 202, 204, in order to further improve the uniformity of current distribution during operation of the Doherty PA package 110-1.

[0134] Brief reference Figure 9In embodiments, the Doherty PA system 192 may be manufactured to additionally include finger-shaped shielding devices, clips, or overlapping structures 220. When present, the finger-shaped shielding structure 220 may include a shielding body 222 mounted above the Doherty PA package 110-1. The shielding body 222 may extend around the periphery of the Doherty PA package 110-1 and may have a lower cavity or recess in which the upper portion of the Doherty PA package 110-1 is accommodated or physically temporarily stored. In other instances, the shielding body 222 may rest on the upper surface of the Doherty PA package 110-1 and may be held in place by, for example, soldering or adhesive attachment. The finger shielding structure 220 further includes a plurality of isolation fingers 224 that extend from the opposing longitudinal edges of the shielding structure body 222 and downward (towards the upper surface 194 of the substrate 196) to extend between some adjacent leads (and thus physically separate or isolate them) (if not all adjacent leads are contained within the Doherty PA package 110-1). In other words, when the finger shielding structure 220 is mounted on the Doherty PA package 110-1, the isolation fingers 224 can be physically distributed among the package leads to further reduce cross-coupling between adjacent signal paths. To provide this functionality, in embodiments, the finger shielding structure 220, particularly the isolation fingers 224, can be wholly or partially constructed of a conductive material (e.g., a Cu-based alloy) and electrically grounded. Additionally, selected portions of the isolation fingers 224, or more generally, the finger shielding structure 220, can be combined with the above. Figure 2 The type of magnetically conductive material described is used to construct or cover the material.

[0135] Despite the advantages described above, in another embodiment, the Doherty PA package 110-1 can be used in conjunction with a substrate containing non-branched interconnect features or transmission lines. In this regard, consider... Figure 10 The Doherty PA system 226 is shown in the figure. As before, the Doherty PA system 226 includes a PCB or other substrate 228 on which multiple interconnect features (signal transmission lines 206, 208, 232, 234, 236, 238) are formed on the upper surface or front side 230. The Doherty PA package 110-1 is soldered or otherwise mounted to the upper surface 230 of the substrate 238 such that the carrier input leads 128-1, 130-1 contact the bonding pad region 212 of the upper left transmission line 232, which has a non-branched, continuous, or block shape factor wrapped around the aforementioned isolation notch. Therefore, the bonding pad region 212 simultaneously contacts the carrier input leads 128-1, 130-1 and crosses the gap or spacing of the spaced package leads 128-1, 130-1 along the longitudinal axis of the Doherty PA package 110-1.

[0136] Similar to the bonding pad region 212 of carrier input leads 128-1, 130-1 and upper left transmission line 232, carrier output leads 128-2, 130-2 contact the upper right transmission line 212 (leaving transmission line 206), which also has a bonding pad region 214 that is neither branched nor integral in shape. Therefore, the bonding pad region 214 contacts leads 128-1, 130-1 while also spanning the gap between them. Finally, lower transmission lines 246, 248 contact carrier input leads 132-1, 134-1, 136-1 and carrier output leads 132-2, 134-2, 136-2, respectively. Furthermore, in this example, the lower transmission lines 246, 248 are given a continuous, non-branching, or non-forking geometry, such that the continuous bonding pad regions 246, 248 are provided for electrical contact with the corresponding package leads of the Doherty PA package 110-1. In addition to contacting the appropriate package leads, the bonding pad regions 246, 248 also span the gaps separating the input-side lead groups 132-1, 134-1, 136-1 and the output-side lead groups 132-2, 134-2, 136-2. If desired, the bonding pad regions 246, 248 may be given open or widened corner regions 250 near the lead pairs 132, 136 to improve current distribution uniformity in the aforementioned manner.

[0137] Therefore, the exemplary Doherty PA package 110-1 and the Doherty PA system in which the Doherty PA package 110-1 can be deployed have been described in detail above. As discussed above, the Doherty PA package 110-1 is manufactured to include redundant peak and carrier signal amplification paths, while providing an asymmetric allocation of die-bonded regions that is beneficial to one or more peak transistors to enhance performance characteristics. Furthermore, when integrated into a larger Doherty PA system (e.g., in combination with the above), Figure 8 and 9 As described above, the Doherty PA package 110-1 is compatible with branch transmission line (interconnect) connection schemes and finger isolation structures. As another advantage, the Doherty PA package 110-1 (and more precisely, the flexible PA package platform 110 on which the Doherty PA package 110-1 is built) offers a design flexibility. Figure 3This provides designers with more opportunities to produce various variations of the Doherty PA package 110-1 optimized for specific applications or uses. For example, the package platform 110 can be used to produce Doherty PA packages to include different combinations of carrier and peak signal amplification paths, to provide asymmetric or symmetrical die-bonded region allocations that benefit one or more peak transistors, to support N-axis Doherty circuit layouts (N > 2), and / or to provide enhanced isolation between carrier and peak paths extending through the PA package. This point will now be emphasized in conjunction with... Figure 11-13 The description may utilize the PA packaging platform 110 ( Figure 3 Several alternative examples of Doherty PA packages manufactured by [the company / organization].

[0138] refer to Figure 11 This presents a PA packaging platform 110 with a second configuration and flexible design. Figure 3 The Doherty PA package 110-2 is manufactured appropriately. This is shown in the accompanying drawings and discussed further below. Figure 12-13 In this drawing, where appropriate, similar reference numerals from previous figures have been retained to indicate similar elements, while line bonding is concealed in the views to avoid obscuring details of the figures. As indicated by arrows 256, 258, 260, 262, two parallel carrier signal amplification paths 256, 258; and two parallel peak signal amplification paths 260, 262 are provided via the flexible PA package 110-2. Furthermore, as indicated by symbol 264, one or both of the leads 132-1, 132-2 located between the carrier signal amplification paths 256, 258 and the peak signal amplification paths 260, 262 serve as isolation leads, which can be mounted in the Doherty PA package 110-2 in a larger Doherty PA system (e.g., Figure 8 and 9 In the Doherty PA system 192 shown, the circuit is electrically coupled to ground (or another reference voltage). Therefore, in this embodiment, the Doherty PA package 110-2 can be described as having a symmetrical, bidirectional, four-path Doherty configuration, wherein the total die bonding area allocated to one or more carrier PA dies 150, 152 is substantially equal to the total die bonding area allocated to one or more peak PA dies 156, 158.

[0139] In some instances, it may be desirable to provide additional signal isolation or shielding between the carrier signal amplification path 258 and the adjacent peak signal amplification path 260, rather than simply grounding the intermediate isolation leads 132-1, 132-2 and / or by keeping the die bonding area between the isolation leads 132-1, 132-2 unoccupied by the device. In such instances, at least one internal package isolation structure 266 may be located within the package body 112 at a position between the carrier PA transistor die 152 and the peak PA transistor die 156 along the longitudinal axis 114. Furthermore, the isolation structure 266 may be laterally aligned with the lead pair 132 and may be electrically coupled to one or both of the isolation leads 132-1, 132-2. In various embodiments, the internal package isolation structure 266 may take the form of a ground plane or a conductive wall electrically coupled between and / or through one or both of the isolation leads 132-1, 132-2 to ground. In other embodiments, the encapsulated internal isolation structure 266 may comprise one or more layers of magnetically conductive material and may have a combination with the above. Figure 2 The isolation features 108-1 and 108-2 have similar structures. Then, Figure 11 The general illustration of isolation feature 266 in the diagram covers various types of conductive and magnetic isolation structures (including those with...). Figure 2 (Structures similar to or the same as those shown in the diagram) are suitable for reducing cross-coupling between the carrier signal path corresponding to arrow 258 and the adjacent peak signal path corresponding to arrow 260.

[0140] Go to Figure 12This paper presents a Doherty PA package 110-3, which is also appropriately manufactured using the flexible PA package platform 110 and has a third Doherty circuit configuration or layout. In this example, the Doherty PA package 110-3 is given an asymmetric, bidirectional, three-path Doherty configuration or circuit topology. In this configuration, the Doherty PA package 110-3 includes a single signal carrier signal amplification path, as indicated by arrow 268. The Doherty PA package 110-3 also includes two parallel peak carrier signal amplification paths, as indicated by arrows 270 and 272. Here, the intervening leads 130-1, 130-2, 132-1, and 132-2 located between signal paths 268 and 270 can be used as isolation leads, and some or all of these leads 130-1, 130-2, 132-1, and 132-2 are coupled to electrical ground, as indicated by symbol 274. Again, the Doherty PA package 110-3 may include one or more isolation structures 276, 278, which may have the structure and composition as previously described. When present, isolation structure 276 may be laterally aligned with leads 130-1, 130-2 and may be electrically coupled to ground via one or both leads 130-1, 130-2. Similarly, isolation structure 238 may be laterally aligned with leads 132-1, 132-2 and may be electrically coupled to ground via one or both leads 132-1, 132-2. In other instances, one or both of isolation structures 276, 278 may be omitted from the Doherty PA package 110-3.

[0141] Figure 13 A Doherty PA package 110-4 with another example row configuration is shown; namely, a three-way, three-path, symmetrical Doherty configuration. In this example, the Doherty PA package 110-4 includes a carrier signal amplification path (indicated by arrow 280), a first type or level peak signal amplification path (indicated by arrow 282), and a second type or level peak signal amplification path (indicated by arrow 284). Again, the package lead located between the carrier signal amplification path 280 and the peak signal amplification path 282 can be coupled to an electrical ground (symbol 286) and / or electrically coupled to a first isolation feature 288 within the Doherty PA package 110-4 to provide additional isolation between signal paths 280, 282. In this example, and for all other isolation features described herein, isolation feature 288 can be a conductive wall or ground plane; and / or can contain a conductor having a wall-like shape factor, to which one or more magnetic layers can be bonded, as described above. Figure 2Similarly, the leads located between peak signal amplification paths 282 and 284 can be coupled to an electrical ground (symbol 286) and / or electrically coupled to a second isolation feature 290 (e.g., ground plane or multilayer wall) within the Doherty PA package 110-4 to provide additional isolation between signal paths 280 and 282 as needed. Connecting the Doherty PA package 110-4 with... Figure 2 A brief comparison of the circuit structures shown in the figure shows that carrier signal amplification path 280 typically corresponds to path 70-1, isolation feature 288 typically corresponds to feature 106-1, peak signal amplification path 282 typically corresponds to path 70-2, isolation feature 290 typically corresponds to feature 106-2, and peak signal amplification path 284 typically corresponds to path 70-3.

[0142] therefore, Figure 11-13 The Doherty PA packages 110-2, 110-3, and 110-4 shown in the diagram collectively provide the utilization of Figure 3 The basic packaging platform 110 shown is another example of a Doherty circuit configuration suitably manufactured. Despite the above-described flexible PA packaging platform 110 ( Figure 3 The Doherty PA packages 110-1, 110-2, 110-3, and 110-4 share specific form factors, lead counts, and common constructions in this example. However, it should be emphasized that other embodiments of the package platform and PA package can be manufactured to have various other form factors, lead counts, and physical constructions as needed. For example, in another embodiment, the Doherty PA package can be manufactured according to this teaching, including six leads divided into a three-lead input-side array and a three-lead output-side array; eight leads divided into a four-lead input-side array and a four-lead output-side array; twelve leads divided into a six-lead input-side array and a six-lead output-side array; and so on. (The following is in conjunction with...) Figure 14 and 15 Provide an alternative description of this aspect.

[0143] Next, let's talk about... Figure 14The diagram illustrates a 10-lead Doherty PA package 292 manufactured according to a three-dimensional, asymmetric configuration. Specifically, the 10-lead Doherty package 292 shown includes: (i) two parallel peak signal amplification paths of a first type (indicated by arrow 294), (ii) a single carrier signal amplification path (indicated by arrow 296), and (iii) two parallel peak signal amplification paths of a second type (indicated by arrow 298). The carrier signal amplification path 296 extends from the carrier input lead 300-1 through the carrier PA die 302 and reaches the carrier output lead 300-2. As previously mentioned, input and output side IPDs 304-1, 304-2 may also be provided in the carrier signal amplification path 296. Parallel peak input paths 294 can each extend from peak input lead 306-1 through peak PA die 308 and reach peak output lead 308-1; possibly also through input-side IPD 312-1 and output-side IPD 312-2, as shown. Similarly, parallel peak input paths 298 can each extend from peak input lead 314-1 through peak PA die 316 and reach peak output lead 318-1; when present, possibly also through input-side IPD 320-1 and output-side IPD 320-2.

[0144] With the aforementioned circuit layout of the Doherty PA package 292, the carrier signal amplification path 296 is located between the parallel peak signal amplification path 294 and the peak signal amplification path 298. Furthermore, an extended isolation gap 322 is provided between the lead pair 132 through which the signal amplification path 296 passes and between adjacent lead pairs 130, 134 on either side of the lead pair 132. As previously discussed, the corresponding width of the isolation gap 322 can be greater than, for example, the lead-to-lead spacing or "intra-group (IG) lead spacing" within a small-pitch lead group along the longitudinal axis 114. Therefore, in at least some embodiments, the provision of the isolation gap 322 can reduce cross-coupling. In other embodiments, the isolation gap 300 can be omitted, such that the lead pairs 128, 130, 132, 134, 136 are equidistantly separated along the longitudinal axis 114 of the Doherty PA package 292.

[0145] Final Reference Figure 15The diagram depicts an exemplary 6-lead Doherty PA package 324. Here, the Doherty PA package 324 includes three input-side leads 326-1, 328-1, and 330-1 distributed in an input-side lead array and three output-side leads 326-2, 328-2, and 330-2 distributed in an output-side lead array. As indicated by arrows 332 and 334, two peak amplification signal paths extend through the body 336 of the Doherty PA package 324. Specifically, each peak signal amplification path 332 and 334 extends from input lead 326-1 or 328-1 through input-side IPD 338-1, through peak PA die 340, through output-side IPD 338-2, and reaches output lead 326-2 or 328-2. In contrast, the single carrier signal amplification path 336 extends from the input lead 330-1 through the input side IPD 342-1, through the carrier PA die 344, through the output side IPD 342-2, and reaches the output lead 330-2.

[0146] As before, an enlarged isolation gap 346 is provided between the upper lead groups 326-1, 328-1 and 326-2, 328-2 and the carrier lead pair 330. The isolation gap 346 is sized such that its width exceeds the lead-to-lead or IG lead spacing in the lead groups 326-1, 328-1 and 326-2, 328-2 along the longitudinal axis of the PA package 324. In another embodiment, the enlarged isolation gap 346 can be eliminated, such that the longitudinal spacing between the corresponding lead pairs 326, 328, 330 is substantially equal. Other configurations are also possible for the illustrated 6-lead Doherty PA package 324. For example, in another embodiment where the Doherty PA package 324 is given a bidirectional, symmetrical, dual-path architecture, the carrier signal amplification path can be formed through the upper lead pair 326, and the peak signal amplification path can be formed through the lower lead pair 330, while the middle lead pair 328 is electrically grounded (or at least not provides a signal amplification path through the middle lead pair 328). In this embodiment, isolation features may, but are not necessarily, included within the Doherty PA package 324 at a location laterally aligned with the middle lead pair 328 and electrically grounded through one or both of leads 328-1 and 328-2.

[0147] Summarize

[0148] Therefore, PA (power amplifier) ​​packages and PA systems incorporating such packages have been provided, incorporating flexible packaging platforms. The aforementioned structural features and construction enhance design flexibility, allowing for the fabrication of different PA circuit configurations using a general-purpose PA package platform. This enables reduced manufacturing costs, particularly when the PA package embodiment is well-suited for leadframe-based fabrication, while allowing for optimization of circuit configurations for specific applications or uses. Performance benefits can be achieved by producing a specific, flexible PA package to include additional peak and / or carrier signal amplification paths, to provide an asymmetric allocation of die-bonded regions favorable to one or more peak transistors, to support N-axis Doherty circuit layouts (N > 2), and / or to provide enhanced isolation between signal-carrying (e.g., peak and carrier) paths as needed. Furthermore, in contrast to asymmetric Doherty packages with leads of varying widths, PA package embodiments can be manufactured to include an asymmetric Doherty layout, disposed between arrays of uniformly wide leads separated along the input and output sides of the package. A uniform-width lead array can include multiple lead groups for forming peak signal amplification paths, and, depending on the total number of leads in the package, for forming carrier signal amplification paths. This can provide greater benefits in reducing internal cross-coupling by keeping the total combined current away from the power device, especially when the PA package is mounted on a substrate with corresponding branch transmission lines. Figure 8 ) and / or when used with finger-shaped isolation devices that are fitted together above and around the PA package ( Figure 10 ).

[0149] In an embodiment, the PA includes a package body having a longitudinal axis and a first set of input-side leads (e.g., Figure 3-5 And leads 132-1, 134-1, 136-1 in 7-10) and the first set of output side leads (e.g., Figure 3-5 And leads 132-2, 134-2, and 136-2 in 7-10). The first set of input-side leads extends from the first side of the package body and is spaced apart by an 1G lead spacing along the longitudinal axis. In contrast, the first set of output-side leads extends from the second side of the package body, is spaced apart by an 1G lead spacing, and is laterally aligned with the first set of input-side leads. First carrier input leads (e.g., Figure 3-5 and Figure 7-10 Lead 130-1 extends from the first side of the package body and is separated from the first set of input-side leads by an input gap isolation gap, the width of which exceeds the intra-group (IG) lead spacing along the longitudinal axis. Similarly, the first carrier output lead (e.g., Figure 3-5The lead 130-2 (as in 7-10) extends from the second side of the package body, separated from the first set of output-side leads by an output-side isolation gap (which may also have an isolation gap width), and is laterally aligned with the first carrier input lead. In some cases, the PA package may additionally include: (i) a second carrier input lead (e.g., ...) extending from the first side of the package body. Figure 3-5 (i) and leads 128-1 in 7-10), wherein the first carrier input lead is located between the second carrier input lead and the first set of input-side leads along the longitudinal axis; and (ii) a second carrier output lead extending from the second side of the package body and laterally aligned with the second carrier input lead (e.g., Figure 3-5 And lead 128-2 in 7-10), wherein the second carrier input lead is located between the second carrier output lead and the first set of output side leads along the longitudinal axis.

[0150] In other embodiments, the PA package may include a package body having a longitudinal axis, a plurality of carrier signal amplification paths through the package body, and a plurality of peak signal amplification paths provided by the package body. The plurality of carrier signal amplification paths may include: X number of carrier input leads, X number of carrier output leads, and at least one carrier PA die contained in the package body and electrically coupled between the carrier input leads and the carrier output leads. In contrast, the plurality of peak signal amplification paths may include Y number of peak input leads, Y number of peak output leads, and at least one peak PA die contained in the package body and electrically coupled between the peak input leads and the peak output leads. In some embodiments, the PA package may include two or more carrier signal amplification paths and an equal or greater number of peak signal amplification paths, such that 1 < X ≤ Y. In other embodiments, the PA package may include more peak signal amplification paths than carrier signal amplification paths, such that X < Y.

[0151] In another embodiment, a PA system includes a PA package and a substrate. The PA package sequentially includes: (i) a package body having a longitudinal axis; (ii) a first set of input-side leads extending from a first side of the package body and spaced apart by an 1G lead spacing along the longitudinal axis; (iii) a first set of output-side leads extending from a second side of the package body, spaced apart by the 1G lead spacing, and laterally aligned with the first set of input-side leads; (iv) a first carrier input lead extending from the first side of the package body and separated from the first set of input-side leads by an isolation gap along the longitudinal axis, the width of the isolation gap exceeding the 1G lead spacing; and (v) a first carrier output lead extending from the second side of the package body, separated from the first set of output-side leads by the isolation gap, and laterally aligned with the first carrier input leads. The substrate includes a top surface on which the PA package is mounted and interconnects (e.g., printed traces) formed on the top surface of the substrate and electrically coupled to the PA package. In some embodiments, the interconnect may include a first branch interconnect having a plurality of transmission line branches, wherein each lead in the input-side lead group contacts a different one of the plurality of transmission line branches. In this embodiment, the input-side lead group may include first, second, and third peak input leads; and simultaneously, the plurality of transmission line branches include a first transmission line branch contacting the first peak input lead and having a first average width; a second transmission line branch contacting the second peak input lead and having a second average width less than the first average width; and a third transmission line branch contacting the first peak input lead and having a third average width greater than the second average width; wherein the second transmission line branch is located between the first and second transmission line branches along the longitudinal axis.

[0152] Although at least one exemplary embodiment has been presented in the foregoing detailed descriptions, it should be understood that numerous variations exist. It should also be understood that one or more exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed descriptions will provide those skilled in the art with a convenient roadmap for implementing exemplary embodiments of the invention. It should be understood that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments without departing from the scope of the invention as set forth in the appended claims. Numerical identifiers, such as “first,” “second,” “third,” etc., have been used above according to the order in which certain elements (e.g., package leads, lead groups, transistors, and transistor carrier dies) are introduced during the process of the foregoing detailed descriptions. Such numerical identifiers may also be used in subsequent claims to indicate the order of introduction in the claims. Therefore, such numerical identifiers may differ between the detailed descriptions and subsequent claims to reflect differences in the order of element introduction.

Claims

1. A power amplifier PA package (110), characterized in that, include: The encapsulation body (112) has a longitudinal axis (114). The first set of input-side leads (132-1, 134-1, 136-1) extends from the first side (115) of the package body (112) and is spaced apart by the in-group lead spacing along the longitudinal axis (114), the first set of input-side leads including the first peak input leads (132-1, 134-1). The first set of output-side leads (132-2, 134-2, 136-2) extends from the second side (117) of the package body (112), is separated by the lead spacing within the set, and is aligned with the first set of input-side leads (132-1, 134-1, 136-1) along a transverse axis perpendicular to the longitudinal axis. The first set of output-side leads includes a first peak output lead (132-2, 134-2), which is aligned with the first peak input lead (132-1, 134-1) along the transverse axis. The second set of input-side leads (128-1, 130-1) extends from the first side (115) of the package body (112), is separated by the lead spacing within the set, and includes the first carrier input leads (128-1, 130-1), wherein the second set of input-side leads (128-1, 130-1) is separated from the first set of input-side leads (132-1, 134-1, 136-1) by an input-side isolation gap (137-1), the input-side isolation gap (137-1) having an isolation gap width along the longitudinal axis (114) greater than the lead spacing within the set; The second set of output-side leads (128-2, 130-2) extends from the second side (117) of the package body (112), is separated by the lead spacing within the set, is aligned with the second set of input-side leads along a transverse axis perpendicular to the longitudinal axis, and includes a first carrier output lead (130-2), wherein the first carrier output lead (130-2) is aligned with the first carrier input lead (130-1) along a transverse axis perpendicular to the longitudinal axis, and the second set of output-side leads (128-2, 130-2) is separated from the first set of output-side leads (132-2, 134-2, 136-2) by an output-side isolation gap (137-2) having the width of the isolation gap; An input-side isolation lead (132-1) extends from the first side (115) of the package body (112); An output-side isolation lead (132-2) extends from the second side (117) of the package body (112) and is aligned with the input-side isolation lead along a transverse axis perpendicular to the longitudinal axis, wherein the input-side isolation lead (132-1) is one of the first group of input-side leads and the output-side isolation lead (132-2) is one of the first group of output-side leads, or the input-side isolation lead (130-1) is one of the second group of output-side leads and the output-side isolation lead (130-2) is one of the second group of output-side leads; A peak PA die (156) is contained in the package body (112) and electrically coupled between the first peak input lead (134-1) and the first peak output lead (134-2); A carrier PA die (152), which is contained within the package body (112) and electrically coupled between the first carrier input lead (130-1) and the first carrier output lead (130-2); and An isolation structure (266) is located between the peak PA die (156) and the carrier PA die (152) along the longitudinal axis (114) and is electrically coupled to at least one of the input-side isolation lead (132-1) and the output-side isolation lead (132-2).

2. The PA package (110) according to claim 1, characterized in that, The first group of input-side leads (132-1, 134-1, 136-1) includes multiple peak input leads extending from the first side (115) of the package body (112) and spaced apart by the lead spacing within the group; and The first set of output-side leads (132-2, 134-2, 136-2) includes multiple peak output leads that extend from the second side (117) of the package body (112), are spaced apart by the lead spacing within the set, and are aligned with the multiple peak input leads along a transverse axis perpendicular to the longitudinal axis.

3. The PA package (110) according to claim 2, characterized in that, The second set of input-side leads (128-1, 130-1) includes a second carrier input lead (128-1), and the first carrier input lead (130-1) is located between the second carrier input lead (128-1) and the first set of input-side leads (132-1, 134-1, 136-1) along the longitudinal axis (114); and The second set of output-side leads (128-1, 130-1) includes a second carrier output lead (128-2), which is aligned with the second carrier input lead (128-1) along a transverse axis perpendicular to the longitudinal axis. The first carrier output lead (130-2) is located between the second carrier output lead (128-2) and the first set of output-side leads (132-2, 134-2, 136-2) along the longitudinal axis (114).

4. The PA package (110) according to claim 1, characterized in that, The first group of input-side leads (132-1, 134-1, 136-1) consists of Y peak input leads; The first group of output-side leads (132-2, 134-2, 136-2) consists of Y peak output leads; The second group of input-side leads (128-1, 130-1) consists of X carrier input leads; The second group of output-side leads (128-2, 130-2) consists of X carrier output leads; and Where Y is greater than X.

5. The PA package (110) according to claim 1, characterized in that, Each of the first set of input-side leads (132-1, 134-1, 136-1), each of the first set of output-side leads (132-2, 134-2, 136-2), the first carrier input lead (130-1), and the first carrier output lead (130-2) have equal maximum lead widths along the longitudinal axis (114).

6. The PA package (110) according to claim 1, characterized in that, The width of the isolation gap (W) G The spacing between the leads in the group is at least 50% larger than the spacing between the leads in the group.

7. A power amplifier (PA) system (192), characterized in that, include: PA package (110) according to any of the preceding claims; as well as Substrate (196), comprising: The upper surface (194) on which the PA package (110) is mounted. and Transmission lines (198, 200, 202, 204) are formed on the upper surface of the substrate and electrically coupled to the first set of input-side leads (132-1, 134-1, 136-1), the first set of output-side leads (132-2, 134-2, 136-2), the first carrier input lead (130-1), and the first carrier output lead.

Images