Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a circuit layer, a first package, a first antenna, and an electronic component. The circuit layer has a first surface and a second surface opposite to the first surface. The first package is disposed on the first surface of the circuit layer. The first antenna penetrates the first package and is electrically connected to the circuit layer. The electronic component is disposed on the second surface of the circuit layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package and a method for manufacturing the same, and more specifically to a semiconductor device package including an antenna and a method for manufacturing the same. Background Technology

[0002] Wireless communication devices such as mobile phones typically include antennas for transmitting and receiving radio frequency (RF) signals. Comparatively, wireless communication devices comprise antennas and communication modules, each mounted on different parts of a circuit board. In comparable approaches, the antenna and communication module are manufactured separately and electrically connected after being placed on the circuit board. Therefore, the two components may incur separate manufacturing costs. Furthermore, it may be difficult to reduce the size of wireless communication devices to achieve a reasonably compact product design. To reduce costs and package size, antenna-in-package (AiP) technology has been developed. However, due to process limitations, it is difficult to integrate dipole antennas into AiP systems. Summary of the Invention

[0003] According to some embodiments of this disclosure, a semiconductor device package includes a circuit layer, a first package body, a first antenna, and electronic components. The circuit layer has a first surface and a second surface opposite to the first surface. The first package body is disposed on the first surface of the circuit layer. The first antenna penetrates the first package body and is electrically connected to the circuit layer. The electronic components are disposed on the second surface of the circuit layer.

[0004] According to some embodiments of this disclosure, a semiconductor device package includes a conductive layer, a first package body, and a first conductive element. The conductive layer has a first surface and a second surface opposite to the first surface. The conductive layer has a first antenna on the first surface of the conductive layer. The first package body is disposed on the first surface of the conductive layer. The first conductive element penetrates the first package body and is electrically connected to a portion of the conductive layer to define the second antenna.

[0005] According to some embodiments of this disclosure, a method of manufacturing an optical module includes: (a) providing a carrier; (b) forming a first conductive layer having a first antenna over the carrier; (c) forming a conductive element on the first conductive layer; and (d) forming a first package on the first conductive layer to cover the conductive element and expose the top end of the conductive element. The conductive element and a portion of the first conductive layer define a second antenna. Attached Figure Description

[0006] Figure 1 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0007] Figure 2 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0008] Figure 3 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0009] Figure 4 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0010] Figure 5 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0011] Figure 6A , Figure 6B and Figure 6C Semiconductor manufacturing methods according to some embodiments of the present disclosure are illustrated.

[0012] Figure 7A , Figure 7B , Figure 7C and Figure 7D Semiconductor manufacturing methods according to some embodiments of the present disclosure are illustrated.

[0013] Figure 8A , Figure 8B , Figure 8C and Figure 8D Semiconductor manufacturing methods according to some embodiments of the present disclosure are illustrated.

[0014] Throughout the accompanying drawings and detailed embodiments, the same reference numerals are used to indicate the same or similar parts. This disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0015] Figure 1 A cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure is shown. The semiconductor device package 1 includes a circuit layer 10, package bodies 11, 12, and 17, electronic components 13, and conductive layers 14, 15, 16, and 18.

[0016] Circuit layer 10 includes one or more interconnect layers (e.g., redistribution layers, RDLs) 10r and one or more dielectric layers 10d. A portion of the interconnect layer 10r is covered or encapsulated by the dielectric layer 10d, while another portion of the interconnect layer 10r is exposed from the dielectric layer 10d to provide electrical connections. Circuit layer 10 has a surface 101 and a surface 102 opposite to surface 101.

[0017] In some embodiments, dielectric layer 10d may comprise pre-impregnated composite fibers (e.g., prepreg), borosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), or any combination of two or more thereof. Examples of prepreg may include, but are not limited to, multilayer structures formed by stacking or laminating multiple prepreg materials / sheets. In some embodiments, according to the design specification, there may be any number of interconnect layers 10r. In some embodiments, interconnect layer 10r is formed or comprises gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), one or more other metals or one or more alloys, or two or more combinations thereof.

[0018] A conductive layer 14 is disposed on the surface 101 of the circuit layer 10 and electrically connected to the interconnect layer 10r exposed from the dielectric layer 10d via a connection layer 10h (e.g., solder). The conductive layer 14 includes the interconnect layer 14r and a passivation layer 14p that covers a portion of the interconnect layer 14r and exposes another portion of the interconnect layer 14r for electrical connection. In some embodiments, the passivation layer 14p comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide. The interconnect layer 14r is or comprises a conductive material such as a metal or a metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof. In some embodiments, an underfill 10u is disposed between the circuit layer 10 and the conductive layer 14 to cover the interconnect layer 10r exposed from the dielectric layer 10d, the interconnect layer 14r exposed from the passivation layer 14p, and the connection layer 10h.

[0019] A package 11 is disposed on a conductive layer 14. The package 11 has a surface 111 facing away from the conductive layer 14 and a surface 112 opposite to the surface 111. In some embodiments, the package 11 comprises an epoxy resin comprising fillers, molding compounds (e.g., epoxy resin molding compounds or other molding compounds), polyimide, phenolic compounds or materials, materials comprising silicone resin dispersed therein, or combinations thereof. One or more interconnect structures 11p (e.g., conductive pillars or conductive elements) penetrate the package 11 to be electrically connected to the interconnect layer 14r of the conductive layer 14. The interconnect structure 11p is or comprises a conductive material such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0020] A conductive layer 15 is disposed on the surface 111 of the package 11 and electrically connected to the interconnect structure 11p. The conductive layer 15 includes interconnect layers 15r1 and 15r2 and a passivation layer 15p. Interconnect layers 15r1 and 15r2 are disposed on the surface of the passivation layer 15p (which contacts the surface 111 of the package 11) and are covered by the package 11. In some embodiments, interconnect layer 15r1 is electrically connected to the interconnect structure 11p to define an antenna, such as a dipole antenna. In some embodiments, passivation layer 15p comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide. Interconnect layers 15r2 are or comprise conductive materials such as metals or metal alloys. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0021] Encapsulation 12 is disposed on conductive layer 15. Encapsulation 12 has a surface 121 facing away from conductive layer 15 and a surface 122 opposite to surface 121. In some embodiments, encapsulation 12 comprises epoxy resin, which includes filler, molding compound (e.g., epoxy resin molding compound or other molding compound), polyimide, phenolic compound or material, material comprising silicone resin dispersed therein, or a combination thereof.

[0022] In some embodiments, the thickness H1 of package 11 is greater than the thickness H2 of package 12. In some embodiments, the ratio of the thickness H1 of package 11 to the thickness H2 of package 12 is approximately 2:1. In some embodiments, the thickness H1 of package 11 is equal to or greater than 500 micrometers (μm).

[0023] A conductive layer 16 is disposed on the surface 121 of the package 12. The conductive layer 16 includes an interconnect layer 16r and a passivation layer 16p. The interconnect layer 16r is disposed on the surface of the passivation layer 16p (which contacts the surface 121 of the package 12) and is covered by the package 12. In some embodiments, the interconnect layer 16r defines an antenna, such as a patch antenna. For example, the interconnect layer 16r is coupled to an interconnect layer 15r2 for signal transmission therebetween. In some embodiments, the passivation layer 16p comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide. The interconnect layer 16r is or comprises a conductive material such as a metal or a metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0024] Electronic component 13 is disposed on surface 102 of circuit layer 10. Electronic component 13 may be an active electronic component such as an integrated circuit (IC) chip or die. In some embodiments, interconnect structure 10r (e.g., RDL) is directly connected to conductive terminals (e.g., copper pillars) on the active surface of the electronic component. In other embodiments, electronic component 13 may be electrically connected to the circuit layer (e.g., electrically connected to interconnect layer 10r) via flip-chip or wire bonding technology. In some embodiments, the back surface of electronic component 13 is bonded or attached to the passivation layer 18p of conductive layer 18 via an adhesive layer (e.g., die attachment film, DAF).

[0025] Package 17 is disposed on surface 102 of circuit layer 10 and covers electronic component 13. In some embodiments, package 17 comprises epoxy resin comprising filler, molding compound (e.g., epoxy resin molding compound or other molding compound), polyimide, phenolic compound or material, material comprising silicone resin dispersed therein, or combinations thereof. One or more interconnect structures 17p (e.g., conductive pillars or conductive elements) penetrate package 17 to be electrically connected to interconnect layer 10r of circuit layer 10. Interconnect structure 17p is or comprises a conductive material such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0026] A conductive layer 18 is disposed on the surface of the package 17 opposite to the circuit layer 10. The conductive layer 14 has an interconnect layer 18r electrically connected to the interconnect structure 17p and a passivation layer 18p covering a portion of the interconnect layer 18r. Another portion of the interconnect layer 18r is exposed from the passivation layer 18p for electrical connection. In some embodiments, electrical contacts 19 are disposed on the interconnect layer 18r exposed from the passivation layer 18p. In some embodiments, the passivation layer 18p comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide. The interconnect layer 18r is or comprises a conductive material such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0027] In AiP systems, the height of the dipole antenna is related to its performance. In some embodiments, a dipole antenna with a height equal to or greater than 500 μm can meet high-performance requirements. In some embodiments, a dipole antenna in an AiP system can be implemented by forming one or more conductive vias (i.e., through-glass vias, TGVs) penetrating a glass substrate. However, the manufacturing cost of forming TGVs is relatively high, and the thickness of the glass substrate is less than 300 μm. In other embodiments, a dipole antenna in an AiP system can be implemented by forming one or more conductive vias (i.e., through-silicon vias, TSVs) penetrating a silicon substrate. However, to form a TSV with the desired height, a multilayer substrate should be used, which will increase manufacturing costs and the overall thickness of the device package. Figure 1 In the embodiment shown, the interconnect structure 11p penetrates the package 11 (molded through-hole, TMV) to define a dipole antenna with a thickness equal to or greater than 500 μm, which can realize a high-performance dipole antenna.

[0028] Figure 2 A cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure is shown. The semiconductor device package 2 is similar to... Figure 1 The semiconductor device package 1 in the text, and one of the differences is that, in Figure 2 In this case, the package 12 is replaced by a glass substrate 22.

[0029] A glass substrate 22 is disposed on the conductive layer 15. The glass substrate 22 has a surface 221 facing away from the circuit layer 15 and a surface 222 opposite to the surface 221. In some embodiments, the thickness H1 of the package 11 is greater than the thickness H3 of the glass substrate 22. In some embodiments, the ratio of the thickness H1 of the package 11 to the thickness H3 of the glass substrate is approximately 2:1.

[0030] Interconnect layer 22r is disposed on surface 221 of glass substrate 22. In some embodiments, interconnect layer 22r defines an antenna such as a patch antenna. Interconnect layer 22r is or contains a conductive material such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0031] A passivation layer 22p is disposed on the surface 221 of the glass substrate 22 to cover the interconnect layer 22r. In some embodiments, the passivation layer 22p comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide.

[0032] Figure 3 A cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure is shown. The semiconductor device package 3 is similar to... Figure 1 The semiconductor device package 1 is described below, and the differences therebetween are also described below.

[0033] Encapsulation 11 is disposed on surface 101 of circuit layer 10. In some embodiments, encapsulation 11 is in contact with circuit layer 10. Encapsulation 11 has a surface 111 facing away from conductive layer 10 and a surface 112 opposite to surface 111. In some embodiments, encapsulation 11 comprises epoxy resin, which includes filler, molding compound (e.g., epoxy resin molding compound or other molding compound), polyimide, phenolic compound or material, material comprising silicone resin dispersed therein, or a combination thereof.

[0034] One or more interconnect structures 11p (e.g., conductive pillars or conductive elements) penetrate the package 11 to be electrically connected to the interconnect layer 10r of the circuit layer 10. In some embodiments, the interconnect structure 11p is directly connected to the interconnect layer 10r of the circuit layer 10 and may be omitted. Figure 1 The interconnect layer 10h and the bottom filler 10u are shown in the diagram. The interconnect structure 11p is or contains a conductive material such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0035] A conductive layer 15 is disposed on the surface 111 of the package 11 and electrically connected to the interconnect structure 11p. The conductive layer 15 includes interconnect layers 15r1 and 15r2 and a passivation layer 15p. Interconnect layers 15r1 and 15r2 are disposed on the surface 111 of the package 11 and covered by the passivation layer 15p. In some embodiments, interconnect layer 15r1 is electrically connected to the interconnect structure 11p to define an antenna, such as a dipole antenna. In some embodiments, the passivation layer 15p comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide. Interconnect layers 15r2 are or comprise conductive materials such as metals or metal alloys. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0036] A conductive layer 16 is disposed on the surface 121 of the package 12. The conductive layer 16 includes an interconnect layer 16r and a passivation layer 16p. The interconnect layer 16r is disposed on the surface 121 of the package 12 and is covered by the passivation layer 16p. In some embodiments, the interconnect layer 16r defines an antenna, such as a patch antenna. For example, the interconnect layer 16r is coupled to an interconnect layer 15r2 for signal transmission therebetween. In some embodiments, the passivation layer 16p comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide. The interconnect layer 16r is or comprises a conductive material such as a metal or a metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0037] Figure 4 A cross-sectional view of a semiconductor device package 4 according to some embodiments of the present disclosure is shown. The semiconductor device package 4 is similar to... Figure 3In addition to the semiconductor device package 3, Figure 3 The encapsulation 11 in the middle can be implemented by using two encapsulations 41 and 42.

[0038] A package 41 is disposed on surface 101 of circuit layer 10. In some embodiments, package 41 comprises epoxy resin, which includes filler, molding compound (e.g., epoxy resin molding compound or other molding compound), polyimide, phenolic compound or material, material comprising silicone resin dispersed therein, or combinations thereof. One or more interconnect structures 41p (e.g., conductive pillars or conductive elements) penetrate package 41 to be electrically connected to interconnect layer 10r of circuit layer 10. Interconnect structure 41p is or comprises a conductive material such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0039] Encapsulation 42 is disposed on encapsulation 41. Encapsulation 42 is in contact with encapsulation 41. In some embodiments, encapsulation 42 comprises epoxy resin, which includes filler, molding compound (e.g., epoxy resin molding compound or other molding compound), polyimide, phenolic compound or material, material comprising silicone resin dispersed therein, or combinations thereof. One or more interconnect structures 42p (e.g., conductive pillars or conductive elements) penetrate encapsulation 42 to be electrically connected to interconnect structure 41p and interconnect layer 15r1. In some embodiments, interconnect layer 15r1, interconnect structure 41p and interconnect structure 42p are electrically connected to define an antenna such as a dipole antenna. Interconnect structure 42p is or comprises a conductive material such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0040] In some embodiments, the sum of the thicknesses of package 41 and package 42, H4, is greater than the thickness H2 of package 12. In some embodiments, the ratio of the sum of the thicknesses of package 41 and package 42, H4, to the thickness H2 of package 12 is approximately 2:1. In some embodiments, the sum of the thicknesses of package 41 and package 42, H4, is equal to or greater than 500 μm.

[0041] Figure 5 A cross-sectional view of a semiconductor device package 5 according to some embodiments of the present disclosure is shown. The semiconductor device package 5 is similar to... Figure 4 In the semiconductor device package 4, besides in Figure 5 The intermediate package 41 is separated from the package 42 by an air gap 41g.

[0042] Interconnect structure 41p is electrically connected to interconnect structure 42p via connection layer 41h (e.g., solder). In some embodiments, interconnect layer 15r1, interconnect structures 41p, 42p and connection layer 41h are electrically connected to define an antenna such as a dipole antenna.

[0043] In some embodiments, the distance H5 between the surface 421 of the package 42 and the surface 412 of the package 41 is greater than the thickness H2 of the package 12. In some embodiments, the ratio of distance H5 to the thickness H2 of the package 12 is approximately 2:1. In some embodiments, distance H5 is equal to or greater than 500 μm.

[0044] Figure 6A , Figure 6B and Figure 6C Semiconductor manufacturing methods according to some embodiments of the present disclosure are illustrated.

[0045] Reference Figure 6A A carrier 69 is provided. In some embodiments, the carrier 69 is a glass carrier. An interconnect layer 68r is formed on the carrier 69, and then a passivation layer 68p is formed on the carrier 69. The passivation layer 68p covers a portion of the interconnect layer 68r and exposes another portion of the interconnect layer 68r for electrical connection.

[0046] refer to Figure 6B One or more interconnect structures 67p (e.g., conductive pillars) are formed on the interconnect layer 68r, and the one or more interconnect structures are electrically connected to a portion of the interconnect layer 68r exposed from the passivation layer 68p. An electronic component 63 is disposed on the passivation layer 68p. The back surface of the electronic component 63 is attached to the passivation layer 68p.

[0047] Still referencing Figure 6B A package 67 is formed on the passivation layer 68p or the package is disposed on the passivation layer, and the package encapsulates the electronic component 63 and the interconnect structure 67p. The package 67 can be formed or disposed by molding techniques such as transfer molding or compression molding. In some embodiments, a package 67 can be formed that completely covers the electronic component 63 and the interconnect structure 67p, and then a portion of the package 67 can be removed, for example, by grinding, to expose the top terminals of the interconnect structure 67p and the active surfaces of the electronic component 63.

[0048] Still referencing Figure 6B An interconnect layer 66r is formed on the package 67, and the interconnect layer is electrically connected to a portion of the interconnect structure 67p exposed from the passivation layer 68p and the active surface of the electronic component 63. A passivation layer 66p is formed on the package 67, and the passivation layer covers a portion of the interconnect layer 66r and exposes another portion of the interconnect layer 66r for electrical connection.

[0049] refer to Figure 6C A circuit layer 60 is formed on the passivation layer 68p, and the circuit layer is electrically connected to a portion of the interconnect layer 68r exposed from the passivation layer 68p. The circuit layer 60 includes the interconnect layer 60r and a dielectric layer 60d covering a portion of the interconnect layer 60r. In some embodiments, any number of interconnect layers 60r may be present, according to the design specification. A connection layer 60h (e.g., solder or under-bump metallization, UBM) is formed on the interconnect layer 60r exposed from the dielectric layer 60d. The carrier 69 is then removed to expose the interconnect layer 68r and the passivation layer 68p.

[0050] Figure 7A , Figure 7B , Figure 7C and Figure 7D A semiconductor manufacturing method according to some embodiments of the present disclosure is illustrated. In some embodiments, a semiconductor manufacturing method may be used. Figure 7A , Figure 7B , Figure 7C and Figure 7D The method in the middle to manufacture Figure 1 Semiconductor device packaging 1.

[0051] Reference Figure 7A A carrier 79 is provided. In some embodiments, the carrier 79 is a glass carrier. A passivation layer 76p is formed on the carrier 79. An interconnect layer 76r is formed on the passivation layer 76p. In some embodiments, the interconnect layer 76r defines an antenna, such as a patch antenna. Then, a package 72 is formed on the passivation layer 76p or the package is disposed on the passivation layer and encapsulates the interconnect layer 76r. The package 72 can be formed or disposed by molding techniques such as transfer molding or compression molding.

[0052] refer to Figure 7B A passivation layer 75p is formed on the package 72. Interconnect layers 75r1 and 75r2 are formed on the passivation layer 75p. In some embodiments, an interconnect structure 71p (e.g., a conductive pillar) is formed on the interconnect layer 75r1 and electrically connected to the interconnect 75r1. Then, a package 71 is formed on the passivation layer 75p to cover the interconnect layers 75r1, 75r2, and the interconnect structure 71p. The package 71 is then thinned to expose the top portion of the interconnect structure 71p for electrical connection. In other embodiments, the package 71 is formed on the passivation layer 75p, forming a through-hole penetrating the package 71 to expose the interconnect layer 75r1, and then the interconnect structure 71p is formed within the through-hole.

[0053] Still referencing Figure 7B A passivation layer 74p is formed on the package 71. One or more openings 74h are formed through the passivation layer 74p to expose the top portion of the interconnect structure 71p exposed from the package 71.

[0054] refer to Figure 7C An interconnect layer 74r1 is formed within the opening 74h to electrically connect to the interconnect structure 71p, and an interconnect layer 74r2 is formed on the passivation layer 74p. Then, a connection layer 70h (e.g., solder or UBM) is formed on the interconnect layers 74r1 and 74r2.

[0055] refer to Figure 7D ,Will Figure 6C The device package shown is disposed on interconnect layers 74r1 and 74r2. In some embodiments, interconnect layer 70h is disposed on... Figure 6C The device package shown is attached to the interconnect layer 60h, and then the interconnect layer 70h is attached to the interconnect layer 60h after the reflow process. In some embodiments, the interconnect layer is attached using, for example, flip-chip technology. Figure 6C The device packaging in the middle is combined with Figure 7C Device packaging within. It can be... Figure 6C Device packaging and Figure 7C An underfill 70u is formed between the device packages to cover the interconnect layers 74r1, 74r2, 60r and the connection layers 60h, 70h. Then, the carrier 79 is removed from the passivation layer 76p to form a structure as shown. Figure 1 The semiconductor device package 1 is shown.

[0056] Figure 8A , Figure 8B , Figure 8C and Figure 8D A semiconductor manufacturing method according to some embodiments of the present disclosure is illustrated. In some embodiments, a semiconductor manufacturing method may be used. Figure 8A , Figure 8B , Figure 8C and Figure 8D The method in the middle to manufacture Figure 2 Semiconductor device packaging 2.

[0057] refer to Figure 8A A glass substrate 82 is provided. An interconnect layer 82r is formed on the glass substrate 82, and then a passivation layer 82p is formed on the glass substrate 82 to cover the interconnect layer 82r. In some embodiments, the interconnect layer 82r defines an antenna such as a patch antenna.

[0058] refer to Figure 8B A carrier 89 is provided. In some embodiments, the carrier 89 is a glass carrier. A passivation layer 82p is disposed on the carrier 89. In some embodiments, a portion of the glass substrate 82 is removed to reduce the thickness of the glass substrate 82. A passivation layer 85p is formed on the glass substrate 82, and then conductive layers 85r1 and 85r2 are formed on the passivation layer 85p.

[0059] In some embodiments, an interconnect structure 81p (e.g., a conductive pillar) is formed on the interconnect layer 85r1 and electrically connected to the interconnect 85r1. Then, a package 81 is formed on the passivation layer 85p to cover the interconnect layers 85r1, 85r2, and the interconnect structure 81p. The package 81 is then thinned to expose the top portion of the interconnect structure 81p for electrical connection. In other embodiments, the package 81 is formed on the passivation layer 85p, forming a through-hole penetrating the package 81 to expose the interconnect layer 85r1, and then the interconnect structure 81p is formed within the through-hole.

[0060] Still referencing Figure 8B A passivation layer 84p is formed on the package 81. One or more openings 84h are formed through the passivation layer 84p to expose the top portion of the interconnect structure 81p exposed from the package 81.

[0061] refer to Figure 8C An interconnect layer 84r1 is formed within the opening 84h to electrically connect to the interconnect structure 81p, and an interconnect layer 84r2 is formed on the passivation layer 84p. Then, a connection layer 80h (e.g., solder or UBM) is formed on the interconnect layers 84r1 and 84r2.

[0062] refer to Figure 8D ,Will Figure 6C The device shown is packaged on interconnect layers 84r1 and 84r2. In some embodiments, interconnect layer 80h is disposed on... Figure 6C The device package shown is attached to the interconnect layer 60h, and then the interconnect layer 80h is attached to the interconnect layer 60h after the reflow process. In some embodiments, the interconnect layer is attached using, for example, flip-chip technology. Figure 6C The device packaging in the middle is combined with Figure 8C Device packaging within. It can be... Figure 6C Device packaging and Figure 8C An underfill 80u is formed between the device packages to cover the interconnect layers 84r1, 84r2, 60r and the connection layers 60h, 80h. Then, the carrier 89 is removed from the passivation layer 82p to form a structure as shown in the image. Figure 2 The semiconductor device package shown is 2.

[0063] As used herein, the terms “substantially,” “substantial,” “approximately,” and “about” are used to indicate and explain small variations. For example, when used in conjunction with numerical values, these terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, the thickness of a film or layer “substantially consistent” can refer to a standard deviation less than or equal to ±10% of the average thickness of the film or layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces within a micrometer range placed along the same plane, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm. If the angle between two surfaces or components is, for example, 90° ± 10°, such as ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°, then the two surfaces or components can be considered "substantially perpendicular." When used in conjunction with an event or situation, the terms "substantially," "basically," "approximately," and "about" can refer to situations where the event or situation occurs precisely or is close to occurring.

[0064] As used herein, unless the context clearly indicates otherwise, the singular terms “an,” “a,” and “the” may include plural indicators. In the description of some embodiments, a component provided “on” or “above” another component may cover cases where the preceding component is directly on the following component (e.g., in physical contact with the following component) and cases where one or more intermediate components are located between the preceding and following components.

[0065] As used herein, the terms “conductive,” “electrically conductive,” and “electrical conductivity” refer to the ability to conduct electric current. Conductive materials generally refer to those materials that offer little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than approximately 10. 4 S / m, such as at least 10 5 S / m or at least 10 6Conductive materials with a conductivity of S / m. The conductivity of a material may sometimes vary with temperature. Unless otherwise stated, the conductivity of a material is measured at room temperature.

[0066] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It is understood that these range formats are for convenience and brevity and should be flexibly interpreted to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0067] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to variables such as those in the manufacturing process. Other embodiments of this disclosure may exist that are not specifically shown. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it is understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not limited by this disclosure.

Claims

1. A semiconductor device package comprising: A circuit layer having a first surface and a second surface opposite to the first surface; A first package is disposed on the first surface of the circuit layer, the first package having a first surface facing away from the circuit layer and a second surface facing the circuit layer. A first antenna penetrates the first package and is electrically connected to the circuit layer. The first antenna includes a first antenna radiation pattern and an interconnect structure to define a dipole antenna. A passivation layer is disposed on the first package to cover the first package and the first antenna; A second package is disposed on the passivation layer, the second package having a first surface facing away from the first package and a second surface facing the first package, the second package being separated from the first package via the passivation layer. A second antenna radiation pattern is positioned adjacent to the first surface of the second package, the second antenna radiation pattern defining a patch antenna; as well as Electronic components, which are mounted on the second surface of the circuit layer. The first and second packages contain epoxy resin, such that the first and second packages are configured to control the thickness ratio of the thickness of the first package to the thickness of the second package as penetrated by the first antenna.

2. The semiconductor device package of claim 1, wherein the first antenna radiation pattern of the first antenna is disposed on the first surface of the first package and the interconnection structure of the first antenna penetrates from the first surface of the first package to the second surface of the first package to achieve high performance of the dipole antenna with a thickness equal to or greater than 500 μm.

3. The semiconductor device package of claim 2, wherein the first antenna radiation pattern is arranged adjacent to the first surface of the first package, and wherein the epoxy resin of the first package and the second package comprises filler and molding compound.

4. The semiconductor device package according to claim 1, wherein the thickness ratio of the first package body through which the first antenna penetrates to the thickness of the second package body is 2:

1.

5. The semiconductor device package according to claim 1, wherein the thickness of the first package is greater than the thickness of the second package, and the thickness of the first package is equal to or greater than 500 μm.

6. The semiconductor device package of claim 1, further comprising: A third package, disposed between the first package and the second package, wherein the third package is in direct contact with the first package; and A second antenna penetrates the third package and is electrically connected to the first antenna, the second antenna being positioned between the first antenna and the radiation pattern of the second antenna.

7. The semiconductor device package of claim 6, further comprising: A fourth package is disposed on the second surface of the circuit layer and covers the electronic component; as well as An interconnect structure that penetrates the fourth package and is electrically connected to the circuit layer.

8. The semiconductor device package of claim 6, wherein the sum of the thickness of the first package and the thickness of the third package is greater than the thickness of the second package.

9. The semiconductor device package of claim 1, further comprising: A third package, disposed between the first package and the second package; and The second antenna includes a third antenna radiation pattern and interconnect structure disposed on the upper surface of the third package. The interconnect structure of the second antenna penetrates the third package and is electrically connected to the interconnect structure of the first antenna via solder. The interconnect structure of the first antenna, the solder, the interconnect structure of the second antenna, and the third antenna radiation pattern are electrically connected to further define the dipole antenna. The third package is spaced apart from the first package by an air gap, which is defined by the first package, the third package, the first antenna, the second antenna, and the solder. The interconnect structure of the first antenna, the solder, and the interconnect structure of the second antenna penetrate from the upper surface of the third package to the second surface of the first package to achieve high performance of the dipole antenna with a thickness equal to or greater than 500 μm.

10. The semiconductor device package of claim 1, wherein the circuit layer further comprises a dielectric layer and an interconnect layer, the interconnect layer being disposed within the dielectric layer and electrically connected to the first antenna.

11. The semiconductor device package of claim 1, further comprising: A third package is disposed on the second surface of the circuit layer and covers the electronic component; as well as An interconnect structure that penetrates the third package and is electrically connected to the circuit layer.

12. A semiconductor device package comprising: A circuit layer having a first surface and a second surface opposite to the first surface; A first package is disposed on the first surface of the circuit layer, the first package having a first surface facing away from the circuit layer and a second surface facing the circuit layer. A first antenna penetrates the first package and is electrically connected to the circuit layer. The first antenna includes a first antenna radiation pattern and an interconnect structure to define a dipole antenna. A passivation layer is disposed on the first package to cover the first package and the first antenna. A glass substrate disposed on the first package, the glass substrate having a first surface facing away from the first package and a second surface facing the first package; The antenna radiation pattern is positioned adjacent to the first surface of the glass substrate; as well as Electronic components, which are mounted on the second surface of the circuit layer. The first package contains epoxy resin, such that the first package is configured to control the thickness ratio of the thickness of the first package penetrating through the first antenna to the thickness of the glass substrate.

13. The semiconductor device package of claim 12, wherein the thickness of the first package is greater than the thickness of the glass substrate.

14. A semiconductor device package comprising: A conductive layer having a first surface and a second surface opposite to the first surface, the conductive layer having a first antenna on the first surface of the conductive layer and a passivation layer adjacent to the second surface of the conductive layer; A first package is disposed on the first surface of the conductive layer; as well as A first conductive element penetrates the first package and is electrically connected to a portion of the conductive layer to define a second antenna, the first antenna and the second antenna defining a dipole antenna; A second package is disposed on the second surface of the conductive layer, and the second package is separated from the first package via the passivation layer; as well as A third antenna, positioned adjacent to the surface of the second package facing away from the conductive layer, defines a patch antenna. The first and second packages contain epoxy resin, such that the first and second packages are configured to control the thickness ratio of the thickness of the first package penetrating the first conductive element to the thickness of the second package.

15. The semiconductor device package of claim 14, wherein the epoxy resin of the first package and the second package comprises filler and molding compound.

16. The semiconductor device package of claim 14, further comprising a circuit layer disposed on a surface of the first package opposite to the conductive layer, wherein the circuit layer has an interconnect structure electrically connected to the first conductive element, and wherein the second antenna penetrates from the upper surface of the first package to the lower surface of the first package to achieve high performance of the dipole antenna with a thickness equal to or greater than 500 μm.

17. The semiconductor device package of claim 14, further comprising: A third package is disposed on the surface of the first package that is opposite to the conductive layer. as well as A second conductive element penetrates the third package and is electrically connected via solder to the first conductive element to define the second antenna. The thickness ratio of the thickness of the first package penetrating through the first conductive element to the thickness of the third package penetrating through the second conductive element and the thickness of the second package is 2:

1.

18. The semiconductor device package of claim 17, wherein the third package body is in contact with the first package body.

19. The semiconductor device package of claim 17, wherein the third package is spaced apart from the first package by an air gap, the air gap being defined by the first package, the third package, the first antenna, the second antenna, and the solder.

20. A semiconductor device package comprising: A conductive layer having a first surface and a second surface opposite to the first surface, the conductive layer having a first antenna on the first surface of the conductive layer and a passivation layer adjacent to the second surface of the conductive layer; A first package is disposed on the first surface of the conductive layer; as well as A first conductive element penetrates the first package and is electrically connected to a portion of the conductive layer to define a second antenna, the first antenna and the second antenna defining a dipole antenna; A glass substrate disposed on the second surface of the conductive layer, the glass substrate being separated from the first package via the passivation layer; as well as A third antenna is disposed on the surface of the glass substrate opposite to the conductive layer, the third antenna defining a patch antenna. The first package contains epoxy resin, such that the first package is configured to control the thickness ratio of the thickness of the first package penetrating through the first antenna to the thickness of the glass substrate.

21. A method for manufacturing an antenna communication module, the method comprising: (a) Provide a carrier; (b) A first conductive layer having a first antenna is formed above the carrier; (c) Forming a first encapsulation on the first conductive layer to cover the first conductive layer; (d) Forming a passivation layer on the first package; (e) An interconnect layer and conductive elements are formed on the passivation layer; as well as (f) A second package is formed on the passivation layer to cover the interconnect layer and the conductive element and expose the top end of the conductive element, the conductive element penetrating the second package, the second package being separated from the first package via the passivation layer. The first conductive layer defines a patch antenna, and the conductive element and the interconnect layer define a dipole antenna. The first and second packages contain epoxy resin, such that the first and second packages are configured to control the thickness ratio of the thickness of the first package to the thickness of the second package penetrating the conductive element.

22. The method of claim 21, wherein the conductive element penetrates from the lower surface of the second package to the upper surface of the second package to achieve high performance of the dipole antenna with a thickness equal to or greater than 500 μm.

23. The method of claim 21, further comprising placing a circuit layer on the first package and electrically connecting the circuit layer to the top end of the conductive element, wherein the epoxy resin of the first package and the second package comprises filler and molding compound.

24. The method of claim 23, wherein the circuit layer has electronic components disposed on a surface of the circuit layer opposite to the first package, and wherein the thickness ratio of the second package through which the conductive element penetrates to the thickness of the first package is 2:1.

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