High Electron Mobility Transistor

Abstract

The present invention discloses a high electron mobility transistor. The method for manufacturing the high electron mobility transistor is as follows: first, a buffer layer is formed on a substrate, then a first barrier layer is formed on the buffer layer, a patterned mask is formed on the first barrier layer, a second barrier layer is formed on both sides of the patterned mask, the patterned mask is removed to form a groove, a gate electrode is formed in the groove, and then a source electrode and a drain electrode are formed on both sides of the gate electrode.

Description

Technical Field

[0001] The invention relates to a high electron mobility transistor and a manufacturing method thereof. Background Art

[0002] High electron mobility transistors based on GaN-based materials have many advantages in electronic, mechanical and chemical properties, such as wide bandgap, high breakdown voltage, high electron mobility, large elastic modulus, high piezoelectric and piezoresistive coefficients, and chemical passivity. The above advantages make GaN-based materials useful for the manufacture of components for applications such as high-brightness light-emitting diodes, power switching components, regulators, battery protectors, panel display drivers, and communication components. Summary of the invention

[0003] An embodiment of the present invention discloses a method for manufacturing a high electron mobility transistor. First, a buffer layer is formed on a substrate, then a first barrier layer is formed on the buffer layer, a patterned mask is formed on the first barrier layer, a second barrier layer is formed on both sides of the patterned mask, the patterned mask is removed to form a groove, a gate electrode is formed in the groove, and then a source electrode and a drain electrode are formed on both sides of the gate electrode.

[0004] Another embodiment of the present invention discloses a high electron mobility transistor, which mainly includes a buffer layer arranged on a substrate, a first barrier layer arranged on the buffer layer, a gate electrode arranged on the first barrier layer, and a second barrier layer arranged on both sides of the gate electrode, wherein the first barrier layer and the second barrier layer contain different concentrations and a source electrode and a drain electrode are respectively arranged on the second barrier layer on both sides of the gate electrode.

[0005] Another embodiment of the present invention discloses a high electron mobility transistor, which mainly includes a buffer layer arranged on a substrate, a barrier layer arranged on the buffer layer, a gate dielectric layer arranged on the barrier layer, and a work function metal layer arranged on the gate dielectric layer, wherein the work function metal layer includes a P-type metal oxide layer, a gate electrode arranged on the work function metal layer, and a source electrode and a drain electrode are respectively arranged on both sides of the gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 4 A schematic diagram of a method for manufacturing a high electron mobility transistor according to an embodiment of the present invention;

[0007] Figure 5 A schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention;

[0008] Figures 6 to 9 A schematic diagram of a method for manufacturing a high electron mobility transistor according to an embodiment of the present invention;

[0009] Fig.10 FIG. 4 is a schematic structural diagram of a high electron mobility transistor according to an embodiment of the present invention.

[0010] Main component symbols

[0011] 12 substrate 14 buffer layer

[0012] 16 first barrier layer 18 patterned mask

[0013] 20 second barrier layer 22 gate electrode

[0014] 24 source electrode 26 drain electrode

[0015] 28 gate dielectric layer 30 U-shaped portion

[0016] 32 first horizontal portion 34 second horizontal portion

[0017] 42 substrate 44 buffer layer

[0018] 46 barrier layer 48 gate dielectric layer

[0019] 50 Work function metal layer 52 Gate electrode

[0020] 54 source electrode 56 drain electrode

[0021] 58 Channel Area DETAILED DESCRIPTION

[0022] Please refer to Figures 1 to 4 , Figures 1 to 4 FIG. 1 is a schematic diagram of a method for manufacturing a high electron mobility transistor for use in a radio frequency device according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, such as a substrate made of silicon, silicon carbide or aluminum oxide (or sapphire), wherein the substrate 12 can be a single-layer substrate, a multi-layer substrate, a gradient substrate or a combination thereof. According to other embodiments of the present invention, the substrate 12 can also include a silicon-on-insulator (SOI) substrate.

[0023] Then, a buffer layer 14 is formed on the surface of the substrate 12. In one embodiment, the buffer layer 14 includes a III-V semiconductor such as gallium nitride, and its thickness can be between 0.5 micrometers and 10 micrometers. In one embodiment, the buffer layer 14 can be formed on the substrate 12 by using a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof.

[0024] Next, a first barrier layer 16 is formed on the surface of the buffer layer 14. In this embodiment, the first barrier layer 16 preferably includes a III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), where 0 < x < 1, x is preferably less than or equal to 20%, and the first barrier layer 16 preferably includes an epitaxial layer formed by an epitaxial growth process. Similar to the way of forming the buffer layer 14 as described above, the first barrier layer 16 can be formed on the buffer layer 14 by using a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof.

[0025] As Figure 2 shown, subsequently, a patterned mask 18 is formed on the first barrier layer 16. In this embodiment, the patterned mask 18 can be formed by first depositing a dielectric material, such as silicon nitride, over the entire surface of the first barrier layer 16, and then using another patterned mask (not shown in the figure) as a mask to etch away a portion of the dielectric material to form the patterned mask 18 on the surface of the first barrier layer 16.

[0026] As Figure 3 shown, then, a second barrier layer 20 is formed on both sides of the patterned mask 18. In this embodiment, the first barrier layer 16 and the second barrier layer 20 preferably include the same material. For example, the second barrier layer 20 also preferably includes a III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-xN), where 0 < x < 1. It should be noted that the first barrier layer 16 and the second barrier layer 20 preferably include different aluminum concentrations or more specifically, the aluminum concentration of the first barrier layer 16 is preferably less than that of the second barrier layer 20. For example, compared with the aforementioned x of the first barrier layer 16 which is preferably less than or equal to 20%, if the second barrier layer 20 includes a III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), where 0 < x < 1, x is preferably greater than 20% and less than or equal to 40%.

[0027] In addition, the thickness of the first barrier layer 16 is preferably less than that of the second barrier layer 20. For example, the thickness of the first barrier layer 16 is preferably less than 10 nm or optimally about 6 nm, while the thickness of the second barrier layer 20 is preferably between 10 nm and 15 nm. Similar to the method of forming the first barrier layer 16 as described above, the second barrier layer 20 can be formed on both sides of the patterned mask 18 by using a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof.

[0028] Then, as Figure 4 shown, first remove the patterned mask 18 to form a groove (not shown in the figure) between the second barrier layers 20, and then form a gate electrode 22 in the groove and a source electrode 24 and a drain electrode 26 on both sides of the gate electrode 22. In this embodiment, the gate electrode 22, the source electrode 24, and the drain electrode 26 are all preferably composed of metal. Among them, the source electrode 24 and the drain electrode 26 preferably include the same material, but the source electrode 24 and the drain electrode 26 can include the same or different materials as the gate electrode 22. According to an embodiment of the present invention, the gate electrode 22, the source electrode 24, and the drain electrode 26 can each include gold, silver, platinum, titanium, aluminum, tungsten, palladium, or a combination thereof. In some embodiments, an electrode material can be formed in the groove and on the surface of the second barrier layer 20 by using an electroplating process, a sputtering process, a resistance heating evaporation process, an electron beam evaporation process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or a combination thereof, and then the electrode material can be patterned by etching to form the gate electrode 22, the source electrode 24, and the drain electrode 26.

[0029] It should be noted that, since the gate electrode 22 is formed in the groove and the source electrode 24 and the drain electrode 26 are respectively formed on the higher surfaces of the second barrier layer 20 on both sides, the upper surface of the gate electrode 22 is preferably slightly higher than the second barrier layer 20 on both sides but slightly lower than the top of the source electrode 24 and the drain electrode 26. In addition, whether the gate electrode 22 and the source electrode 24 and the drain electrode 26 on both sides are formed simultaneously or separately, the height of the gate electrode 22 itself can be selected to be equal to the height of the source electrode 24 and the drain electrode 26 on both sides, slightly higher than the height of the source electrode 24 and the drain electrode 26 on both sides, or slightly lower than the height of the source electrode 24 and the drain electrode 26 on both sides, and these variations are all within the scope of the present invention.

[0030] Please refer to Figure 5 , Figure 5 A schematic diagram of a high electron mobility transistor applied to a power device according to an embodiment of the present invention is disclosed. Figure 5 As shown, compared with the above embodiment Figure 4 After removing the patterned mask 18 and forming the groove, the gate electrode 22, the source electrode 24 and the drain electrode 26 are directly formed. The present invention can also choose to first form a gate dielectric layer 28 to cover the surface of the second barrier layer 20 and fill the groove but not fill the groove, and perform another photolithography and etching process to remove part of the gate dielectric layer 28 on both sides of the groove, and then form the gate electrode 22 on the gate dielectric layer 28 in the groove and the source electrode 24 and the drain electrode 26 on both sides of the gate electrode 22 according to the above-mentioned process. In this embodiment, the gate dielectric layer 28 is preferably disposed between the gate electrode 22 and the first barrier layer 16 and the second barrier layer 20, and the gate dielectric layer 28 includes a U-shaped cross-section. In detail, the gate dielectric layer 28 includes a U-shaped portion 30 disposed between the gate electrode 22 and the first barrier layer 16 and the second barrier layer 20, a first horizontal portion 32 disposed on one side of the U-shaped portion 30 and contacting the source electrode 24, and a second horizontal portion 34 disposed on the other side of the U-shaped portion 30 and contacting the drain electrode 26.

[0031] In this embodiment, the gate dielectric layer 28 may include silicon dioxide (SiO 2 ), silicon nitride (SiN) or a high dielectric constant (high-k) material, wherein the high dielectric constant dielectric layer preferably comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO 2 ), hafnium silicate oxide (hafnium silicon oxide, HfSiO 4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (tantalum oxide, Ta 2 O 5 ), yttrium oxide (yttrium oxide, Y 2 O 3 ), zirconium oxide (zirconium oxide, ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuthtantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 ,PZT), barium strontium titanate (Ba x Sr 1-x TiO 3 , BST), or a group consisting of their combinations.

[0032] Please refer to Figures 6 to 9 , Figures 6 to 9 FIG. 1 is a schematic diagram of a method for manufacturing a high electron mobility transistor according to an embodiment of the present invention. Figure 6 As shown, a substrate 42 is first provided, such as a substrate made of silicon, silicon carbide or aluminum oxide (or sapphire), wherein the substrate 42 can be a single-layer substrate, a multi-layer substrate, a gradient substrate or a combination thereof. According to other embodiments of the present invention, the substrate 42 can also include a silicon-on-insulator (SOI) substrate.

[0033] Then, a buffer layer 44 is formed on the surface of the substrate 42. In one embodiment, the buffer layer 44 includes a III-V semiconductor such as gallium nitride, and its thickness can be between 0.5 micrometers and 10 micrometers. In one embodiment, the buffer layer 44 can be formed on the substrate 42 by using a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof.

[0034] Next, a barrier layer 46 is formed on the surface of the buffer layer 44. In this embodiment, the barrier layer 46 preferably includes a III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), where 0 < x < 1, and the barrier layer 46 preferably includes an epitaxial layer formed by an epitaxial growth process. Similar to the way of forming the buffer layer 44 as described above, the barrier layer 46 can be formed on the buffer layer 44 by using a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof.

[0035] As Figure 7 shown, a gate dielectric layer 48 is then formed on the surface of the barrier layer 46. In this embodiment, the gate dielectric layer 48 can include silicon dioxide (SiO 2 ), silicon nitride (SiN), a high dielectric constant (high-k) material, or a combination thereof. Among them, the high dielectric constant dielectric layer preferably includes a dielectric material with a dielectric constant greater than 4, such as selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (tantalum oxide, Ta 2 O 5 ), yttrium oxide (yttriumoxide, Y 2 O 3 ), zirconium oxide (zirconium oxide, ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 ,SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), barium strontium titanate (Ba x Sr 1-x TiO 3 , BST), or a group consisting of their combinations.

[0036] like Figure 8 As shown, a work function metal layer 50 is then formed on the surface of the gate dielectric layer 48, wherein the work function metal layer 50 preferably comprises a P-type metal oxide layer. More specifically, the work function metal layer 50 preferably comprises magnesium zinc oxide (MgZnO), copper oxide (CuO), nickel oxide (NiO), chromium oxide (Cr 2 O 3 ), cobalt oxide (Co 3 O 4 ), manganese oxide (Mn 3 O 4 ) or a combination thereof. According to an embodiment of the present invention, the work function metal layer 50 can be used to reduce gate leakage current and control threshold voltage. In addition, since the work function metal layer 50 is preferably formed by low temperature growth in this embodiment, the problem of crystallization of the gate dielectric layer 48 below will not occur after the work function metal layer 50 is grown.

[0037] like Fig. 9As shown, a pattern transfer process is then performed, for example, a pattern mask may be used to remove part of the work function metal layer 50 and part of the gate dielectric layer 48 to expose the surface of the barrier layer 46 on both sides, and then a gate electrode 52 is formed on the work function metal layer 50, and a source electrode 54 and a drain electrode 56 are formed on both sides of the gate electrode 52. As in the above embodiment, the gate electrode 52, the source electrode 54 and the drain electrode 56 are preferably made of metal, wherein the source electrode 54 and the drain electrode 56 preferably include the same material, but the source electrode 54 and the drain electrode 56 may include the same or different materials as the gate electrode 52. According to one embodiment of the present invention, the gate electrode 52, the source electrode 54 and the drain electrode 56 may each include gold, silver, platinum, titanium, aluminum, tungsten, palladium or a combination thereof. In some embodiments, electrode materials may be formed on the surfaces of the work function metal layer 50 and the barrier layer 46 by electroplating, sputtering, resistance heating evaporation, electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof, and then the electrode materials are patterned by etching to form the gate electrode 52, the source electrode 54, and the drain electrode 56.

[0038] From a structural point of view, the upper surfaces of the source electrode 54 and the drain electrode 56 can be selected to be slightly lower than, aligned with, or slightly higher than the upper surface of the work function metal layer 50, but both are lower than the top of the gate electrode 52. The heights of the source electrode 54 and the drain electrode 56 can be selected to be aligned with, slightly lower than, or slightly higher than the height of the gate electrode 52. In addition, the width of the gate electrode 52 is preferably smaller than the width of the work function metal layer 50 and / or the gate dielectric layer 48. It should be noted that although the gate dielectric layer 48 of this embodiment is an example of a single-layer structure, it is not limited to this. According to an embodiment of the present invention, the gate dielectric layer 48 can also include a composite layer structure, for example, it can be more detailed to include a dielectric layer composed of silicon oxide disposed on the surface of the barrier layer 46 and a high dielectric constant dielectric layer disposed on the surface of the dielectric layer. In other words, the gate dielectric layer 48 composed of the dielectric layer and the high dielectric constant dielectric layer and the work function metal layer 50 form a sandwich structure disposed between the barrier layer 46 and the gate electrode 52. According to another embodiment of the present invention, if the gate dielectric layer 48 includes at least one high-k dielectric layer and / or a metal oxide layer, the metal oxide layer in the gate dielectric layer 48 preferably includes a different material from the metal oxide layer 50 thereon.

[0039] Please refer to Fig.10 , Fig.10 A schematic diagram of a high electron mobility transistor according to an embodiment of the present invention is disclosed. Fig.10 As shown, the present invention can also be combined with the aforementioned Figure 5 The structure and Figure 8 Another structure is obtained by forming a work function metal layer on the gate dielectric layer. Figure 5 After forming the gate dielectric layer 28, an additional Figure 8 The work function metal layer 50 is formed on the surface of the gate dielectric layer 28, and then another photolithography and etching process is performed to remove part of the work function metal layer 50 and part of the gate dielectric layer 28 on both sides of the groove, and then the gate electrode 22 is formed on the work function metal layer 50 in the groove according to the above-mentioned process, and the source electrode 24 and the drain electrode 26 are formed on both sides of the gate electrode 22. In this embodiment, the work function metal layer 50 and the aforementioned work function metal layer have the same material selection, and because the work function metal layer 50 and the gate dielectric layer 28 are patterned together, both have the same cross-sectional profile or shape, for example, each includes the aforementioned U-shaped portion and two horizontal portions respectively connecting the two sides of the U-shaped horizontal portion, which will not be further described here.

[0040] In addition, as Fig. 9 In the embodiment of the present invention, although the gate dielectric layer 28 of the present embodiment is a single-layer structure, it is not limited thereto. According to an embodiment of the present invention, the gate dielectric layer 28 may include a composite layer structure, for example, it may include a dielectric layer composed of silicon oxide disposed on the surface of the first barrier layer 16 and a high dielectric constant dielectric layer disposed on the surface of the dielectric layer. In other words, the gate dielectric layer 28 composed of the dielectric layer and the high dielectric constant dielectric layer and the work function metal layer 50 form a sandwich structure disposed between the first barrier layer 16 and the gate electrode 22. In addition, according to another embodiment of the present invention, if the gate dielectric layer 28 includes at least one high dielectric constant dielectric layer and / or a metal oxide layer, the metal oxide layer in the gate dielectric layer 28 preferably includes a different material from the metal oxide layer 50 above.

[0041] Generally speaking, as mentioned above Figure 4 , Figure 5 , Fig. 9 and Fig.10 As shown, due to the different band gaps of the materials of the buffer layer and the barrier layer, the interface between the buffer layer and the barrier layer preferably forms a heterojunction. The band at the heterojunction is bent, and a quantum well is formed deep in the conduction band bend, which confines the electrons generated by the piezoelectric effect in the quantum well, thereby forming a channel region 58 or a two-dimensional electron gas (2DEG) at the interface between the buffer layer and the barrier layer, thereby forming a conduction current.

[0042] Compared with the prior art, in which a portion of the barrier layer is removed by etching or even the channel region is formed into a groove and then a gate electrode is filled in to prepare an enhanced mode high electron mobility transistor, the present invention Figures 1 to 4 The embodiment mainly forms a patterned mask 18 on the first barrier layer 16 to define the position where the gate electrode is to be formed later, and then forms a second barrier layer 20 on both sides of the patterned mask 18, removes the patterned mask 18 to form a groove, and then forms the gate electrode 22, the source electrode 24 and the drain electrode 26. In this way, the problem that the barrier layer is easily damaged under the gate electrode and affects the threshold voltage when removing the barrier layer by etching can be improved.

[0043] In addition to adjusting the thickness of the first barrier layer 16 and the second barrier layer 20 directly below and on both sides of the gate electrode 22, the present invention also reduces the aluminum concentration in the second barrier layer 20 on both sides of the gate electrode 22, thereby converting the high electron mobility transistor from a normally on operation mode to a normally off operation mode. More specifically, the present invention mainly reduces the thickness of the first barrier layer 16 directly below the gate electrode 22 but increases the thickness of the second barrier layer 20 on both sides of the gate electrode 22, for example, the thickness of the first barrier layer 16 directly below the gate electrode 22 is controlled to be less than 10 nanometers and the thickness of the second barrier layer 20 is preferably between 10 nanometers and 15 nanometers, and at the same time controls the aluminum concentration in the first barrier layer 16 to be less than the aluminum concentration in the second barrier layer 20, thereby reducing the two micro electron gases directly below the gate electrode 22 to achieve a normally off operation mode.

[0044] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A high electron mobility transistor (HEMT), characterized in that: Include: A buffer layer is disposed on the substrate; a barrier layer disposed on the buffer layer; A gate dielectric layer is disposed on the barrier layer; A work function metal layer is disposed on the gate dielectric layer, wherein the work function metal layer comprises a P-type metal oxide layer, wherein the P-type metal oxide layer comprises a U-shaped portion and two horizontal portions respectively connecting two sides of the U-shaped portion; A gate electrode is disposed on the work function metal layer, wherein the gate electrode does not cover the two horizontal portions of the P-type metal oxide layer; and The source electrode and the drain electrode are respectively arranged on both sides of the gate electrode, wherein the source electrode contacts the gate dielectric layer and the side wall of the work function metal layer. 2 . The high electron mobility transistor of claim 1 , wherein the buffer layer comprises a Group III-V semiconductor. 3 . The high electron mobility transistor of claim 1 , wherein the buffer layer comprises gallium nitride.

4. The high electron mobility transistor of claim 1, wherein the barrier layer comprises aluminum gallium nitride (Al x Ga 1-x N).

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