Integrated circuit device and method for manufacturing the same

Abstract

The present disclosure relates to integrated circuit devices and methods for manufacturing the same. A method includes: forming a gate dielectric, the gate dielectric including a first portion extending over a first semiconductor region; forming a barrier layer, the barrier layer including a first portion extending over the first portion of the gate dielectric; forming a first work function adjustment layer, the first work function adjustment layer including a first portion located over the first portion of the barrier layer; doping a doping element into the first work function adjustment layer; removing the first portion of the first work function adjustment layer; thinning the first portion of the barrier layer; and forming a work function layer on the first portion of the barrier layer.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit devices and methods of manufacturing the same. Background Art

[0002] Metal oxide semiconductor (MOS) devices typically include a metal gate that is formed to address the poly-depletion effect in conventional polysilicon gates. The poly-depletion effect occurs when an applied electric field sweeps carriers from the gate region near the gate dielectric, thereby forming a depletion layer. In an n-doped polysilicon layer, the depletion layer includes ionized non-mobile donor sites, wherein in a p-doped polysilicon layer, the depletion layer includes ionized non-mobile acceptor sites. The depletion effect produces an increase in the effective gate dielectric thickness, making it more difficult to produce an inversion layer at the semiconductor surface.

[0003] The metal gate may include multiple layers to meet the requirements of NMOS devices and PMOS devices. The formation of the metal gate generally includes: depositing multiple metal layers, forming a fill metal region with tungsten, and then performing a chemical mechanical polishing (CMP) process to remove the excess portion of the metal layer. The remaining portion of the metal layer forms the metal gate. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing an integrated circuit device is provided, comprising: forming a gate dielectric, the gate dielectric comprising a first portion extending on a first semiconductor region; forming a barrier layer, the barrier layer comprising a first portion extending above the first portion of the gate dielectric; forming a first work function adjustment layer, the first work function adjustment layer comprising a first portion located above the first portion of the barrier layer; doping doping elements into the first work function adjustment layer; removing the first portion of the first work function adjustment layer; thinning the first portion of the barrier layer; and forming a work function layer on the first portion of the barrier layer.

[0005] According to another embodiment of the present disclosure, a method for manufacturing an integrated circuit device is provided, comprising: depositing a barrier layer, the barrier layer comprising a first portion and a second portion located in a first transistor region and a second transistor region, respectively; depositing a first titanium nitride layer, the first titanium nitride layer comprising a first portion and a second portion overlapping the first portion and the second portion of the barrier layer, respectively; doping aluminum into the first titanium nitride layer; removing the first portion of the first titanium nitride layer, and not removing the second portion of the first titanium nitride layer; partially etching the barrier layer to reduce the thickness of the first portion of the barrier layer, wherein the second portion of the barrier layer is protected by the second portion of the first titanium nitride layer; and forming a work function layer, the work function layer comprising a first portion in contact with the first portion of the barrier layer and a second portion in contact with the second portion of the first titanium nitride layer.

[0006] According to another embodiment of the present disclosure, an integrated circuit device is provided, comprising: a semiconductor region; a gate dielectric located above the semiconductor region; a barrier layer located above the gate dielectric; a first titanium nitride layer located above the barrier layer, wherein the first titanium nitride layer also includes aluminum; and a work function layer located above the first titanium nitride layer, wherein the aluminum atomic percentage of the first titanium nitride layer is higher than the aluminum atomic percentage in an overlying layer located above the first titanium nitride layer and in contact with the first titanium nitride layer, and is higher than the aluminum atomic percentage in an underlying layer located below the first titanium nitride layer and in contact with the first titanium nitride layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1-6 , 7A, 7B, 8A, 8B, 9-21, 22A, and 22B illustrate perspective and cross-sectional views of intermediate stages in forming a fin field effect transistor (FinFET) according to some embodiments.

[0009] Fig.23 A process flow for forming a FinFET according to some embodiments is shown. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0012] According to some embodiments, a transistor with a replacement gate and a method for forming the same are provided. According to some embodiments, an intermediate stage of forming a transistor is shown. Some variations of some embodiments are discussed. In various views and illustrative embodiments, the same figure marks are used to represent the same elements. In the illustrated embodiment, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concepts of the present disclosure. Planar transistors and all-around gate (GAA) transistors may also employ the concepts of the present disclosure. According to some embodiments of the present disclosure, aluminum is doped into a (titanium nitride) work function adjustment layer to increase the etching selectivity between a (tantalum nitride) barrier layer and a titanium nitride work function adjustment layer, so that when the barrier layer is thinned, the loss of the thickness of the work function adjustment layer is reduced, and the expansion between the threshold voltages of the transistors can be prevented from being reduced.

[0013] Figure 1-6 , 7A, 7B, 8A, 8B, 9-21, 22A, and 22B show perspective and cross-sectional views of intermediate stages of forming a fin field effect transistor (FinFET) according to some embodiments. The processes shown in these figures are also schematically reflected in Fig.23 In the process flow 400 shown in FIG.

[0014] exist Figure 1In the embodiment, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, for example, a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (for example, with a p-type or n-type dopant) or undoped. The semiconductor substrate 20 may be a portion of a wafer 10 (for example, a silicon wafer). Typically, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate (typically a silicon or glass substrate). Other substrates may also be used, for example, a multilayer or gradient substrate. According to some embodiments, the semiconductor material of the semiconductor substrate 20 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0015] Further references Figure 1 , a well region 22 is formed in the substrate 20. Fig.23 In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 402. According to some embodiments of the present disclosure, the well region 22 is a p-type well region formed by injecting p-type impurities (which may be boron, indium, etc.) into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is an n-type well region formed by injecting n-type impurities (which may be phosphorus, arsenic, antimony, etc.) into the substrate 20. The resulting well region 22 may extend to the top surface of the substrate 20. The n-type or p-type impurity concentration may be equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm -3 in the range between.

[0016] refer to Figure 2 , the isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is alternatively referred to as a shallow trench isolation (STI) region. Fig.23In the process flow 400 shown in , the corresponding process is shown as process 404. The portion of the substrate 20 located between adjacent STI regions 24 is called a semiconductor strip 26. In order to form the STI region 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20, and then the pad oxide layer 28 and the hard mask layer 30 are patterned. The pad oxide layer 28 can be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also be used as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using low pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The patterned photoresist is then used as an etching mask to pattern the hard mask layer 30 to form a Figure 2 A hard mask 30 is shown.

[0017] Next, the patterned hard mask layer 30 is used as an etching mask to etch the pad oxide layer 28 and the substrate 20, followed by filling the resulting trenches in the substrate 20 with (one or more) dielectric materials. A planarization process (e.g., a chemical mechanical polishing (CMP) process, or a mechanical grinding process) is performed to remove excess portions of the dielectric material, and the remaining portions of the (one or more) dielectric materials are the STI regions 24. The STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc. formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 24 may also include a dielectric material located above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material located above the liner dielectric may include silicon oxide.

[0018] The top surface of hard mask 30 and the top surface of STI region 24 may be at substantially the same level as each other. Semiconductor strips 26 are located between adjacent STI regions 24. According to some embodiments of the present disclosure, semiconductor strips 26 are portions of original substrate 20, and thus the material of semiconductor strips 26 is the same as the material of substrate 20. In an alternative embodiment of the present disclosure, semiconductor strips 26 are alternative strips formed by etching a portion of substrate 20 located between STI regions 24 to form a groove, and performing epitaxy to re-grow another semiconductor material in the groove. Therefore, semiconductor strips 26 are formed of a semiconductor material different from that of substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0019] refer to Figure 3 , STI region 24 is recessed so that the top of semiconductor strip 26 protrudes above top surface 24A of the remaining portion of STI region 24 to form a protruding fin 36. Fig.23 In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 406. The etching can be performed using a dry etching process, wherein, for example, HF3 and NH3 are used as etching gases. In the etching process, plasma can be generated. Argon gas can also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 24 is performed using a wet etching process. For example, the etching chemical can include HF.

[0020] In the embodiments shown above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, allowing the creation of patterns with smaller pitches, for example, than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0021] refer to Figure 4 , a dummy gate stack 38 is formed to extend over the top surface and sidewalls of the (protruding) fin 36. Fig.23In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 408. The dummy gate stack 38 may include a dummy gate dielectric 40 and a dummy gate electrode 42 located above the dummy gate dielectric 40. The dummy gate electrode 42 may be formed, for example, using polysilicon, and other materials may also be used. Each dummy gate stack 38 may also include one (or more) hard mask layers 44 located above the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a multilayer thereof. The dummy gate stack 38 may span a single or multiple protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fins 36.

[0022] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. Fig.23 In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 408. According to some embodiments of the present disclosure, the gate spacer 46 is formed of (one or more) dielectric materials (e.g., silicon nitride, silicon carbonitride, etc.), and may have a single-layer structure, or may have a multi-layer structure including a plurality of dielectric layers.

[0023] An etching process is then performed to etch the portions of the protruding fins 36 that are not covered by the dummy gate stack 38 and the gate spacers 46, thereby producing Figure 5 The structure shown in Fig.23 4, the corresponding process is shown as process 410. The recess may be anisotropic, and thus the portion of the fin 36 directly below the dummy gate stack 38 and the gate spacer 46 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 may be lower than the top surface 24A of the STI region 24. The space left by the etched portion of the protruding fin 36 is referred to as a recess 50. The recess 50 includes portions on opposite sides of the dummy gate stack 38, and portions between the remaining portions of the protruding fin 36.

[0024] Next, epitaxial regions (source / drain regions) 54 are formed by selectively growing (by epitaxy) semiconductor material in the recesses 50, thereby producing Figure 6 In the structure. Fig.23In the process flow 400 shown in , the corresponding process is shown as process 412. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 54 includes a III-V compound semiconductor, for example, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or a multilayer thereof. After the groove 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and a facet can be formed. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. A void (air gap) 56 may be generated. According to some embodiments of the present disclosure, when the top surface of the epitaxial region 54 is still wavy, or when the merged top surface of the epitaxial region 54 becomes flat (this is achieved by further growth on the epitaxial region 54, such as Figure 6 As shown), the formation of the epitaxial region 54 can be completed.

[0025] After the epitaxy step, the epitaxy region 54 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also indicated using reference numeral 54. According to an alternative embodiment of the present disclosure, when the epitaxy region 54 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation step is skipped.

[0026] Fig. 7A 1 shows a perspective view of the structure after forming a contact etch stop layer (CESL) 58 and an interlayer dielectric (ILD) 60. Fig.23 In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 414. CESL 58 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. ILD 60 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. ILD 60 may be formed of an oxygen-containing dielectric material (which may be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.). A planarization process (e.g., a CMP process, or a mechanical grinding process) may be performed to make the top surfaces of ILD 60, dummy gate stack 38, and gate spacer 46 at the same level with each other.

[0027] Figure 7BA cross-sectional view of an intermediate structure in which a first FinFET, a second FinFET, and a third FinFET are formed on the same substrate 20 is shown. The first FinFET, the second FinFET, and the third FinFET are formed in device regions 100, 200, and 300, respectively. According to some embodiments, the first FinFET, the second FinFET, and the third FinFET have the same conductivity type and may all be p-type FinFETs or all be n-type FinFETs. The first FinFET, the second FinFET, and the third FinFET are intended to be formed with different threshold voltages having sufficient differences (extensions). For example, when the FinFET is an n-type FinFET, the FinFET in the device region 100 ( Fig.22A 190 in the device region 300) has the lowest threshold voltage among FinFETs 190, 290, and 390, and the FinFET ( Fig.22A 390) has the highest threshold voltage. Conversely, when the FinFETs are p-type FinFETs, the FinFETs in device region 100 have the highest threshold voltage among FinFETs 190, 290, and 390, and the FinFETs in device region 300 have the lowest threshold voltage. According to alternative embodiments, the first FinFET, the second FinFET, and the third FinFET have different conductivity types, and each of the first FinFET, the second FinFET, and the third FinFET may be a p-type FinFET or an n-type FinFET in any combination. The initial formation process of each of the first FinFET, the second FinFET, and the third FinFET may include the following: Figures 1 to 7A The process shown in FIG. 1 and thus can have Fig. 7A A structure similar to the structure shown in FIG. Figure 7B The structure in each of the first device region 100, the second device region 200 and the third device region 300 shown can be obtained from Fig. 7A The reference cross section 7B-7B shown is obtained.

[0028] In the formation Fig. 7A and 7B After the structure shown, the dummy gate stacks 38 in the device regions 100, 200 and 300 are replaced with metal gates and replacement gate dielectrics, as shown in FIG. Fig. 8A , 8B and 9-20. Fig. 8A , 8B 9-20, top surface 24A of STI region 24 is shown, and semiconductor fin 24' protrudes above corresponding top surface 24A.

[0029] To form a replacement gate, first remove Fig. 7A and 7B The hard mask layer 44, the dummy gate electrode 42, and the dummy gate dielectric 40 are formed as shown. Fig. 8A and 8B The opening 59 is shown. Fig.23 In the process flow 400 shown in FIG. 5 , the corresponding process is shown as process 416 . The top surface and sidewalls of the protruding fin 24 ′ are exposed to the opening 59 .

[0030] Next, refer to Fig. 9 , forming gate dielectrics 63, which extend into the openings 59 respectively. Fig.23 In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 418. According to some embodiments of the present disclosure, the gate dielectric 63 includes an interfacial layer (IL) 61, which is formed on the exposed surface of the protruding fin 24'. Each IL 61 may include an oxide layer (e.g., a silicon oxide layer) formed by thermal oxidation, a chemical oxidation process, or a deposition process of the protruding fin 24'. The gate dielectric 63 may also include a high-k dielectric layer 62 located above the corresponding IL 61. The high-k dielectric layer 62 may be formed of a high-k dielectric material (e.g., hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or hafnium oxide, etc.). The dielectric constant (k value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0, sometimes as high as 21.0 or higher. The high-k dielectric layer 62 covers and may contact the corresponding underlying IL 61. The high-k dielectric layer 62 is formed as a conformal layer and extends on the sidewalls of the protruding fin 24' and the top surface and sidewalls of the gate spacer. According to some embodiments of the present disclosure, ALD or CVD is used to form high-k dielectric layer 62. High-k dielectric layers 62 in device regions 100, 200, and 300 may be part of the same dielectric layer and formed simultaneously from the same material and have the same thickness, or formed separately from different materials and / or have different thicknesses.

[0031] Then, a capping layer 64 and a barrier layer 66 are conformally formed on the gate dielectric 63. Fig.23In the process flow 400 shown in , the corresponding process is shown as process 420. The cap layer 64 and the barrier layer 66 may also be referred to as a first sub-cap layer and a second sub-cap layer, respectively. According to some embodiments, each of the cap layer 64 and the barrier layer 66 may be a single layer, or may include additional sub-layers. The barrier layer 66 may be used to prevent the subsequently deposited metal-containing material from diffusing into the gate dielectric 63. In addition, as shown in the figure, if the cap layer 64 is formed of the same material as the subsequently formed work function adjustment layer, the barrier layer 66 may be used as an etch stop layer during the subsequent etching of the work function adjustment layer in the device regions 100 and 200, which will become clearer in the subsequent description. The cap layer 64 may be formed of titanium nitride (TiN) or the like conformally deposited on the gate dielectric 63 by ALD, CVD, or the like, or may include titanium nitride (TiN) or the like conformally deposited on the gate dielectric 63 by ALD, CVD, or the like. The barrier layer 66 may be formed of, or may include, tantalum nitride (TaN) or the like conformally deposited on the cap layer 64 by ALD, CVD, or the like. The thickness of the cap layer 64 may be about 1000 Å. Peace and the thickness of the barrier layer 66 may be in the range of about Peace in the range between.

[0032] refer to Fig.10 , the first work function adjustment layer 68A is conformally formed on the barrier layer 66. Fig.23 In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 422. The first work function adjustment layer 68A may be formed of any acceptable material to adjust the work function of the device to a desired amount depending on the application of the device to be formed, and may be deposited using any acceptable deposition process. According to some embodiments, the first work function adjustment layer 68A is formed of titanium nitride (TiN) or the like deposited by ALD, CVD, or the like, or may include titanium nitride (TiN) or the like deposited by ALD, CVD, or the like. The first work function adjustment layer 68A may be free of doping elements (e.g., aluminum). The thickness of the first work function adjustment layer 68A may be about 1000 Å. Peace in the range between.

[0033] refer to Fig.11 , an etch mask 70 is formed, and then the etch mask 70 is patterned to cover the device region 300 while leaving the device regions 100 and 200 uncovered. Thus, portions of the work function adjustment layer 68A located in the device regions 100 and 200 are exposed. According to some embodiments, the etch mask 70 includes a photoresist.

[0034] After forming the patterned etching mask 70, an etching process is performed to pattern the first work function adjusting layer 68A. Fig.23 In the process flow 400 shown in , the corresponding process is shown as process 424. In the patterning process, portions of the first work function adjustment layer 68A are removed from the first device region 100 and the second device region 200, leaving portions of the first work function adjustment layer 68A located in the device region 300. During this etching process, the barrier layer 66 can be used as an etch stop layer. According to some embodiments, the first work function adjustment layer 68A can be etched, for example, using a fluorine-containing chemical (e.g., a hydrogen fluoride (HF) solution). The etching mask 70 is then removed, for example, by using an appropriate ashing process when the etching mask 70 is a photoresist. The resulting structure is as shown in FIG. Fig.12 shown.

[0035] Fig.13 The formation of a second work function adjusting layer 68B is shown, which is conformally formed and extends into the device regions 100, 200 and 300. Fig.23 In the process flow 400 shown in FIG. 1 , the corresponding process is shown as process 426. In the device regions 100 and 200, the second work function adjustment layer 68B can contact the top surface of the barrier layer 66. In the device region 300, the second work function adjustment layer 68B can contact the first work function adjustment layer 68A. The second work function adjustment layer 68B can be formed of any acceptable material to adjust the work function of the device to a desired amount depending on the application of the device to be formed, and can be deposited using any acceptable deposition process. According to some embodiments, the second work function adjustment layer 68B is deposited using CVD, ALD, etc. The thickness of the second work function adjustment layer 68B can be about 1000 Å. Peace in the range between.

[0036] According to some embodiments, the second work function adjustment layer 68B includes titanium nitride (TiN). The atomic ratio of titanium to nitride in the second work function adjustment layer 68B may be the same as or different from the atomic ratio of titanium to nitride in the first work function adjustment layer 68A. The work function adjustment layers 68A and 68B may be distinguishable from each other or indistinguishable. For example, there may or may not be a distinguishable interface between the work function adjustment layers 68A and 68B. The work function adjustment layer 68B may or may not include a doping element, which may be aluminum, or another applicable element capable of affecting the etch selectivity (ES) between the second work function adjustment layer 68B and the barrier layer 66. More specifically, when doped into the second work function adjustment layer 68B, the doping element causes the etching rate of the second work function adjustment layer 68B to be smaller (compared to undoped) during the subsequent thinning process of the barrier layer 66, such as Fig.15In addition, the deposited first work function adjusting layer 68A may not have doping elements.

[0037] According to some embodiments, the second work function adjustment layer 68B includes TiN doped with aluminum, and thus the second work function adjustment layer 68B is a TiAlN layer. The deposition of the second work function adjustment layer 68B may be performed by CVD or ALD. The process gas for introducing titanium into TiAlN may be, for example, TiCl4, etc. The process gas for introducing nitrogen into TiAlN may include, for example, ammonia (NH3), etc. The process gas for introducing aluminum into TiAlN may include, for example, AlCl3, etc. According to some embodiments of the present disclosure, the atomic percentage of aluminum is in a range between about 10% and about 20%.

[0038] According to an alternative embodiment, the second work function adjustment layer 68B (as deposited) includes TiN and does not have a doping element (e.g., aluminum), and the doping element is doped in a subsequent hot soak process. The deposition of the second work function adjustment layer 68B can also be performed by CVD or ALD, wherein the precursor can include TiCl4, ammonia, etc. According to some embodiments, during the deposition of the work function adjustment layer 68B, the temperature of the wafer 10 is in a range between about 300°C and about 550°C, or can be in a range between about 400°C and about 450°C. The flow rate of TiCl4 can be in a range between about 30 sccm and about 300 sccm. The flow rate of ammonia can be in a range between about 500 sccm and about 5,000 sccm.

[0039] refer to Fig.14 When the deposited work function adjusting layer 68B does not have the doping element, a thermal soaking process (indicated by arrow 69) is performed to dope the doping element into the work function adjusting layer 68B. Fig.23 In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 428. According to some embodiments in which the deposited second work function adjustment layer 68B already includes a doping element, a thermal soaking process may be performed or may be skipped. Fig.23 Process 428 shown in process flow 400 in FIG. 4 is marked with a dashed rectangle to indicate that it may be performed or not performed. According to some embodiments, the process gas used for the hot soak process includes an aluminum-containing process gas (e.g., AlCl3, etc.) and may include some carrier gas (e.g., H2, Ar, etc.). According to some embodiments, the hot soak process causes the doping element to reach a desired atomic percentage (e.g., about 10% to about 20%) in the work function adjustment layer 68B, and no (or substantially no) doping element diffuses into the barrier layer 66 and the first work function adjustment layer 68A.

[0040] According to some embodiments of the present disclosure, a thermal soak process is performed, wherein the wafer 10 is at a temperature in a range between about 300° C. and about 550° C., or at a temperature in a range between about 400° C. and about 450° C., and the pressure of the process gas may be between about 0.5 Torr and about 30 Torr. The thermal soak time may be in a range between about 1 second and about 300 seconds.

[0041] refer to Fig.15 , forming an etch mask 72, and then patterning the etch mask 72 to cover the device regions 200 and 300 while leaving the device region 100 uncovered. Thus, a portion of the work function adjustment layer 68B located in the device region 100 is exposed. According to some embodiments, the etch mask 72 includes a photoresist.

[0042] After forming the patterned etching mask 72, an etching process is performed to pattern the work function adjustment layer 68B. Fig.23 In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 430. The portion of the work function adjustment layer 68B located in the device region 100 is removed, and the portion of the work function adjustment layer 68B located in the device regions 200 and 300 is retained. In the etching process, the barrier layer 66 can be used as an etching stop layer. According to some embodiments, the work function adjustment layer 68B is etched, for example, using a fluorine-containing chemical (e.g., a hydrogen fluoride (HF) solution). The etching mask 72 is then removed, for example, by using an appropriate ashing process when the etching mask 72 is a photoresist. The resulting structure is as shown in FIG. Fig.16 In the device region 100, the barrier layer 66 is exposed. In the device regions 200 and 300, the work function adjusting layer 68B is exposed.

[0043] Fig.17 A selective thinning process by etching is shown, wherein the barrier layer 66 in the device region 100 is thinned (partially or completely removed). In the etching process, the portion of the barrier layer 66 located in the device region 100 and the portion of the work function adjustment layer 68B located in the device regions 200 and 300 are exposed to an etchant. The etchant is selected so that the etch selectivity ES (which is the ratio of the etch rate of the barrier layer 66 to the etch rate of the work function adjustment layer 68B) is high. For example, the etch selectivity ES may be higher than about 5, and may be in the range of between about 5 and 10 or higher. It should be understood that the etching process is performed after removing the etching mask 72, rather than using the etching mask 72 as an etching mask. The reason is that the etching may be performed at a high temperature, which may be high enough to cause damage to the etching mask 72, and the damaged etching mask 72 may contaminate the etching chamber.

[0044] According to some embodiments of the present disclosure, chlorine-based chemicals are used to perform etching of the barrier layer 66. According to some embodiments, the selective etching is performed using a chlorine-based gas, which may be a metal chloride gas, such as TiCl x 、TaCl x 、WCl x etc., or a combination thereof. It is understood that TiCl x 、TaCl x and WCl x It may be a liquid or a gas, depending on the temperature, and the liquid evaporates into a gas at a high temperature. The selective etching process may be a thermal etching process that does not generate plasma. According to some embodiments, when a chlorine-based gas is used for selective etching, the temperature of the wafer 10 may be in a range between about 200° C. and about 600° C., wherein the flow rate of the chlorine-based gas is in a range between about 100 sccm and about 10,000 sccm. The etching duration may be in a range between about 10 seconds and about 300 seconds, for example, between about 30 seconds and about 120 seconds.

[0045] The etching causes the thickness of the portion of the barrier layer 66 located in the device region 100 to increase from the thickness T1 before etching ( Fig.16 ) is reduced to the thickness T2 after etching ( Fig.17 ). The ratio T2 / T1 may be less than about 0.7, or less than about 0.5. The ratio T2 / T1 may also be 0, which means that the portion of the barrier layer 66 located in the device region 100 is removed. The ratio may also be in the range between about 0.1 and about 0.5. For example, the thickness T1 before etching may be about Peace and thickness T2 can be in the range of about Peace in the range between.

[0046] As described above, due to the doping of the doping element, the etching selectivity ES increases, for example, to a value between about 5 and about 10. Therefore, in the selective etching, the thickness reduction of the work function adjusting layer 68B in the device regions 200 and 300 is small.

[0047] The thickness of the barrier layer 66 and the work function adjustment layers 68A and 68B affect the corresponding FinFETs 190, 290 and 390 ( Fig.22A) threshold voltage. For example, when FinFETs 190, 290, and 390 are n-type FinFETs, the reduction of barrier layer 66 and work function adjustment layers 68A and 68B lowers the threshold voltage of the corresponding FinFETs 190, 290, and 390. When barrier layer 66 is etched, the threshold voltage of FinFET 190 is reduced. It is expected that the threshold voltages of FinFETs 190, 290, and 390 have a large spread to meet the requirements of different circuits. In the etching of barrier layer 66, if work function adjustment layer 68B is etched too much in device regions 200 and 300, FinFETs 290 and 390 ( Fig.22A ) will also be reduced too much, so that the spread between the threshold voltage of FinFET 190 and the threshold voltages of FinFETs 290 and 390 is undesirably reduced. Therefore, the spread between the threshold voltages of FinFETs 190, 290, and 390 is maintained.

[0048] When FinFETs 190, 290, and 390 are p-type FinFETs, the thinning of the barrier layer 66 and the work function adjustment layers 68A and 68B increases the threshold voltage of FinFETs 190, 290, and 390. By doping the work function adjustment layer 68B, when the barrier layer 66 is etched, due to the high etching selectivity ES, the thickness reduction of the work function adjustment layer 68B becomes smaller, and the increase in the threshold voltage of FinFETs 290 and 390 becomes smaller. The threshold voltage extension is also maintained. Experimental results show that if the work function adjustment layer 68B is not doped with a doping element, the etching selectivity ES is about 3, and when the work function adjustment layer 68B is doped with, for example, aluminum, the etching selectivity ES increases to about 5 to 10. The thickness loss of the work function adjustment layer 68B is significantly reduced, so that the flat band voltage V of the resulting FinFET (when the layer 68B is doped) is FB Change in ΔV FB The resulting FinFET ΔV is approximately (when layer 68B is undoped) FB 1 / 7 of.

[0049] refer to Fig.18 , the work function layer 74 is conformally formed and extends into the device regions 100, 200, and 300. The work function layer 74 may be formed by ALD, CVD, etc. Fig.23In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 432. The work function layer 74 may be a single layer of uniform composition (having the same elements and having the same percentage of the same elements), or may include multiple sublayers formed of different materials. The work function layer 74 may include a work function metal selected according to whether the corresponding FinFET formed in the device regions 100, 200, and 300 is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer 74 may include an aluminum-based layer (e.g., formed of TiAl, TiAlN, TiAlC, TaAlN, or TaAlC, or including TiAl, TiAlN, TiAlC, TaAlN, or TaAlC). The aluminum-based layer may be in contact with or not in contact with the barrier layer 66 (located in the device region 200) and the work function adjustment layer 68B (located in the device region 200). When the FinFET is a p-type FinFET, the work function layer 74 may have or not have an aluminum-containing layer. For example, the work function layer 74 of the p-type FinFET may include a TiN layer, a TaN layer, and another TiN layer, and may not have an aluminum-containing material. The aluminum-free portion of the work function layer 74 may be in contact with the work function adjustment layer 68B. According to some embodiments, the portions of the work function layer 74 located in the device regions 100, 200, and 300 are formed of the same material and may or may not be formed in a common deposition process. According to alternative embodiments, the portions of the work function layer 74 located in the device regions 100, 200, and 300 are formed of different materials, which are formed in separate deposition processes. For example, each of the portions of the work function layer 74 located in the device regions 100, 200, and 300 may be formed of a p-type work function material and an n-type work function material in any combination.

[0050] Regardless of whether the FinFETs in device regions 200 and 300 are n-type FinFETs or p-type FinFETs, the work function layer 74 may not include aluminum (as deposited prior to any subsequent annealing), or the work function layer may include an aluminum-containing sublayer, but the aluminum-containing layer is separated from the work function adjusting layer 68B by an aluminum-free sublayer (as deposited) in contact with the work function adjusting layer 68B. Therefore, although subsequent thermal processing may produce aluminum diffusion, the work function adjusting layer 68B still has a higher aluminum atomic percentage (concentration) than the overlying aluminum-free sublayer and the underlying layer (barrier layer 66 in device region 200 or work function adjusting layer 68A in device region 300).

[0051] refer to Fig.19 , the barrier layer 76 (which is also a blocking layer) is conformally formed and extends into the device regions 100, 200 and 300. Fig.23In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 434. According to some embodiments, the barrier layer 76 includes titanium nitride (TiN) or the like deposited by ALD, CVD, or the like. The thickness of the barrier layer 76 may be about Peace in the range between.

[0052] Fig.19 Also shown is the formation of fill metal region 78. In accordance with some embodiments, fill metal region 78 is formed of tungsten, cobalt, or the like, which may be deposited using ALD, CVD, or a combination thereof. Fig.23 In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 436. After forming the fill metal region 78, a planarization process may be performed to remove excess portions of the deposited layer, such as Fig.19 As shown, gate stacks 180, 280 and 380 are generated, as shown in FIG. Fig. 20 As shown. Fig.23 4, the corresponding process is shown as process 438. Gate stacks 180, 280, and 380 include gate electrodes 179, 279, and 379, respectively. Gate electrode 179 includes capping layer 64, barrier layer 66, work function layer 74, barrier layer 76, and fill metal region 78. Gate electrode 279 includes capping layer 64, barrier layer 66, work function adjustment layer 68B, work function layer 74, barrier layer 76, and fill metal region 78. Gate electrode 379 includes capping layer 64, barrier layer 66, work function adjustment layers 68A and 68B, work function layer 74, barrier layer 76, and fill metal region 78.

[0053] Fig.21 The formation of a hard mask 82 according to some embodiments is shown. The formation of the hard mask 82 may include: performing an etching process to recess the gate stacks 180, 280, and 380 so that grooves are formed between the gate spacers 46; filling the grooves with a dielectric material; and then performing a planarization process (e.g., a CMP process, or a mechanical grinding process) to remove excess portions of the dielectric material. The hard mask 82 may be formed of silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc.

[0054] Fig.22AThe formation of source / drain contact plugs 84 and silicide regions 86 is shown. The formation of source / drain contact plugs 84 includes etching ILD 60 to expose the underlying portion of CESL 58, and then etching the exposed portion of CESL 58 to form a contact opening through which the source / drain regions 54 are exposed. In a subsequent process, a metal layer (e.g., a Ti layer) is deposited and extends into the contact opening. A metal nitride capping layer may be performed. An annealing process is then performed to react the metal layer with the top of the source / drain regions 54 to form silicide regions 86, as shown in FIG. Fig. 20 As shown. Filling metal material (e.g., tungsten, cobalt, etc.) is then filled into the contact openings, and then planarized to remove excess material, resulting in source / drain contact plugs 84. Etch stop layer 91 and ILD 93 may then be deposited. Gate contact plugs 88 are also formed to penetrate hard mask 82 to contact gate electrodes 179, 279, and 379. Source / drain contact plugs 89 are also formed. FinFETs 190, 290, and 390 are thereby formed.

[0055] Fig. 22B A perspective view of a FinFET is shown, which may be represented as Fig.22A Any of the FinFETs 190, 290, and 390 shown in FIG. A gate contact plug 88, source / drain silicide regions 86, and source / drain contact plugs 84 are also shown.

[0056] Embodiments of the present disclosure have some advantageous features. An integrated circuit may have transistors with different threshold voltages. It is desirable that the spread between the threshold voltages of the transistors is significant. By doping the work function adjustment layer with a doping element (e.g., aluminum), when etching the barrier layer of one transistor, the unfavorable etching of the exposed work function adjustment layer in other transistors is reduced, and the unfavorable reduction in the spread of the threshold is reduced.

[0057] According to some embodiments of the present disclosure, a method includes: forming a gate dielectric, the gate dielectric including a first portion extending on a first semiconductor region; forming a barrier layer, the barrier layer including a first portion extending above the first portion of the gate dielectric; forming a first work function adjustment layer, the first work function adjustment layer including a first portion located above the first portion of the barrier layer; doping a doping element into the first work function adjustment layer; removing the first portion of the first work function adjustment layer; thinning the first portion of the barrier layer; and forming a work function layer on the first portion of the barrier layer. In an embodiment, the first work function adjustment layer includes titanium nitride, and the doping element includes aluminum. In an embodiment, doping the doping element includes: in-situ doping aluminum when depositing the first work function adjustment layer. In an embodiment, doping the doping element is performed after depositing the first work function adjustment layer. In an embodiment, doping the doping element includes: thermally immersing the first work function adjustment layer in an aluminum-containing gas. In an embodiment, the gate dielectric further comprises a second portion extending on the second semiconductor region, the barrier layer further comprises a second portion extending above the second portion of the gate dielectric, and the first work function adjustment layer further comprises a second portion extending above the second portion of the barrier layer, and wherein, when the first portion of the first work function adjustment layer is removed, the second portion of the first work function adjustment layer is protected from removal by the etching mask. In an embodiment, when the first portion of the barrier layer is thinned, the second portion of the barrier layer is protected by the second portion of the first work function adjustment layer. In an embodiment, the method further comprises: before forming the first work function adjustment layer, forming a second work function adjustment layer; and after forming the second work function adjustment layer, patterning the second work function adjustment layer to remove a portion of the second work function adjustment layer overlapping the first portion of the barrier layer.

[0058] According to some embodiments of the present disclosure, a method includes: depositing a barrier layer, the barrier layer including a first portion and a second portion located in a first transistor region and a second transistor region, respectively; depositing a first titanium nitride layer, the first titanium nitride layer including a first portion and a second portion overlapping the first portion and the second portion of the barrier layer, respectively; doping aluminum into the first titanium nitride layer; removing the first portion of the first titanium nitride layer and not removing the second portion of the first titanium nitride layer; partially etching the barrier layer to reduce the thickness of the first portion of the barrier layer, wherein the second portion of the barrier layer is protected by the second portion of the first titanium nitride layer; and forming a work function layer, the work function layer including a first portion in contact with the first portion of the barrier layer and a second portion in contact with the second portion of the first titanium nitride layer. In an embodiment, the barrier layer further includes a third portion located in the third transistor region, and the first titanium nitride layer further includes a third portion located above the third portion of the barrier layer, and the method further includes: before forming the first titanium nitride layer, depositing a second titanium nitride layer, the second titanium nitride layer including a first portion, a second portion, and a third portion overlapping the first portion, the second portion, and the third portion of the barrier layer, respectively; and before forming the first titanium nitride layer, removing the first portion and the second portion of the second titanium nitride layer. In an embodiment, no aluminum is doped into the second titanium nitride layer before forming the first titanium nitride layer. In an embodiment, doping aluminum into the first titanium nitride layer includes: thermally soaking the first titanium nitride layer in an aluminum-containing gas. In an embodiment, partially etching the barrier layer is performed using a metal chloride gas. In an embodiment, when partially etching the barrier layer, the thickness of the first portion of the barrier layer is reduced by a percentage in the range of about 50% to about 90%. In an embodiment, during the partial etching of the barrier layer, the second portion of the first titanium nitride layer is exposed to the same etching gas used to etch the barrier layer.

[0059] According to some embodiments of the present disclosure, an integrated circuit device includes: a semiconductor region; a gate dielectric located above the semiconductor region; a barrier layer located above the gate dielectric; a first titanium nitride layer located above the barrier layer, wherein the first titanium nitride layer also includes aluminum; and a work function layer located above the first titanium nitride layer, wherein the aluminum atomic percentage of the first titanium nitride layer is higher than the aluminum atomic percentage in the overlying layer located above the first titanium nitride layer and in contact with the first titanium nitride layer, and is higher than the aluminum atomic percentage in the underlying layer located below the first titanium nitride layer and in contact with the first titanium nitride layer. In an embodiment, the overlying layer is a work function layer. In an embodiment, the integrated circuit device further includes a second titanium nitride layer located between the first titanium nitride layer and the barrier layer, wherein the underlying layer is a second titanium nitride layer. In an embodiment, the work function layer, the first titanium nitride layer, the barrier layer, and the gate dielectric are included in a p-type transistor. In an embodiment, the underlying layer is a barrier layer.

[0060] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0061] Example 1. A method for manufacturing an integrated circuit device, comprising: forming a gate dielectric, the gate dielectric including a first portion extending over a first semiconductor region; forming a barrier layer, the barrier layer including a first portion extending over the first portion of the gate dielectric; forming a first work function adjustment layer, the first work function adjustment layer including a first portion located over the first portion of the barrier layer; doping doping elements into the first work function adjustment layer; removing the first portion of the first work function adjustment layer; thinning the first portion of the barrier layer; and forming a work function layer on the first portion of the barrier layer.

[0062] Example 2. The method of Example 1, wherein the first work function adjustment layer comprises titanium nitride and the doping element comprises aluminum.

[0063] Example 3. The method according to Example 1, wherein doping the doping element comprises: in-situ doping aluminum when depositing the first work function adjustment layer.

[0064] Example 4. The method according to Example 1, wherein doping the doping element is performed after depositing the first work function adjustment layer.

[0065] Example 5. The method according to Example 4, wherein doping the doping element comprises: thermally immersing the first work function adjustment layer in an aluminum-containing gas.

[0066] Example 6. A method according to Example 1, wherein the gate dielectric also includes a second portion extending over the second semiconductor region, the blocking layer also includes a second portion extending above the second portion of the gate dielectric, and the first work function adjustment layer also includes a second portion extending above the second portion of the blocking layer, and wherein, when the first portion of the first work function adjustment layer is removed, the second portion of the first work function adjustment layer is protected from removal by an etching mask.

[0067] Example 7. The method of Example 6, wherein when the first portion of the barrier layer is thinned, the second portion of the barrier layer is protected by the second portion of the first work function adjusting layer.

[0068] Example 8. The method according to Example 1 further includes: forming a second work function adjustment layer before forming the first work function adjustment layer; and after forming the second work function adjustment layer, patterning the second work function adjustment layer to remove a portion of the second work function adjustment layer overlapping with the first portion of the blocking layer.

[0069] Example 9. A method for manufacturing an integrated circuit device, comprising: depositing a barrier layer, the barrier layer comprising a first portion and a second portion located in a first transistor region and a second transistor region, respectively; depositing a first titanium nitride layer, the first titanium nitride layer comprising a first portion and a second portion overlapping with the first portion and the second portion of the barrier layer, respectively; doping aluminum into the first titanium nitride layer; removing the first portion of the first titanium nitride layer and not removing the second portion of the first titanium nitride layer; partially etching the barrier layer to reduce the thickness of the first portion of the barrier layer, wherein the second portion of the barrier layer is protected by the second portion of the first titanium nitride layer; and forming a work function layer, the work function layer comprising a first portion in contact with the first portion of the barrier layer and a second portion in contact with the second portion of the first titanium nitride layer.

[0070] Example 10. A method according to Example 9, wherein the barrier layer also includes a third portion located in a third transistor region, and the first titanium nitride layer also includes a third portion located above the third portion of the barrier layer, and the method further includes: before forming the first titanium nitride layer, depositing a second titanium nitride layer, the second titanium nitride layer including a first portion, a second portion, and a third portion that overlap with the first portion, the second portion, and the third portion of the barrier layer, respectively; and before forming the first titanium nitride layer, removing the first portion and the second portion of the second titanium nitride layer.

[0071] Example 11. The method of Example 10, wherein no aluminum is doped into the second titanium nitride layer before forming the first titanium nitride layer.

[0072] Example 12. The method of Example 9, wherein doping the aluminum into the first titanium nitride layer comprises thermally soaking the first titanium nitride layer in an aluminum-containing gas.

[0073] Example 13. The method of Example 9, wherein partially etching the barrier layer is performed using a metal chloride gas.

[0074] Example 14. The method of Example 9, wherein when the barrier layer is partially etched, the thickness of the first portion of the barrier layer is reduced by a percentage in a range of about 50% to about 90%.

[0075] Example 15. The method of Example 9, wherein during the partial etching of the barrier layer, the second portion of the first titanium nitride layer is exposed to the same etching gas used to etch the barrier layer.

[0076] Example 16. An integrated circuit device, comprising: a semiconductor region; a gate dielectric located above the semiconductor region; a barrier layer located above the gate dielectric; a first titanium nitride layer located above the barrier layer, wherein the first titanium nitride layer also includes aluminum; and a work function layer located above the first titanium nitride layer, wherein the aluminum atomic percentage of the first titanium nitride layer is higher than the aluminum atomic percentage in an overlying layer located above the first titanium nitride layer and in contact with the first titanium nitride layer, and is higher than the aluminum atomic percentage in an underlying layer located below the first titanium nitride layer and in contact with the first titanium nitride layer.

[0077] Example 17. The integrated circuit device of Example 16, wherein the overlying layer is the work function layer.

[0078] Example 18. The integrated circuit device of Example 16, further comprising a second titanium nitride layer between the first titanium nitride layer and the barrier layer, wherein the underlying layer is the second titanium nitride layer.

[0079] Example 19. The integrated circuit device of Example 16, wherein the work function layer, the first titanium nitride layer, the barrier layer, and the gate dielectric are included in a p-type transistor.

[0080] Example 20. The integrated circuit device of Example 16, wherein the underlying layer is the barrier layer.

Claims

1. A method for manufacturing an integrated circuit device, comprising: forming a gate dielectric including a first portion extending over the first semiconductor region; forming a barrier layer including a first portion extending over the first portion of the gate dielectric; forming a first work function adjusting layer, the first work function adjusting layer comprising a first portion located above the first portion of the barrier layer; doping a doping element into the first work function adjustment layer, wherein the doping element comprises aluminum; removing the first portion of the first work function adjusting layer, wherein the first portion of the first work function adjusting layer extends in a trench between gate spacers, and a first bottom portion of the first portion of the first work function adjusting layer at a bottom of the trench is removed; After the first portion of the first work function adjusting layer is removed, thinning the first portion of the barrier layer, wherein a second bottom portion of the first portion of the barrier layer at the bottom of the trench is thinned; as well as After the thinning, a work function layer is formed on the first portion of the barrier layer, wherein the work function layer includes aluminum.

2. The method according to claim 1, wherein: The first work function adjusting layer includes titanium nitride.

3. The method according to claim 1, wherein: Doping the doping element includes: in-situ doping aluminum when depositing the first work function adjustment layer.

4. The method according to claim 1, wherein: Doping the doping element is performed after depositing the first work function adjusting layer.

5. The method according to claim 4, wherein: Doping the doping element includes: thermally immersing the first work function adjustment layer in an aluminum-containing gas.

6. The method according to claim 1, wherein: The gate dielectric also includes a second portion extending on the second semiconductor region, the barrier layer also includes a second portion extending above the second portion of the gate dielectric, and the first work function adjustment layer also includes a second portion extending above the second portion of the barrier layer, and wherein, when the first portion of the first work function adjustment layer is removed, the second portion of the first work function adjustment layer is protected from being removed by an etching mask.

7. The method according to claim 6, wherein: When the first portion of the barrier layer is thinned, the second portion of the barrier layer is protected by the second portion of the first work function adjusting layer.

8. The method according to claim 1, further comprising: Before forming the first work function adjustment layer, forming a second work function adjustment layer; as well as After forming the second work function adjusting layer, the second work function adjusting layer is patterned to remove a portion of the second work function adjusting layer overlapping the first portion of the barrier layer.

9. A method for manufacturing an integrated circuit device, comprising: removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench, respectively, in the dielectric layer, wherein the first trench and the second trench are respectively in the first transistor region and the second transistor region; depositing a barrier layer, the barrier layer comprising a first portion and a second portion extending into the first trench and the second trench, respectively; depositing a first titanium nitride layer, the first titanium nitride layer comprising a first portion and a second portion overlapping the first portion and the second portion of the barrier layer, respectively; doping aluminum into the first titanium nitride layer; removing the first portion of the first titanium nitride layer, wherein all of the first portion of the first titanium nitride layer in the first trench is removed and the second portion of the first titanium nitride layer in the second trench is not removed; After the first portion of the first titanium nitride layer is removed, partially etching the first portion of the barrier layer to reduce a thickness of the first portion of the barrier layer, wherein a thickness of a portion of the first portion of the barrier layer at a bottom of the first trench is reduced, and the second portion of the barrier layer is protected by the second portion of the first titanium nitride layer; as well as A work function layer is formed, the work function layer including a first portion directly contacting the first portion of the barrier layer and a second portion directly contacting the second portion of the first titanium nitride layer, wherein the work function layer includes aluminum.

10. The method according to claim 9, wherein: The barrier layer further includes a third portion located in a third transistor region, and the first titanium nitride layer further includes a third portion located above the third portion of the barrier layer, and the method further includes: Before forming the first titanium nitride layer, depositing a second titanium nitride layer, the second titanium nitride layer comprising a first portion, a second portion, and a third portion respectively overlapping the first portion, the second portion, and the third portion of the barrier layer; and Before forming the first titanium nitride layer, the first portion and the second portion of the second titanium nitride layer are removed.

11. The method according to claim 10, wherein: Before forming the first titanium nitride layer, no aluminum is doped into the second titanium nitride layer.

12. The method according to claim 9, wherein: Doping the aluminum into the first titanium nitride layer includes thermally immersing the first titanium nitride layer in an aluminum-containing gas.

13. The method according to claim 9, wherein: Partially etching the barrier layer is performed using a metal chloride gas.

14. The method according to claim 9, wherein: When the barrier layer is partially etched, a thickness of a portion of the first portion of the barrier layer at the bottom of the first trench is reduced by a percentage in a range of 50% to 90%.

15. The method according to claim 9, wherein: During the partial etching of the barrier layer, the second portion of the first titanium nitride layer is exposed to the same etching gas used to etch the barrier layer.

16. An integrated circuit device comprising: Semiconductor region; a gate dielectric disposed above the semiconductor region; a barrier layer located above the gate dielectric; A first titanium nitride layer, located above the barrier layer, wherein the first titanium nitride layer further includes aluminum; and A work function layer located above the first titanium nitride layer, wherein the aluminum atomic percentage of the first titanium nitride layer is higher than the aluminum atomic percentage in an overlying layer located above and in contact with the first titanium nitride layer, and higher than the aluminum atomic percentage in an underlying layer located below and in contact with the first titanium nitride layer, wherein the overlying layer is the work function layer and the work function layer includes aluminum.

17. The integrated circuit device of claim 16, further comprising a second titanium nitride layer disposed between the first titanium nitride layer and the barrier layer, wherein: The underlying layer is the second titanium nitride layer.

18. The integrated circuit device according to claim 16, wherein: The work function layer, the first titanium nitride layer, the barrier layer, and the gate dielectric are included in a p-type transistor.

19. The integrated circuit device according to claim 16, wherein: The underlying layer is the barrier layer.

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