A method for preparing a multilayer superjunction semiconductor device

Abstract

The present invention relates to the technical field of manufacturing semiconductor devices, and in particular to a method for preparing a multi-layer super junction semiconductor device, comprising: step S1, performing an epitaxial process on a semiconductor substrate having a first conductive type of impurity to form an epitaxial layer; step S2, depositing a protective layer on the epitaxial layer, and performing an etching process on the epitaxial layer to form a plurality of grooves on the epitaxial layer; step S3, performing an epitaxial process on the plurality of grooves to form a filling area having a second conductive type of impurity; step S4, removing the protective layer, performing a polishing process to make the filling area flush with the upper surface of the epitaxial layer, and the filling area and the epitaxial layer are alternately arranged to form a layer of super junction structure; repeating steps S1 to S4 multiple times to form a composite structure having multiple layers of super junction structure. Beneficial effect: The super junction device formed by the preparation method of the present invention can achieve higher voltage resistance, improve the EMI problem of ultra-high voltage devices, and has a low process cost.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for preparing a multi-layer super junction semiconductor device. Background Art

[0002] Superjunction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is an improved junction proposed on the basis of the traditional planar VDMOS (vertical double diffused metal-oxide semiconductor field-effect transistor) theory. Superjunction devices are used for the epitaxial layer that withstands the voltage. They use an alternating N-type + P-type structure to replace the ordinary single-type epitaxial layer (pure N-type or pure P-type). Using the theory of charge balance, while achieving high voltage resistance, the on-resistance of the product is greatly reduced. Smaller on-resistance means that at the same current density, its chip area is smaller, and the gate charge related to the chip area is correspondingly reduced, so the charging and discharging process of the capacitor is faster. The reduction in chip area not only means that a smaller package can be achieved, but also means a reduction in the switching power consumption of the device, which is very helpful for the miniaturization and energy saving of power products with power MOSFET as the core device.

[0003] The alternatingly arranged NP-type epitaxial layer is the main voltage-bearing layer of the superjunction device, and its forming process is the core process of the superjunction device. In the prior art, the preparation process of super junction structure is mainly divided into two types: (1) multiple epitaxial implantation process. Taking N-type epitaxial layer as an example (i.e. N-type MOS), in order to form a matching P-type structure in the multiple epitaxial process, multiple epitaxial layer growth and P-type ion implantation must be performed. The number of growths is directly proportional to the cost. Although the process cost is relatively high, different implantation doses, energies and other process parameters can be controlled after each epitaxy to form different P-type region distributions at different depths as required, so that the device's capacitance charging and discharging process changes more smoothly during the on-off process, reducing dv / dt and di / dt, and enhancing its anti-EMI (Electro Magnetic Interference) characteristics; (2) deep trench etching and refilling process. Although this process can form a P-type region at one time and has a low process cost, its process difficulty will also increase with the increase of the depth to width ratio of the P-type region (abbreviated as aspect ratio). In addition, if Figure 1 As shown in the figure, the super junction structure formed by the deep trench process has a PN junction concentration and shape formed at one time. The steep trench is more susceptible to voltage when the depletion layer expands, and its capacitance changes more dramatically, causing obvious EMI problems.

[0004] Therefore, in view of the above-mentioned technical problems existing in the preparation process of the prior art, the present invention proposes a novel preparation method for a multi-layer super junction semiconductor device, which can not only solve the problem of high process cost in multiple epitaxial injection processes, but also avoid the obvious EMI problem caused by the deep trench process, thereby enhancing the product's anti-electromagnetic interference capability. Summary of the invention

[0005] In view of the above problems existing in the prior art, a method for preparing a multi-layer super junction semiconductor device is now provided.

[0006] The specific technical solutions are as follows:

[0007] The present invention includes a method for preparing a multilayer superjunction semiconductor device, comprising:

[0008] Step S1, performing an epitaxial process on a semiconductor substrate having first conductivity type impurities to form an epitaxial layer;

[0009] Step S2, depositing a protective layer on the epitaxial layer, and performing an etching process on the epitaxial layer to form a plurality of grooves on the epitaxial layer;

[0010] Step S3, performing the epitaxial process on the plurality of grooves to form a filling region having impurities of the second conductivity type;

[0011] Step S4, removing the protective layer, performing a polishing process to make the filling area and the upper surface of the epitaxial layer flush, and the filling area and the epitaxial layer are alternately arranged to form a super junction structure;

[0012] Repeat steps S1 to S4 a plurality of times to form a composite structure having a plurality of layers of the super junction structure.

[0013] Preferably, it also includes:

[0014] In step S5, a base region, a gate oxide layer, a polysilicon gate, a source region, an interlayer dielectric layer and a metal source layer are sequentially formed on the composite structure, and after a grinding process is performed on the semiconductor structure to reach a preset thickness, a layer of metal is deposited on the back side of the semiconductor substrate to form a metal drain layer.

[0015] Preferably, the composite structure includes three layers of super junction structures: a first layer of super junction structure, a second layer of super junction structure and a third layer of super junction structure.

[0016] Preferably, the impurity concentration of the epitaxial layer of the first super junction structure is less than the impurity concentration of the epitaxial layer of the second super junction structure, and the concentration ratio is in the range of 5% to 15%;

[0017] The impurity concentration of the epitaxial layer of the second super junction structure is less than the impurity concentration of the epitaxial layer of the third super junction structure, and the concentration ratio is in a range of 5% to 15%.

[0018] Preferably, the depth and shape of the plurality of grooves are the same.

[0019] Preferably, the thickness of the epitaxial layer of the first super junction structure is greater than the thickness of the epitaxial layer of the second super junction structure, and the thickness of the epitaxial layer of the second super junction structure is equal to the thickness of the epitaxial layer of the third super junction structure.

[0020] Preferably, a difference between a thickness of the epitaxial layer of the first super junction structure and a thickness of the epitaxial layer of the second super junction structure is not less than 5 μm.

[0021] Preferably, in the same layer of the super junction structure, the impurity concentration of the filling region and the impurity concentration of the epitaxial layer maintain charge balance.

[0022] Preferably, the preset thickness ranges from 200 to 300 μm.

[0023] Preferably, the first conductive type impurity is N-type, and the second conductive type impurity is P-type; and / or

[0024] The first conductive type impurity is P type, and the second conductive type impurity is N type.

[0025] The technical solution of the present invention has the following advantages or beneficial effects: providing a method for preparing a multi-layer super junction semiconductor device, forming a super junction device by multiple epitaxial growth and multiple etching and filling, and the trench depth can reach multiple times the trench depth of the traditional single deep trench process, which can not only achieve higher voltage resistance, but also improve the EMI problem of ultra-high voltage devices; in addition, compared with the traditional multiple epitaxial growth and injection process, the preparation method of the present invention has lower process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The embodiments of the present invention will be described more fully with reference to the attached drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0027] Figure 1 A schematic diagram of the structure of a super junction MOSFET formed by a conventional deep trench process;

[0028] Figure 2 This is a schematic diagram of the structure of the epitaxial layer after the first epitaxy in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the structure of the epitaxial layer after the first etching in an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of the structure of the epitaxial layer after the first filling in an embodiment of the present invention;

[0031] Figure 5 is a schematic diagram of a second layer of super junction structure formed in an embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of a third layer of super junction structure formed in an embodiment of the present invention;

[0033] Figure 7 A schematic diagram of the overall structure of a super junction MOSFET formed by the preparation method in an embodiment of the present invention;

[0034] Figure 8 The depletion layer boundary curve of the super junction MOSFET formed by the traditional deep trench process gradually widens with Vds;

[0035] Fig. 9 A curve variation diagram showing that the depletion layer boundary curve of the super junction MOSFET formed by the preparation method in the embodiment of the present invention gradually widens as Vds;

[0036] Fig.10 is a flow chart of the steps of a method for preparing a single-layer super junction structure in an embodiment of the present invention;

[0037] Reference numerals:

[0038] Semiconductor substrate 1; first epitaxial layer 2a; second epitaxial layer 2b; third epitaxial layer 2c; first filling region 3a; second filling region 3b; third filling region 3c; base region 4; source region 5; gate oxide layer 6; polysilicon gate 7; interlayer dielectric layer 8; metal source layer 9; metal drain layer 10; protective layer 11; groove 12. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0041] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0042] The present invention includes a method for preparing a multilayer superjunction semiconductor device, such as Fig.10 As shown, including:

[0043] Step S1, performing an epitaxial process on a semiconductor substrate 1 having first conductivity type impurities to form an epitaxial layer 2;

[0044] Step S2, depositing a protective layer 11 on the epitaxial layer 2, and performing an etching process on the epitaxial layer 2 to form a plurality of grooves 12 on the epitaxial layer 2;

[0045] Step S3, performing an epitaxial process on the plurality of grooves 12 to form a filling region 3 having impurities of the second conductive type;

[0046] Step S4, removing the protective layer 11, performing a polishing process to make the upper surface of the filling area 3 and the epitaxial layer 2 flush, and the filling area 3 and the epitaxial layer 2 are alternately arranged to form a super junction structure;

[0047] Repeat steps S1 to S4 a plurality of times to form a composite structure having a plurality of layers of super junction structures.

[0048] Specifically, through the above technical solution, and taking into account the process cost and anti-EMI effect of the product, the super junction structure in the embodiment of the present invention is preferably three-layer, including a first epitaxial layer 2a, a second epitaxial layer 2b, and a third epitaxial layer 2c. The first conductive type impurity and the second conductive type impurity in this embodiment are preferably N-type and P-type. The preparation method specifically includes the following steps:

[0049] Step S1, such as Figure 2 , using an epitaxial process, growing a first epitaxial layer 2a on an N-type semiconductor substrate, wherein the concentration of the first epitaxial layer 2a varies according to different voltage requirements;

[0050] Step S2, such as Figure 3 First, a protective layer 11 is deposited on the first epitaxial layer 2a. The material of the protective layer 11 can be preferably silicon oxide Si3N4. The position of the first filling area 3a is etched in the first epitaxial layer 2 by using a photolithography mask process. Under the protection of the protective layer 11, a plurality of grooves 12 are etched in the first epitaxial layer 2 by using a dry etching process. The etching width is between 3 and 5 um, and the etching depth of the first layer groove 12 is not less than the thickness of the second epitaxial layer 2b.

[0051] Step S3, such as Figure 4 , performing an epitaxial process on the groove 12, epitaxially growing a P-type impurity in the groove 12, forming a first layer filling region 3a having a P-type impurity, and the impurity concentration of the first layer filling region 3a maintains charge balance with the impurity concentration of the first epitaxial layer 2a;

[0052] Step S4, after removing the protective layer 11, a polishing process is used to make the upper surface of the first filling region 3a and the first epitaxial layer 2a flush, so as to form a first layer super junction structure in which the first filling region 3a and the first epitaxial layer 2a are alternately arranged;

[0053] Further, after forming the first layer super junction structure, repeat steps S1 to S4 twice, form a second layer super junction structure on the first layer super junction structure, and form a third layer super junction structure on the second layer super junction structure. Use an epitaxial process to grow the second epitaxial layer 2b on the first layer super junction structure (the first layer filling area 3a and the first epitaxial layer 2a), then use a photolithography mask process to etch out a second layer groove, perform an epitaxial process in the second layer groove to perform epitaxial growth of P-type impurities, and form a second layer filling area 3b. Finally, use a polishing process to make the second layer filling area 3b and the upper surface of the second epitaxial layer 2b flush, forming a second layer super junction structure in which the second layer filling area 3b and the second epitaxial layer 2b are alternately arranged ( Figure 5 Similarly, through the above steps S1 to S4, a third super junction structure is formed on the basis of the second super junction structure ( Figure 6 shown).

[0054] Specifically, assuming that the thickness of the first epitaxial layer is a, the thickness of the second epitaxial layer is b, the thickness of the third epitaxial layer is c, and the total thickness of the epitaxial layer of the super junction structure is A, then A=a+b+c. Compared with the traditional single deep trench process, the trench depth of the super junction device in this embodiment can reach three times the trench depth of the traditional single deep trench process, and has a higher withstand voltage capability (above 800V); compared with the traditional multiple epitaxial injection process, the preparation method of the present invention does not need to perform ion injection for each filling area, and only requires one etching filling to form a layer of filling area (each layer contains multiple filling areas), which can effectively reduce the process cost.

[0055] As a preferred embodiment, in order to ensure that after the super junction structure is formed, the PN junction formed by the bottom of the filling region (P-type region) with the second conductive type impurities and the epitaxial layer (N-type region) with the first conductive type impurities is directly or indirectly affected by the high-concentration doped substrate, destroying the charge balance of the epitaxial layer, the thickness of the epitaxial layer of the first super junction structure (the first epitaxial layer 2a) is greater than the thickness of the epitaxial layer of the second super junction structure (the second epitaxial layer 2b), and the difference is not less than 5μm, and the thickness of the epitaxial layer of the second super junction structure (the second epitaxial layer 2b) is equal to the thickness of the epitaxial layer of the third super junction structure (the third epitaxial layer 2c). In addition, in this embodiment, the thickness of the second epitaxial layer 2b is 1 / 3 of the designed trench depth of the super junction semiconductor device.

[0056] In a preferred embodiment, Figure 7As shown, the preparation method also includes: step S5, forming a body region 4 with P-type impurities, a gate oxide layer 6, a polysilicon gate 7, a source region 5 with N-type impurities, an interlayer dielectric layer 8 and a metal source layer 9 in sequence on the composite structure composed of three epitaxial layers, and performing a chemical mechanical polishing process on the semiconductor structure to reach a preset thickness, the preset thickness is preferably 200 to 300 μm, and depositing a layer of metal on the back side of the semiconductor substrate 1, the metal can be selected as Ag (silver), to form a metal drain layer 10.

[0057] In a preferred embodiment, the impurity concentration of the epitaxial layer of the first super junction structure is less than the impurity concentration of the epitaxial layer of the second super junction structure, and the concentration ratio is in the range of 5% to 15%.

[0058] The impurity concentration of the epitaxial layer of the second super junction structure is less than the impurity concentration of the epitaxial layer of the third super junction structure, and the concentration ratio is in the range of 5% to 15%.

[0059] Specifically, in this embodiment, the impurity concentration of the second epitaxial layer 2b is greater than the impurity concentration of the first epitaxial layer 2a, and the impurity concentration of the third epitaxial layer 2c is greater than the impurity concentration of the second epitaxial layer 2b, thereby forming a structure in which the concentration of the epitaxial layer and the concentration of the filling region change simultaneously from bottom to top, which can improve the situation that the product capacitance changes drastically with the voltage between the drain and the source, and enhance the ability of the super junction semiconductor device to resist electromagnetic interference in practical use. It should be noted that, after analysis and verification, if the difference in the impurity concentration of the upper and lower layers is too large, the conversion rate between the two interfaces will be more complicated, and the impurity filling region (P-type region) that needs to be balanced with the epitaxial layer (N-type region) will have a correspondingly increased difficulty in forming the process control, which is not conducive to the stability of product performance; if the concentration change rate is too low, its effect on the capacitance change rate is not obvious, and the improvement of the anti-EMI effect is not good, so the impurity concentration ratio of the adjacent two layers of super junction structure is controlled as much as possible between 5% and 15%, and the process difficulty is reduced as much as possible while improving the anti-EMI effect.

[0060] For power MOSFET, as the width of the depletion layer gradually increases, its capacitance will decrease accordingly. In particular, the expansion of the depletion layer in the epitaxial layer directly affects the drain-source capacitance Cds and the gate-drain capacitance Cgd, while the gate-source capacitance Cgs is less affected. The input capacitance Ciss = Cgs + Cgd, the output capacitance Coss = Cds + Cgd, and the feedback capacitance Crss = Cgd. Figure 8 As shown in the figure, with the increase of drain-source voltage, especially when Vds changes from 0 to 100V, the widening of the depletion layer of the traditional deep trench super junction MOSFET changes dramatically, resulting in a dramatic change in capacitance in this voltage range, which is easily affected by EMI in the circuit system. Fig. 9As shown in FIG. 1 , when the drain-source voltage Vds of the super junction device of the present invention changes from 0 to 100 V, its change curve is obviously better than that of FIG. Figure 8 The change curve is gentle, and its capacitance change rate is relatively gentle, which is beneficial to improving the product's anti-EMI ability.

[0061] Through the above technical solution, epitaxial layers and filling areas with gradually increasing impurity concentrations from bottom to top are used, so that the resistance of the superjunction structure at the lower layer is higher than that of the superjunction structure at the upper layer, and the withstand voltage of the superjunction structure at the lower layer is also higher than that of the upper layer. After the PN junction is formed, according to the PN junction depletion theory, under the action of the drain-source voltage, the PN junction depletion layer at the lower layer will be wider than the depletion layer at the bottom of the epitaxial layer with uniform impurity concentration in the prior art. If the rate of change of the impurity concentration is controlled, the depletion layer of the epitaxial layer can be made more uniform from top to bottom, and the parasitic capacitance associated with the depletion layer can change more smoothly.

[0062] In a preferred embodiment, the depth and shape of the multiple grooves are the same. Specifically, in order to simplify the preparation process, the etching parameters (angle, rate, etc.) of the three layers of grooves are kept consistent, and the depth and shape of the three layers of grooves 12 are the same, all of which are trapezoids that are wide at the top and narrow at the bottom. When filling three different layers of grooves 12, the same process parameters can also be used. It is only necessary to adjust the concentration of the filled impurities during filling, wherein the impurity concentration of the first layer filling area 3a should be less than the impurity concentration of the second layer filling area 3b, and the impurity concentration of the second layer filling area 3b should be less than the impurity concentration of the third layer filling area 3c. The concentration change is the same as the concentration change of the epitaxial layer, and the rate of change of the impurity concentration is controlled between 5% and 15%. Through the above technical solution, the preparation process can be effectively simplified and the production cost can be reduced.

[0063] The beneficial effects of the embodiments of the present invention are: providing a method for preparing a multi-layer super junction semiconductor device, forming a super junction device by multiple epitaxial growth and multiple etching and filling, and the trench depth can reach multiple times the trench depth of the traditional single deep trench process, which can not only achieve higher voltage resistance, but also improve the EMI problem of ultra-high voltage devices; in addition, compared with the traditional multiple epitaxial growth and injection process, the preparation method of the present invention has lower process cost.

[0064] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a multilayer superjunction semiconductor device, characterized in that: include: Step S1, performing an epitaxial process on a semiconductor substrate having first conductivity type impurities to form an epitaxial layer; Step S2, depositing a protective layer on the epitaxial layer, and performing an etching process on the epitaxial layer to form a plurality of grooves on the epitaxial layer; Step S3, performing the epitaxial process on the plurality of grooves to form a filling region having impurities of the second conductivity type; Step S4, removing the protective layer, performing a polishing process to make the filling area and the upper surface of the epitaxial layer flush, and the filling area and the epitaxial layer are alternately arranged to form a super junction structure; Repeating steps S1 to S4 a plurality of times to form a composite structure having a plurality of layers of the super junction structure; The composite structure comprises three layers of super junction structures: a first layer of super junction structure, a second layer of super junction structure and a third layer of super junction structure, the second layer of super junction structure is formed on the first layer of super junction structure, and the third layer of super junction structure is formed on the second layer of super junction structure; The impurity concentration of the epitaxial layer of the first super junction structure is less than the impurity concentration of the epitaxial layer of the second super junction structure, and the concentration ratio is in the range of 5% to 15%; The impurity concentration of the epitaxial layer of the second super junction structure is less than the impurity concentration of the epitaxial layer of the third super junction structure, and the concentration ratio is in the range of 5% to 15%; A structure is formed in which the concentration of the epitaxial layer and the concentration of the filling region change simultaneously from bottom to top.

2. The preparation method according to claim 1, characterized in that: Also includes: In step S5, a base region, a gate oxide layer, a polysilicon gate, a source region, an interlayer dielectric layer and a metal source layer are sequentially formed on the composite structure, and after a grinding process is performed on the semiconductor structure to reach a preset thickness, a layer of metal is deposited on the back side of the semiconductor substrate to form a metal drain layer.

3. The preparation method according to claim 1, characterized in that: The depth and shape of the plurality of grooves are the same.

4. The preparation method according to claim 1, characterized in that: The thickness of the epitaxial layer of the first super junction structure is greater than the thickness of the epitaxial layer of the second super junction structure, and the thickness of the epitaxial layer of the second super junction structure is equal to the thickness of the epitaxial layer of the third super junction structure.

5. The preparation method according to claim 4, characterized in that: A difference between a thickness of the epitaxial layer of the first super junction structure and a thickness of the epitaxial layer of the second super junction structure is not less than 5 μm.

6. The preparation method according to claim 1, characterized in that: In the same layer of the super junction structure, the impurity concentration of the filling region and the impurity concentration of the epitaxial layer maintain charge balance.

7. The preparation method according to claim 2, characterized in that: The preset thickness ranges from 200 to 300 μm.

8. The preparation method according to claim 2, characterized in that: The first conductive type impurity is N-type, and the second conductive type impurity is P-type; or The first conductive type impurity is P type, and the second conductive type impurity is N type.

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