wiring structure

Abstract

A wiring structure includes an upper conductive structure, a lower conductive structure, and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The at least one lower dielectric layer of the lower conductive structure is substantially free of glass fibers. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and joins the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.

Description

Technical Field

[0001] This disclosure relates to a wiring structure and a method of manufacturing, and more particularly to a wiring structure comprising at least two conductive structures attached together by an intermediate layer, and a method for manufacturing said wiring structure. Background Technology

[0002] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips integrate an increasing number of electronic components to achieve better electrical performance and more functions. Correspondingly, semiconductor chips have more input / output (I / O) connections. To manufacture semiconductor packages containing semiconductor chips with an increased number of I / O connections, the circuit layers of the semiconductor substrate supporting the semiconductor chips may need to be increased accordingly. Therefore, the thickness of the semiconductor substrate may increase, and the yield of the semiconductor substrate may decrease. Summary of the Invention

[0003] In some embodiments, a wiring structure includes: (a) an upper conductive structure comprising at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer; (b) a lower conductive structure comprising at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer, wherein the at least one lower dielectric layer of the lower conductive structure is substantially free of glass fiber; and (c) an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure.

[0004] In some embodiments, a wiring structure includes: (a) an upper conductive structure comprising at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer; (b) a lower conductive structure comprising at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer; and (c) an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure, the coefficient of thermal expansion of the upper conductive structure is less than the coefficient of thermal expansion of the intermediate layer, and the coefficient of thermal expansion of the intermediate layer is less than the coefficient of thermal expansion of the lower conductive structure.

[0005] In some embodiments, a wiring structure includes: (a) a low-density stack structure comprising at least one dielectric layer and at least one low-density circuit layer in contact with the dielectric layer, wherein the at least one dielectric layer of the low-density stack structure comprises a first insulating film; (b) a high-density stack structure disposed on the low-density stack structure, wherein the high-density stack structure comprises at least one dielectric layer and at least one high-density circuit layer in contact with the dielectric layer of the high-density stack structure; and (c) an intermediate layer disposed between the low-density stack structure and the high-density stack structure and bonding the low-density stack structure and the high-density stack structure together, wherein the low-density stack structure is electrically connected to the high-density stack structure, and the intermediate layer comprises a second insulating film. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of some embodiments of this disclosure can be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0008] Figure 2 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0009] Figure 2A A top view showing an example of a reference mark of the upper conductive structure of some embodiments of this disclosure.

[0010] Figure 2B A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of this disclosure.

[0011] Figure 2C show Figure 2A The reference mark of the upper conductive structure and Figure 2B A top view of a composite image of the reference marks on the lower conductive structure.

[0012] Figure 2D A top view showing an example of a reference mark of the upper conductive structure of some embodiments of this disclosure.

[0013] Figure 2E A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of this disclosure.

[0014] Figure 2F show Figure 2D The reference mark of the upper conductive structure and Figure 2E A top view of a composite image of the reference marks on the lower conductive structure.

[0015] Figure 2G A top view showing an example of a reference mark of the upper conductive structure of some embodiments of this disclosure.

[0016] Figure 2H A top view showing an example of a reference mark of a lower conductive structure according to some embodiments of this disclosure.

[0017] Figure 2I show Figure 2G The reference mark of the upper conductive structure and Figure 2H A top view of a composite image of the reference marks on the lower conductive structure.

[0018] Figure 3 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0019] Figure 4 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0020] Figure 5 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0021] Figure 6 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0022] Figure 7 A cross-sectional view showing the connection between the package structure and the substrate.

[0023] Figure 8 A cross-sectional view showing the connection between the package structure and the substrate.

[0024] Figure 9 Cross-sectional views showing wiring structures of some embodiments of this disclosure.

[0025] Figure 10 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0026] Figure 11 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0027] Figure 12 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0028] Figure 13 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0029] Figure 14This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0030] Figure 15 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0031] Figure 16 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0032] Figure 17 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0033] Figure 18 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0034] Figure 19 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0035] Figure 20 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0036] Figure 21 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0037] Figure 22 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0038] Figure 23 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0039] Figure 24 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0040] Figure 25 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0041] Figure 26 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0042] Figure 27 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0043] Figure 28This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0044] Figure 29 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0045] Figure 30 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0046] Figure 31 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0047] Figure 32 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0048] Figure 33 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0049] Figure 34 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0050] Figure 35 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0051] Figure 36 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0052] Figure 37 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0053] Figure 38 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0054] Figure 39 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0055] Figure 40 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0056] Figure 41 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0057] Figure 42This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0058] Figure 43 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0059] Figure 44 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0060] Figure 45 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0061] Figure 46 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0062] Figure 47 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0063] Figure 48 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0064] Figure 49 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0065] Figure 50 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0066] Figure 51 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0067] Figure 52 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0068] Figure 53 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0069] Figure 54 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures.

[0070] Figure 55 This disclosure shows one or more stages of some embodiments of the method for manufacturing wiring structures. Detailed Implementation

[0071] Throughout the drawings and detailed description, common reference numerals are used to indicate the same or similar components. Embodiments of this disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0072] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0073] To meet the requirements of increased I / O count, the number of dielectric layers on the substrate must be increased. In some embodiments, the manufacturing process of the core substrate may include the following steps. First, a core with two copper foils disposed on both sides of the core is provided. Subsequently, multiple dielectric layers and multiple circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in one dielectric layer. Therefore, the core substrate may include multiple stacked dielectric layers and multiple circuit layers embedded in the dielectric layers on both sides of the core. Because the line width / line space (L / S) of the circuit layers of such a core substrate can be greater than or equal to 10 micrometers (μm) / 10 μm, the number of dielectric layers of such a core substrate must be relatively large. Although the manufacturing cost of such a core substrate is lower, the manufacturing yield of the circuit layers and dielectric layers of such a core substrate is also lower, thus the yield of such a core substrate is low. In addition, the dielectric layers are relatively thick, therefore, such a core substrate is relatively thick. In a comparative embodiment, if the package has 10,000 I / O counts, then such a core substrate may require twelve layers of circuit layers and dielectric layers. The manufacturing yield of one layer (comprising a circuit layer and a dielectric layer) of this type of core substrate can be 90%. Therefore, the yield of this type of core substrate can be (0.9). 12 =28.24%. Furthermore, the warpage of the twelve circuit and dielectric layers can accumulate, potentially resulting in severe warpage in the top few layers. Consequently, the manufacturing yield of such core substrates may be even lower.

[0074] To address the above issues, in some embodiments, a coreless substrate is provided. The coreless substrate may include multiple dielectric layers and multiple fan-out circuit layers. In some embodiments, the fabrication process of the coreless substrate may include the following steps: First, a carrier is provided. Subsequently, multiple dielectric layers and multiple fan-out circuit layers are formed or stacked on the surface of the carrier. A fan-out circuit layer may be embedded within a dielectric layer. Subsequently, the carrier is removed. Therefore, the coreless substrate may consist only of multiple stacked dielectric layers and multiple fan-out circuit layers embedded within the dielectric layers. Because the linewidth / spacing (L / S) of the fan-out circuit layers in such a coreless substrate can be less than or equal to 2 μm / 2 μm, the number of dielectric layers in such a coreless substrate can be reduced. Furthermore, the fabrication yield of the fan-out circuit layers and dielectric layers in such a coreless substrate is high. For example, the fabrication yield of one layer (including one fan-out circuit layer and one dielectric layer) in such a coreless substrate can be 99%. However, the fabrication cost of such a coreless substrate is relatively high.

[0075] At least some embodiments of this disclosure provide wiring structures with an acceptable trade-off between yield and manufacturing cost. In some embodiments, the wiring structure includes an upper conductive structure and a lower conductive structure bonded to the upper conductive structure via an intermediate layer. At least some embodiments of this disclosure further provide techniques for manufacturing the wiring structures.

[0076] Figure 1 This diagram shows a cross-sectional view of a wiring structure 1 according to some embodiments of the present disclosure. The wiring structure 1 includes an upper conductive structure 2, a lower conductive structure 3, an intermediate layer 12, and at least one upper through via 14.

[0077] The upper conductive structure 2 includes at least one dielectric layer (including, for example, two first dielectric layers 20 and one second dielectric layer 26) and at least one circuit layer (including, for example, three first circuit layers 24 and one second circuit layer 28 formed of metal, metal alloy or other conductive material) in contact with the dielectric layer (e.g., the first dielectric layer 20 and the second dielectric layer 26). The dielectric layer (including, for example, two first dielectric layers 20 and one second dielectric layer 26) may be referred to as the upper dielectric layer, and the circuit layer (including, for example, three first circuit layers 24 and one second circuit layer 28) may be referred to as the upper circuit layer. In one embodiment, the upper conductive structure 2 may resemble a coreless substrate and may be wafer-type, panel-type or strip-type. In some embodiments, the upper conductive structure 2 may resemble a coreless substrate and may be wafer-type, panel-type or strip-type. The upper conductive structure 2 may also be referred to as a "stacked structure" or a "high-density conductive structure" or a "high-density stacked structure". The circuit layer of the upper conductive structure 2 (comprising, for example, three circuit layers 24) may also be referred to as a "high-density circuit layer". In some embodiments, the density of circuit lines (including, for example, traces or pads) in the high-density circuit layer is greater than the density of circuit lines in the low-density circuit layer. That is, the count of circuit lines (including, for example, traces or pads) per unit area of ​​the high-density circuit layer is greater than the count of circuit lines per unit area of ​​the low-density circuit layer, for example, about 1.2 times or more, about 1.5 times or more, or about 2 times or more. Alternatively or in combination, the linewidth / spacing (L / S) of the high-density circuit layer is smaller than the L / S of the low-density circuit layer, for example, about 90% or less, about 50% or less, or about 20% or less. In addition, a conductive structure containing a high-density circuit layer may be designated as a "high-density conductive structure", and a conductive structure containing a low-density circuit layer may be designated as a "low-density conductive structure".

[0078] The upper conductive structure 2 has a top surface 21 and a bottom surface 22 opposite to the top surface 21, and defines at least one through hole 23. Each through hole 23 is a single and continuous through hole. The upper conductive structure 2 includes multiple dielectric layers (e.g., two first dielectric layers 20 and one second dielectric layer 26), multiple circuit layers (e.g., three first circuit layers 24 and one second circuit layer 28), and at least one inner via 25. The dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) are stacked on top of each other. For example, the second dielectric layer 26 is disposed on the first dielectric layer 20, and therefore, the second dielectric layer 26 is the topmost dielectric layer. In one embodiment, the material of the dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) is transparent and can be seen through by the human eye or a machine. That is, a marking set adjacent to the bottom surface 22 of the upper conductive structure 2 can be identified or detected by the human eye or a machine from the top surface 21 of the upper conductive structure 2. In some embodiments, the transparent material of the dielectric layer has a transmittance of at least about 60%, at least about 70%, or at least about 80% for wavelengths in the visible range (or other relevant wavelengths for detecting the marker).

[0079] Furthermore, each first dielectric layer 20 has a top surface 201 and a bottom surface 202 opposite to the top surface 201, and defines a through-hole 203 having an inner surface 2031. The second dielectric layer 26 has a top surface 261 and a bottom surface 262 opposite to the top surface 261, and defines a through-hole 263 having an inner surface 2631. The bottom surface 262 of the second dielectric layer 26 is disposed on and in contact with the top surface 201 of the adjacent first dielectric layer 20. Therefore, the top surface 21 of the upper conductive structure 2 is the top surface 261 of the second dielectric layer 26, and the bottom surface 22 of the upper conductive structure 2 is the bottom surface 202 of the bottommost first dielectric layer 20.

[0080] like Figure 1As shown, each via 203 of the first dielectric layer 20 tapers downwards along the direction from the top surface 21 of the upper conductive structure 2 toward the bottom surface 22, meaning the size of the top portion of the via 203 is larger than the size of the bottom portion. The via 263 of the second dielectric layer 26 also tapers downwards, meaning the size of the top portion of the via 263 is larger than the size of the bottom portion. Furthermore, the via 263 of the second dielectric layer 26 is aligned with and communicates with the via 203 of the first dielectric layer 20. The bottom portion of the via 263 of the second dielectric layer 26 is adjacent to or connected to the top portion of the via 203 of the first dielectric layer 20 beneath the second dielectric layer 26. The size of the bottom portion of the via 263 of the second dielectric layer 26 is substantially equal to the size of the top portion of the via 203 of the first dielectric layer 20 beneath the second dielectric layer 26. Therefore, the inner surface 2631 of the via 263 of the second dielectric layer 26 is coplanar or aligned with the inner surface 2031 of the via 203 of the first dielectric layer 20. It should be noted that the aforementioned "coplanar" surfaces do not necessarily need to be flat. In some embodiments, the inner surfaces 2631 of the via 263 of the second dielectric layer 26 and the inner surfaces 2031 of the via 203 of the first dielectric layer 20 are curved surfaces and are portions of the inner surface 231 of a single, continuous via 23 for accommodating the upper through-hole 14. The via 263 of the second dielectric layer 26 and the via 203 of the first dielectric layer 20 are collectively configured as part of a single via 23. Figure 1 As shown, the cross-sections of the inner surface 2631 of the via 263 in the second dielectric layer 26 and one side of the inner surface 2031 of the via 203 in the first dielectric layer 20 are substantially straight line segments. That is, the cross-sections of the inner surface 2631 of the via 263 in the second dielectric layer 26 and one side of the inner surface 2031 of the via 203 in the first dielectric layer 20 can extend along the same substantially straight line. A single via 23 penetrates the upper conductive structure 2; that is, the single via 23 extends from the top surface 21 of the upper conductive structure 2 to the bottom surface 22 of the upper conductive structure 2. The single via 23 gradually narrows downwards.

[0081] The first circuit layer 24 may be a fan-out circuit layer or a redistribution layer (RDL), and the L / S ratio of the first circuit layer 24 may be less than or equal to 2μm / 2μm, or less than or equal to 1.8μm / 1.8μm. Each first circuit layer 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. In some embodiments, the first circuit layer 24 is embedded in a corresponding first dielectric layer 20, and the top surface 241 of the first circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. In some embodiments, the first circuit layer 24 may include a seed layer 243 and a conductive metal material 244 disposed on the seed layer 243. Figure 1 As shown, the bottommost first circuit layer 24 is disposed on the bottom surface 22 of the upper conductive structure 2 (i.e., the bottom surface 202 of the bottommost first dielectric layer 20) and protrudes from the bottom surface 22. Furthermore, the second circuit layer 28 is disposed on the top surface 21 of the upper conductive structure 2 (i.e., the top surface 261 of the second dielectric layer 26) and protrudes from the top surface 21. The L / S ratio of the second circuit layer 28 can be greater than or equal to the L / S ratio of the first circuit layer 24. Figure 1 As shown in the embodiment, there are no horizontally connected or extended circuit layers in the second dielectric layer 26.

[0082] The upper conductive structure 2 includes a plurality of internal vias 25. Some internal vias 25 are disposed between two first circuit layers 24 to electrically connect the two first circuit layers 24. Some internal vias 25 are disposed between the first circuit layer 24 and the second circuit layer 28 to electrically connect the first circuit layer 24 and the second circuit layer 28. In some embodiments, the internal vias 25 may include a seed layer 251 and a conductive metal material 252 disposed on the seed layer 251. In some embodiments, the internal vias 25 and the corresponding first circuit layers 24 may be integrally formed as a monolithic or single-piece structure. Each internal via 25 gradually narrows upward along the direction from the bottom surface 22 of the upper conductive structure 2 toward the top surface 21. That is, the size (e.g., width) of the top portion of the internal via 25 is smaller than the size (e.g., width) of the bottom portion of the internal via 25 closer to the bottom surface 22. In some embodiments, the maximum width of the internal guide hole 25 (e.g., at the bottom portion) may be less than or equal to about 25 μm, such as about 25 μm, about 20 μm, about 15 μm or about 10 μm.

[0083] The lower conductive structure 3 includes at least one dielectric layer (including, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) and at least one circuit layer (including, for example, a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a') that contacts the dielectric layer (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a), which is formed of metal, metal alloy, or other conductive material. In some embodiments, the lower conductive structure 3 may resemble a core substrate, further including a core portion 37, and may be wafer-type, panel-type, or strip-type.

[0084] The lower conductive structure 3 has a top surface 31 and a bottom surface 32 opposite to the top surface 31. The lower conductive structure 3 includes multiple dielectric layers (e.g., a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a), multiple circuit layers (e.g., a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a'), and at least one internal via (including, for example, multiple upper vias 35 and multiple lower vias 35a). The lower conductive structure 3 may also be referred to as a "stacked structure," a "low-density conductive structure," or a "low-density stacked structure." The circuit layer of the lower conductive structure 3 (including, for example, a first upper circuit layer 34; two second upper circuit layers 38, 38'; a first lower circuit layer 34a; and two second lower circuit layers 38a, 38a') can also be referred to as a "low-density circuit layer". For example... Figure 1 As shown, the lower conductive structure 3 has a top surface 31 and a bottom surface 32 opposite to the top surface 31. The lower conductive structure 3 includes multiple dielectric layers (e.g., a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a and a second lower dielectric layer 36a), multiple circuit layers (e.g., a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a and two second lower circuit layers 38a, 38a'), and at least one internal via (including, for example, multiple upper interconnect vias 35 and multiple lower interconnect vias 35a).

[0085] In some embodiments, the core portion 37 of the lower conductive structure 3 is substantially free of reinforcement material, such as glass fiber. That is, the core portion 37 of the lower conductive structure 3 may not contain reinforcement material such as glass fiber and may contain a homogeneous material component of resin. Alternatively, the core portion 37 of the lower conductive structure 3 may contain a small amount of reinforcement material, such as glass fiber, for example, about 5% or less, about 3% or less, or about 2% or less. In addition, the material of the core portion 37 may contain an insulating film, such as Ajinomoto build-up film (ABF). Furthermore, the Young's modulus of the core portion 37 of the lower conductive structure 3 may be greater than or equal to about 4.0 GPa at 23°C, for example, about 4.0 GPa or greater at 23°C, about 5.0 GPa or greater at 23°C, or about 7.5 GPa or greater at 23°C.

[0086] The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371, and defines a plurality of through-holes 373 extending through the core portion 37. Interconnection vias 39 are disposed or formed in each through-hole 373 for vertical connection. In some embodiments, each interconnection via 39 includes a base metal layer 391 and an insulating material 392. The base metal layer 391 is disposed or formed on the sidewall of the through-hole 373 and defines a central through-hole. The insulating material 392 fills the central through-hole defined by the base metal layer 391. In some embodiments, the insulating material may be omitted from the interconnection via 39, and it may comprise a bulk metal material filling the through-hole 373.

[0087] In some embodiments, at least one dielectric layer of the lower conductive structure 3 (comprising, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) is substantially free of reinforcing materials such as glass fibers. That is, the dielectric layer of the lower conductive structure 3 (comprising, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) may not contain reinforcing materials such as glass fibers and may contain a homogeneous material composition of resin. Alternatively, the dielectric layer of the lower conductive structure 3 (comprising, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) may contain, for example, a small amount of reinforcing material such as glass fibers, such as about 5% by weight or less, about 3% by weight or less, or about 2% by weight or less. Additionally, the dielectric layer of the lower conductive structure 3 (comprising, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) may contain an insulating film, such as ABF. Furthermore, the Young's modulus of the dielectric layer of the lower conductive structure 3 (comprising, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) may be greater than or equal to approximately 4.0 GPa at 23°C, for example, approximately 4.0 GPa or greater at 23°C, approximately 5.0 GPa or greater at 23°C, or approximately 7.5 GPa or greater at 23°C. In some embodiments, the lower conductive structure 3 may be a resin-coated copper-foil (RCC) substrate. The entire lower conductive structure 3 may be substantially free of reinforcing materials such as glass fibers.

[0088] A first upper dielectric layer 30 is disposed on the top surface 371 of the core portion 37, and has a top surface 301 and a bottom surface 302 opposite to the top surface 301. Therefore, the bottom surface 302 of the first upper dielectric layer 30 contacts the top surface 371 of the core portion 37. A second upper dielectric layer 36 is stacked or disposed on the first upper dielectric layer 30, and has a top surface 361 and a bottom surface 362 opposite to the top surface 361. Therefore, the bottom surface 362 of the second upper dielectric layer 36 contacts the top surface 301 of the first upper dielectric layer 30, and the second upper dielectric layer 36 is the topmost dielectric layer. Additionally, a first lower dielectric layer 30a is disposed on the bottom surface 372 of the core portion 37, and has a top surface 301a and a bottom surface 302a opposite to the top surface 301a. Therefore, the top surface 301a of the first lower dielectric layer 30a contacts the bottom surface 372 of the core portion 37. The second lower dielectric layer 36a is stacked or disposed on the first lower dielectric layer 30a, and has a top surface 361a and a bottom surface 362a opposite to the top surface 361a. Therefore, the top surface 361a of the second lower dielectric layer 36a contacts the bottom surface 302a of the first lower dielectric layer 30a, and the second lower dielectric layer 36a is the bottommost dielectric layer. Figure 1 As shown, the top surface 31 of the lower conductive structure 3 is the top surface 361 of the second upper dielectric layer 36, and the bottom surface 32 of the lower conductive structure 3 is the bottom surface 362a of the second lower dielectric layer 36a.

[0089] The thickness of each dielectric layer of the upper conductive structure 2 (e.g., the first dielectric layer 20 and the second dielectric layer 26) is less than or equal to about 40%, less than or equal to about 35%, and less than or equal to about 30% of the thickness of each dielectric layer of the lower conductive structure 3 (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a). For example, the thickness of each dielectric layer of the upper conductive structure 2 (e.g., the first dielectric layer 20 and the second dielectric layer 26) may be less than or equal to about 7 μm, and the thickness of each dielectric layer of the lower conductive structure 3 (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a) may be about 40 μm.

[0090] The L / S ratio of the first upper circuit layer 34 can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first upper circuit layer 34 can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2. The first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In some embodiments, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37 and is covered by the first upper dielectric layer 30. The bottom surface 342 of the first upper circuit layer 34 contacts the top surface 371 of the core portion 37. In some embodiments, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be formed of copper foil (e.g., may constitute part of copper foil). The second metal layer 344 is disposed on the first metal layer 343 and may be a copper-plated layer. The third metal layer 345 is disposed on the second metal layer 344 and may be another copper-plated layer. In some embodiments, the third metal layer 345 may be omitted.

[0091] The L / S ratio of the second upper circuit layer 38 can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second upper circuit layer 38 can be approximately equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2. The second upper circuit layer 38 has a top surface 381 and a bottom surface 382 opposite to the top surface 381. In some embodiments, the second upper circuit layer 38 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 and is covered by the second upper dielectric layer 36. The bottom surface 382 of the second upper circuit layer 38 contacts the top surface 301 of the first upper dielectric layer 30. In some embodiments, the second upper circuit layer 38 is electrically connected to the first upper circuit layer 34 through an upper interconnect via 35. That is, the upper interconnect via 35 is disposed between the second upper circuit layer 38 and the first upper circuit layer 34 for electrically connecting the second upper circuit layer 38 and the first upper circuit layer 34. In some embodiments, the second upper circuit layer 38 and the upper interconnect via 35 are integrally formed as a single block or single piece structure. Each upper interconnect via 35 gradually narrows downwards from the top surface 31 of the lower conductive structure 3 toward the bottom surface 32.

[0092] Additionally, in some embodiments, the second upper circuit layer 38' is disposed on and protrudes from the top surface 361 of the second upper dielectric layer 36. In some embodiments, the second upper circuit layer 38 is electrically connected to the second upper circuit layer 38' via an upper interconnect via 35. That is, the upper interconnect via 35 is disposed between the second upper circuit layers 38 and 38' to electrically connect the second upper circuit layers 38 and 38'. In some embodiments, the second upper circuit layer 38' and the upper interconnect via 35 are integrally formed as a single piece or monolithic structure.

[0093] The L / S ratio of the first lower circuit layer 34a can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first lower circuit layer 34a can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2. The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In some embodiments, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37 and is covered by the first lower dielectric layer 30a. The top surface 341a of the first lower circuit layer 34a contacts the bottom surface 372 of the core portion 37. In some embodiments, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be formed of copper foil. The second metal layer 344a is disposed on the first metal layer 343a and may be a copper-plated layer. The third metal layer 345a is disposed on the second metal layer 344a and may be another copper-plated layer. In some embodiments, the third metal layer 345a may be omitted.

[0094] The L / S ratio of the second lower circuit layer 38a can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second lower circuit layer 38a can be approximately equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2. The second lower circuit layer 38a has a top surface 381a and a bottom surface 382a opposite to the top surface 381a. In some embodiments, the second lower circuit layer 38a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a and is covered by the second lower dielectric layer 36a. The top surface 381a of the second lower circuit layer 38a contacts the bottom surface 302a of the first lower dielectric layer 30a. In some embodiments, the second lower circuit layer 38a is electrically connected to the first lower circuit layer 34a through a lower interconnect via 35a. That is, the lower interconnect via 35a is disposed between the second lower circuit layer 38a and the first lower circuit layer 34a for electrically connecting the second lower circuit layer 38a and the first lower circuit layer 34a. In some embodiments, the second lower circuit layer 38a and the lower interconnect via 35a are integrally formed as a single block or single piece structure. The lower interconnect via 35a gradually narrows upwards along the direction from the bottom surface 32 of the lower conductive structure 3 toward the top surface 31.

[0095] In some embodiments, the second lower circuit layer 38a' is disposed on and protrudes from the bottom surface 362a of the second lower dielectric layer 36a. In some embodiments, the second lower circuit layer 38a' is electrically connected to the second lower circuit layer 38a via a lower interconnect via 35a. That is, the lower interconnect via 35a is disposed between the second lower circuit layers 38a and 38a' for electrically connecting the second lower circuit layers 38a and 38a'. In some embodiments, the second lower circuit layer 38a' and the lower interconnect via 35a are integrally formed as a single piece or a single component structure.

[0096] In some embodiments, each interconnect via 39 is electrically connected to the first upper circuit layer 34 and the first lower circuit layer 34a. The base metal layer 391 of the interconnect via 39, the second metal layer 344 of the first upper circuit layer 34, and the second metal layer 344a of the first lower circuit layer 34a can be integrally and simultaneously formed as a single block or a single piece structure.

[0097] An intermediate layer 12 is inserted or disposed between the upper conductive structure 2 and the lower conductive structure 3 to bond the upper conductive structure 2 and the lower conductive structure 3 together. That is, the intermediate layer 12 adheres to the bottom surface 22 of the upper conductive structure 2 and the top surface 31 of the lower conductive structure 3. In some embodiments, the intermediate layer 12 may be an adhesive layer cured from an adhesive material (e.g., a cured adhesive material, such as an adhesive polymer). The intermediate layer 12 has a top surface 121 and a bottom surface 122 opposite to the top surface 121, and defines at least one first through-hole 123 having an inner surface 1241. The top surface 121 of the intermediate layer 12 contacts the bottom surface 22 of the upper conductive structure 2 (that is, the bottom surface 22 of the upper conductive structure 2 is attached to the top surface 121 of the intermediate layer 12), and the bottom surface 122 of the intermediate layer 12 contacts the top surface 31 of the lower conductive structure 3. Therefore, the bottommost first circuit layer 24a (e.g., first circuit layer 24a) of the upper conductive structure 2 and the topmost circuit layer 38' (e.g., second upper circuit layer 38') of the lower conductive structure 3 are embedded in the intermediate layer 12. In some embodiments, the bonding force between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2 is greater than the bonding force between the dielectric layer (e.g., the bottommost first dielectric layer 20) of the upper conductive structure 2 and the intermediate layer 12. The surface roughness of the boundary between the two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2 is greater than the surface roughness of the boundary between the dielectric layer (e.g., the bottommost first dielectric layer 20) of the upper conductive structure 2 and the intermediate layer 12, for example, in terms of root mean squared surface roughness, about 1.1 times or more, about 1.3 times or more, or about 1.5 times or more.

[0098] In some embodiments, the material of the intermediate layer 12 is transparent and can be seen through by the human eye or a machine. That is, markings disposed adjacent to the top surface 31 of the lower conductive structure 3 can be identified or detected by the human eye or a machine from the top surface 21 of the upper conductive structure 2. In some embodiments, the intermediate layer 12 is substantially free of reinforcing materials such as glass fibers. That is, the intermediate layer 12 may not contain reinforcing materials such as glass fibers and may contain a homogeneous material composition of resin. Alternatively, the intermediate layer 12 may contain a small amount of reinforcing material, such as glass fibers, for example, about 5% by weight or less, about 3% by weight or less, or about 2% by weight or less. In addition, the material of the intermediate layer 12 may contain an insulating film, such as ABF. Furthermore, the Young's modulus of the intermediate layer 12 may be greater than or equal to about 4.0 GPa at 23°C, for example, about 4.0 GPa or greater at 23°C, about 5.0 GPa or greater at 23°C, or about 7.5 GPa or greater at 23°C.

[0099] In some embodiments, both the intermediate layer 12 and the lower conductive structure 3 may comprise an insulating film material, such as an ABF-type material. Furthermore, the coefficient of thermal expansion (CTE) of the upper conductive structure 2 is less than the CTE of the intermediate layer 12, and the CTE of the intermediate layer 12 is less than the CTE of the lower conductive structure 3. Therefore, the CTE value of the intermediate layer 12 lies between the CTE values ​​of the upper conductive structure 2 and the lower conductive structure 3. In some embodiments, the CTE of the intermediate layer 12 may be less than the CTE of the lower conductive structure 3 but greater than or equal to about 0.8 times (e.g., greater than or equal to about 0.85 times, about 0.9 times, or about 0.95 times) of the lower conductive structure 3. Therefore, the CTE of the intermediate layer 12 is close to the CTE of the lower conductive structure 3. This reduces delamination between the intermediate layer 12 and the lower conductive structure 3. Additionally, in some embodiments, the CTE of the upper conductive structure 2 may be less than the CTE of the intermediate layer 12 but greater than or equal to about 0.8 times the CTE of the intermediate layer 12 (e.g., greater than or equal to about 0.85 times, about 0.9 times, or about 0.95 times). Therefore, the CTE of the upper conductive structure 2 is close to the CTE of the intermediate layer 12. This reduces delamination between the upper conductive structure 2 and the intermediate layer 12.

[0100] The via 123 extends through the intermediate layer 12. In some embodiments, the via 123 of the intermediate layer 12 may extend through the bottom first circuit layer 24 of the upper conductive structure 2 and terminate at or above the top circuit layer of the lower conductive structure 3 (e.g., the second upper circuit layer 38'). That is, the via 123 of the intermediate layer 12 does not extend through the top circuit layer of the lower conductive structure 3 (e.g., the second upper circuit layer 38'). The via 123 of the intermediate layer 12 may expose a portion of the top circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38').

[0101] like Figure 1As shown, the via 123 of the intermediate layer 12 gradually narrows downwards from the top surface 121 to the bottom surface 122 of the intermediate layer 12; that is, the size of the top portion of the via 123 is larger than the size of the bottom portion of the via 123. Furthermore, the via 123 of the intermediate layer 12 is aligned with and communicates with the via 203 of the first dielectric layer 20 and the via 263 of the second dielectric layer 26. The bottom portion of the via 203 of the bottommost first dielectric layer 20 is positioned adjacent to or connected to the top portion of the via 123 of the intermediate layer 12. The size of the bottom portion of the via 203 of the bottommost first dielectric layer 20 is approximately equal to the size of the top portion of the via 123 of the intermediate layer 12. Therefore, the inner surface 1231 of the via 123 of the intermediate layer 12 is coplanar or aligned with the inner surface 2031 of the via 203 of the first dielectric layer 20 and the inner surface 2631 of the via 263 of the second dielectric layer 26. In some embodiments, the inner surface 1231 of the via 123 of the intermediate layer 12 may be a curved surface and is part of the inner surface 231 of a single continuous via 23 for receiving the upper through-hole 14. The via 123 of the intermediate layer 12, the via 203 of the first dielectric layer 20, and the via 263 of the second dielectric layer 26 are configured together to form or define a single via 23. Therefore, a single via 23 includes the via 123 of the intermediate layer 12, the via 203 of the first dielectric layer 20, and the via 263 of the second dielectric layer 26.

[0102] like Figure 1 As shown, the cross-sectional views of the via 123 of the intermediate layer 12, the inner surface 2031 of the via 203 of the first dielectric layer 20, and one side of the inner surface 2631 of the via 263 of the second dielectric layer 26 are generally straight segments. That is, the cross-sectional views of the inner surface 1231 of the via 123 of the intermediate layer 12, the inner surface 2031 of the via 203 of the first dielectric layer 20, and one side of the inner surface 2631 of the via 263 of the second dielectric layer 26 can extend along the same generally straight line. A single via 23 extends through the upper conductive structure 2 and the intermediate layer 12; that is, a single via 23 extends from the top surface 21 of the upper conductive structure 2 to the bottom portion of the intermediate layer 12 to expose a portion of the topmost circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'). The single via 23 gradually narrows downwards. The maximum width of a single via 23 (e.g., at the top portion) can be from about 25 μm to about 60 μm.

[0103] The upper through-hole 14 is formed or disposed in a corresponding single through-hole 23 and is made of metal, metal alloy, or other conductive material. Therefore, the upper through-hole 14 extends through at least a portion of the upper conductive structure 2 and the intermediate layer 12, and is electrically connected to the topmost circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'). Figure 1As shown, the upper through-hole 14 extends through and contacts the bottom first circuit layer 24 of the upper conductive structure 2, and terminates at or above a portion of the top circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'), contacting said portion. The upper through-hole 14 extends from the top surface 21 of the upper conductive structure 2 to the bottom surface 122 of the intermediate layer 12. Therefore, the upper through-hole 14 extends to contact a portion of the lower conductive structure 3, and the upper through-hole 14 does not extend through the lower conductive structure 3. In some embodiments, the low-density circuit layer (e.g., the second upper circuit layer 38') of the low-density conductive structure (e.g., the lower conductive structure 3) is electrically connected to the high-density circuit layer (e.g., the bottom first circuit layer 24) of the high-density conductive structure (e.g., the upper conductive structure 2) only through the upper through-hole 14 extending through the high-density circuit layer (e.g., the bottom first circuit layer 24) of the high-density conductive structure (e.g., the upper conductive structure 2). The length (along the longitudinal axis) of the upper through-hole 14 is greater than the thickness of the high-density conductive structure (e.g., the upper conductive structure 2). Furthermore, the upper through-hole 14 gradually narrows downwards; that is, the size of the top portion of the upper through-hole 14 is greater than the size of the bottom portion. Therefore, the narrowing direction of the internal through-hole 25 of the upper conductive structure 2 differs from the narrowing direction of the upper through-hole 14. In some embodiments, the upper through-hole 14 is a monolithic or single-piece structure with a homogeneous material composition, and the peripheral surface of the upper through-hole 14 is a generally continuous surface without boundaries. The upper through-hole 14 and the second circuit layer 28 can be integrally formed as a monolithic or single-piece structure. In some embodiments, the maximum width of the upper through-hole 14 can be less than about 40 μm, for example, about 30 μm or about 20 μm.

[0104] like Figure 1 As shown, the upper conductive structure 2 includes a high-density region 41 and a low-density region 47. In some embodiments, the density of circuit lines (including traces or pads) in the high-density region 41 is greater than the density of circuit lines in the low-density region 47. That is, the count of circuit lines (including traces or pads) per unit area in the high-density region 41 is greater than the count of circuit lines per unit area in the low-density region 47. Alternatively or in combination, the L / S ratio of the circuit layers in the high-density region 41 is less than the L / S ratio of the circuit layers in the low-density region 47. Furthermore, the upper through-hole 14 is disposed in the low-density region 47 of the high-density conductive structure (e.g., the upper conductive structure 2). In some embodiments, the high-density region 41 may be a chip bonding region.

[0105] like Figure 1As shown in the embodiments illustrated, the wiring structure 1 is a combination of an upper conductive structure 2 and a lower conductive structure 3. The circuit layer 24 of the upper conductive structure 2 has fine pitch, high yield, and low thickness; and the circuit layers of the lower conductive structure 3 (e.g., a first upper circuit layer 34, second upper circuit layers 38, 38', a first lower circuit layer 34a, and second lower circuit layers 38a, 38a') have low manufacturing cost. Therefore, the wiring structure 1 offers a favorable trade-off between yield and manufacturing cost, and has a relatively low thickness. In some embodiments, if the package has 10,000 I / Os, the wiring structure 1 comprises three first circuit layers 24 of the upper conductive structure 2 and six circuit layers of the lower conductive structure 3 (e.g., a first upper circuit layer 34, second upper circuit layers 38, 38', a first lower circuit layer 34a, and second lower circuit layers 38a, 38a'). The manufacturing yield of one layer of the first circuit layer 24 of the upper conductive structure 2 can be 99%, and the manufacturing yield of one layer of the circuit layer of the lower conductive structure 3 (e.g., the first upper circuit layer 34, the second upper circuit layers 38, 38', the first lower circuit layer 34a, and the second lower circuit layers 38a, 38a') can be 90%. Therefore, the yield of the wiring structure 1 can be improved. Furthermore, the warpage of the upper conductive structure 2 and the warpage of the lower conductive structure 3 are separate and do not affect each other. In some embodiments, the warpage shape of the upper conductive structure 2 may be different from the warpage shape of the lower conductive structure 3. For example, the warpage shape of the upper conductive structure 2 may be convex, and the warpage shape of the lower conductive structure 3 may be concave. In some embodiments, the warpage shape of the upper conductive structure 2 may be the same as the warpage shape of the lower conductive structure 3; however, the warpage of the lower conductive structure 3 does not accumulate on the warpage of the upper conductive structure 2. Therefore, the yield of the wiring structure 1 can be further improved.

[0106] Furthermore, during the manufacturing process, the lower conductive structure 3 and the upper conductive structure 2 can be tested separately before being joined together. Therefore, known good lower conductive structures 3 and known good upper conductive structures 2 can be selectively joined together. Defective (or unqualified) lower conductive structures 3 and defective (or unqualified) upper conductive structures 2 can be discarded. Therefore, the yield of the wiring structure 1 can be further improved.

[0107] Figure 2 A cross-sectional view of a wiring structure 1a according to some embodiments of the present disclosure is shown. The wiring structure 1a is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2a and the lower conductive structure 3a. For example... Figure 2As shown, both the upper conductive structure 2a and the lower conductive structure 3a are strip structures. Therefore, the wiring structure 1a is a strip structure. In some embodiments, the lower conductive structure 3a may be a panel structure carrying multiple strip upper conductive structures 2a. Therefore, the wiring structure 1a is a panel structure. From a top view, the length of the upper conductive structure 2a (e.g., about 240 mm) is greater than the width of the upper conductive structure 2a (e.g., about 95 mm). Additionally, from a top view, the length of the lower conductive structure 3a is greater than the width of the lower conductive structure 3a. Furthermore, the lateral peripheral surface 27 of the upper conductive structure 2a is not coplanar with the lateral peripheral surface 33 of the lower conductive structure 3a (e.g., it is recessed inward or otherwise offset from it). In some embodiments, during the manufacturing process, both the lower conductive structure 3a and the upper conductive structure 2a may be known good strip structures. Alternatively, the upper conductive structure 2a may be a known good strip structure, and the lower conductive structure 3a may be a known good panel structure. Therefore, the yield of wiring structure 1a can be further improved.

[0108] like Figure 2 As shown, the upper conductive structure 2a includes at least one reference mark 43 at its corner, and the lower conductive structure 3a has at least one reference mark 45 at its corner. During the manufacturing process, the reference mark 43 of the upper conductive structure 2a is aligned with the reference mark 45 of the lower conductive structure 3a to ensure the relative positions of the upper conductive structure 2a and the lower conductive structure 3a. In one embodiment, the reference mark 43 of the upper conductive structure 2a is disposed on and protrudes from the bottom surface 22 of the upper conductive structure 2a (e.g., the bottom surface 202 of the bottommost first dielectric layer 20). The reference mark 43 and the bottommost first circuit layer 24 may be co-layered or partially co-layered and may be formed simultaneously. Additionally, the reference mark 45 of the lower conductive structure 3a is disposed on and protrudes from the top surface 31 of the lower conductive structure 3a (e.g., the top surface 361 of the second upper dielectric layer 36). The reference mark 45 and the second upper circuit layer 38' may be co-layered or partially co-layered and may be formed simultaneously.

[0109] Figure 2A A top view showing an example of a reference mark 43a of the upper conductive structure 2a according to some embodiments of the present disclosure. The reference mark 43a of the upper conductive structure 2a has a continuous cross shape.

[0110] Figure 2B A top view showing an example of a reference mark 45a of the lower conductive structure 3a according to some embodiments of the present disclosure. The reference mark 45a of the lower conductive structure 3a comprises four square segments at the four corners.

[0111] Figure 2C show Figure 2A The reference mark 43a of the upper conductive structure 2a and Figure 2B The combined image is a top view of the reference mark 45a of the lower conductive structure 3a. When the upper conductive structure 2a is precisely aligned with the lower conductive structure 3a, the combined image shows the complete reference mark 43a and the complete reference mark 45a, as shown. Figure 2C As shown. That is to say, from the top view, datum mark 43a does not cover or overlap datum mark 45a.

[0112] Figure 2D A top view showing an example of a reference mark 43b of the upper conductive structure 2a according to some embodiments of the present disclosure. The reference mark 43b of the upper conductive structure 2a is a continuously inverted "L" shape.

[0113] Figure 2E A top view showing an example of a reference mark 45b of a lower conductive structure 3a according to some embodiments of the present disclosure. The reference mark 45b of the lower conductive structure 3a has a continuously inverted "L" shape that is substantially the same as the reference mark 43b of the upper conductive structure 2a.

[0114] Figure 2F show Figure 2D The reference mark 43b of the upper conductive structure 2a and Figure 2E The combined image is a top view of the reference mark 45b of the lower conductive structure 3a. When the upper conductive structure 2a and the lower conductive structure 3a are precisely aligned, the combined image only shows the reference mark 43b of the upper conductive structure 2a, as shown. Figure 2F As shown. That is to say, from the top view, datum mark 43b completely covers or overlaps datum mark 45b.

[0115] Figure 2G A top view showing an example of a reference mark 43c of an upper conductive structure 2a according to some embodiments of the present disclosure. The reference mark 43c of the upper conductive structure 2a has a continuous circular shape.

[0116] Figure 2H A top view showing an example of a reference mark 45c of a lower conductive structure 3a according to some embodiments of the present disclosure. The reference mark 45c of the lower conductive structure 3a has a continuous circular shape that is larger than that of the reference mark 43c of the upper conductive structure 2a.

[0117] Figure 2I show Figure 2G The reference mark 43c of the upper conductive structure 2a and Figure 2HA top view of the combined image of the reference mark 45c of the lower conductive structure 3a. When the upper conductive structure 2a and the lower conductive structure 3a are precisely aligned, the combined image shows two concentric circles, as shown. Figure 2I As shown. That is, the reference mark 43c is set at the center of the reference mark 45c.

[0118] Figure 3 This illustration shows a cross-sectional view of a wiring structure 1b according to some embodiments of the present disclosure. The wiring structure 1b is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2b and the lower conductive structure 3b. In the upper conductive structure 2b, the second dielectric layer 26 is replaced by the topmost first dielectric layer 20. Additionally, the upper conductive structure 2b may further include a topmost circuit layer 24'. The topmost circuit layer 24' may omit the seed layer and can be electrically connected to the lower circuit layer 24 via an internal via 25. The top surface of the topmost circuit layer 24' may be substantially coplanar with the top surface 21 of the upper conductive structure 2b (e.g., the top surface 201 of the topmost first dielectric layer 20). Therefore, the top surface of the topmost circuit layer 24' can be exposed from the top surface 21 of the upper conductive structure 2b (e.g., the top surface 201 of the topmost first dielectric layer 20). Furthermore, the bottommost first dielectric layer 20 may cover the bottommost circuit layer 24. Therefore, the entire bottom surface 22 of the upper conductive structure 2b (e.g., the bottom surface 202 of the bottommost first dielectric layer 20) is substantially flat.

[0119] In the lower conductive structure 3b, the second upper dielectric layer 36 and the second upper circuit layers 38, 38' are omitted. Therefore, the top surface 31 of the lower conductive structure 3b is the generally flat top surface 301 of the first upper dielectric layer 30. In addition, it includes two additional second lower dielectric layers 36a and two additional second lower circuit layers 38a'.

[0120] Intermediate layer 12 is adhered to the bottom surface 22 of upper conductive structure 2b and the top surface 31 of lower conductive structure 3b. Therefore, the entire top surface 121 and the entire bottom surface 122 of intermediate layer 12 are substantially flat. Intermediate layer 12 does not contain or contact horizontally extending or connected circuit layers. That is, no horizontally extending or connected circuit layers are disposed or embedded in intermediate layer 12. Upper through-hole 14 extends through upper conductive structure 2b and intermediate layer 12, and further extends into a portion of lower conductive structure 3b (e.g., the first upper dielectric layer 30) to contact the first upper circuit layer 34.

[0121] Figure 4 This illustration shows a cross-sectional view of a wiring structure 1c according to some embodiments of the present disclosure. The wiring structure 1c is similar to... Figure 1The wiring structure 1 shown differs in that it includes an upper conductive structure 2c, a lower conductive structure 3c, and at least one through-hole 16. Each first dielectric layer 20 defines a via 203 having an inner surface 2031. The intermediate layer 12 defines at least one via 124 having an inner surface 1241. The second upper dielectric layer 36 defines a via 363 having an inner surface 3631. The first upper dielectric layer 30 defines a via 303 having an inner surface 3031. The core portion 37 defines a via 374 having an inner surface 3741. The first lower dielectric layer 30a defines a via 303a having an inner surface 3031a. The second lower dielectric layer 36a defines a via 363a having an inner surface 3631a.

[0122] like Figure 4 As shown, the vias 263 of the second dielectric layer 26, 203 of the first dielectric layer 20, 124 of the intermediate layer 12, 363 of the second upper dielectric layer 36, 303 of the first upper dielectric layer 30, 374 of the core portion 37, 303a of the first lower dielectric layer 30a, and 363a of the second lower dielectric layer 36a are aligned and interconnected with each other. Therefore, the inner surfaces 2631 of via 263, 2031 of via 203, 1241 of via 124, 3631 of via 363, 3031 of via 303, 3741 of via 374, 3031a of via 303a, and 3631a of via 363 are coplanar or aligned with each other. In some embodiments, the inner surface 2631 of the via 263 of the second dielectric layer 26, the inner surface 2031 of the via 203 of the first dielectric layer 20, the inner surface 1241 of the via 124 of the intermediate layer 12, the inner surface 3631 of the via 363, the inner surface 3031 of the via 303, the inner surface 3741 of the via 374, the inner surface 3031a of the via 303a, and the inner surface 3631a of the via 363 may be curved or flat surfaces, and may be a portion of the inner surface 171 of a single continuous via 17 for accommodating the through hole 16. The vias 263 of the second dielectric layer 26, 203 of the first dielectric layer 20, 124 of the intermediate layer 12, 363 of the second upper dielectric layer 36, 303 of the first upper dielectric layer 30, 374 of the core portion 37, 303a of the first lower dielectric layer 30a, and 363a of the second lower dielectric layer 36a are configured together to form or define a single via 17.

[0123] like Figure 1As shown, the cross-sectional views of one side of the inner surface 2631 of through-hole 263, the inner surface 2031 of through-hole 203, the inner surface 1241 of through-hole 124 of intermediate layer 12, the inner surface 3631 of through-hole 363, the inner surface 3031 of through-hole 303, the inner surface 3741 of through-hole 374, the inner surface 3031a of through-hole 303a, and the inner surface 3631a of through-hole 363a are generally straight segments. A single through-hole 17 extends through the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3 (including the second lower circuit layer 38a'); that is, the single through-hole 17 extends from the top surface 21 of the upper conductive structure 2 to the bottom surface 32 of the lower conductive structure 3. The maximum width of the single through-hole 17 can be from about 100 μm to about 1000 μm. In some embodiments, the single through-hole 17 can be formed by mechanical drilling. Therefore, via 17 may not gradually narrow, and the inner surface 171 of via 17 may be substantially perpendicular to the top surface 21 of the upper conductive structure 2 and / or the bottom surface 32 of the lower conductive structure 3. That is, the sizes of via 263 in the second dielectric layer 26, via 203 in the first dielectric layer 20, via 124 in the intermediate layer 12, via 363 in the second upper dielectric layer 36, via 303 in the first upper dielectric layer 30, via 374 in the core portion 37, via 303a in the first lower dielectric layer 30a, and via 363a in the second lower dielectric layer 36a are approximately equal to each other.

[0124] Each through-hole 16 is formed or disposed in a corresponding through-hole 17 and is made of metal, metal alloy, or other conductive material. Therefore, the through-hole 16 extends through the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3. For example... Figure 4 As shown, the lower through-hole 16 extends through and contacts the bottommost circuit layer 24 of the upper conductive structure 2, the topmost circuit layer (e.g., the second upper circuit layer 38') of the lower conductive structure 3, and the bottommost circuit layer (e.g., the second lower circuit layer 38a') of the lower conductive structure 3. In some embodiments, the low-density circuit layer (e.g., the second upper circuit layer 38') of the low-density conductive structure (e.g., the lower conductive structure 3) is electrically connected to the high-density circuit layer (e.g., the first circuit layer 24) of the high-density conductive structure (e.g., the upper conductive structure 2) only through the through-hole 16. The length (along the longitudinal axis) of the through-hole 16 is greater than the thickness of the low-density conductive structure (e.g., the lower conductive structure 3) or the thickness of the high-density conductive structure (e.g., the upper conductive structure 2). In some embodiments, the through-hole 16 is a monolithic or single-piece structure with a homogeneous material composition, and the outer peripheral surface 163 of the through-hole 16 is a generally continuous surface without boundaries. The through-hole 16 and the outer circuit layer 28 can be integrally formed.

[0125] Figure 5This illustration shows a cross-sectional view of a wiring structure 1d according to some embodiments of the present disclosure. The wiring structure 1d is similar to... Figure 4 The wiring structure 1c shown differs in the structure of the upper conductive structure 2d and the lower conductive structure 3d. For example... Figure 5 As shown, both the upper conductive structure 2d and the lower conductive structure 3d are strip structures. Therefore, the wiring structure 1d is a strip structure. In some embodiments, the lower conductive structure 3d may be a panel structure carrying multiple strip upper conductive structures 2d. Therefore, the wiring structure 1d is a panel structure. From a top view, the length of the upper conductive structure 2d (e.g., about 240 mm) is greater than the width of the upper conductive structure 2d (e.g., about 95 mm). Additionally, from a top view, the length of the lower conductive structure 3d is greater than the width of the lower conductive structure 3d. Furthermore, the lateral peripheral surface 27 of the upper conductive structure 2d is not coplanar with the lateral peripheral surface 33 of the lower conductive structure 3d (e.g., it is recessed from it or otherwise displaced from it). In some embodiments, during the manufacturing process, both the lower conductive structure 3d and the upper conductive structure 2d may be known good strip structures. Alternatively, the upper conductive structure 2d may be a known good strip structure, and the lower conductive structure 3d may be a known good panel structure. Therefore, the yield of wiring structure 1d can be further improved.

[0126] like Figure 5 As shown, the upper conductive structure 2d includes at least one reference mark 43 at its corner, and the lower conductive structure 3d includes at least one reference mark 45 at its corner. During the manufacturing process, the reference mark 43 of the upper conductive structure 2d is aligned with the reference mark 45 of the lower conductive structure 3d to fix the relative positions of the upper conductive structure 2d and the lower conductive structure 3d. In one embodiment, the reference mark 43 of the upper conductive structure 2d is disposed on and protrudes from the bottom surface 22 of the upper conductive structure 2d (e.g., the bottom surface 202 of the bottommost first dielectric layer 20). The reference mark 43 and the bottommost circuit layer 24 may be co-layered or partially co-layered and may be formed simultaneously. Additionally, the reference mark 45 of the lower conductive structure 3d is disposed on and protrudes from the top surface 31 of the lower conductive structure 3d (e.g., the top surface 361 of the second upper dielectric layer 36). The reference mark 45 and the second upper circuit layer 38' may be co-layered or partially co-layered and may be formed simultaneously.

[0127] Figure 6 This illustration shows a cross-sectional view of a wiring structure 1e according to some embodiments of the present disclosure. The wiring structure 1e is similar to... Figure 4 The wiring structure 1c shown differs in the structure of the through-hole 18 and the external circuit layer 28'. For example... Figure 6As shown in the image, Figure 4 The guide hole 16 is replaced by the guide hole 18, and Figure 4 The external circuit layer 28 is replaced by an external circuit layer 28'. In some embodiments, the via 18 includes a conductive layer 181 (e.g., a metal layer) and an insulating material 182. The conductive layer 181 is disposed or formed on the inner surface 171 of the via 17 and defines a central via. The insulating material 182 fills the central via defined by the conductive layer 181. The conductive layer 181 and the external circuit layer 28' may be integrally formed simultaneously.

[0128] Figure 7 This is a cross-sectional view illustrating the bonding between the package structure 4 and the substrate 46 according to some embodiments. The package structure 4 includes a wiring structure 1f, a semiconductor chip 42, a plurality of first connection elements 44, and a plurality of second connection elements 48. Figure 7 The wiring structure 1f is similar to Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2f and the lower conductive structure 3f. Both the upper conductive structure 2f and the lower conductive structure 3f are bare dies and can be singulated simultaneously. Therefore, wiring structure 1f is a unit structure. That is, the lateral peripheral surface 27f of the upper conductive structure 2f, the lateral peripheral surface 33f of the lower conductive structure 3f, and the lateral peripheral surface of the intermediate layer 12 are substantially coplanar with each other. The semiconductor chip 42 is electrically connected and bonded to the second circuit layer 28 of the upper conductive structure 2b via a first connecting element 44 (e.g., solder bumps or other conductive bumps). The second lower circuit layer 38a' of the lower conductive structure 3f is electrically connected and bonded to the substrate 46 (e.g., a motherboard, such as a printed circuit board (PCB)) via a second connecting element 48 (e.g., solder bumps or other conductive bumps).

[0129] Figure 8 This is a cross-sectional view illustrating the bonding between the package structure 4a and the substrate 46 according to some embodiments. The package structure 4a includes a wiring structure 1g, a semiconductor chip 42, a plurality of first connecting elements 44, a plurality of second connecting elements 48, and a heat sink 80. Figure 8 The wiring structure 1g is similar to Figure 4The wiring structure 1c shown differs in the structure of the upper conductive structure 2g and the lower conductive structure 3g. Both the upper conductive structure 2g and the lower conductive structure 3g are bare dies and can be individually divided simultaneously. Therefore, the wiring structure 1g is a unit structure. That is, the lateral peripheral surface 27g of the upper conductive structure 2g, the lateral peripheral surface 33g of the lower conductive structure 3g, and the lateral peripheral surface of the intermediate layer 12 are substantially coplanar with each other. The semiconductor chip 42 has an active surface 421 and a back surface 422 opposite to the active surface 421. The active surface 421 of the semiconductor chip 42 is electrically connected and bonded to the external circuit layer 28 of the upper conductive structure 2g via a first connecting element 44 (e.g., solder bumps or other conductive bumps). The second lower circuit layer 38a' of the lower conductive structure 3f is electrically connected and bonded to the substrate 46 (e.g., a motherboard, such as a PCB board) via a second connecting element 48 (e.g., solder bumps or other conductive bumps).

[0130] The heat sink 80 covers the semiconductor chip 42, and a portion of the heat sink 80 is thermally connected to the through-hole 16. For example... Figure 8 As shown, a bottom filler 491 is included to cover and protect the first connection element 44 and the external circuit layer 28. The inner surface of the heat sink 80 is bonded to the back surface 422 of the semiconductor chip 42 by an adhesive layer 492. The bottom portion of the sidewall of the heat sink 80 is attached to the through-hole 16 or a portion of the external circuit layer 28 integrally formed with the through-hole 16. During operation of the semiconductor chip 42, there are two paths (including a first path 90 and a second path 91) to dissipate the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42) to the substrate 46. Taking the first path 90 as an example, a portion of the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42) is transferred upward through the body of the semiconductor chip 42, the back surface 422 of the semiconductor chip 42, and the adhesive layer 492 to the heat sink 80, then horizontally, and subsequently downward in the heat sink 80 to enter the through-hole 16. Taking the second path 91 as an example, another portion of the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42) is transported downwards through the first connecting element 44, the external circuit layer 28, and the stacked internal vias 25, and then horizontally in the bottommost circuit layer 24 of the upper conductive structure 2c to enter the through-hole 16. Finally, the heat in the through-hole 16 will be transported downwards to the substrate 46. Since there are two paths (including the first path 90 and the second path 91) to dissipate the heat generated by the semiconductor chip 42 (especially from the active surface 421 of the semiconductor chip 42), the heat will be dissipated effectively and rapidly.

[0131] Figure 9This illustration shows a cross-sectional view of a wiring structure 1h according to some embodiments of the present disclosure. The wiring structure 1h is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the through-hole 373a and the interconnecting via 39 in the lower conductive structure 3. (As shown...) Figure 9 As shown, the through hole 373a can be formed by laser drilling and can gradually narrow downwards. Therefore, the interconnecting vias 39 formed or disposed in the through hole 373a can gradually narrow downwards.

[0132] Figures 10 to 47 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture... Figure 1 The wiring structure 1 and / or shown Figure 7 The packaging structure shown is 4.

[0133] refer to Figures 10 to 29 A lower conductive structure 3 is provided. The lower conductive structure 3 is manufactured as follows. (See reference) Figure 10 A core portion 37 is provided, having a top copper foil 50 and a bottom copper foil 52. The core portion 37 can be of wafer type, panel type, or strip type. The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371. The top copper foil 50 is disposed on the top surface 371 of the core portion 37, and the bottom copper foil 52 is disposed on the bottom surface 372 of the core portion 37.

[0134] In some embodiments, the core portion 37 is substantially free of reinforcing material, such as glass fiber. That is, the core portion 37 may not contain reinforcing material such as glass fiber and may contain a homogeneous material component of resin. Alternatively, the core portion 37 may contain a small amount of reinforcing material, such as glass fiber, for example, about 5% by weight or less, about 3% by weight or less, or about 2% by weight or less. Additionally, the material of the core portion 37 may include an insulating film, such as ABF. Furthermore, the Young's modulus of the core portion 37 may be greater than or equal to about 4.0 GPa at 23°C, for example, about 4.0 GPa or greater at 23°C, about 5.0 GPa or greater at 23°C, or about 7.5 GPa or greater at 23°C.

[0135] refer to Figure 11 Multiple through holes 373 are formed by drilling techniques (such as laser drilling or mechanical drilling) or other suitable techniques to extend through the core portion 37, the top copper foil 50 and the bottom copper foil 52.

[0136] refer to Figure 12 A second metal layer 54 is formed or disposed on the sidewalls of the top copper foil 50, the bottom copper foil 52, and the first through hole 373 using plating technology or other suitable techniques. A portion of the second metal layer 54 on the sidewall of each first through hole 373 defines a central through hole.

[0137] refer to Figure 13 Insulating material 392 is placed to fill the central through hole defined by the second metal layer 54.

[0138] refer to Figure 14 A top third metal layer 56 and a bottom third metal layer 56a are formed or disposed on the second metal layer 54 by means of plating technology or other suitable technology. The third metal layers 56 and 56a are covered with insulating material 392.

[0139] refer to Figure 15 A top photoresist layer 57 is formed or disposed on the top third metal layer 56, and a bottom photoresist layer 57a is formed or disposed on the bottom third metal layer 56a. Then, the photoresist layers 57 and 57a are patterned by exposure and development.

[0140] refer to Figure 16 The portions of the top copper foil 50, the second metal layer 54, and the top third metal layer 56 not covered by the top photoresist layer 57 are removed using etching or other suitable techniques. The portions of the top copper foil 50, the second metal layer 54, and the top third metal layer 56 covered by the top photoresist layer 57 are retained to form the first upper circuit layer 34. Simultaneously, the portions of the bottom copper foil 52, the second metal layer 54, and the bottom third metal layer 56a not covered by the bottom photoresist layer 57a are removed using etching or other suitable techniques. The portions of the bottom copper foil 52, the second metal layer 54, and the bottom third metal layer 56a covered by the bottom photoresist layer 57a are retained to form the first lower circuit layer 34a. Meanwhile, the portions of the second metal layer 54 and the insulating material 392 disposed in the via 373 form interconnect vias 39. Figure 16 As shown, the first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In some embodiments, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37. The bottom surface 342 of the first upper circuit layer 34 contacts the top surface 371 of the core portion 37. In some embodiments, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be formed from a portion of the top copper foil 50. The second metal layer 344 is disposed on the first metal layer 343 and may be a copper plating layer formed from the second metal layer 54. The third metal layer 345 is disposed on the second metal layer 344 and may be another copper plating layer formed from the top third metal layer 56.

[0141] The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In some embodiments, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37. The top surface 341a of the first lower circuit layer 34a contacts the bottom surface 372 of the core portion 37. In some embodiments, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a, and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be formed from a portion of the bottom copper foil 52. The second metal layer 344a is disposed on the first metal layer 343a and may be a copper plating layer formed from the second metal layer 54. The third metal layer 345a is disposed on the second metal layer 344a and may be another copper plating layer formed from the bottom third metal layer 56a. The interconnect via 39 includes a base metal layer 391 formed from the second metal layer 54 and an insulating material 392. In some embodiments, the interconnect via 39 may comprise a block of metal material filling the via 373. The interconnect via 39 electrically connects the first upper circuit layer 34 and the first lower circuit layer 34a.

[0142] refer to Figure 17 The top photoresist layer 57 and the bottom photoresist layer 57a are removed by stripping techniques or other suitable techniques.

[0143] refer to Figure 18 A first upper dielectric layer 30 is formed or disposed on the top surface 371 of the core portion 37 using lamination technology or other suitable technology to cover the top surface 371 and the first upper circuit layer 34 of the core portion 37. Simultaneously, a first lower dielectric layer 30a is formed or disposed on the bottom surface 372 of the core portion 37 using lamination technology or other suitable technology to cover the bottom surface 372 and the first lower circuit layer 34a of the core portion 37.

[0144] In some embodiments, the first upper dielectric layer 30 and the first lower dielectric layer 30a may be substantially free of reinforcing materials such as glass fibers. That is, the first upper dielectric layer 30 and the first lower dielectric layer 30a may not contain reinforcing materials such as glass fibers and may contain a homogeneous material composition of resin. Alternatively, the first upper dielectric layer 30 and the first lower dielectric layer 30a may contain a small amount of reinforcing material, such as glass fibers, for example, about 5% or less, about 3% or less, or about 2% or less. In addition, the material of the first upper dielectric layer 30 and the first lower dielectric layer 30a may contain an insulating film, such as ABF. Furthermore, the Young's modulus of the first upper dielectric layer 30 and the first lower dielectric layer 30a may be greater than or equal to about 4.0 GPa at 23°C, for example, about 4.0 GPa or greater at 23°C, about 5.0 GPa or greater at 23°C, or about 7.5 GPa or greater at 23°C.

[0145] refer to Figure 19 At least one via 303 is formed by drilling or other suitable techniques to extend through the first upper dielectric layer 30, thereby exposing a portion of the first upper circuit layer 34. Simultaneously, at least one via 303a is formed by drilling or other suitable techniques to extend through the first lower dielectric layer 30a, thereby exposing a portion of the first lower circuit layer 34a.

[0146] refer to Figure 20 A top metal layer 58 is formed on the first upper dielectric layer 30 and in the via 303 using plating technology or other suitable techniques to form the upper interconnect via 35. Simultaneously, a bottom metal layer 60 is formed on the first lower dielectric layer 30a and in the via 303a using plating technology or other suitable techniques to form the lower interconnect via 35a. Figure 20 As shown, the upper interconnect via 35 gradually narrows downwards, and the lower interconnect via 35a gradually narrows upwards.

[0147] refer to Figure 21 A top photoresist layer 59 is formed or disposed on the top metal layer 58, and a bottom photoresist layer 59a is formed or disposed on the bottom metal layer 60. Then, the photoresist layers 59 and 59a are patterned by exposure and development.

[0148] refer to Figure 22 The portions of the top metal layer 58 not covered by the top photoresist layer 59 are removed using etching or other suitable techniques. The portions of the top metal layer 58 covered by the top photoresist layer 59 are retained to form the second upper circuit layer 38. Simultaneously, the portions of the bottom metal layer 60 not covered by the bottom photoresist layer 59a are removed using etching or other suitable techniques. The portions of the bottom metal layer 60 covered by the bottom photoresist layer 59a are retained to form the second lower circuit layer 38a.

[0149] refer to Figure 23 The top photoresist layer 59 and the bottom photoresist layer 59a are removed by stripping techniques or other suitable techniques.

[0150] refer to Figure 24A second upper dielectric layer 36 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 using lamination technology or other suitable techniques to cover the top surface 301 of the first upper dielectric layer 30 and the second upper circuit layer 38. Simultaneously, a second lower dielectric layer 36a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a using lamination technology or other suitable techniques to cover the bottom surface 302a of the first lower dielectric layer 30a and the second lower circuit layer 38a. In some embodiments, the second upper dielectric layer 36 and the second lower dielectric layer 36a may substantially not contain reinforcing materials such as glass fibers. That is, the second upper dielectric layer 36 and the second lower dielectric layer 36a may not contain reinforcing materials such as glass fibers and may contain homogeneous material components of resin. Alternatively, the second upper dielectric layer 36 and the second lower dielectric layer 36a may contain, for example, a small amount of reinforcing material, such as glass fiber, of about 5% by weight or less, about 3% by weight or less, or about 2% by weight or less. Additionally, the materials of the second upper dielectric layer 36 and the second lower dielectric layer 36a may include an insulating film, such as ABF. Furthermore, the Young's modulus of the second upper dielectric layer 36 and the second lower dielectric layer 36a may be greater than or equal to about 4.0 GPa at 23°C, for example, about 4.0 GPa or greater at 23°C, about 5.0 GPa or greater at 23°C, or about 7.5 GPa or greater at 23°C.

[0151] refer to Figure 25 At least one via 363 is formed by drilling or other suitable techniques to extend through the second upper dielectric layer 36, thereby exposing a portion of the second upper circuit layer 38. Simultaneously, at least one via 363a is formed by drilling or other suitable techniques to extend through the second lower dielectric layer 36a, thereby exposing a portion of the second lower circuit layer 38a.

[0152] refer to Figure 26 A top metal layer 62 is formed on the second upper dielectric layer 36 and in the via 363 using plating technology or other suitable techniques to form the upper interconnect via 35. Simultaneously, a bottom metal layer 64 is formed on the second lower dielectric layer 36a and in the via 363a using plating technology or other suitable techniques to form the lower interconnect via 35a.

[0153] refer to Figure 27 A top photoresist layer 63 is formed or disposed on the top metal layer 62, and a bottom photoresist layer 63a is formed or disposed on the bottom metal layer 64. Then, the photoresist layers 63 and 63a are patterned by exposure and development.

[0154] refer to Figure 28The portion of the top metal layer 62 not covered by the top photoresist layer 63 is removed using etching or other suitable techniques. The portion of the top metal layer 62 covered by the top photoresist layer 63 is retained to form the second upper circuit layer 38'. Simultaneously, the portion of the bottom metal layer 64 not covered by the bottom photoresist layer 63a is removed using etching or other suitable techniques. The portion of the bottom metal layer 64 covered by the bottom photoresist layer 63a is retained to form the second lower circuit layer 38a'.

[0155] refer to Figure 29 The top photoresist layer 63 and the bottom photoresist layer 63a are removed using a stripping technique or other suitable technique. Simultaneously, the lower conductive structure 3 is formed, and dielectric layers (including a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) are cured. At least one of the circuit layers (including, for example, a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a') is in contact with at least one of the dielectric layers (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a). Then, the electrical properties of the lower conductive structure 3 (e.g., open circuit / short circuit) are tested.

[0156] refer to Figures 30 to 40 An upper conductive structure 2 is provided. The upper conductive structure 2 is manufactured as follows. (See reference...) Figure 30 A carrier 65 is provided. The carrier 65 can be a glass carrier and can be of wafer type, panel type or strip type.

[0157] refer to Figure 31 A release layer 66 is coated on the bottom surface of the carrier 65.

[0158] refer to Figure 32 A conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 using physical vapor deposition (PVD) or other suitable techniques.

[0159] refer to Figure 33 A second dielectric layer 26 is formed on the conductive layer 67 by coating technology or other suitable technology.

[0160] refer to Figure 34 At least one via 264 is formed by exposure and development techniques or other suitable techniques to extend through the second dielectric layer 26, thereby exposing a portion of the conductive layer 67.

[0161] refer to Figure 35Seed layers 68 are formed on the bottom surface 262 of the second dielectric layer 26 and in the via 264 using PVD technology or other suitable techniques.

[0162] refer to Figure 36 A photoresist layer 69 is formed on the seed layer 68. Then, the photoresist layer 69 is patterned to expose portions of the seed layer 68 using exposure and development techniques or other suitable techniques. The photoresist layer 69 defines a plurality of openings 691. At least one opening 691 of the photoresist layer 69 corresponds to and is aligned with a via 264 of the second dielectric layer 26.

[0163] refer to Figure 37 Conductive material 70 (e.g., metallic material) is placed in the opening 691 of the photoresist layer 69 and on the seed layer 68 by means of plating technology or other suitable technology.

[0164] refer to Figure 38 The photoresist layer 69 is removed by stripping techniques or other suitable techniques.

[0165] refer to Figure 39 The portion of the seed layer 68 not covered by the conductive material 70 is removed by etching or other suitable techniques. Simultaneously, a circuit layer 24 and at least one internal via 25 are formed. The circuit layer 24 may be a fan-out circuit layer or an RDL, and the L / S ratio of the circuit layer 24 may be less than or equal to about 2 μm / about 2 μm, or less than or equal to about 1.8 μm / about 1.8 μm. The circuit layer 24 is disposed on the bottom surface 262 of the second dielectric layer 26. In some embodiments, the circuit layer 24 may include a seed layer 243 formed by the seed layer 68 and a conductive material 244 disposed on the seed layer 243 and formed by the conductive material 70. The internal via 25 is disposed in the via 264 of the second dielectric layer 26. In some embodiments, the internal via 25 may include a seed layer 251 and a conductive material 252 disposed on the seed layer 251. The internal via 25 gradually narrows upwards.

[0166] refer to Figure 40 By repeating Figures 33 to 39 In this phase, multiple first dielectric layers 20 and multiple circuit layers 24 are formed. In some embodiments, each circuit layer 24 is embedded in a corresponding first dielectric layer 20, and the top surface 241 of the circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. Simultaneously, an upper conductive structure 2 is formed, and dielectric layers (including first dielectric layer 20 and second dielectric layer 26) are cured. At least one of the circuit layers (including, for example, three circuit layers 24) is in contact with at least one of the dielectric layers (e.g., first dielectric layer 20 and second dielectric layer 26). Then, the electrical properties of the upper conductive structure 2 are tested (e.g., open circuit / short circuit).

[0167] refer to Figure 41 An adhesive layer 12 is formed or coated on the top surface 31 of the lower conductive structure 3. In some embodiments, the adhesive layer 12 may be substantially free of reinforcing materials such as glass fibers. That is, the adhesive layer 12 may not contain reinforcing materials such as glass fibers and may contain a homogeneous material component of resin. Alternatively, the adhesive layer 12 may contain a small amount of reinforcing material, such as glass fibers, for example, about 5% by weight or less, about 3% by weight or less, or about 2% by weight or less. In addition, the material of the adhesive layer 12 may contain an insulating film, such as ABF. Furthermore, the Young's modulus of the adhesive layer 12 may be greater than or equal to about 4.0 GPa at 23°C, for example, about 4.0 GPa or greater at 23°C, about 5.0 GPa or greater at 23°C, or about 7.5 GPa or greater at 23°C.

[0168] refer to Figure 42 The upper conductive structure 2 is attached to the lower conductive structure 3 via an adhesive layer 12. In some embodiments, a known good upper conductive structure 2 is attached to a known good lower conductive structure 3. The adhesive layer 12 is then cured to form an intermediate layer 12. In some embodiments, the upper conductive structure 2 can be pressed onto the lower conductive structure 3. Therefore, the thickness of the intermediate layer 12 is determined by the gap between the upper conductive structure 2 and the lower conductive structure 3. The top surface 121 of the intermediate layer 12 contacts the bottom surface 22 of the upper conductive structure 2 (i.e., the bottom surface 22 of the upper conductive structure 2 is attached to the top surface 121 of the intermediate layer 12), and the bottom surface 122 of the intermediate layer 12 contacts the top surface 31 of the lower conductive structure 3. Therefore, the bottommost circuit layer 24 of the upper conductive structure 2 and the second upper circuit layer 38' of the lower conductive structure 3 are embedded in the intermediate layer 12. In some embodiments, the bonding force between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2 is greater than the bonding force between the dielectric layer of the upper conductive structure 2 (e.g., the bottom first dielectric layer 20) and the intermediate layer 12. The surface roughness of the boundary between the two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2 is greater than the surface roughness of the boundary between the dielectric layer of the upper conductive structure 2 (e.g., the bottom first dielectric layer 20) and the intermediate layer 12.

[0169] refer to Figure 43 Remove the carrier 65, release layer 66 and conductive layer 67 to expose a portion of the internal via 25.

[0170] refer to Figure 44At least one via 23 is formed by drilling (e.g., laser drilling) to extend through at least a portion of the upper conductive structure 2 and the intermediate layer 12 to expose a circuit layer of the lower conductive structure 3 (e.g., a second upper circuit layer 38'). The via 23 may include vias 263 of the second dielectric layer 26, a plurality of vias 203 of the first dielectric layer 20, and vias 123 of the intermediate layer 12. In some embodiments, the via 23 extends through the bottommost first circuit layer 24 of the upper conductive structure 2 and terminates at or above the topmost circuit layer of the lower conductive structure 3 (i.e., the second upper circuit layer 38'). That is, the via 23 does not extend through the topmost circuit layer of the lower conductive structure 3 (e.g., the second upper circuit layer 38'). The via 23 may expose a portion of the topmost circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'). Figure 44 As shown, the via 23 gradually narrows downwards; that is, the size of the top portion of the via 23 is larger than the size of the bottom portion. Furthermore, the inner surface 1231 of the via 123 in the intermediate layer 12 is coplanar or aligned with the inner surface 2031 of the via 203 in the first dielectric layer 20 and the inner surface 2631 of the via 263 in the second dielectric layer 26. Therefore, the cross-sectional views of one side of the via 123 in the intermediate layer 12, the inner surface 2031 of the via 203 in the first dielectric layer 20, and the inner surface 2631 of the inner surface 2631 of the via 263 in the second dielectric layer 26 are approximately straight segments. That is, the cross-sectional views of one side of the inner surface 1231 of the via 123 in the intermediate layer 12, the inner surface 2031 of the via 203 in the first dielectric layer 20, and the inner surface 2631 of the inner surface 2631 of the via 263 in the second dielectric layer 26 can extend along the same approximately straight line. That is, the inner surface of a single continuous through-hole 23 can be a generally flat or continuous surface. The single through-hole 23 gradually narrows downwards.

[0171] refer to Figure 45 A metal layer 72 is formed on the surface 21 of the upper conductive structure 2 and in the through hole 23 by means of plating technology or other suitable technology, so as to form at least one upper through hole 14 in the through hole 23.

[0172] refer to Figure 46 A top photoresist layer 73 is formed or disposed on the metal layer 72, and a bottom photoresist layer 73a is formed or disposed on the bottom surface 32 of the lower conductive structure 3. Next, the top photoresist layer 73 is patterned using exposure and development techniques or other suitable techniques.

[0173] refer to Figure 47The portion of metal layer 72 not covered by the top photoresist layer 73 is removed using etching or other suitable techniques. The portion of metal layer 72 covered by the top photoresist layer 73 is retained to form the second circuit layer 28. Next, the top photoresist layer 73 and the bottom photoresist layer 73a are removed using stripping or other suitable techniques to obtain... Figure 1 Wiring structure 1.

[0174] In some embodiments, semiconductor chip 42 ( Figure 7 The upper conductive structure 2 is electrically connected and bonded to the outer circuit layer 28 of the upper conductive structure 2 via multiple first connecting elements 44 (e.g., solder bumps or other conductive bumps). Then, the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3 are simultaneously separated to form... Figure 7 The package structure 4 shown is a wiring structure 1f and a semiconductor chip 42. Figure 7 The wiring structure 1f includes a separate upper conductive structure 2f and a separate lower conductive structure 3f. That is, the lateral peripheral surface 27f of the upper conductive structure 2f, the lateral peripheral surface 33f of the lower conductive structure 3f, and the lateral peripheral surface of the intermediate layer 12 are substantially coplanar with each other. Next, the second lower circuit layer 38a' of the lower conductive structure 3c is electrically connected and bonded to the substrate 46 (e.g., motherboard, such as PCB) through a plurality of second connecting elements 48 (e.g., solder bumps or other conductive bumps).

[0175] Figures 48 to 51 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture... Figure 2 The wiring structure 1a shown in the diagram. The initial stage of the described process and Figures 10 to 40 The stages described herein are the same or similar. Figure 48 Depicted in Figure 40 The stage following the stage described in the text.

[0176] refer to Figure 48 The reference mark 43 and the bottommost first circuit layer 24 are formed simultaneously and are located on the same layer. Therefore, the reference mark 43 is placed on the bottom surface 22 of the upper conductive structure 2a and protrudes from it. Next, the upper conductive structure 2a, the carrier 65, the release layer 66, and the conductive layer 67 are simultaneously cut or separated individually to form a plurality of strips 2'. Each strip 2' contains the upper conductive structure 2a, which is a strip structure. Next, the strips 2' are tested. Alternatively, the upper conductive structure 2 can be tested before the cutting process.

[0177] refer to Figure 49The reference mark 45 and the second upper circuit layer 38' are formed simultaneously and located on the same layer. Therefore, the reference mark 45 is placed on and protrudes from the top surface 31 of the lower conductive structure 3. The lower conductive structure 3 includes multiple strip regions 3'. Next, the strip regions 3' are tested. Then, an adhesive layer 12 is formed or applied to the top surface 31 of the lower conductive structure 3.

[0178] refer to Figure 50 The strip 2' is attached to the strip region 3' of the lower conductive structure 3 via the adhesive layer 12. The upper conductive structure 2a faces and is attached to the lower conductive structure 3. During the attachment process, the reference mark 43 of the upper conductive structure 2a is aligned with the reference mark 45 of the lower conductive structure 3 to fix the relative positions of the upper conductive structure 2a and the lower conductive structure 3. In some embodiments, a known good strip 2' is selectively attached to a known good strip region 3' of the lower conductive structure 3. For example, wiring structure 1a ( Figure 2 The desired yield rate can be set to 80%. That is, (yield rate of upper conductive structure 2a) × (yield rate of strip region 3' of lower conductive structure 3) is set to be greater than or equal to 80%. If the yield rate of upper conductive structure 2a (or strip 2') is less than, for example, the predetermined yield rate of 80% (which will be designated as a defective or non-conforming component), then the defective (or non-conforming) upper conductive structure 2a (or strip 2') is discarded. If the yield rate of upper conductive structure 2a (or strip 2') is greater than or equal to, for example, the predetermined yield rate of 80% (which will be designated as a known good or conforming component), then the known good upper conductive structure 2a (or strip 2') can be used. In addition, if the yield rate of strip region 3' of lower conductive structure 3 is less than, for example, the predetermined yield rate of 80% (which will be designated as a defective or non-conforming component), then the defective (or non-conforming) strip region 3' is marked and will not be coupled to any strip 2'. If the yield of the strip region 3' of the lower conductive structure 3 is greater than or equal to, for example, a predetermined yield of 80% (this will be designated as a known good or qualified component), then a known good upper conductive structure 2a (or strip 2') can be bonded to the known good strip region 3' of the lower conductive structure 3. It should be noted that an upper conductive structure 2a (or strip 2') with a yield of 80% will not be bonded to a strip region 3' of the lower conductive structure 3 with a yield of 80%, because the wiring structure 1a ( Figure 2 The yield obtained is 64%, lower than the expected yield of 80%. The upper conductive structure 2a (or strip 2') with an 80% yield can be bonded to the strip region 3' of the lower conductive structure 3 with a 100% yield; therefore, the wiring structure 1a ( Figure 2The yield obtained can be 80%. Additionally, the upper conductive structure 2a (or strip 2') with a 90% yield can be bonded to the strip region 3' of the lower conductive structure 3 with a yield greater than 90%, because the wiring structure 1a ( Figure 2 The yield rate obtained can be greater than 80%.

[0179] refer to Figure 51 The adhesive layer 12 is cured to form the intermediate layer 12. Next, the carrier 65, release layer 66, and conductive layer 67 are removed. Then, the described process... Figure 51 The stages following the stages shown are similar to Figures 44 to 47 The stages described herein. Next, the lower conductive structure 3 and the intermediate layer 12 are cut along the strip region 3' to obtain Figure 2 Wiring structure 1a.

[0180] Figures 52 to 55 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture... Figure 4 The wiring structure 1c shown in the diagram illustrates the initial stage of the process and... Figures 10 to 43 The stages described herein are the same or similar. Figure 52 Depicted in Figure 43 The stage following the stage described in [the text]. (See reference] Figure 52 At least one through-hole 17 is formed by drilling (e.g., mechanical drilling or laser drilling) to extend through the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3. Simultaneously, the upper conductive structure 2 becomes the upper conductive structure 2c, and the lower conductive structure 3 becomes the lower conductive structure 3c. The through-hole 17 may include through-holes 263 in the second dielectric layer 26, multiple through-holes 203 in the first dielectric layer 20, through-holes 124 in the intermediate layer 12, through-holes 363 in the second upper dielectric layer 36, through-holes 303 in the first upper dielectric layer 30, through-holes 374 in the core portion 37, through-holes 303a in the first lower dielectric layer 30a, and through-holes 363a in the second lower dielectric layer 36a. Figure 52 As shown, the through hole 17 may not gradually narrow; that is, the size of the top portion of the through hole 17 is approximately equal to the size of the bottom portion of the through hole 17.

[0181] refer to Figure 53 A metal layer 72 is formed on the top surface 21 of the upper conductive structure 2 and in the through hole 17 by means of plating technology or other suitable technology, so as to form at least one through hole 16 in the through hole 17.

[0182] refer to Figure 54A top photoresist layer 73 is formed or disposed on the metal layer 72, and a bottom photoresist layer 73a is formed or disposed on the bottom surface 32 of the lower conductive structure 3. Next, the top photoresist layer 73 is patterned using exposure and development techniques or other suitable techniques.

[0183] refer to Figure 55 The portion of metal layer 72 not covered by the top photoresist layer 73 is removed using etching or other suitable techniques. The portion of metal layer 72 covered by the top photoresist layer 73 is retained to form the external circuit layer 28. Next, the top photoresist layer 73 and the bottom photoresist layer 73a are removed using stripping or other suitable techniques to obtain... Figure 4 Wiring structure 1c.

[0184] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” “below,” etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, the limitation being that the advantage of the embodiments of this disclosure is not affected by such arrangement.

[0185] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to examples in which the event or situation clearly occurred and examples in which the event or situation is very close to occurring. For example, when used in conjunction with numerical values, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the first value is within a range of less than or equal to ±10% of the second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value can be considered "substantially" the same as or equal to the second value.

[0186] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0187] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple indicators.

[0188] As used herein, the terms "conductive" and "electrically conductive" refer to the ability to conduct electric current. Conductive materials are generally those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0189] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0190] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Artistic representations in this disclosure may differ from actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A wiring structure comprising: An upper conductive structure includes multiple upper dielectric layers, multiple upper circuit layers in contact with the multiple upper dielectric layers, multiple internal vias, and at least one reference mark, wherein the multiple internal vias gradually narrow upwards, wherein the material of the upper dielectric layers is transparent, and wherein the upper conductive structure is a coreless substrate. A lower conductive structure includes a plurality of lower dielectric layers, a plurality of lower circuit layers in contact with the plurality of lower dielectric layers, and at least one reference mark, wherein the lower conductive structure is a core substrate, wherein the line spacing of the lower circuit layers of the lower conductive structure is greater than the line spacing of the upper circuit layers of the upper conductive structure, and wherein the reference mark of the upper conductive structure is aligned with the reference mark of the lower conductive structure. An intermediate layer, disposed between the upper conductive structure and the lower conductive structure, and bonding the upper and lower conductive structures together, wherein the upper conductive structure is electrically connected to the lower conductive structure, and wherein the intermediate layer is made of a transparent material; and At least one upper through-hole extends through the upper conductive structure and the intermediate layer, and is electrically connected to and terminates at the topmost circuit layer of the plurality of lower circuit layers of the lower conductive structure, wherein the upper through-hole does not extend through the lower conductive structure, and wherein the upper through-hole gradually narrows downward.

2. The wiring structure according to claim 1, wherein some of the plurality of internal vias of the upper conductive structure are disposed between two adjacent upper circuit layers in the upper circuit layer to electrically connect the two adjacent upper circuit layers in the upper circuit layer, and other some of the plurality of internal vias are exposed from the top surface of the upper conductive structure.

3. The wiring structure according to claim 1, wherein the reference mark of the upper conductive structure and the bottom circuit layer of the upper conductive structure are on the same layer and formed simultaneously, wherein the reference mark of the lower conductive structure and the top circuit layer of the lower conductive structure are on the same layer and formed simultaneously.

4. The wiring structure according to claim 3, wherein the bottommost circuit layer of the upper conductive structure and the topmost circuit layer of the lower conductive structure are embedded in the intermediate layer.

5. The wiring structure according to claim 1, wherein the bottom surface of the upper through-hole is located in the intermediate layer and is higher than the bottom surface of the intermediate layer.

6. The wiring structure according to claim 1, wherein the lateral peripheral surface of the upper conductive structure is not coplanar with the lateral peripheral surface of the lower conductive structure.

7. The wiring structure according to claim 1, further comprising: An external circuit layer is disposed on and protrudes from the top surface of the upper conductive structure, wherein the upper through-hole and the external circuit layer are integrally formed.

8. The wiring structure according to claim 7, wherein the external circuit layer contacts the internal via of the upper conductive structure.

9. The wiring structure according to claim 7, wherein the upper conductive structure includes a high-density region and a low-density region, the density of circuit lines in the high-density region is greater than the density of circuit lines in the low-density region, the upper through-hole is disposed in the low-density region of the upper conductive structure, and the high-density region is a chip bonding region.

10. The wiring structure according to claim 9, further comprising: A semiconductor chip is electrically connected and bonded to the external circuit layer of the upper conductive structure via a first connecting element, wherein the second lower circuit layer of the lower conductive structure is electrically connected and bonded to the substrate via a second connecting element.

11. The wiring structure according to claim 9, wherein within the vertical projection range of the high-density area, there is no vertical conductive path between the upper conductive structure and the lower conductive structure.

12. A wiring structure comprising: An upper conductive structure includes multiple upper dielectric layers, multiple upper circuit layers in contact with the multiple upper dielectric layers, multiple internal vias, and at least one reference mark, wherein the multiple internal vias gradually narrow upwards, wherein the material of the upper dielectric layers is transparent, wherein the reference mark of the upper conductive structure and the bottommost circuit layer of the multiple upper circuit layers of the upper conductive structure are on the same layer and formed simultaneously, wherein the upper conductive structure includes a low-density region and a high-density region located between the low-density regions; A lower conductive structure includes multiple lower dielectric layers, multiple lower circuit layers in contact with the multiple lower dielectric layers, and at least one reference mark, wherein the line spacing of the lower circuit layers of the lower conductive structure is greater than the line spacing of the upper circuit layers of the upper conductive structure, wherein the reference mark of the lower conductive structure and the topmost circuit layer of the multiple lower circuit layers of the lower conductive structure are on the same layer and formed simultaneously, wherein the reference mark of the upper conductive structure is aligned with the reference mark of the lower conductive structure; An intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure, the coefficient of thermal expansion of the upper conductive structure is less than the coefficient of thermal expansion of the intermediate layer, and the coefficient of thermal expansion of the intermediate layer is less than the coefficient of thermal expansion of the lower conductive structure, wherein the material of the intermediate layer is transparent, and wherein the topmost circuit layer of the lower conductive structure and the bottommost circuit layer of the upper conductive structure are embedded in the intermediate layer; as well as At least one via extending through the upper conductive structure, the intermediate layer, and the lower conductive structure, wherein the at least one via has a uniform width, wherein the via is disposed in the low-density region of the upper conductive structure, wherein the via extends through and contacts the bottommost circuit layer of the upper conductive structure, the topmost circuit layer of the lower conductive structure, and the bottommost circuit layer of the lower conductive structure, wherein there is no vertical conductive path between the upper conductive structure and the lower conductive structure within the vertical projection range of the high-density region.

13. The wiring structure according to claim 12, wherein the coefficient of thermal expansion of the intermediate layer is greater than 0.8 times the coefficient of thermal expansion of the lower conductive structure.

14. The wiring structure of claim 12, wherein some of the plurality of internal vias of the upper conductive structure are disposed between two adjacent ones in the upper circuit layer to electrically connect the two adjacent ones in the upper circuit layer, and other some of the plurality of internal vias are exposed from the top surface of the upper conductive structure.

15. The wiring structure of claim 12, wherein the through-hole comprises a conductive layer and an insulating material, the conductive layer defining a central hole, and the insulating material filling the central hole of the conductive layer, wherein the wiring structure further comprises: An external circuit layer is disposed on and protrudes from the top surface of the upper conductive structure, wherein the conductive layer and the external circuit layer are integrally formed.

16. The wiring structure according to claim 15, wherein the bottom surface of the conductive layer and the bottom surface of the bottommost circuit layer of the lower conductive structure are coplanar.

17. The wiring structure according to claim 15, wherein the external circuit layer directly contacts the plurality of internal vias of the upper conductive structure.

18. The wiring structure according to claim 12, wherein the upper conductive structure is a coreless substrate and the lower conductive structure is a core substrate.

19. The wiring structure according to claim 12, wherein the lower conductive structure further comprises: A core substrate has a top surface and a bottom surface opposite the top surface, and defines a first through-hole and a second through-hole extending through the core portion, wherein the through-hole extends through the second through-hole; A substrate interconnect via is disposed in the first through-hole for vertical connection; and Multiple upper interconnect vias are used to electrically connect the multiple lower circuit layers, wherein each upper interconnect via gradually narrows downwards from the top surface to the bottom surface of the lower conductive structure, and the narrowing direction of the multiple upper interconnect vias of the lower conductive structure is different from the narrowing direction of the multiple internal vias of the upper conductive structure.

20. The wiring structure of claim 19, wherein the side surface of the lower conductive structure is offset from the side surface of the upper conductive structure, wherein the width of the upper conductive structure is smaller than the width of the intermediate layer.

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