wiring structure

Abstract

A wiring structure includes at least an upper conductive structure, a lower conductive structure, and an intermediate layer. The upper conductive structure includes at least an upper dielectric layer, at least an upper circuit layer in contact with the upper dielectric layer, and at least a bonding portion electrically connected to the upper circuit layer. The lower conductive structure includes at least a lower dielectric layer and at least a lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.

Description

Technical Field

[0001] This disclosure relates to a wiring structure and a method of manufacturing it, and to a wiring structure comprising at least two conductive structures attached or bonded together by an intermediate layer, and a method of manufacturing said wiring structure. Background Technology

[0002] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips integrate an increasing number of electronic components to achieve better electrical performance and more functions. Correspondingly, semiconductor chips have more input / output (I / O) connections. To manufacture semiconductor packages containing semiconductor chips with an increased number of I / O connections, the size of the circuit layers in the semiconductor substrate supporting the semiconductor chips may increase accordingly. Consequently, the thickness and warpage of the semiconductor substrate may increase, and the yield of the semiconductor substrate may decrease. Summary of the Invention

[0003] In some embodiments, a wiring structure includes: (a) at least one upper conductive structure comprising at least one upper dielectric layer, at least one upper circuit layer in contact with the upper dielectric layer, and at least one bonding portion electrically connected to the upper circuit layer; (b) a lower conductive structure comprising at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer; and (c) an intermediate layer disposed between the at least one upper conductive structure and the lower conductive structure and bonding the at least one upper conductive structure and the lower conductive structure together, wherein the at least one upper conductive structure is electrically connected to the lower conductive structure.

[0004] In some embodiments, a wiring structure includes: (a) a low-density stack structure including at least one dielectric layer, at least one low-density circuit layer in contact with the dielectric layer, and at least one bonding portion electrically connected to the low-density circuit layer; (b) at least one high-density stack structure disposed on the low-density stack structure, wherein the high-density stack structure includes at least one dielectric layer, at least one high-density circuit layer in contact with the dielectric layer of the high-density stack structure, and at least one bonding portion electrically connected to the high-density circuit layer; (c) an intermediate layer disposed between the low-density stack structure and the high-density stack structure and bonding the low-density stack structure together; and (d) a plurality of bonding lines connecting the at least one bonding portion of the at least one high-density stack structure to the at least one bonding portion of the low-density stack structure.

[0005] In some embodiments, a wiring structure includes: (a) a low-density stack structure including at least one dielectric layer and at least one low-density circuit layer in contact with the dielectric layer; (b) at least one high-density stack structure disposed on the low-density stack structure, wherein the high-density stack structure includes at least one dielectric layer, at least one high-density circuit layer in contact with the dielectric layer of the high-density stack structure, and at least one bonding portion electrically connected to the high-density circuit layer; (c) an intermediate layer disposed between the low-density stack structure and the high-density stack structure and bonding the low-density stack structure together; and (d) a plurality of vias extending through at least a portion of the at least one high-density stack structure, the intermediate layer, and at least a portion of the low-density stack structure, and electrically connecting the at least one high-density stack structure and the low-density stack structure. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of some embodiments of this disclosure can be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0008] Figure 2 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0009] Figure 3 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0010] Figure 4 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0011] Figure 5 illustrate Figure 4 A 3D diagram of the wiring structure.

[0012] Figure 6 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0013] Figure 7 illustrate Figure 6 A 3D diagram of the wiring structure.

[0014] Figure 8 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0015] Figure 9A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0016] Figure 10 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0017] Figure 11 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0018] Figure 12 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0019] Figure 13 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0020] Figure 14 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0021] Figure 15 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0022] Figure 16 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0023] Figure 17 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0024] Figure 18 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0025] Figure 19 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0026] Figure 20 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0027] Figure 21 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0028] Figure 22 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0029] Figure 23 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0030] Figure 24 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0031] Figure 25 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0032] Figure 26 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0033] Figure 27 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0034] Figure 28 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0035] Figure 29 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0036] Figure 30 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0037] Figure 31 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0038] Figure 32 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0039] Figure 33 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0040] Figure 34 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0041] Figure 35 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0042] Figure 36This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0043] Figure 37 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. Detailed Implementation

[0044] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0045] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0046] To meet the increased I / O count requirements, the number of dielectric layers on the substrate must be increased. In some embodiments, the manufacturing process of the core substrate may include the following steps. First, a core with two copper foils disposed on both sides of the core is provided. Subsequently, multiple dielectric layers and multiple circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in one dielectric layer. Therefore, the core substrate may include multiple stacked dielectric layers and multiple circuit layers embedded in the dielectric layers on both sides of the core. Because the linewidth / line space (L / S) of the circuit layers of such a core substrate can be greater than or equal to 10 micrometers (μm) / 10 μm, the number of dielectric layers of such a core substrate must be relatively large. Although the manufacturing cost of such a core substrate is lower, the manufacturing yield of the circuit layers and dielectric layers of such a core substrate is also lower, thus the yield of such a core substrate is low. In addition, the dielectric layers are relatively thick, therefore, such a core substrate is relatively thick. In a comparative embodiment, if the package has 10,000 I / O counts, then such a core substrate may require twelve circuit layers and dielectric layers. The manufacturing yield of one layer (comprising a circuit layer and a dielectric layer) of this type of core substrate can be 90%. Therefore, the yield of this type of core substrate can be (0.9). 12=28.24%. Furthermore, the warpage of the twelve circuit and dielectric layers can accumulate, potentially resulting in severe warpage in the top few layers. Consequently, the manufacturing yield of such core substrates may be even lower.

[0047] To address the above issues, in some embodiments, a coreless substrate is provided. The coreless substrate may comprise multiple dielectric layers and multiple fan-out circuit layers. In some embodiments, the fabrication process of the coreless substrate may include the following steps: First, a carrier is provided. Subsequently, multiple dielectric layers and multiple fan-out circuit layers are formed or stacked on the surface of the carrier. A fan-out circuit layer may be embedded within a dielectric layer. Subsequently, the carrier is removed. Therefore, the coreless substrate may comprise only multiple stacked dielectric layers and multiple fan-out circuit layers embedded within the dielectric layers. Because the linewidth / spacing (L / S) of the fan-out circuit layers in such a coreless substrate can be less than or equal to 2 μm / 2 μm, the number of dielectric layers in such a coreless substrate can be reduced. Furthermore, the fabrication yield of the fan-out circuit layers and dielectric layers in such a coreless substrate is high. For example, the fabrication yield of one layer (comprising one fan-out circuit layer and one dielectric layer) in such a coreless substrate can be 99%. However, the fabrication cost of such a coreless substrate is relatively high.

[0048] At least some embodiments of this disclosure provide wiring structures with an acceptable trade-off between yield and manufacturing cost. In some embodiments, the wiring structure includes an upper conductive structure and a lower conductive structure bonded to the upper conductive structure via an intermediate layer. At least some embodiments of this disclosure further provide techniques for manufacturing the wiring structures.

[0049] Figure 1 A cross-sectional view illustrating a wiring structure 1 according to some embodiments of the present disclosure is provided. The wiring structure 1 includes at least one upper conductive structure (including, for example, a first upper conductive structure 2a), a lower conductive structure 3, an intermediate layer 12, and a plurality of first bonding wires 15a.

[0050] The first upper conductive structure 2a includes at least one dielectric layer (including, for example, a first dielectric layer 20 and a second dielectric layer 26), at least one circuit layer (including, for example, a first circuit layer 24 and a second circuit layer 24' formed of a metal, metal alloy, or other conductive material), and at least one bonding portion 14a. The circuit layer (including, for example, the first circuit layer 24 and the second circuit layer 24') is in contact with the dielectric layer (e.g., the first dielectric layer 20 and the second dielectric layer 26). The bonding portion 14a is electrically connected to the circuit layer (including, for example, the first circuit layer 24 and the second circuit layer 24'). In some embodiments, the bonding portion 14a extends through the second dielectric layer 26 and contacts the first circuit layer 24. That is, the second dielectric layer 26 defines a via for accommodating the bonding portion 14a. Furthermore, the bonding portion 14a tapers downwardly; that is, the size of the top portion of the bonding portion 14a is larger than the size of the bottom portion of the bonding portion 14a. In some embodiments, the bonding portion 14a is a monolithic structure or a single-piece structure having a homogeneous material composition. The bonding portion 14a may be a bonding pad, such as a finger pad for wire bonding. The dielectric layer (e.g., the first dielectric layer 20 and the second dielectric layer 26) may also be referred to as the upper dielectric layer, and the circuit layer (including, for example, the first circuit layer 24 and the second circuit layer 24') may also be referred to as the upper circuit layer.

[0051] In some embodiments, the first upper conductive structure 2a may resemble a coreless substrate and may be of wafer type, panel type, or strip type. The first upper conductive structure 2a may also be referred to as a "stacked structure," a "high-density conductive structure," or a "high-density stacked structure." The circuit layers of the first upper conductive structure 2a (including, for example, a first circuit layer 24 and a second circuit layer 24') may also be referred to as "high-density circuit layers." In some embodiments, the density of circuit lines (including, for example, traces or pads) in the high-density circuit layer is greater than the density of circuit lines in the low-density circuit layer. That is, the count of circuit lines (including, for example, traces or pads) per unit area of ​​the high-density circuit layer is greater than the count of circuit lines per equal unit area of ​​the low-density circuit layer, for example, about 1.2 times or more, about 1.5 times or more, or about 2 times or more. Alternatively or in combination, the linewidth / spacing (L / S) of the high-density circuit layer is less than the L / S of the low-density circuit layer, for example, about 90% or less, about 50% or less, or about 20% or less. In addition, conductive structures containing high-density circuit layers can be designated as "high-density conductive structures", and conductive structures containing low-density circuit layers can be designated as "low-density conductive structures".

[0052] The first upper conductive structure 2a has a top surface 21, a bottom surface 22 opposite to the top surface 21, and a side surface 23a extending between the top surface 21 and the bottom surface 22. The first upper conductive structure 2a includes multiple dielectric layers (e.g., a first dielectric layer 20 and a second dielectric layer 26), multiple circuit layers (e.g., a first circuit layer 24 and a second circuit layer 24'), multiple bonding portions 14a, and at least one inner via 25. The dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) are stacked one on top of the other. For example, the second dielectric layer 26 is disposed on the first dielectric layer 20, and therefore, the second dielectric layer 26 is the topmost dielectric layer. In one embodiment, the material of the dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) is transparent and can be seen through by the human eye or a machine. That is, markings disposed on the bottom surface 22 of the adjacent first upper conductive structure 2a can be identified or detected by the human eye or a machine from the top surface 21 of the first upper conductive structure 2a. In some embodiments, the transparent material of the dielectric layer has a transmittance of at least about 60%, at least about 70%, or at least about 80% for wavelengths in the visible range (or other relevant wavelengths for detecting the marker).

[0053] Furthermore, the first dielectric layer 20 has a top surface 201 and a bottom surface 202 opposite to the top surface 201. The second dielectric layer 26 has a top surface 261 and a bottom surface 262 opposite to the top surface 261. The bottom surface 262 of the second dielectric layer 26 is disposed on and in contact with the top surface 201 of the adjacent first dielectric layer 20. Therefore, the top surface 21 of the upper conductive structure 2a is the top surface 261 of the second dielectric layer 26, and the bottom surface 22 of the upper conductive structure 2a is the bottom surface 202 of the bottommost first dielectric layer 20.

[0054] The first circuit layer 24 may be a fan-out circuit layer or a redistribution layer (RDL), and the L / S ratio of the first circuit layer 24 may be less than or equal to 2 μm / 2 μm, or less than or equal to 1.8 μm / 1.8 μm. The first circuit layer 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. In some embodiments, the first circuit layer 24 is embedded in the first dielectric layer 20, and the top surface 241 of the first circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. In some embodiments, the first circuit layer 24 may include a seed layer 243 and a conductive material 244 (e.g., a metallic material) disposed on the seed layer 243. In addition, the second circuit layer 24' is embedded in the second dielectric layer 26, and the top surface of the second circuit layer 24' may be substantially coplanar with the top surface 261 of the second dielectric layer 26. The L / S of the second circuit layer 24' can be greater than or equal to the L / S of the first circuit layer 24.

[0055] The first upper conductive structure 2a includes a plurality of internal vias 25. The internal vias 25 are disposed between the first circuit layer 24 and the second circuit layer 24' for electrical connection between the first circuit layer 24 and the second circuit layer 24'. In some embodiments, the internal vias 25 may include a seed layer 251 and a conductive material 252 (e.g., a metallic material) disposed on the seed layer 251. In some embodiments, the internal vias 25 and the first circuit layer 24 may be integrally formed as a single piece or monolithic structure. The internal vias 25 gradually narrow upwards from the bottom surface 22 of the upper conductive structure 2a toward the top surface 21. That is, the size (e.g., width) of the top portion of the internal via 25 is smaller than the size (e.g., width) of the bottom portion of the internal via 25 closer to the bottom surface 22. Therefore, the narrowing direction of the internal vias 25 is different from the narrowing direction of the joining portion 14a. In some embodiments, the maximum width of the internal guide hole 25 (e.g., at the bottom portion) may be less than or equal to about 25 μm, such as about 25 μm, about 20 μm, about 15 μm or about 10 μm.

[0056] The lower conductive structure 3 includes at least one dielectric layer (including, for example, a first upper dielectric layer 30, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) and at least one circuit layer (including, for example, a first upper circuit layer 34, a second upper circuit layer 38, a first lower circuit layer 34a, and a second lower circuit layer 38a) in contact with the dielectric layer (e.g., the first upper dielectric layer 30, the first lower dielectric layer 30a, and the second lower dielectric layer 36a), formed of, for example, a metal, a metal alloy, or other conductive material. The dielectric layer (e.g., the first upper dielectric layer 30, the first lower dielectric layer 30a, and the second lower dielectric layer 36a) may also be referred to as the lower dielectric layer, and the circuit layer (e.g., the first upper circuit layer 34, the second upper circuit layer 38, the first lower circuit layer 34a, and the second lower circuit layer 38a) may also be referred to as the lower circuit layer. In some embodiments, the lower conductive structure 3 may resemble a core substrate, further comprising a core portion 37, and may be wafer-type, panel-type, or strip-type. The lower conductive structure 3 may also be referred to as a "stacked structure," a "low-density conductive structure," or a "low-density stacked structure." The circuit layers of the lower conductive structure 3 (including, for example, a first upper circuit layer 34, a second upper circuit layer 38, a first lower circuit layer 34a, and a second lower circuit layer 38a) may also be referred to as "low-density circuit layers." Figure 1As shown, the lower conductive structure 3 has a top surface 31, a bottom surface 32 opposite to the top surface 31, and a side surface 33 extending between the top surface 31 and the bottom surface 32. The lower conductive structure 3 includes multiple dielectric layers (e.g., a first upper dielectric layer 30, a first lower dielectric layer 30a, and a second lower dielectric layer 36a), multiple circuit layers (e.g., a first upper circuit layer 34, a second upper circuit layer 38, a first lower circuit layer 34a, and a second lower circuit layer 38a), and at least one internal via (including, for example, multiple upper interconnect vias 35 and multiple lower interconnect vias 35a).

[0057] The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371, and defines a plurality of through holes 373 extending through the core portion 37. Interconnection vias 39 are disposed or formed in each through hole 373 for vertical connection. In some embodiments, each interconnection via 39 includes a base metal layer 391 and an insulating material 392. The base metal layer 391 is disposed or formed on the sidewall of the through hole 373 and defines a central through hole. The insulating material 392 fills the central through hole defined by the base metal layer 391. In some embodiments, the insulating material may be omitted from the interconnection via 39, and it may comprise a bulk metal material filling the through hole 373.

[0058] A first upper dielectric layer 30 is disposed on the top surface 371 of the core portion 37, and has a top surface 301 and a bottom surface 302 opposite to the top surface 301. Therefore, the bottom surface 302 of the first upper dielectric layer 30 contacts the top surface 371 of the core portion 37. A first lower dielectric layer 30a is disposed on the bottom surface 372 of the core portion 37, and has a top surface 301a and a bottom surface 302a opposite to the top surface 301a. Therefore, the top surface 301a of the first lower dielectric layer 30a contacts the bottom surface 372 of the core portion 37. A second lower dielectric layer 36a is stacked or disposed on the first lower dielectric layer 30a, and has a top surface 361a and a bottom surface 362a opposite to the top surface 361a. Therefore, the top surface 361a of the second lower dielectric layer 36a contacts the bottom surface 302a of the first lower dielectric layer 30a, and the second lower dielectric layer 36a is the bottommost dielectric layer. Figure 1 As shown, the top surface 31 of the lower conductive structure 3 is the top surface 301 of the first upper dielectric layer 30, and the bottom surface 32 of the lower conductive structure 3 is the bottom surface 362a of the second lower dielectric layer 36a.

[0059] The thickness of each dielectric layer (e.g., the first dielectric layer 20 and the second dielectric layer 26) of the first upper conductive structure 2a is less than or equal to about 40%, less than or equal to about 35%, and less than or equal to about 30% of the thickness of each dielectric layer (e.g., the first upper dielectric layer 30, the first lower dielectric layer 30a, and the second lower dielectric layer 36a) of the lower conductive structure 3. For example, the thickness of each dielectric layer (e.g., the first dielectric layer 20 and the second dielectric layer 26) of the first upper conductive structure 2a may be less than or equal to about 7 μm, and the thickness of each dielectric layer (e.g., the first upper dielectric layer 30, the first lower dielectric layer 30a, and the second lower dielectric layer 36a) of the lower conductive structure 3 may be about 40 μm.

[0060] The L / S ratio of the first upper circuit layer 34 may be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first upper circuit layer 34 may be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the first upper conductive structure 2a. The first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In some embodiments, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37 and is covered by the first upper dielectric layer 30. The bottom surface 342 of the first upper circuit layer 34 contacts the top surface 371 of the core portion 37. In some embodiments, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be formed of copper foil (e.g., may constitute part of copper foil). The second metal layer 344 is disposed on the first metal layer 343 and may be a copper-plated layer. The third metal layer 345 is disposed on the second metal layer 344 and may be another copper-plated layer. In some embodiments, the third metal layer 345 may be omitted.

[0061] The L / S ratio of the second upper circuit layer 38 can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second upper circuit layer 38 can be approximately equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the first upper conductive structure 2a. The second upper circuit layer 38 has a top surface 381 and a bottom surface 382 opposite to the top surface 381. In some embodiments, the second upper circuit layer 38 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 and is covered by the second upper dielectric layer 36. The bottom surface 382 of the second upper circuit layer 38 contacts the top surface 301 of the first upper dielectric layer 30. In some embodiments, the second upper circuit layer 38 is electrically connected to the first upper circuit layer 34 through an upper interconnect via 35. That is, the upper interconnect via 35 is disposed between the second upper circuit layer 38 and the first upper circuit layer 34 for electrically connecting the second upper circuit layer 38 and the first upper circuit layer 34. In some embodiments, the second upper circuit layer 38 and the upper interconnect via 35 are integrally formed as a single block or single piece structure. Each upper interconnect via 35 gradually narrows downwards along the direction from the top surface 31 of the lower conductive structure 3 toward the bottom surface 32.

[0062] The L / S ratio of the first lower circuit layer 34a can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first lower circuit layer 34a can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the first upper conductive structure 2a. The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In some embodiments, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37 and is covered by a first lower dielectric layer 30a. The top surface 341a of the first lower circuit layer 34a contacts the bottom surface 372 of the core portion 37. In some embodiments, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be formed of copper foil. The second metal layer 344a is disposed on the first metal layer 343a and may be a copper-plated layer. The third metal layer 345a is disposed on the second metal layer 344a and may be another copper-plated layer. In some embodiments, the third metal layer 345a may be omitted.

[0063] The L / S ratio of the second lower circuit layer 38a can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second lower circuit layer 38a can be approximately equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the first upper conductive structure 2a. The second lower circuit layer 38a has a top surface 381a and a bottom surface 382a opposite to the top surface 381a. In some embodiments, the second lower circuit layer 38a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a and is covered by the second lower dielectric layer 36a. The top surface 381a of the second lower circuit layer 38a contacts the bottom surface 302a of the first lower dielectric layer 30a. In some embodiments, the second lower circuit layer 38a is electrically connected to the first lower circuit layer 34a through a lower interconnect via 35a. That is, the lower interconnect via 35a is disposed between the second lower circuit layer 38a and the first lower circuit layer 34a for electrical connection between the second lower circuit layer 38a and the first lower circuit layer 34a. In some embodiments, the second lower circuit layer 38a and the lower interconnect via 35a are integrally formed as a single piece or a single component structure. The lower interconnect via 35a gradually narrows upwards along the direction from the bottom surface 32 of the lower conductive structure 3 toward the top surface 31.

[0064] In some embodiments, each interconnect via 39 is electrically connected to the first upper circuit layer 34 and the first lower circuit layer 34a. The base metal layer 391 of the interconnect via 39, the second metal layer 344 of the first upper circuit layer 34, and the second metal layer 344a of the first lower circuit layer 34a can be integrally and simultaneously formed as a single block or a single piece structure.

[0065] In some embodiments, from a top view, the size of the first upper conductive structure 2a is smaller than the size of the lower conductive structure 3. The gap between the side surface 23a of the first upper conductive structure 2a and the side surface 33 of the lower conductive structure 3 may be about 100 μm; therefore, the first upper conductive structure 2a does not completely cover (or at least partially exposes) the joint portion (e.g., pad portion 384) of the lower conductive structure 3.

[0066] An intermediate layer 12 is inserted or disposed between the first upper conductive structure 2a and the lower conductive structure 3 to bond the first upper conductive structure 2a and the lower conductive structure 3 together. That is, the intermediate layer 12 adheres to the bottom surface 22 of the first upper conductive structure 2a and the top surface 31 of the lower conductive structure 3. In some embodiments, the intermediate layer 12 may be an adhesive layer that is cured from an adhesive material (e.g., a cured adhesive material, such as an adhesive polymer). The intermediate layer 12 has a top surface and a bottom surface opposite to the top surface. The top surface of the intermediate layer 12 contacts the bottom surface 22 of the first upper conductive structure 2a (that is, the bottom surface 22 of the first upper conductive structure 2a is attached to the top surface of the intermediate layer), and the bottom surface of the intermediate layer 12 contacts the top surface 31 of the lower conductive structure 3. In some embodiments, the bonding force between two adjacent dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) of the first upper conductive structure 2a is greater than the bonding force between the dielectric layer (e.g., the first dielectric layer 20) of the first upper conductive structure 2a and the intermediate layer 12. The surface roughness of the boundary between the two adjacent dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) of the first upper conductive structure 2a is greater than the surface roughness of the boundary between the dielectric layer (e.g., the first dielectric layer 20) of the first upper conductive structure 2a and the intermediate layer 12, for example, in terms of root mean squared surface roughness, about 1.1 times or more, about 1.3 times or more, or about 1.5 times or more.

[0067] The first bonding line 15a connects the bonding portion 14a of the first upper conductive structure 2a to the corresponding bonding portion (e.g., pad portion 384) of the second upper circuit layer 38 of the lower conductive structure 3. Therefore, the first upper conductive structure 2a is electrically connected to the lower conductive structure 3 via the first bonding line 15a.

[0068] like Figure 1As illustrated in the embodiments described herein, wiring structure 1 is a combination of a first upper conductive structure 2a and a lower conductive structure 3. The first circuit layer 24 and the second circuit layer 26 of the first upper conductive structure 2a have fine pitch, high yield, and low thickness; and the circuit layers of the lower conductive structure 3 (e.g., first upper circuit layer 34, second upper circuit layer 38, first lower circuit layer 34a, and second lower circuit layer 38a) have low manufacturing cost. Therefore, wiring structure 1 offers a favorable trade-off between yield and manufacturing cost, and wiring structure 1 has a relatively low thickness. In some embodiments, if the package has 10,000 I / Os, then wiring structure 1 comprises two circuit layers of the first upper conductive structure 2a (e.g., first circuit layer 24 and second circuit layer 26) and four circuit layers of the lower conductive structure 3 (e.g., first upper circuit layer 34, second upper circuit layer 38, first lower circuit layer 34a, and second lower circuit layer 38a). The manufacturing yield of one layer in the first circuit layer 24 and the second circuit layer 26 of the first upper conductive structure 2a can be 99%, and the manufacturing yield of one layer in the circuit layers of the lower conductive structure 3 (e.g., the first upper circuit layer 34, the second upper circuit layer 38, the first lower circuit layer 34a, and the second lower circuit layer 38a) can be 90%. Therefore, the yield of the wiring structure 1 can be improved. Furthermore, the warpage of the first upper conductive structure 2a and the warpage of the lower conductive structure 3 are separate and do not affect each other. In some embodiments, the warpage shape of the first upper conductive structure 2a may be different from the warpage shape of the lower conductive structure 3. For example, the warpage shape of the first upper conductive structure 2a may be convex, and the warpage shape of the lower conductive structure 3 may be concave. In some embodiments, the warpage shape of the first upper conductive structure 2a may be the same as the warpage shape of the lower conductive structure 3; however, the warpage of the lower conductive structure 3 does not accumulate on the warpage of the first upper conductive structure 2a. Therefore, the yield of wiring structure 1 can be further improved.

[0069] Furthermore, during the manufacturing process, the lower conductive structure 3 and the first upper conductive structure 2a are tested separately before being joined together. Therefore, known good lower conductive structures 3 and known good first upper conductive structures 2a can be selectively joined together. Defective (or unqualified) lower conductive structures 3 and defective (or unqualified) first upper conductive structures 2a can be discarded. Therefore, the yield of the wiring structure 1 can be further improved.

[0070] Figure 2 This illustration shows a cross-sectional view of a wiring structure 1a according to some embodiments of the present disclosure. The wiring structure 1a is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the joint portion 14 of the first upper conductive structure 2. For example... Figure 2As shown, the bonding portion 14 includes a pad portion 244' and a via portion 25a. The pad portion 244' may be part of the second circuit layer 24' of the first upper conductive structure 2. The via portion 25a is disposed between the first circuit layer 24 and the second circuit layer 24' for electrical connection between the first circuit layer 24 and the second circuit layer 24'. The top portion of the via portion 25a contacts and / or is electrically connected to the pad portion 244' of the second circuit layer 24'. In some embodiments, the via portion 25a may include a seed layer 251 and a conductive material 252 (e.g., a metallic material) disposed on the seed layer 251. In some embodiments, the via portion 25a and the first circuit layer 24 may be integrally formed as a monolithic or single-piece structure. The via portion 25a gradually narrows upwards along a direction from the bottom surface 22 of the upper conductive structure 2 toward the top surface 21. That is, the size (e.g., width) of the top portion of the via portion 25a is smaller than the size (e.g., width) of the bottom portion of the via portion 25a closer to the bottom surface 22. Therefore, the gradual narrowing direction of the internal guide hole 25 is the same as the gradual narrowing direction of the guide hole portion 25a of the joining portion 14. In some embodiments, the size of the guide hole portion 25a may be larger than the size of the internal guide hole 25. Figure 2 As shown, the end of the first bonding line 15a contacts and / or is electrically connected to the pad portion 244' of the second circuit layer 24' of the first upper conductive structure 2. In some embodiments, the pad portion 244' of the second circuit layer 24' of the first upper conductive structure 2 may be omitted, and the top portion of the via portion 25a may be exposed from the top surface 261 of the second dielectric layer 26. Therefore, the via portion 25a is the bonding portion 14, and the end of the first bonding line 15a may directly contact and / or be electrically connected to the top portion of the via portion 25a.

[0071] Figure 3 This illustration shows a cross-sectional view of a wiring structure 1b according to some embodiments of the present disclosure. The wiring structure 1b is similar to... Figure 1 The wiring structure 1 shown differs in that at least one upper conductive structure comprises multiple upper conductive structures stacked one on top of the other (e.g., a first upper conductive structure 2a, a second upper conductive structure 2b, and a third upper conductive structure 2c). The structures of the second upper conductive structure 2b and the third upper conductive structure 2c are substantially the same as the structure of the first upper conductive structure 2a. The second upper conductive structure 2b has a side surface 23b and includes a bonding portion 14b. The third upper conductive structure 2c has a side surface 23c and includes a bonding portion 14c. Figure 3As shown, the upper conductive structures (e.g., the first upper conductive structure 2a, the second upper conductive structure 2b, and the third upper conductive structure 2c) are of different sizes. For example, from a top view, the second upper conductive structure 2b is smaller than the first upper conductive structure 2a, and the third upper conductive structure 2c is smaller than the second upper conductive structure 2b. The gap between the side surface 23b of the second upper conductive structure 2b and the side surface 23a of the first upper conductive structure 2a can be about 80 μm; therefore, the second upper conductive structure 2b does not completely cover (or at least partially exposes) the joint portion 14a of the first upper conductive structure 2a. Furthermore, the gap between the side surface 23c of the third upper conductive structure 2c and the side surface 23b of the second upper conductive structure 2b can be about 80 μm; therefore, the third upper conductive structure 2c does not completely cover (or at least partially exposes) the joint portion 14b of the second upper conductive structure 2b.

[0072] Additionally, the wiring structure 1b further includes at least one intervening layer 13 (e.g., an adhesive layer) and a plurality of second bonding wires 15b. One intervening layer 13 is disposed between a first upper conductive structure 2a and an adjacent second upper conductive structure 2b, bonding the two adjacent upper conductive structures (e.g., the first upper conductive structure 2a and the second upper conductive structure 2b) together. Another intervening layer 13 is disposed between a second upper conductive structure 2b and an adjacent third upper conductive structure 2c, bonding the two adjacent upper conductive structures (e.g., the second upper conductive structure 2b and the third upper conductive structure 2c) together. Second bonding wires 15b are included for connecting the bonding portions of two adjacent upper conductive structures. For example, some of the second bonding wires 15b connect the bonding portions 14b of the second upper conductive structure 2b and the bonding portions 14a of the first upper conductive structure 2a. Some of the second bonding wires 15b connect the bonding portions 14c of the third upper conductive structure 2c and the bonding portions 14b of the second upper conductive structure 2b.

[0073] In some embodiments, there may be no internal vias between the upper conductive structures (e.g., the first upper conductive structure 2a, the second upper conductive structure 2b, and the third upper conductive structure 2c) for internal electrical connection. That is, there may be no internal electrical connection path between the upper conductive structures (e.g., the first upper conductive structure 2a, the second upper conductive structure 2b, and the third upper conductive structure 2c). Therefore, the upper conductive structures (e.g., the first upper conductive structure 2a, the second upper conductive structure 2b, and the third upper conductive structure 2c) may be electrically connected to each other only through the second bonding line 15b.

[0074] Figure 4 A cross-sectional view illustrating a wiring structure 1c according to some embodiments of the present disclosure. Figure 5 illustrate Figure 4 A 3D view of the wiring structure 1c. The wiring structure 1c is similar to... Figure 1 The wiring structure 1 shown differs in that it includes multiple electronic devices (e.g., a first memory die 40a, a second memory die 40b, a third memory die 40c, a fourth memory die 40d, and a fifth memory die 40e) and multiple third bonding lines 15c. The electronic devices (e.g., the first memory die 40a, the second memory die 40b, the third memory die 40c, the fourth memory die 40d, and the fifth memory die 40e) are stacked vertically on top of each other and on a first upper conductive structure 2a. The positions of the electronic devices (e.g., the first memory die 40a, the second memory die 40b, the third memory die 40c, the fourth memory die 40d, and the fifth memory die 40e) can be shifted or laterally displaced from each other to facilitate the wire bonding process. For example, the second memory die 40b is shifted from the first memory die 40a to expose the bonding portion of the first memory die 40a. Figure 4 and Figure 5 As shown, the electronic devices (e.g., the first memory die 40a, the second memory die 40b, the third memory die 40c, the fourth memory die 40d, and the fifth memory die 40e) may be the same size or different from each other.

[0075] The bonding portion, including the third bonding line 15c for connecting electronic devices (e.g., the first memory die 40a, the second memory die 40b, the third memory die 40c, the fourth memory die 40d, and the fifth memory die 40e), is connected to the bonding portion 14a of the first upper conductive structure 2a. Figure 5As shown, the first upper conductive structure 2a may include a plurality of bonding regions 27 (e.g., a first bonding region 271, a second bonding region 272, a third bonding region 273, a fourth bonding region 274, a fifth bonding region 275, and a sixth bonding region 276). Each of the bonding regions 27 (e.g., the first bonding region 271, the second bonding region 272, the third bonding region 273, the fourth bonding region 274, the fifth bonding region 275, and the sixth bonding region 276) includes a plurality of bonding portions 14a. In some embodiments, a first memory die 40a is electrically connected to the bonding portion 14a in the first bonding region 271 via a third bonding line 15c. A second memory die 40b is electrically connected to the bonding portion 14a in the second bonding region 272 via a third bonding line 15c. A third memory die 40c is electrically connected to the bonding portion 14a in the third bonding region 273 via a third bonding line 15c. A fourth memory die 40d is electrically connected to the bonding portion 14a in the fourth bonding region 274 via a third bonding line 15c. The fifth memory die 40e is electrically connected to the bonding portion 14a in the fifth bonding region 275 via the third bonding line 15c. Additionally, the bonding portion 14a in the sixth bonding region 276 is electrically connected to the pad portion 384 of the lower conductive structure 3 via the first bonding line 15a.

[0076] Figure 6 A cross-sectional view illustrating a wiring structure 1d according to some embodiments of the present disclosure. Figure 7 illustrate Figure 6 A 1D 3D view of the wiring structure. The 1D wiring structure is similar to... Figure 3 The wiring structure 1b shown differs in that it includes multiple electronic devices (e.g., a first memory die 40a, a second memory die 40b, a third memory die 40c, a fourth memory die 40d, and a fifth memory die 40e) and multiple third bonding lines 15c. The electronic devices (e.g., the first memory die 40a, the second memory die 40b, the third memory die 40c, the fourth memory die 40d, and the fifth memory die 40e) are stacked vertically on top of each other and on a third upper conductive structure 2c. The positions of the electronic devices (e.g., the first memory die 40a, the second memory die 40b, the third memory die 40c, the fourth memory die 40d, and the fifth memory die 40e) can be shifted or laterally displaced from each other to facilitate the wire bonding process. For example, the second memory die 40b is shifted from the first memory die 40a to expose the bonding portion of the first memory die 40a. Figure 6 and Figure 7 As shown, the electronic devices (e.g., the first memory die 40a, the second memory die 40b, the third memory die 40c, the fourth memory die 40d, and the fifth memory die 40e) may be the same size or different from each other.

[0077] A third bonding line 15c is included for connecting the bonding portion of electronic devices (e.g., first memory die 40a, second memory die 40b, third memory die 40c, fourth memory die 40d, and fifth memory die 40e) to the bonding portion (e.g., bonding portions 14a, 14b, 14c) of upper conductive structures (e.g., first upper conductive structure 2a, second upper conductive structure 2b, and third upper conductive structure 2c). In some embodiments, the first memory die 40a and the second memory die 40b can be electrically connected to the bonding portion 14c of the third upper conductive structure 2c via the third bonding line 15c. The third memory die 40c and the fourth memory die 40d can be electrically connected to the bonding portion 14b of the second upper conductive structure 2b via the third bonding line 15c. The fifth memory die 40e can be electrically connected to the bonding portion 14a of the first upper conductive structure 2a via the third bonding line 15c.

[0078] Figure 8 The diagram illustrates a cross-sectional view of a wiring structure 1e according to some embodiments of the present disclosure. The wiring structure 1e is similar to... Figure 1 The wiring structure 1 shown differs in that the first bonding line 15a and the pad portion 384 of the lower conductive structure 3 are omitted, and it additionally includes a plurality of through vias 16. The through vias 16 extend through at least a portion of the first upper conductive structure 2a, the intermediate layer 12, and at least a portion of the lower conductive structure 3. Figure 8 As shown, through-holes 16 extend between the bottom surface 32 of the lower conductive structure 3 and the top surface 21 of the first upper conductive structure 2a, and are disposed in a non-bonded region. Through-holes 16 may extend through and / or contact some circuit layers of the first upper conductive structure 2a and the lower conductive structure 3; therefore, the first upper conductive structure 2a is electrically connected to the lower conductive structure 3 via through-holes 16. Each of the through-holes 16 may be a monolithic structure, and the diameter of each of the through-holes 16 may be approximately 1 mm. The through-holes 16 may be formed by mechanical drilling, and each of the through-holes 16 may have a substantially uniform width. In addition to serving as an electrical connection path, the through-holes 16 may also serve as a heat dissipation path.

[0079] Figure 9 This illustration shows a cross-sectional view of a wiring structure 1f according to some embodiments of the present disclosure. The wiring structure 1f is similar to... Figure 3The wiring structure 1b shown differs in that the first bonding line 15a, the second bonding line 15b, and the pad portion 384 of the lower conductive structure 3 are omitted, and it additionally includes a plurality of through-holes 16. The through-holes 16 extend through at least a portion of the first upper conductive structure 2a, at least a portion of the second upper conductive structure 2b, at least a portion of the third upper conductive structure 2c, the intermediate layer 12, and at least a portion of the lower conductive structure 3. Figure 9 As shown, the through-hole 16 extends between the bottom surface 32 of the lower conductive structure 3 and the top surface of the third upper conductive structure 2c, and is disposed in a non-bonded region. The through-hole 16 may extend through and / or contact some circuit layers of the first upper conductive structure 2a, the second upper conductive structure 2b, and the third upper conductive structure 2c of the lower conductive structure 3; therefore, the first upper conductive structure 2a, the second upper conductive structure 2b, and the third upper conductive structure 2c are electrically connected to the lower conductive structure 3 through the through-hole 16. In addition to serving as an electrical connection path, the through-hole 16 may also serve as a heat dissipation path.

[0080] Figure 10 This illustration shows a cross-sectional view of a wiring structure 1g according to some embodiments of the present disclosure. The wiring structure 1g is similar to... Figure 4 The wiring structure 1c shown differs in that the first bonding line 15a and the pad portion 384 of the lower conductive structure 3 are omitted, and it additionally includes a plurality of through-holes 16. The through-holes 16 extend through at least a portion of the first upper conductive structure 2a, the intermediate layer 12, and at least a portion of the lower conductive structure 3. Figure 10 As shown, the through-hole 16 extends between the bottom surface 32 of the lower conductive structure 3 and the top surface 21 of the first upper conductive structure 2a, and is positioned in a non-bonded region. The through-hole 16 may extend through and / or contact some circuit layers of the first upper conductive structure 2a and the lower conductive structure 3; therefore, the first upper conductive structure 2a is electrically connected to the lower conductive structure 3 through the through-hole 16. In addition to serving as an electrical connection path, the through-hole 16 can also serve as a heat dissipation path. Figure 10 As shown, the through-hole 16 is disposed under electronic devices (e.g., first memory die 40a, second memory die 40b, third memory die 40c, fourth memory die 40d, and fifth memory die 40e) and is thermally connected to the electronic devices. Therefore, the first memory die 40a can contact the through-hole 16 and can dissipate the heat generated by the electronic devices through the through-hole 16.

[0081] Figure 11 This illustration shows a cross-sectional view of a wiring structure 1h according to some embodiments of the present disclosure. The wiring structure 1h is similar to... Figure 6The wiring structure 1d shown differs in that the first bonding line 15a, the second bonding line 15b, and the pad portion 384 of the lower conductive structure 3 are omitted, and it additionally includes a plurality of through-holes 16. The through-holes 16 extend through at least a portion of the first upper conductive structure 2a, at least a portion of the second upper conductive structure 2b, at least a portion of the third upper conductive structure 2c, the intermediate layer 12, and at least a portion of the lower conductive structure 3. Figure 11 As shown, the through-hole 16 extends between the bottom surface 32 of the lower conductive structure 3 and the top surface of the third upper conductive structure 2c, and is disposed in a non-bonded region. The through-hole 16 may extend through and / or contact some circuit layers of the first upper conductive structure 2a, the second upper conductive structure 2b, the third upper conductive structure 2c, and the lower conductive structure 3; therefore, the first upper conductive structure 2a, the second upper conductive structure 2b, and the third upper conductive structure 2c are electrically connected to the lower conductive structure 3 through the through-hole 16. In addition to serving as an electrical connection path, the through-hole 16 can also serve as a heat dissipation path. Figure 11 As shown, the through-hole 16 is disposed under electronic devices (e.g., first memory die 40a, second memory die 40b, third memory die 40c, fourth memory die 40d, and fifth memory die 40e) and is thermally connected to the electronic devices. Therefore, the first memory die 40a can contact the through-hole 16 and can dissipate the heat generated by the electronic devices through the through-hole 16.

[0082] Figures 12 to 24 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing... Figure 1 Wiring structure 1 is shown in the figure.

[0083] refer to Figure 12 A lower conductive structure 3 is provided. The lower conductive structure 3 includes a core portion 37, at least one dielectric layer (including, for example, a first upper dielectric layer 30, a first lower dielectric layer 30a, and a second lower dielectric layer 36a), and at least one circuit layer (including, for example, a first upper circuit layer 34, a second upper circuit layer 38, a first lower circuit layer 34a, and a second lower circuit layer 38a) in contact with the dielectric layer (e.g., the first upper dielectric layer 30, the first lower dielectric layer 30a, and the second lower dielectric layer 36a). In some embodiments, the lower conductive structure 3 may be manufactured as follows.

[0084] A core portion 37 with top and bottom copper foils is provided. The core portion 37 can be wafer-type, panel-type, or strip-type. The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371. The top copper foil is disposed on the top surface 371 of the core portion 37, and the bottom copper foil is disposed on the bottom surface 372 of the core portion 37. Then, a plurality of through-holes 373 are formed to extend through the core portion 37, the top copper foil, and the bottom copper foil by means of drilling technology (e.g., laser drilling or mechanical drilling) or other suitable technology.

[0085] Next, a second metal layer is formed or disposed on the top copper foil, the bottom copper foil, and the sidewalls of the first via 373 using plating technology or other suitable techniques. A portion of the second metal layer on the sidewall of each first via 373 defines a central via. Next, an insulating material 392 is disposed to fill the central via defined by the second metal layer. Next, a top third metal layer and a bottom third metal layer are formed or disposed on the second metal layer using plating technology or other suitable techniques. The third metal layer covers the insulating material 392. Next, the top copper foil, the second metal layer, and the top third metal layer are patterned to form a first upper circuit layer 34. Simultaneously, the bottom copper foil, the second metal layer, and the bottom third metal layer are patterned to form a first lower circuit layer 34a. Meanwhile, portions of the second metal layer and the insulating material 392 disposed in the via 373 form interconnect vias 39. In some embodiments, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. A first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be formed from a portion of the top copper foil. A second metal layer 344 is disposed on the first metal layer 343 and may be a copper-plated layer formed from the second metal layer. A third metal layer 345 is disposed on the second metal layer 344 and may be another copper-plated layer formed from the top third metal layer.

[0086] In some embodiments, a first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37. The first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a, and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37 and may be formed from a portion of a bottom copper foil. The second metal layer 344a is disposed on the first metal layer 343a and may be a copper-plated layer formed from the second metal layer. The third metal layer 345a is disposed on the second metal layer 344a and may be another copper-plated layer formed from the bottom third metal layer. The interconnect via 39 includes a base metal layer 391 formed from the second metal layer and an insulating material 392. In some embodiments, the interconnect via 39 may include a bulk metal material filling the via 373. The interconnect via 39 electrically connects the first upper circuit layer 34 and the first lower circuit layer 34a.

[0087] Next, a first upper dielectric layer 30 is formed or disposed on the top surface 371 of the core portion 37 using lamination technology or other suitable technology to cover the top surface 371 and the first upper circuit layer 34 of the core portion 37. Simultaneously, a first lower dielectric layer 30a is formed or disposed on the bottom surface 372 of the core portion 37 using lamination technology or other suitable technology to cover the bottom surface 372 and the first lower circuit layer 34a of the core portion 37.

[0088] Next, at least one via is formed using drilling or other suitable techniques to extend through the first upper dielectric layer 30, thereby exposing a portion of the first upper circuit layer 34. Simultaneously, at least one via is formed using drilling or other suitable techniques to extend through the first lower dielectric layer 30a, thereby exposing a portion of the first lower circuit layer 34a. Next, a top metal layer is formed on the first upper dielectric layer 30 and in the via using plating or other suitable techniques to form an upper interconnect via 35. Simultaneously, a bottom metal layer is formed on the first lower dielectric layer 30a and in the via using plating or other suitable techniques to form a lower interconnect via 35a. Figure 12 As shown, the upper interconnecting via 35 gradually narrows downwards, and the lower interconnecting via 35a gradually narrows upwards.

[0089] Next, the top metal layer is patterned to form the second upper circuit layer 38. Simultaneously, the bottom metal layer 0 is patterned to form the second lower circuit layer 38a. Then, using lamination techniques or other suitable techniques, a second lower dielectric layer 36a is formed or disposed on the bottom surface of the first lower dielectric layer 30a to cover the first lower dielectric layer 30a and the second lower circuit layer 38a. Simultaneously, a lower conductive structure 3 is formed. Next, the electrical properties of the lower conductive structure 3 are tested (e.g., open circuit / short circuit).

[0090] refer to Figures 13 to 22 A first upper conductive structure 2a is provided. The first upper conductive structure 2a is manufactured as follows. (See reference) Figure 13 A carrier 65 is provided. The carrier 65 may be a glass carrier and may be of wafer type, panel type, or strip type. Next, a release layer 66 is coated on the bottom surface of the carrier 65. Next, a conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 by physical vapor deposition (PVD) or other suitable techniques. Next, a second circuit layer 24' is formed on the conductive layer 67.

[0091] refer to Figure 14A second dielectric layer 26 is formed on the conductive layer 67 by coating technology or other suitable technology to cover the second circuit layer 24'.

[0092] refer to Figure 15 At least one via 264 is formed by exposure and development techniques or other suitable techniques to extend through the second dielectric layer 26, thereby exposing a portion of the second circuit layer 24'.

[0093] refer to Figure 16 Seed layers 68 are formed on the bottom surface 262 of the second dielectric layer 26 and in the vias 264 using PVD technology or other suitable techniques.

[0094] refer to Figure 17 A photoresist layer 69 is formed on the seed layer 68. Then, the photoresist layer 69 is patterned to expose portions of the seed layer 68 using exposure and development techniques or other suitable techniques. The photoresist layer 69 defines a plurality of openings 691. At least one opening 691 of the photoresist layer 69 corresponds to and is aligned with a via 264 of the second dielectric layer 26.

[0095] refer to Figure 18 Conductive material 70 (e.g., metallic material) is placed in the opening 691 of the photoresist layer 69 and on the seed layer 68 by means of plating technology or other suitable technology.

[0096] refer to Figure 19 The photoresist layer 69 is removed by stripping techniques or other suitable techniques.

[0097] refer to Figure 20 The portion of the seed layer 68 not covered by the conductive material 70 is removed by etching or other suitable techniques. Simultaneously, a first circuit layer 24 and at least one internal via 25 are formed. The first circuit layer 24 may be a fan-out circuit layer or an RDL, and the L / S ratio of the first circuit layer 24 may be less than or equal to about 2 μm / about 2 μm, or less than or equal to about 1.8 μm / about 1.8 μm. The first circuit layer 24 is disposed on the bottom surface 262 of the second dielectric layer 26. In some embodiments, the first circuit layer 24 may include a seed layer 243 formed by the seed layer 68 and a conductive material 244 disposed on the seed layer 243 and formed by the conductive material 70. The internal via 25 is disposed in the via 264 of the second dielectric layer 26. In some embodiments, the internal via 25 may include a seed layer 251 and a conductive material 252 disposed on the seed layer 251.

[0098] The internal guide hole 25 gradually narrows upwards.

[0099] refer to Figure 21A first dielectric layer 20 is formed or disposed on the second dielectric layer 26 to cover the first circuit layer 24.

[0100] refer to Figure 22 The carrier 65, release layer 66, and conductive layer 67 are removed. Next, at least one via is formed in the second dielectric layer 26 to expose a portion of the first circuit layer 24. Then, a metallic material fills the via of the second dielectric layer 26 to form at least one bonding portion 14a. In some embodiments, the bonding portion 14a extends through the second dielectric layer 26 and contacts the first circuit layer 24. Furthermore, the bonding portion 14a gradually narrows downwards; that is, the size of the top portion of the bonding portion 14a is larger than the size of the bottom portion of the bonding portion 14a. In some embodiments, the bonding portion 14a is a monolithic structure or a one-piece structure with isomorphic material composition. The bonding portion 14a may be a bonding pad, such as a finger pad for wire bonding.

[0101] Next, the dielectric layers (including the first dielectric layer 20 and the second dielectric layer 26) are cured. Then, a single-step process is performed to form the first upper conductive structure 2a. Next, the electrical properties of the first upper conductive structure 2a are tested (e.g., open circuit / short circuit).

[0102] refer to Figure 23 The first upper conductive structure 2a is attached to the lower conductive structure 3 via an adhesive layer 12. The adhesive layer 12 does not completely cover the bonding portion (e.g., pad portion 384) of the lower conductive structure 3. The bonding portion 14a of the first upper conductive structure 2a faces upward. In some embodiments, a known good upper conductive structure 2 is attached to a known good lower conductive structure 3. The adhesive layer 12 is then cured to form an intermediate layer 12. In some embodiments, the first upper conductive structure 2a can be pressed onto the lower conductive structure 3. Therefore, the thickness of the intermediate layer 12 is determined by the gap between the first upper conductive structure 2a and the lower conductive structure 3.

[0103] refer to Figure 24 Multiple first bonding lines 15a are formed to connect the bonding portion 14a of the first upper conductive structure 2a and the bonding portion (e.g., pad portion 384) of the second upper circuit layer 38 of the lower conductive structure 3. Therefore, the first upper conductive structure 2a is electrically connected to the lower conductive structure 3 via the first bonding lines 15a. Next, the lower conductive structure 3 is individually divided to form... Figure 1 Wiring structure 1 is shown in the figure.

[0104] Figures 25 to 26 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing... Figure 4 and Figure 5 The wiring structure 1c shown in the diagram. The initial stage of the described process and Figures 12 to 23 The stages described herein are the same or similar. Figure 25 Depicted in Figure 23 The stage following the stage described in the text.

[0105] refer to Figure 25 Multiple electronic devices (e.g., first memory die 40a, second memory die 40b, third memory die 40c, fourth memory die 40d, and fifth memory die 40e) are stacked vertically on top of each other and stacked and adhered to the first upper conductive structure 2a. The positions of the electronic devices (e.g., first memory die 40a, second memory die 40b, third memory die 40c, fourth memory die 40d, and fifth memory die 40e) may be shifted or laterally displaced from each other to facilitate wire bonding processes. For example, the second memory die 40b may be shifted from the first memory die 40a to expose the bonding portion of the first memory die 40a. The sizes of the electronic devices (e.g., first memory die 40a, second memory die 40b, third memory die 40c, fourth memory die 40d, and fifth memory die 40e) may be the same or different from each other.

[0106] refer to Figure 26 Multiple first bonding lines 15a are formed to connect the bonding portion 14a of the first upper conductive structure 2a and the bonding portion (e.g., pad portion 384) of the second upper circuit layer 38 of the lower conductive structure 3. Therefore, the first upper conductive structure 2a is electrically connected to the lower conductive structure 3 via the first bonding lines 15a. Additionally, multiple third bonding lines 15c are formed to connect the bonding portions of electronic devices (e.g., the first memory die 40a, the second memory die 40b, the third memory die 40c, the fourth memory die 40d, and the fifth memory die 40e) to the bonding portion 14a of the first upper conductive structure 2a. Figure 5As shown, the first upper conductive structure 2a may include a plurality of bonding regions 27 (e.g., a first bonding region 271, a second bonding region 272, a third bonding region 273, a fourth bonding region 274, a fifth bonding region 275, and a sixth bonding region 276). Each of the plurality of bonding regions 27 (e.g., the first bonding region 271, the second bonding region 272, the third bonding region 273, the fourth bonding region 274, the fifth bonding region 275, and the sixth bonding region 276) includes a plurality of bonding portions 14a. In some embodiments, a first memory die 40a is electrically connected to the bonding portion 14a in the first bonding region 271 via a third bonding line 15c. A second memory die 40b is electrically connected to the bonding portion 14a in the second bonding region 272 via a third bonding line 15c. A third memory die 40c is electrically connected to the bonding portion 14a in the third bonding region 273 via a third bonding line 15c. A fourth memory die 40d is electrically connected to the bonding portion 14a in the fourth bonding region 274 via a third bonding line 15c. The fifth memory die 40e is electrically connected to the bonding portion 14a in the fifth bonding region 275 via the third bonding line 15c. Additionally, the bonding portion 14a in the sixth bonding region 276 is electrically connected to the pad portion 384 of the lower conductive structure 3 via the first bonding line 15a. Next, the lower conductive structure 3 is individually divided to form as shown... Figure 4 and Figure 5 The wiring structure 1c shown is illustrated.

[0107] Figures 27 to 33 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing... Figure 2 The wiring structure 1a shown in the diagram. The initial stage of the described process and Figure 12 The stages described herein are the same or similar. Figure 27 Depicted in Figure 12 The stage following the stage described in the text.

[0108] refer to Figure 27 A carrier 65 is provided. The carrier 65 may be a glass carrier and may be of wafer type, panel type, or strip type. Next, a release layer 66 is coated on the bottom surface of the carrier 65. Next, a conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 using PVD technology or other suitable techniques. Next, a second circuit layer 24' is formed on the conductive layer 67. The second circuit layer 24' includes a pad portion 244'.

[0109] refer to Figure 28 A second dielectric layer 26 is formed on the conductive layer 67 by coating technology or other suitable technology to cover the second circuit layer 24'.

[0110] refer to Figure 29At least one via 264 and at least one via 265 are formed by exposure and development techniques or other suitable techniques to extend through the second dielectric layer 26, thereby exposing a portion of the second circuit layer 24' and a portion of the pad portion 244', respectively.

[0111] refer to Figure 30 Seed layers 68 are formed on the bottom surface 262 of the second dielectric layer 26 and in the vias 264 and 265 using PVD technology or other suitable techniques.

[0112] refer to Figure 31 A photoresist layer 69 is formed on the seed layer 68. Then, the photoresist layer 69 is patterned to expose portions of the seed layer 68 using exposure and development techniques or other suitable techniques. The photoresist layer 69 defines a plurality of openings 691. The openings 691 of the photoresist layer 69 correspond to and are aligned with the vias 264 and 265 of the second dielectric layer 26.

[0113] refer to Figure 32 Conductive material 70 (e.g., metallic material) is placed in the opening 691 of the photoresist layer 69 and on the seed layer 68 by means of plating technology or other suitable technology.

[0114] refer to Figure 33 The photoresist layer 69 is removed by stripping techniques or other suitable techniques.

[0115] refer to Figure 34 The portion of the seed layer 68 not covered by the conductive material 70 is removed by etching or other suitable techniques. Simultaneously, a first circuit layer 24, at least one internal via 25, and at least one via portion 25a are formed. The internal via 25 is disposed in a via 264 of the second dielectric layer 26. In some embodiments, the internal via 25 may include a seed layer 251 and conductive material 252 disposed on the seed layer 251. The internal via 25 gradually narrows upwards. Additionally, the top portion of the via portion 25a contacts and / or electrically connects to the pad portion 244' of the second circuit layer 24'. In some embodiments, the via portion 25a may include a seed layer 251 and conductive material 252 (e.g., a metallic material) disposed on the seed layer 251. In some embodiments, the via portion 25a and the first circuit layer 24 may be integrally formed as a single piece or monolithic structure. The via portion 25a gradually narrows upwards. Therefore, the narrowing direction of the internal via 25 is the same as the narrowing direction of the via portion 25a. The pad portion 244' and the guide hole portion 25a are configured together to form the joint portion 14.

[0116] refer to Figure 35A first dielectric layer 20 is formed or disposed on the second dielectric layer 26 to cover the first circuit layer 24. Next, the dielectric layers (including the first dielectric layer 20 and the second dielectric layer 26) are cured. Next, the carrier 65, release layer 66, and conductive layer 67 are removed. Next, a single-step process is performed to form the first upper conductive structure 2. Next, the electrical properties of the first upper conductive structure 2 are tested (e.g., open circuit / short circuit).

[0117] Next, the first upper conductive structure 2 is attached to the lower conductive structure 3 via the adhesive layer 12. The adhesive layer 12 does not completely cover the bonding portion (e.g., pad portion 384) of the lower conductive structure 3, with the bonding portion 14a of the first upper conductive structure 2 facing upwards. In some embodiments, a known good upper conductive structure 2 is attached to a known good lower conductive structure 3. The adhesive layer 12 is then cured to form an intermediate layer 12.

[0118] Next, a plurality of first bonding lines 15a are formed to connect the pad portion 244' of the bonding portion 14 of the first upper conductive structure 2 and the bonding portion (e.g., pad portion 384) of the second upper circuit layer 38 of the lower conductive structure 3. In some embodiments, the pad portion 244' of the second circuit layer 24' of the first upper conductive structure 2 may be omitted, and the top portion of the via portion 25a may be exposed to form the top surface 261 of the second dielectric layer 26. Therefore, the via portion 25a is the bonding portion 14, and the ends of the first bonding lines 15a may directly contact and / or electrically connect to the top portion of the via portion 25a. Next, the lower conductive structure 3 is formed as follows: Figure 2 The wiring structure 1a is shown.

[0119] Figure 36 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing... Figure 3 The wiring structure 1b shown is illustrated. The initial stage of the described process is related to... Figures 12 to 23 The stages described herein are the same or similar. Figure 36 Depicted in Figure 23 The stage following the stage described in the text.

[0120] refer to Figure 36A second upper conductive structure 2b is stacked on and attached to a first upper conductive structure 2a via an interlayer 13, and a third upper conductive structure 2c is stacked on and attached to a second upper conductive structure 2b via an interlayer 13. The structures of the second upper conductive structure 2b and the third upper conductive structure 2c may be substantially the same as the structure of the first upper conductive structure 2a. The sizes of the upper conductive structures (e.g., the first upper conductive structure 2a, the second upper conductive structure 2b, and the third upper conductive structure 2c) are different from each other. For example, from a top view, the size of the second upper conductive structure 2b is smaller than the size of the first upper conductive structure 2a, and the size of the third upper conductive structure 2c is smaller than the size of the second upper conductive structure 2b.

[0121] Next, a plurality of second bonding lines 15b are formed to connect the bonding portions of two adjacent upper conductive structures. For example, some of the second bonding lines 15b connect the bonding portion 14b of the second upper conductive structure 2b and the bonding portion 14a of the first upper conductive structure 2a. Some of the second bonding lines 15b connect the bonding portion 14c of the third upper conductive structure 2c and the bonding portion 14b of the second upper conductive structure 2b.

[0122] Next, the single-part lower conductive structure 3 is formed as follows: Figure 3 The wiring structure 1b shown is illustrated.

[0123] Figure 37 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing... Figure 6 and Figure 7 The wiring structure 1d shown is illustrated. The initial stage of the described process is related to... Figures 12 to 23 and Figure 36 The stages described herein are the same or similar. Figure 37 Depicted in Figure 36 The stage following the stage described in the text.

[0124] refer to Figure 37Multiple electronic devices (e.g., first memory die 40a, second memory die 40b, third memory die 40c, fourth memory die 40d, and fifth memory die 40e) are stacked vertically on top of each other and stacked and adhered to a third upper conductive structure 2c. The positions of the electronic devices (e.g., first memory die 40a, second memory die 40b, third memory die 40c, fourth memory die 40d, and fifth memory die 40e) may be shifted or laterally displaced from each other to facilitate wire bonding processes. For example, the second memory die 40b may be shifted from the first memory die 40a to expose the bonding portion of the first memory die 40a. The sizes of the electronic devices (e.g., first memory die 40a, second memory die 40b, third memory die 40c, fourth memory die 40d, and fifth memory die 40e) may be the same or different from each other.

[0125] Next, a plurality of first bonding lines 15a are formed to connect the bonding portion 14a of the first upper conductive structure 2a and the bonding portion (e.g., pad portion 384) of the second upper circuit layer 38 of the lower conductive structure 3. A plurality of second bonding lines 15b are formed to connect the bonding portions of two adjacent upper conductive structures. For example, some of the second bonding lines 15b connect the bonding portion 14b of the second upper conductive structure 2b and the bonding portion 14a of the first upper conductive structure 2a. Some of the second bonding lines 15b connect the bonding portion 14c of the third upper conductive structure 2c and the bonding portion 14b of the second upper conductive structure 2b. Additionally, multiple third bonding lines 15c are formed to connect the bonding portions of electronic devices (e.g., the first memory die 40a, the second memory die 40b, the third memory die 40c, the fourth memory die 40d, and the fifth memory die 40e) to the bonding portions 14a, 14b, and 14c of upper conductive structures (e.g., the first upper conductive structure 2a, the second upper conductive structure 2b, and the third upper conductive structure 2c).

[0126] In some embodiments, the first memory die 40a and the second memory die 40b are electrically connected to the bonding portion 14c of the third upper conductive structure 2c via the third bonding line 15c. The third memory die 40c and the fourth memory die 40d are electrically connected to the bonding portion 14b of the second upper conductive structure 2b via the third bonding line 15c. The fifth memory die 40e is electrically connected to the bonding portion 14a of the first upper conductive structure 2a via the third bonding line 15c. Next, the lower conductive structure 3 is formed as shown... Figure 6 and Figure 7 The wiring structure shown is 1d.

[0127] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” “below,” etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not affected by such arrangements.

[0128] As used herein, the terms “approximately,” “generally,” “about,” and “approximately” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to examples in which the event or situation clearly occurred and examples in which the event or situation is very close to occurring. For example, when used in conjunction with numerical values, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the first value is within a range of less than or equal to ±10% of the second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value can be considered "substantially" the same as or equal to the second value.

[0129] If the displacement between two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar.

[0130] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple indicators.

[0131] As used herein, the terms "conductive" and "electrically conductive" refer to the ability to conduct electric current. Conductive materials are generally those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0132] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0133] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments of this disclosure may exist that are not specifically described. The specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A wiring structure comprising: A low-density stacked structure comprising at least one dielectric layer, at least one low-density circuit layer in contact with the dielectric layer, and at least one bonding portion electrically connected to the low-density circuit layer; At least one high-density stacked structure disposed on the low-density stacked structure, wherein the high-density stacked structure includes at least one dielectric layer, at least one high-density circuit layer in contact with the dielectric layer of the high-density stacked structure, and at least one bonding portion electrically connected to the high-density circuit layer. An intermediate layer is disposed between the low-density stacked structure and the high-density stacked structure and bonds the low-density stacked structure and the high-density stacked structure together; and Multiple bonding lines connect at least one bonding portion of the at least one high-density stacked structure to at least one bonding portion of the at least one low-density stacked structure.

2. The wiring structure according to claim 1, wherein the high-density stacking structure comprises a plurality of dielectric layers, a plurality of high-density circuit layers, the at least one bonding portion and at least one internal via, the internal via being disposed between two adjacent high-density circuit layers for electrically connecting the two adjacent high-density circuit layers, the narrowing direction of the internal via being different from the narrowing direction of the bonding portion.

3. The wiring structure according to claim 1, wherein the high-density stacking structure comprises a plurality of bonding regions, and each of the bonding regions comprises a plurality of bonding portions.

4. The wiring structure according to claim 1, wherein the size of the at least one high-density stacking structure is smaller than the size of the low-density stacking structure.

5. A wiring structure comprising: A low-density stacked structure comprising at least one dielectric layer and at least one low-density circuit layer in contact with said dielectric layer; At least one high-density stacked structure disposed on the low-density stacked structure, wherein the high-density stacked structure includes at least one dielectric layer, at least one high-density circuit layer in contact with the dielectric layer of the high-density stacked structure, and at least one bonding portion electrically connected to the high-density circuit layer. An intermediate layer is disposed between the low-density stacked structure and the high-density stacked structure and bonds the low-density stacked structure and the high-density stacked structure together; and Multiple through-holes extend through at least a portion of the at least one high-density stacked structure, the intermediate layer, and at least a portion of the low-density stacked structure, and electrically connect the at least one high-density stacked structure and the low-density stacked structure.

6. The wiring structure according to claim 5, wherein the line spacing of the low-density circuit layer in the low-density stacked structure is greater than the line spacing of the high-density circuit layer in the at least one high-density stacked structure.

7. The wiring structure of claim 5, further comprising a plurality of electronic devices and a plurality of bonding wires, wherein the electronic devices are stacked on the at least one high-density stacked structure, and the bonding wires connect the electronic devices to the at least one bonding portion of the at least one high-density stacked structure.

8. The wiring structure according to claim 7, wherein the through-hole is disposed under the electronic device.

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