Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same; wherein the semiconductor device comprises: a semiconductor device layer, which comprises one or more semiconductor devices; a first electrode interconnection layer, which is arranged on the first side of the semiconductor device layer; one or more first metal pillars, which are arranged on the first side of the semiconductor device layer and are electrically connected to the first electrode interconnection layer; a first insulating material, which is arranged around the one or more first metal pillars, wherein the first insulating material is an injection moldable material; and a second electrode interconnection layer, which is arranged on the second side opposite to the first side of the semiconductor device layer. In the technical solution of the present invention, a good supporting strength is achieved without a temporary substrate and the related processes of the semiconductor process are completed, which is convenient, fast and low in cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Group III nitride semiconductors are important semiconductor materials, mainly including AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. Due to the advantages of direct band gap, wide bandgap, high breakdown electric field strength, etc., Group III nitride semiconductors represented by GaN have broad application prospects in the fields of light-emitting devices, power electronics, and radio frequency devices.

[0003] Unlike traditional non-polar semiconductor materials such as Si, III-nitride semiconductors have polarity, that is, they are polar semiconductor materials. Polar semiconductors have many unique properties. What is particularly important is that there are fixed polarization charges on the surface of polar semiconductors or at the interface between two different polar semiconductors. The presence of these fixed polarization charges can attract mobile electron or hole carriers to form two-dimensional electron gas 2DEG or two-dimensional hole gas 2DHG. The generation of these two-dimensional electron gas 2DEG or two-dimensional hole gas 2DHG does not require an additional electric field, nor does it rely on the doping effect in the semiconductor, and is spontaneously generated. The two-dimensional electron gas or two-dimensional hole gas at the interface of the polar semiconductor can have a high surface charge density. At the same time, since doping is not required, the two-dimensional electron gas or two-dimensional hole gas is greatly reduced in ion scattering and other effects, so it has a higher mobility. The high surface charge density and mobility make the two-dimensional electron or hole gas spontaneously generated at this interface have good conduction ability and high response speed.

[0004] Combined with the inherent advantages of nitride semiconductors such as high breakdown electric field strength, this two-dimensional electron gas or two-dimensional hole gas can be used to make high-mobility transistors, which perform significantly better than traditional Si or GaAs devices in high-energy, high-voltage or high-frequency applications. However, the existing structure has many defects, which seriously restricts its application scope. Summary of the invention

[0005] In response to the technical problems existing in the prior art, the present invention proposes a semiconductor device, comprising: a semiconductor device layer, which includes one or more semiconductor devices; a first electrode interconnection layer, which is arranged on a first side of the semiconductor device layer; one or more first metal pillars, which are arranged on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material, which is arranged around the one or more first metal pillars, wherein the first insulating material is an injection moldable material; and a second electrode interconnection layer, which is arranged on a second side opposite to the first side of the semiconductor device layer.

[0006] In the semiconductor device as described above, one or more semiconductor devices in the semiconductor device layer include: one or more of a Schottky diode, a HEMT, and a HHMT.

[0007] The semiconductor device as described above, wherein one or more semiconductor devices in the semiconductor device layer have a vertical channel.

[0008] The semiconductor device as described above, wherein the second electrode interconnection layer is electrically connected to the second electrode on the second side of the semiconductor device layer.

[0009] In the semiconductor device as described above, the first metal pillar is a copper pillar.

[0010] In the semiconductor device as described above, the height of the first metal pillar is greater than 60 micrometers, greater than 80 micrometers, or greater than 100 micrometers.

[0011] In the semiconductor device as described above, the first insulating material is distributed around the one or more metal pillars by injection molding.

[0012] In the semiconductor device as described above, the first insulating material is an organic material.

[0013] In the semiconductor device as described above, the first insulating material is one or more of epoxy resin EP, polystyrene PS, ABS, polycarbonate PC, high-density polyethylene HDPE, polypropylene PP, and polyvinyl chloride PVC.

[0014] The semiconductor device as described above further includes one or more second metal pillars, which are arranged on the second side of the semiconductor device layer and electrically connected to the second electrode interconnection layer; and a second insulating material, which is arranged around the one or more second metal pillars, wherein the second insulating material is an injection moldable material.

[0015] The semiconductor device as described above further includes: a third electrode interconnection layer, which is arranged on the first side of the semiconductor device layer; and one or more third metal pillars, which are arranged on the first side of the semiconductor device layer and electrically connected to the third electrode interconnection layer; wherein the first insulating material is configured to also be distributed around the one or more third metal pillars.

[0016] According to another aspect of the present invention, a semiconductor device is provided, which is obtained by cutting from any of the semiconductor devices described above.

[0017] According to another aspect of the present invention, a semiconductor device is provided, which is obtained by cutting and packaging any of the semiconductor devices described above.

[0018] According to another aspect of the present invention, a method for manufacturing a semiconductor device is proposed, comprising: forming one or more first metal pillars on a first electrode interconnection layer on a first side of a semiconductor device layer; injecting a first insulating material so that the first insulating material is distributed around the one or more first metal pillars; removing the substrate; and forming a second electrode interconnection layer on a second side opposite to the first side of the semiconductor device layer; wherein the height of the first metal pillar is greater than 60 microns, greater than 80 microns, or greater than 100 microns.

[0019] The method as described above further comprises: after removing the substrate, forming a second electrode on the second side opposite to the first side of the semiconductor device layer.

[0020] The method as described above further comprises: removing a portion of the first insulating material to expose the one or more first metal pillars.

[0021] The method as described above further includes: forming a third electrode interconnection layer on the first side of the semiconductor device layer, and forming one or more third metal pillars on the third electrode interconnection layer on the first side of the semiconductor device layer; wherein the step of injecting the first insulating material further includes: distributing the first insulating material around the one or more third metal pillars.

[0022] The method as described above further comprises: forming one or more second metal pillars on the second electrode interconnection layer on the second side of the semiconductor device layer; and injecting a second insulating material so that the insulating material is distributed around the one or more second metal pillars.

[0023] According to another aspect of the present invention, a method for manufacturing a semiconductor device is proposed, comprising: forming a semiconductor device layer on a substrate, which includes one or more semiconductor devices; forming a first electrode interconnection layer on a first side of the semiconductor device layer; forming one or more first metal pillars on the first electrode interconnection layer on the first side of the semiconductor device layer; injecting a first insulating material so that the first insulating material is distributed around the one or more first metal pillars; removing the substrate; and forming a second electrode interconnection layer on a second side opposite to the first side of the semiconductor device layer; wherein the height of the first metal pillar is greater than 60 microns, greater than 80 microns, or greater than 100 microns.

[0024] The method as described above further includes: forming one or more third metal pillars on the third electrode interconnection layer on the first side of the semiconductor device layer; wherein the step of injecting the first insulating material further includes: distributing the first insulating material around the one or more third metal pillars.

[0025] The method as described above further comprises: forming one or more second metal pillars on the second electrode interconnection layer on the second side of the semiconductor device layer; and injecting a second insulating material so that the insulating material is distributed around the one or more second metal pillars.

[0026] The method as described above further comprises: cutting the semiconductor device layer to separate the one or more semiconductor devices.

[0027] The method as described above further comprises: packaging the separated one or more semiconductor devices.

[0028] In the technical solution of the present invention, a good supporting strength is achieved and relevant processes of semiconductor manufacturing can be completed without the need for a temporary substrate, which is convenient, fast and low-cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The preferred embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0030] Figure 1 is a schematic structural diagram of a HEMT according to an embodiment of the present invention;

[0031] Figure 2A is a schematic diagram of a top view of a single-channel HHMT according to an embodiment of the present invention;

[0032] Figure 2B is a schematic diagram of a cross-sectional structure of a single-channel HHMT according to an embodiment of the present invention;

[0033] Figure 3 is a schematic structural diagram of a HEMT according to another embodiment of the present invention;

[0034] Figure 4 is a schematic structural diagram of a HEMT according to another embodiment of the present invention;

[0035] Figure 5AA-Figure 5VB A schematic diagram of a process for preparing a dual-channel HHMT according to an embodiment of the present invention; and

[0036] Figure 6A-6G is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0039] The present invention provides a semiconductor device, wherein two electrodes are located on both sides of the semiconductor device. In some embodiments of the present invention, such a structure can not only improve the withstand voltage of the semiconductor device, but also facilitate the circuit interconnection of the semiconductor device. In some embodiments of the present invention, the substrate can be partially or completely removed, thereby reducing or avoiding the influence of the substrate (especially a foreign substrate, such as a silicon substrate) on the device performance.

[0040] The semiconductor device proposed in the present invention may be a Schottky diode, HEMT, HHMT or other semiconductor devices. HEMT is used as an example for description below.

[0041] Figure 1 1 is a schematic diagram of the structure of a HEMT according to an embodiment of the present invention. In this embodiment, the HEMT 100 is a dual-channel device, which includes two vertical two-dimensional electron gases 2DEG as conductive channels. Figure 1 According to the embodiment shown, those skilled in the art are fully capable of obtaining a single-channel device including only one vertical 2DEG, which is also within the protection scope of the present invention.

[0042] As shown in the figure, HEMT100 includes a substrate 101 and a first nucleation layer 102A and a second nucleation layer 102B. The first nucleation layer 102A and the second nucleation layer 102B are formed on the vertical interface relative to the substrate 101. In some embodiments, the nucleation layers 102A and 102B may be AlN. In this article, the nucleation layer may further include a buffer layer (not shown). The buffer layer may have a single layer or multilayer structure, including one or more of AlN, GaN, AlGaN, InGaN, AlInN and AlGaInN.

[0043] The first channel layer 103A and the second channel layer 103B are formed by epitaxial growth from the nucleation layers 102A and 102B, respectively. Further, the first barrier layer 104A and the second barrier layer 104B are formed by epitaxial growth from the first channel layer 103A and the second channel layer 103B, respectively. The first barrier layer 104A is formed on the right side of the first channel layer 103A, the two are arranged horizontally and a first heterojunction is formed therebetween, and a vertical 2DEG is formed in the first heterojunction. The second barrier layer 104B is formed on the left side of the second channel layer 103B, the two are arranged horizontally and a second heterojunction is formed therebetween, and a vertical 2DEG is formed in the second heterojunction. Under normal growth conditions, the surface of the channel layer and barrier layer grown on the Si(111), Al2O3(0001) and SiC(0001) surfaces is the (0001) plane, that is, the direction from the Si substrate to the channel layer and barrier layer is <0001> Crystal direction. Under such a crystal direction, there is 2DEG in the channel layer near the interface between the channel layer and the barrier layer. As those skilled in the art understand, if the first barrier layer 104A is formed on the left side of the first channel layer 103A, or the second barrier layer 104B is formed on the right side of the second channel layer 103B, then according to the crystal direction, there is a two-dimensional hole gas 2DHG in the channel layer near the interface between the channel layer and the barrier layer. Thus, a dual-channel HHMT can be obtained.

[0044] like Figure 1 As shown, the first channel layer 103A and the second channel layer 103B are partially formed on the sides of the nucleation layers 102A and 102B, extending to occupy the space between the nucleation layers 102A and 102B. In some embodiments, the other portions between the nucleation layers 102A and 102B may be filled with an insulating material 112, such as SiO2.

[0045] like Figure 1 As shown, the portions of the substrate 101 extending horizontally below and above the nucleation layers 102A and 102B may include separation layers 111A and 111B, respectively, covering the horizontal surface of the substrate 101, separating the substrate 101 from other parts of the device, thereby further improving the withstand voltage capability. The separation layers 111A and 111B are electrically insulating and include one or more of silicon oxide, silicon nitride, and the like.

[0046] In some embodiments, a shielding layer 113 may be included on the spacer layer 111B extending horizontally above the nucleation layer 102A. An insulating layer 114 may be included on the shielding layer 113. The shielding layer 113 and the insulating layer 114 can provide support and protection for the device. The shielding layer 113 and the insulating layer 114 are electrically insulating and include one or more of silicon oxide, silicon nitride, etc.

[0047] In some embodiments, the first and second channel layers 103A and 103B may be defined by grooves. For example, after forming the nucleation layers 102A and 102B, the shielding layer 113 may be deposited. The height of the shielding layer 113 may be determined according to the desired height of the heterojunction. A first groove and a second groove may be formed on the shielding layer 113. The first groove extends downward, exposing the nucleation layer 102A. The first groove extends downward, exposing the nucleation layer 102B. Further, the first and second channel layers 103A and 103B may be epitaxially grown from the nucleation layers 102A and 102B, and the first groove and the second groove may be filled. Thus, the shapes of the first and second channel layers 103A and 103B may be defined by the first and second grooves.

[0048] Further, the first and second barrier layers 104A and 104B can be defined by grooves. For example, after forming the first and second channel layers 103A and 103B, two other third grooves and a fourth groove are formed on the shielding layer 113 to expose the left and right sides of the first and second channel layers 103A and 103B, respectively; then, the first and second barrier layers 104A and 104B can be epitaxially grown on the side of the channel layer exposed in the grooves, and the grooves can be filled. Thus, the shapes of the first and second barrier layers 104A and 104B can also be defined by the grooves.

[0049] The heterojunction structure defined by the trench involved in the present invention has the following advantages: according to actual needs, a trench structure that can meet the needs can be formed first, and then a device that is difficult to achieve by conventional means can be gradually formed in the trench. For example, it is easy to form a structure with a low aspect ratio by epitaxial growth in the prior art; however, it is usually difficult to form a structure with a high aspect ratio. When its vertical height is high and its width is small, the traditional epitaxial growth method is difficult to achieve. As disclosed in some embodiments of the present invention, such a structure can be easily achieved by the trench structure proposed by the present invention. On the other hand, a 2DEG with a higher height can be formed by trench definition. The HEMT formed in this way has a larger on-current between the source and the drain when the horizontal projection distance between the electrodes remains unchanged, so it is easier to obtain a high-power HEMT.

[0050] In some embodiments, the aspect ratio of the channel layer to the barrier layer of the semiconductor device of the present invention can be 1:2, 1:5, or 1:20. For example, the length of the bottom of the channel layer and the barrier layer is 1 μm (micrometer), and the height of the channel layer 103 and the barrier layer 104 can be 2 μm, 5 μm, 20 μm. In fact, through the definition of the groove, any desired aspect ratio can be achieved with the help of the groove.

[0051] In general applications, the channel layer and the barrier layer are lower than or equal to the height of the grooves they define. In some special applications, the channel layer and the barrier layer can also extend above these grooves. However, due to the loss of the restriction of the grooves, the growth of the channel layer and the barrier layer may be more difficult to control. Therefore, even if the channel layer and the barrier layer are higher than these grooves, the height of the higher will be limited.

[0052] In this embodiment, the HEMT 100 includes a first electrode 107 and a second electrode 108. The first electrode 107 is located on the upper side of the first heterojunction and is in electrical contact with the 2DEG in the first heterojunction. The upper side here refers to the portion above the centerline of the first heterojunction. Based on the height of the first heterojunction, the horizontal line position at 1 / 2 of its height is the centerline position of the first heterojunction. Figure 1 The area above the center line is the upper side of the first heterojunction. The first electrode can be located at any position on the upper side that can electrically contact the vertical 2DEG of the first heterojunction. For example, the first electrode 107 can be as follows Figure 1 As shown, the first electrode 107 can be in electrical contact with the 2DEG perpendicular to the first heterojunction from the upper surface of the first heterojunction; or, the first electrode 107 can be in electrical contact with the 2DEG perpendicular to the first heterojunction from the first barrier layer side; or, the first electrode 107 can be in electrical contact with the 2DEG perpendicular to the first heterojunction from the first channel layer side. The present invention is not limited to this.

[0053] Similarly, the second electrode 108 is located at the lower side of the first heterojunction and is in electrical contact with the 2DEG in the first heterojunction. The lower side here refers to the part below the centerline of the first heterojunction. Figure 1 As shown, the second electrode 108 is in electrical contact with the 2DEG perpendicular to the first heterojunction from one side of the first barrier layer. Preferably, the first electrode 107 and the second electrode 108 are as far apart as possible to maximize the length of the vertical conductive channel and improve the withstand voltage performance of the device.

[0054] refer to Figure 1 Since the first electrode 107 and the second electrode 108 are respectively located on the upper side and the lower side of the center line of the first heterojunction, the projection of the first electrode and its connecting conductor on the vertical channel surface has no overlapping area with the projection of the second electrode and its connecting conductor on the vertical channel surface. Furthermore, on a third plane perpendicular to the vertical channel surface and the horizontal plane, the projection of the first electrode and its connecting conductor on the vertical channel surface has no overlapping area with the projection of the second electrode and its connecting conductor on the vertical channel surface.

[0055] like Figure 1As shown, for the dual-channel HEMT100, the first electrode 107 and the second electrode 108 are also electrically contacted with the vertical 2DEG of the second heterojunction as another channel, thereby forming a dual-channel semiconductor device. The increased conductive channel can increase the on-current, thereby having higher power; and the dual conductive channel has better withstand voltage and heat resistance than the single conductive channel. Moreover, electrodes with the same properties of the dual conductive channel structure can be shared. Those skilled in the art should note that although Figure 1 The first electrode 107 includes two parts corresponding to the first heterojunction and the second heterojunction, but the two parts are electrically connected to the same conductor interconnect layer, and therefore, can be regarded as one electrode.

[0056] In some embodiments, one of the first electrode 107 and the second electrode 108 can be in ohmic contact with the first and second heterojunctions; the other can be in Schottky contact with the first and second heterojunctions, and the characteristics of the Schottky contact are used to form a Schottky diode, which is also a semiconductor device protected by the present invention.

[0057] In some embodiments, Figure 1 Above the first heterojunction shown, a first conductor interconnection layer 131 is included, which is electrically connected to the first electrode 107. Not surprisingly, the first conductor interconnection layer 131 is also located on the upper side of the first heterojunction. The manufacture and interconnection of the first conductor interconnection layer 131 are well known to those skilled in the art and will not be described in detail here.

[0058] In some embodiments, Figure 1 Below the first heterojunction shown, a second conductor interconnection layer 132 is included, which is electrically connected to the second electrode 108. Not surprisingly, the second conductor interconnection layer 132 is also located on the lower side of the second heterojunction. As is known to those skilled in the art, the second conductor interconnection layer 132 can be formed in a variety of ways and electrically connected to the second electrode 108. For example, Figure 1 The semiconductor device shown is flipped, and then a through hole is formed on the substrate 101, and the flipped second electrode 108 is exposed; next, a second conductor interconnection layer 132 can be formed on the substrate 101 by depositing metal, etc., and the through hole is filled, and the second conductor interconnection layer 132 is electrically connected to the second electrode 108, so as to obtain Figure 1 The structure shown.

[0059] In this embodiment, the HEMT 100 further includes a third electrode 109. The third electrode 109 is provided between the first electrode 107 and the second electrode 108 as a gate electrode, and can control the current intensity between the first electrode 107 and the second electrode 108 to form a HEMT structure. Specifically, the voltage of the third electrode 109 can control the depth of the heterojunction potential well formed by the channel layer-barrier layer, control the surface charge density of the 2DEG in the potential well, and further control the working current between the first electrode 107 and the second electrode 108. In some embodiments, the horizontal extension length of the third electrode 109 is not less than the length of the 2DEG 105A, so as to achieve control of the current path between the first electrode 107 and the second electrode 108.

[0060] In some embodiments, the second electrode 108 is in ohmic contact with the first and second channel layers 103A and 103B and the first and second barrier layers 104A and 104B, and is preferably connected to a high voltage as a drain. The first electrode 107 is also in ohmic contact, and is preferably used as a source, as far away from the drain of the second electrode as possible. Furthermore, the midline position of the third electrode 109 is also located on the upper side of the first heterojunction and as close to the first electrode 107 as possible, so as to increase the distance between the drain and the gate, and effectively improve the withstand voltage performance of the HEMT 100.

[0061] In some embodiments, Figure 1 Above the first heterojunction shown, a third conductor interconnection layer 133 is included, which is electrically connected to the third electrode 109. Not surprisingly, the third conductor interconnection layer 133 is also located on the upper side of the first heterojunction. The manufacture and interconnection of the third conductor interconnection layer 133 are well known to those skilled in the art and will not be described in detail here. Figure 1 Since the third electrode is also located on the upper side of the first heterojunction, the projection of the third electrode and its connecting conductor on the vertical channel surface has no overlapping area with the projection of the second electrode and its connecting metal on the vertical channel surface. On the third plane surface perpendicular to the vertical channel surface and the horizontal plane, the projection of the third electrode and its connecting conductor on the third plane has no overlapping area with the projection of the second electrode and its connecting metal on the third plane.

[0062] It is worth noting that the interconnection structure of the third electrode 109 passes through the interconnection structure of the first electrode 107, and is entirely located within the area defined by the first electrode 107. This eliminates the need to occupy additional chip area, which is beneficial to improving the integration of the device.

[0063] Figure 2A and Figure 2B FIG. 1 is a schematic diagram of the structure of a HEMT according to another embodiment of the present invention. As shown in the figure, HEMT200 is also a dual-channel device. Figure 1The structure of HEMT100 shown is similar, including a substrate 201, first and second nucleation layers 202A and 202B, first and second channel layers 203A and 203B, and first and second barrier layers 204A and 204B; wherein a first heterojunction and a second heterojunction are formed between the first and second channel layers 203A and 203B and the first and second barrier layers 204A and 204B, respectively. Further, the portions of the substrate 201 extending horizontally above and below the first and second nucleation layers 202A and 202B include separation layers 211A and 211B, respectively, to separate the substrate 201 from other parts of the device. HEMT200 also includes an insulating material 212 between the first and second barrier layers 204A and 204B, a shielding layer 213 above the separation layer 211B, and a protective layer 214 above the shielding layer 213. HEMT200 also includes a first electrode 207, a second electrode 208, and a third electrode 209. Figure 1 Parts with similar structures in the illustrated embodiment have similar functions and will not be described in detail here.

[0064] and Figure 1 The difference of the illustrated embodiment is that the first and second channel layers 203A and 203B and the first and second barrier layers 204A and 204B are located above the first and second nucleation layers 202A and 202B, so that the first heterojunction and the second heterojunction are further away from the substrate 201. This can further improve the performance of the HEMT 200. Figure 2A and Figure 2B The second conductor interconnection layer 232 is shown in the figure, but the first and third conductor interconnection layers are not shown. The second conductor interconnection layer 232 can be manufactured and interconnected with the second electrode 208 by the same method as in the embodiment of the present invention. Figure 1 Embodiment in a similar manner. Figure 2A and Figure 2B The difference is that Figure 2B In the embodiment, the second electrode is located below the first and second nucleation layers 202A and 202B, and is electrically contacted with the first and second heterojunctions through the first and second nucleation layers 202A and 202B, respectively. Preferably, the first and second nucleation layers 202A and 202B are doped to have improved conductivity. In some embodiments, the first and second nucleation layers 202A and 202B are doped after being formed on the vertical side of the substrate 201, and then the first and second channel layers 203A and 203B are formed. In some embodiments, the first and second nucleation layers 202A and 202B are doped after being turned over and exposed again. In this way, the influence of doping on the lattice of the nucleation layer can be avoided, which is beneficial to the subsequent epitaxial growth. In some embodiments, the first and second nucleation layers 202A and 202B can be the same nucleation layer, and there is no insulating material between them.

[0065] It is worth noting that Figure 2A and Figure 2B In the illustrated embodiment, because the first heterojunction and the second heterojunction are both located above the substrate 201, the entire substrate 201 and the first and second nucleation layers 202A and 202B and the insulating material 212 therebetween can be removed without affecting the structure above them, thereby completely avoiding the influence of a foreign substrate, such as a silicon substrate, on device performance.

[0066] Figure 3 is a schematic diagram of the structure of a HEMT according to another embodiment of the present invention. In order to more clearly illustrate the structure of this embodiment, Figure 3 Three dual-channel HEMTs 300A-300C are shown in FIG.

[0067] Taking HEMT300A as an example, its structure is similar to Figure 1 The structure of HEMT100 shown is similar, including a substrate 301, first and second nucleation layers 302A and 302B, first and second channel layers 303A and 303B, and first and second barrier layers 304A and 304B; wherein first heterojunctions and second heterojunctions are formed between the first and second channel layers 303A and 303B and the first and second barrier layers 304A and 304B, respectively. Further, the portions of the substrate 301 extending horizontally above and below the first and second nucleation layers 302A and 302B include separation layers 311A ​​and 311B, respectively, to separate the substrate 301 from other portions of the device. HEMT300 also includes an insulating material 312 between the first and second barrier layers 304A and 304B and a shielding layer 313 above the separation layer 311B. Figure 1 Parts with similar structures in the illustrated embodiment have similar functions and will not be described in detail here. Figure 1 Different from the embodiment of the present invention, the first and second channel layers 303A and 303B are covered with a protection layer 314 to provide further protection.

[0068] HEMT 300 further includes a first electrode 307, a second electrode 308, and a third electrode 309. The first electrode 307 and the third electrode 309 are connected to Figure 1 The second electrode 308 can be manufactured in a different manner. For example, the semiconductor device shown in FIG. 2 can be flipped over, and then a groove is formed on the substrate 301 to expose the flipped first and second heterojunctions; then, the second electrode 308 can be formed on the first and second heterojunctions by depositing metal or the like. After the second electrode is formed, an insulating material 315 is filled in the groove; then, a through hole is formed in the insulating material 315. Next, metal is deposited on the entire device surface to form a second conductor interconnection layer 332, and the through hole is filled to electrically connect the second conductor interconnection layer 332 to the second electrode 308, thereby obtaining Figure 3The structure shown. Figure 3 In the HEMT structure, the substrate 301 only plays a role in supporting the device and is sufficiently separated from the active part of the semiconductor device, thereby further reducing the impact on the device and significantly improving the performance of the device.

[0069] Figure 4 is a schematic diagram of the structure of a HEMT according to another embodiment of the present invention. In order to more clearly illustrate the structure of this embodiment, Figure 4 Three dual-channel HEMTs 400A-400C are shown in FIG.

[0070] Taking HEMT400A as an example, its structure is similar to Figure 1 The structure of HEMT100 shown is similar, including first and second nucleation layers 402A and 402B, first and second channel layers 403A and 403B, and first and second barrier layers 404A and 404B; wherein a first heterojunction and a second heterojunction are formed between the first and second channel layers 403A and 403B and the first and second barrier layers 404A and 404B, respectively. Further, horizontally extending separation layers 411A and 411B are included above and below the first and second nucleation layers 402A and 402B. HEMT400 also includes an insulating material 412 between the first and second barrier layers 404A and 404B and a shielding layer 414 above the separation layer 411B. HEMT400 also includes a first electrode 407, a second electrode 408, and a third electrode 409. The first electrode 407 and the third electrode 409 are connected to Figure 1 The embodiment of is similar to that of Figure 1 Parts with similar structures in the illustrated embodiment have similar functions and will not be described in detail here. Figure 1 Different from the embodiment of the present invention, the first and second channel layers 403A and 403B are covered with a protection layer 414 to provide further protection.

[0071] Figure 4 The embodiments described and Figure 1-Figure 3 The difference of the embodiment is that the substrate is completely removed. Based on the embodiment shown in FIG. 2 , the following description is made. Figure 4 A manufacturing method of an embodiment. For example, Figure 1 The semiconductor device shown is flipped, the substrate 401 is first thinned, and then the entire semiconductor device is placed in an etching liquid to completely remove the substrate 401 and expose the flipped first and second heterojunctions; next, a second electrode 408 can be formed on the first and second heterojunctions by depositing metal, and then a second conductor interconnection layer 432 is further formed, thereby obtaining Figure 4The structure shown in FIG. In the trenches between the HEMTs, an insulating material 415 may be filled. This step may be performed before or after forming the second electrode 408. Those skilled in the art should note that although Figure 4 The figure shows the separation layer 411A and the insulating material 415 filled therein after the substrate is removed. However, since the separation layer 411A is relatively thin, such a schematic diagram cannot represent the actual structure.

[0072] exist Figure 4 In the HEMT structure, the substrate 401 is completely removed, thereby avoiding the influence of the substrate, especially the foreign substrate (such as a silicon substrate) on the device, and greatly improving the performance of the device. Figure 4 The semiconductor device formed after removing the substrate from the structure of FIG. 2 is shown.

[0073] In some embodiments, in the step of removing the substrate as described above, the substrate, the nucleation layer and the insulating material between the nucleation layers can also be completely removed, leaving only the portion above the substrate in the structure shown in FIG. 2; and then forming the second electrode and the second conductor interconnect layer. Figure 1 Starting from the structure of the present invention, a semiconductor device after the substrate is removed can also be obtained. These methods are also within the scope of the present invention.

[0074] The present invention also includes a method for manufacturing a semiconductor device. Figure 4 The manufacturing process of the dual-channel HEMT is taken as an example to illustrate the manufacturing method of the semiconductor device of the present invention. Semiconductor devices with other structures can also be manufactured by similar methods.

[0075] Figure 5AA-Figure 5VB FIG. 1 is a flow chart of a method for manufacturing a high electron mobility transistor (HEMT) according to an embodiment of the present invention; wherein Figure 5AA-Figure 5VA is a top view of each step of a HEMT manufacturing method according to an embodiment of the present invention, Figure 5AB-Figure 5VB 1 is a cross-sectional view of various steps of a HEMT manufacturing method according to an embodiment of the present invention. In this embodiment, a semiconductor device is manufactured on a silicon substrate. As those skilled in the art will appreciate, other substrates such as intrinsic GaN, Al2O3 (sapphire), SiC, etc., can also achieve similar structures.

[0076] As shown in the figure, the preparation method 500 of HEMT includes: in step 5001, as Figure 5AA and 5AB As shown, a Si substrate 501 is provided.

[0077] In step 5002, a plurality of first trenches are formed on a substrate, such as Figure 5BA and 5BB As shown. For example, the substrate 501 is etched by photolithography technology, and a plurality of rectangular first grooves 521 are formed on the substrate 501, exposing the vertical interfaces 541 and 542 of the substrate 501; wherein the vertical interfaces 541 and 542 of the substrate in the first groove 521 are the (111) planes of the Si substrate. There are other methods in the art to obtain the first groove 521, and these methods can also be applied here.

[0078] In some embodiments, the number of first grooves provided on the same substrate depends on the requirements of specific integration, voltage resistance, etc., and only three grooves are used as an example for explanation. The method involved in the present invention can pre-construct the shape and size of the groove according to actual needs. For example, when forming a semiconductor device with a relatively high voltage resistance, the groove depth is also deeper.

[0079] In step 5003, a protective layer 531 is formed on the surface of the substrate and the first groove on the substrate. Figure 5CA and 5CB A SiN protective layer 531 is grown on the substrate 501 using LPCVD or other techniques to cover the surfaces of the substrate 501 and the plurality of trenches 521 .

[0080] In step 5004, the protective layer 531 extending horizontally from the bottom surface of the first trench and the upper surface of the substrate is removed, and the protective layer 531 on the sidewall of the first trench is retained. Figure 5DA and 5DB As shown, by using a vertically oriented etching technique, only the protective layer 531 formed of SiN on the vertical interfaces 541 and 542 is retained, exposing the Si substrate 501 at the bottom of the trench 521. The protective layer 531 covers the substrate vertical interfaces 541 and 542 of the substrate trench 521.

[0081] In step 5005, a first separation layer is formed on the substrate and the first trench, such as Figure 5EA and 5EB As shown. The bottom surface of the first trench 521 is covered with a separation layer 511. In some embodiments, SiO2 can be formed using a deposition technique to form a first separation layer 515 on the substrate 501. Since the vertical interfaces 541 and 542 of the substrate 501 are covered with a protective layer 531, the separation layer 515 is substantially not grown on the vertical interfaces 541 and 542 of the substrate 501.

[0082] In step 5006, the protective layer on the sidewall of the trench is removed. Figure 5FA and 5FBAs shown. The spacer layer 511 above the substrate 501 covers the mask, and the protective layer 531 on the sidewall of the first trench 521 is partially etched by a selective etching technique. For example, the etching may include removing a portion of the sidewall of the first trench 521. After etching, the vertical interfaces 541 and 542 of the substrate 501 are exposed. There are other methods in the art to remove the protective layer and expose the vertical interface of the substrate. These methods can also be applied here.

[0083] In step 5007, a first nucleation layer and a second nucleation layer are formed at the vertical interface, such as Figure 5GA and 5GB As shown. The first and second nucleation layers 502A and 502B are grown on the exposed vertical surfaces 541 and 542 of the substrate 501. The nucleation layers 502A and 502B include AlN. In some embodiments, after AlN is formed, one or more buffer materials of AlN, GaN, AlGaN, InGaN, AlInN and AlGaInN can be further grown. In some embodiments, the nucleation layer grows in the vertical direction while extending horizontally (not shown). By controlling the process parameters, the growth of the nucleation layer can be made as horizontal as possible. And, although there is growth in the vertical direction, it will not affect the device structure.

[0084] In step 5008, a shielding layer is formed on the surface of the entire device, such as Figure 5HA and 5HB As shown. Figure 5GA and 5GB In the structure shown, a SiO2 shielding layer 512 is formed by a deposition process. The shielding layer 512 fills the groove 521 and forms a SiO2 shielding layer 512 of a certain height on the substrate. In some embodiments, if a semiconductor device with a larger aspect ratio is desired to be formed, the height of the shielding layer 512 will be increased accordingly.

[0085] In step 5009, the shielding layer is patterned to form a plurality of second grooves, such as Figure 5IA and Figure 5IB As shown. By vertical etching technology, vertical second trenches 523 and 524 are etched on the shielding layer 512. Basically, the second trenches 523 and 524 define the height of the second layer of the semiconductor device and limit the height of the nucleation layer to the first layer. At the bottom of the trenches 523 and 524, the upper surface and side surfaces of the nucleation layers 502A and 502B are exposed.

[0086] Those skilled in the art should note that the nucleation layers 502A and 502B are formed on the (111) surface of the Si substrate, and therefore, the nucleation layers 502A and 502B have hexagonal symmetry. After the upper surface and side surfaces of the nucleation layers 502A and 502B are exposed, other structures formed in the grooves 523 and 524 also have hexagonal symmetry.

[0087] In step 5010, first and second channel layers are grown in a plurality of second trenches, such as Figure 5JA and Figure 5JB As shown. Channel layers 503A and 503B are formed on the nucleation layer 502 by epitaxial growth. For conventional epitaxial growth, the horizontal growth is difficult to control, so it is difficult for the semiconductor structure to maintain completely vertical growth, and multiple growth surfaces may appear. The structure involved in the present invention can maintain continuous growth on the same surface, thereby improving the electrical properties of the device.

[0088] In step 5011, a third trench is formed between the first channel layer and the second channel layer. Figure 5KA and 5KB In some embodiments, the shielding layer 512 between the nucleation layers 503A and 503B is etched to form a third trench 525. Since the third trench 525 is formed between the two second trenches 523 and 524, it can be considered that the third trench 545 and the second trenches 523 and 524 together constitute a larger trench with the shielding layer as the sidewall.

[0089] In step 5012, a first barrier layer and a second barrier layer are formed on one side of the first channel layer and the second channel layer in the third trench, respectively. Figure 5LA and 5LB As shown. Barrier layers 504A and 504B are formed by epitaxial growth in the third trench 525. In some embodiments, a barrier layer can be grown to fill the third trench 525, and then barrier layers 504A and 504B are formed by etching the barrier layers 504A and 504B. In some embodiments, the barrier layer can be the same height as the channel layer. In a preferred embodiment, in order to save process and avoid unnecessary etching from damaging the crystal structure, two barrier layers are selected to be epitaxially grown from the channel layer on both sides of the third trench 525, and the space between the two barrier layers is reserved. In this way, as shown in the figure, part of the barrier layer will also be formed on the upper surface of the channel layer.

[0090] In step 5013, a second spacer layer is formed on the entire device, such as Figure 5MA and 5MB SiO2 is deposited on the semiconductor device by a deposition process to fill the space between the barrier layers 504A and 504B and partially cover the channel layer and the barrier layer, thereby forming a second separation layer 513 .

[0091] In step 5014, the second spacer layer is patterned, and a portion of the second spacer layer between the first barrier layer 504A and the second barrier layer 504B is removed. Figure 5NA and 5NB The portion of the second spacer layer 513 between the barrier layers 504A and 504B is partially removed by vertical etching technology.

[0092] In step 5015, a third electrode is formed between the first barrier layer and the second barrier layer. Figure 5OA and 5OB As shown. A third electrode 509 is formed on the spacer layer 513 retained between the first and second barrier layers by an electrode deposition method. In some embodiments, the electrode 509 is disposed closer to the upper position as a gate, and the electrode 509 is as far away from the second electrode 508 (drain) as a gate as possible to improve the overall voltage resistance of the device.

[0093] In step 5016, a third separation layer is formed on the third electrode, such as Figure 5PA and 5PB SiO2 is deposited on the third electrode 509 by a deposition process to fill the space between the first barrier layer and the second barrier layer above the third electrode 509 to form a third separation layer 515 .

[0094] In step 5017, the upper surfaces of the first heterojunction and the second heterojunction are exposed, and a first electrode 507 is formed on the first heterojunction and the second heterojunction. Figure 5QA and 5Q As shown. As shown in the figure, the second separation layer above the first heterojunction and the second heterojunction and the first barrier layer and the second barrier layer extending horizontally that may exist are removed by patterning, exposing the upper surfaces of the first heterojunction and the second heterojunction. In some embodiments, portions of the first and second channel layers and the first and second barrier layers may be further removed to ensure good electrical contact. Next, the electrode material is filled to form the first electrode 507. Although the first electrode 507 shown in the figure includes two portions that contact the first heterojunction and the second heterojunction respectively, the two portions are electrically connected to the same interconnect layer and can therefore be considered to be the same electrode.

[0095] In some embodiments, subsequent steps include forming a first conductor interconnect layer and a third conductor interconnect layer, and electrically connecting them to the first electrode and the third electrode, respectively. These steps are well known to those skilled in the art and will not be described in detail here.

[0096] In step 5018, the entire semiconductor device is turned over and the substrate 501 is removed. Figure 5RA and Figure 5RB As shown in the figure, after the semiconductor device is flipped, the substrate 501 faces upward. The substrate 501 is first thinned, and then the entire substrate 501 is removed from the semiconductor device by wet etching.

[0097] In step 5019, the first heterojunction and the second heterojunction are exposed, such as Figure 5SA and Figure 5SBAs shown in the figure, after removing the substrate 501, the separation layer above the first heterojunction and the second heterojunction and part of the insulating material between the two are removed to expose the first heterojunction and the second heterojunction. In some embodiments, over-etching can be appropriately performed to ensure good electrical contact.

[0098] In step 5020, a second electrode 508 is formed, such as Figure 5TA and Figure 5TB As shown in the figure, by depositing metal, a metal electrode, namely, a second electrode 508, is formed on the first heterojunction and the second heterojunction. The second electrode 508 is in electrical contact with both the first heterojunction and the second heterojunction and the vertical 2DEG.

[0099] In step 5021, a passivation layer is formed, and then a portion of the passivation layer is etched to expose the second electrode 508. Figure 5UA and Figure 5UB As shown in the figure, by depositing SiO2, a passivation layer is formed to fill the space between each HEMT. Of course, part of the SiO2 is deposited on the second electrode 508. Then, the SiO2 on the second electrode 508 is removed by etching technology to expose the second electrode.

[0100] In step 5022, a second conductor interconnect layer is formed, such as Figure 5VA and Figure 5VB As shown. As shown, by depositing metal, a second conductor interconnection layer is formed to electrically connect multiple electrodes 508. In some embodiments, the second electrode 508 and the second conductor interconnection layer can be made of the same material. In some embodiments, the step of forming the second conductor interconnection layer is not necessary. In step 5020, the second electrode 508 and the second conductor interconnection layer can be formed simultaneously.

[0101] In the embodiment shown in FIG5 , the shapes of the first and second channel layers 503A and 503B and the first and second barrier layers 504A and 504B are defined by the grooves. As mentioned above, such a structure has many advantages. In some embodiments, the first and second channel layers 503A and 503B and the first and second barrier layers 504A and 504B may not be defined by the grooves, but the epitaxial growth of the first and second channel layers and the first and second barrier layers may be controlled by adjusting the process parameters.

[0102] Those skilled in the art should note that Figure 5AA-Figure 5VB The embodiment described is only an exemplary method for manufacturing the semiconductor device of the present invention. There are other manufacturing processes and methods in the art, which can also be applied here to obtain the semiconductor device of the present invention. These methods are also within the scope of the present invention.

[0103] As will be appreciated by those skilled in the art, the height of the vertical channel semiconductor device formed on the substrate of the present invention is generally limited. Compared to the height of the substrate, the height of the semiconductor device is relatively small. For example, the height of the substrate is generally above 500 microns, while the height of the semiconductor device is generally several to several tens of microns. One problem brought about by this is that in the process of removing the substrate, the semiconductor device itself is relatively thin, has insufficient mechanical strength, and has weak self-supporting force, and is easily damaged.

[0104] In order to solve this problem, the conventional method is to fix the wafer including the substrate and the semiconductor device on a temporary substrate before removing the substrate. After removing the substrate and forming the second electrode and the second conductor interconnection layer, the temporary substrate is removed. Since the mechanical strength of the semiconductor device can be improved by thickening the metal of the conductor interconnection layer when using the temporary substrate, the semiconductor device itself can have a better self-supporting ability after the process is completed.

[0105] However, the prior art methods are complicated and costly. The present invention proposes a process that can achieve good support strength and complete the process without the need for a temporary substrate.

[0106] Figure 6A-6G is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 6A The state of the semiconductor device (i.e., wafer) before the substrate is removed is shown. As shown in the figure, the wafer includes a substrate 601 and a semiconductor device layer 602 thereon. The semiconductor device layer 602 includes a vertical channel semiconductor device of the present invention, including but not limited to one or more of Schottky diodes, HEMTs, and HHMTs. A plurality of first conductor interconnection layers 603 (e.g., source interconnection layers) and a plurality of third conductor interconnection layers 604 (e.g., gate interconnection layers) are included above the semiconductor device layer 602. As is known to those skilled in the art, the semiconductor device layer 602 can be implemented using the above-mentioned method or other methods in the art, which will not be repeated here.

[0107] The method of this embodiment further includes the following steps: in step 610, a plurality of metal pillars, such as copper pillars, are formed on the plurality of first electrode interconnection layers 603 and the plurality of third electrode interconnection layers 604; Figure 6B As shown. A plurality of metal pillars are formed on each electrode interconnection layer and are electrically connected to each electrode interconnection layer. The height of the metal pillars is relatively high to provide sufficient support in subsequent steps. In some embodiments, the height of the metal pillars is greater than 50 microns, 80 microns, or 100 microns.

[0108] In some embodiments, if the semiconductor device layer includes a device such as a Schottky diode, the third electrode interconnection layer 604 will not appear on the semiconductor device. Therefore, the third electrode interconnection layer 604 is not necessary.

[0109] In step 620, an injection molding process is used to inject insulating material between the plurality of metal pillars, such as Figure 6C As shown. The insulating material includes two states: a fluid state and a solidified state. During the injection molding process, the insulating material is in a fluid state, and after injection, it flows between multiple metal pillars. After a period of time thereafter, the insulating material is transformed into a solidified state, has good mechanical strength, and can provide support in the subsequent substrate removal step. In some embodiments, the insulating material includes at least an organic material, such as one or more of epoxy resin, polystyrene PS, ABS, polycarbonate PC, high-density polyethylene HDPE, polypropylene PP, and polyvinyl chloride PVC.

[0110] In this embodiment, an injection molding process is used. The injection molding process is a traditional process that is easy to integrate with semiconductor processes and has relatively low cost. During the injection molding process, the insulating material is heated and becomes a fluid state. However, the temperature of the insulating material does not cause damage to the semiconductor device. After injection molding, the insulating material enters between the multiple metal pillars and is distributed around the multiple metal pillars. The insulating material becomes a solidified state as the temperature decreases, which can not only protect the metal pillars, but also provide sufficient mechanical strength without the need for a temporary substrate.

[0111] Those skilled in the art should understand that temperature change is only one way to cause the state of the insulating material to change. There are other ways in the art to cause the phase change of the insulating material, including but not limited to: ultraviolet light irradiation, laser curing, chemical reaction, etc. Depending on the characteristics of the semiconductor device, these types of insulating materials can also be selected.

[0112] In step 630, a portion of the insulating material is removed to expose a plurality of metal pillars, such as Fig.6D As shown. This step can also be completed in a later step. Exposing multiple metal pillars can prepare for subsequent electrical connection. Similarly, for the metal pillars and insulating materials formed on the other side, a similar method can be used to remove part of the insulating material and expose the metal pillars to ensure electrical connection.

[0113] In step 640, the silicon substrate is removed, such as Fig. 6EAs shown. Due to the support of multiple metal pillars and solidified insulating materials, the wafer still has good mechanical strength. In the process of removing the substrate, it is not easy to be damaged. In some embodiments, the entire wafer is turned over and supported in a supporting device; then the substrate is thinned first, and then the entire substrate is removed by wet etching. In the process of removing the substrate, since the insulating material provides sufficient mechanical strength, the entire wafer is supported in the supporting device and will not be damaged.

[0114] In step 650, a second electrode and a second electrode interconnection layer are formed, such as Fig. 6F As shown. Those skilled in the art should note that the formation of the second electrode and the formation of the second electrode interconnection layer can be completed in the same step; or they can be completed in different steps. In some embodiments, after removing the substrate, the second electrode can be formed at an appropriate position of the exposed half-electrode device layer 602, thereby forming a second electrode interconnection layer 632 electrically connected to the second electrode. In some embodiments, other steps may be included between the formation of the second electrode and the formation of the second electrode interconnection layer. These steps include, but are not limited to, depositing insulating materials such as SiO2 to form a passivation layer, etc.

[0115] In some embodiments, the wafer may be cut after step 650, and after the semiconductor device layer is cut, one or more semiconductor devices are separated. Next, a packaging step may be included to obtain a semiconductor device that can be actually used.

[0116] In step 660, a plurality of metal pillars, such as copper pillars, are formed on the second electrode interconnection layer; and an injection molding process is then used to inject an insulating material, such as Figure 6G As shown. Similar to steps 610 and 620, multiple metal pillars can also be formed on one side of the second electrode and an insulating material can be injected to further improve the physical strength of the half-electrode device. At the same time, the insulating material also seals the entire semiconductor device layer, and in some embodiments, the subsequent packaging process can be saved. After step 660, the wafer can be cut. In some embodiments, one or more semiconductor devices after cutting can also be packaged again to obtain a semiconductor device that can be actually used.

[0117] refer to Figure 6G The obtained semiconductor device includes a first electrode interconnection layer, a third electrode interconnection layer, and metal pillars for electrical connection on the first side (upper side); and insulating materials are distributed between these metal pillars to provide the required mechanical strength for the semiconductor device. The second side (lower side) of the semiconductor device includes a second electrode and a second electrode interconnection layer. Optionally, the semiconductor device may also include metal pillars for electrical connection of the second electrode interconnection layer and insulating materials distributed between these metal pillars. Thus, additional mechanical strength is provided on the second side of the semiconductor device.

[0118] The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: a semiconductor device layer including one or more semiconductor devices; A first electrode interconnection layer, which is disposed on a first side of the semiconductor device layer; One or more first metal pillars, which are disposed on a first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; A first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection moldable material; as well as A second electrode interconnection layer is disposed on a second side opposite to the first side of the semiconductor device layer; The first metal pillar and the first insulating material are located on a side of the first electrode interconnection layer away from the semiconductor device layer, the first electrode interconnection layer is electrically connected to the first electrode, and the substrate of the semiconductor device is removed; One or more semiconductor devices in the semiconductor device layer have a vertical channel.

2. The semiconductor device according to claim 1, wherein one or more semiconductor devices in the semiconductor device layer include: One or more of a Schottky diode, a HEMT, and a HHMT. 3 . The semiconductor device according to claim 1 , wherein the second electrode interconnection layer is electrically connected to the second electrode on the second side of the semiconductor device layer. The semiconductor device according to claim 1 , wherein the first metal pillar is a copper pillar. 5 . The semiconductor device according to claim 1 , wherein a height of the first metal pillar is greater than 60 micrometers, greater than 80 micrometers, or greater than 100 micrometers. The semiconductor device as claimed in claim 1 , wherein the first insulating material is distributed around the one or more metal pillars by injection molding. The semiconductor device according to claim 1 , wherein the first insulating material is an organic material. 8 . The semiconductor device according to claim 1 , wherein the first insulating material is one or more of epoxy resin EP, polystyrene PS, ABS, polycarbonate PC, high-density polyethylene HDPE, polypropylene PP, and polyvinyl chloride PVC.

9. The semiconductor device as described in claim 1 further includes one or more second metal pillars, which are arranged on the second side of the semiconductor device layer and electrically connected to the second electrode interconnection layer; and a second insulating material, which is arranged around the one or more second metal pillars, wherein the second insulating material is an injection moldable material.

10. The semiconductor device according to claim 1, further comprising: A third electrode interconnection layer, which is disposed on the first side of the semiconductor device layer; as well as One or more third metal pillars are arranged on the first side of the semiconductor device layer and are electrically connected to the third electrode interconnection layer; wherein the first insulating material can also be configured to be distributed around the one or more third metal pillars.

11. A semiconductor device obtained by cutting from the semiconductor apparatus according to any one of claims 1 to 10.

12. A semiconductor device obtained by cutting and packaging the semiconductor apparatus according to any one of claims 1 to 10.

13. A method for manufacturing a semiconductor device, comprising: forming one or more first metal pillars on the first electrode interconnect layer on the first side of the semiconductor device layer; Injection-molding a first insulating material so that the first insulating material is distributed around the one or more first metal pillars; removing the substrate; as well as forming a second electrode interconnection layer on a second side opposite to the first side of the semiconductor device layer; Wherein, the height of the first metal pillar is greater than 60 microns, greater than 80 microns, or greater than 100 microns; The first metal column and the first insulating material are located on a side of the first electrode interconnection layer away from the semiconductor device layer, and the first electrode interconnection layer is electrically connected to the first electrode; One or more semiconductor devices in the semiconductor device layer have a vertical channel.

14. The method of claim 13, further comprising: After removing the substrate, a second electrode is formed on the second side opposite to the first side of the semiconductor device layer.

15. The method of claim 13, further comprising: A portion of the first insulating material is removed to expose the one or more first metal pillars.

16. The method of claim 13, further comprising: One or more third metal pillars are formed on the third electrode interconnection layer on the first side of the semiconductor device layer; wherein the step of injecting the first insulating material further includes: distributing the first insulating material around the one or more third metal pillars.

17. The method of claim 13, further comprising: forming one or more second metal pillars on the second electrode interconnect layer on the second side of the semiconductor device layer; The second insulating material is injection-molded so that the insulating material is distributed around the one or more second metal pillars.

18. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device layer on a substrate, the semiconductor device layer comprising one or more semiconductor devices; forming a first electrode interconnection layer on a first side of the semiconductor device layer; forming one or more first metal pillars on the first electrode interconnect layer on the first side of the semiconductor device layer; Injection-molding a first insulating material so that the first insulating material is distributed around the one or more first metal pillars; removing the substrate; as well as forming a second electrode interconnection layer on a second side opposite to the first side of the semiconductor device layer; Wherein, the height of the first metal pillar is greater than 60 microns, greater than 80 microns, or greater than 100 microns; The first metal column and the first insulating material are located on a side of the first electrode interconnection layer away from the semiconductor device layer, and the first electrode interconnection layer is electrically connected to the first electrode; One or more semiconductor devices in the semiconductor device layer have a vertical channel.

19. The method of claim 18, further comprising: A third electrode interconnection layer is formed on the first side of the semiconductor device layer, and one or more third metal pillars are formed on the third electrode interconnection layer on the first side of the semiconductor device layer; wherein the third metal pillar can be formed simultaneously with the first metal pillar; wherein the step of injecting the first insulating material further includes: making the first insulating material distributed around the one or more third metal pillars.

20. The method of claim 18, further comprising: forming one or more second metal pillars on the second electrode interconnect layer on the second side of the semiconductor device layer; The second insulating material is injection-molded so that the insulating material is distributed around the one or more second metal pillars.

21. The method of claim 18, further comprising: The semiconductor device layer is cut to separate the one or more semiconductor devices.

22. The method of claim 21, further comprising: The separated one or more semiconductor devices are packaged.

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