Ferroelectric memory device, method for forming same, and integrated chip

Abstract

Embodiments of the present disclosure relate to a ferroelectric memory device. The ferroelectric memory device includes a pair of source / drain regions disposed in a semiconductor substrate. A gate dielectric is disposed above the semiconductor substrate and between the source / drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, wherein both the first conductive structure and the second conductive structure have an overall negative charge that is greater than or equal to an overall negative charge of the ferroelectric structure.

Description

Technical Field

[0001] The present disclosure relates to ferroelectric memory devices. Background Art

[0002] Many modern electronic devices include nonvolatile memory. Nonvolatile memory is electronic memory that can store data without power. A promising candidate for the next generation of nonvolatile memory is ferroelectric random-access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal–oxide–semiconductor (CMOS) logic manufacturing processes. Summary of the invention

[0003] One aspect of the present disclosure provides a ferroelectric memory device comprising: a pair of source / drain regions, a gate dielectric, a first conductive structure, a ferroelectric structure, and a second conductive structure. The pair of source / drain regions are disposed in a semiconductor substrate. The gate dielectric is disposed above the semiconductor substrate and between the source / drain regions. The first conductive structure is disposed on the gate dielectric. The ferroelectric structure is disposed on the first conductive structure. The second conductive structure is disposed on the ferroelectric structure, wherein both the first conductive structure and the second conductive structure have an overall negative charge, and the overall negative charge is greater than or equal to the overall negative charge of the ferroelectric structure.

[0004] Another aspect of the present disclosure provides an integrated chip, comprising: a semiconductor device, a first interlayer dielectric (ILD) structure, a first conductive via, and a polarization switching structure. The semiconductor device is disposed on a semiconductor substrate. The first interlayer dielectric (ILD) structure is disposed above the semiconductor device and the semiconductor substrate. The first conductive via is disposed in the first interlayer dielectric structure and is electrically coupled to the semiconductor device. The polarization switching structure is disposed above the first interlayer dielectric structure and is electrically coupled to the first conductive via, wherein the polarization switching structure includes a ferroelectric structure disposed between the first conductive structure and the second conductive structure, and wherein both the first conductive structure and the second conductive structure have an overall negative charge, and the overall negative charge is greater than or equal to the overall negative charge of the ferroelectric structure.

[0005] Yet another aspect of the present disclosure provides a method for forming a ferroelectric memory device, the method comprising: forming a dielectric layer above a semiconductor substrate; forming a first conductive layer above the dielectric layer, wherein the first conductive layer has a first overall negative charge; forming a ferroelectric layer on the first conductive layer, wherein the ferroelectric layer has a second overall negative charge, the second overall negative charge being less than or equal to the first overall negative charge; forming a second conductive layer on the ferroelectric layer, wherein the second conductive layer has a third overall negative charge, the third overall negative charge being greater than or equal to the second negative charge; etching the second conductive layer, the ferroelectric layer, and the first conductive layer to form a polarization switching structure above the semiconductor substrate; and forming a first conductive via, the first conductive via being above the polarization switching structure and electrically coupled to the polarization switching structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, the aspects of the present disclosure can be better understood from the following detailed description. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, for clarity of discussion, the size of each feature may be arbitrarily increased or reduced.

[0007] Figure 1 depicts a cross-sectional view of some embodiments of a first integrated chip (IC) including a first wake-up-free ferroelectric memory device;

[0008] Figure 2 Draw Figure 1 An enlarged cross-sectional view of some embodiments of a device gate stack;

[0009] Figure 3 A top view of some embodiments of a first conductive structure, a ferroelectric structure, and a second conductive structure is shown, wherein the first conductive structure, the ferroelectric structure, and the second conductive structure are moved from Figure 1 in which their stack orientation is arranged adjacent to each other;

[0010] Figure 4 Draw Figure 1 cross-sectional views of some more detailed embodiments of the first integrated chip;

[0011] Figure 5 Draw Figure 4 cross-sectional views of some other embodiments of the first integrated chip;

[0012] Figure 6 Draw Figure 4 cross-sectional views of some other embodiments of the first integrated chip;

[0013] Figure 7 depicts a cross-sectional view of some embodiments of a second integrated chip including a second wake-up-free ferroelectric memory device;

[0014] Figure 8 Draw Figure 7 cross-sectional views of some other embodiments of a second integrated chip;

[0015] Fig. 9 Draw Figure 7 cross-sectional views of some other embodiments of a second integrated chip;

[0016] Fig.10 Draw Fig. 9 cross-sectional views of some other embodiments of a second integrated chip;

[0017] Figures 11 to 20 Drawing for forming Figure 5 a series of cross-sectional views of some embodiments of a first integrated chip;

[0018] Fig.21 A flow chart illustrating some embodiments of a method for forming an integrated chip including a front-end-of-line wake-up-free ferroelectric memory device;

[0019] Fig. 22 A flow chart illustrating some embodiments of a method for forming an integrated chip including a back-end-of-line wake-up-free ferroelectric memory device;

[0020] Among them, the symbols are as follows:

[0021] 100...first integrated chip 101a...first wake-up-free ferroelectric memory device

[0022] 102 ... semiconductor substrate 104 ... isolation structure

[0023] 106a, 106b ... source / drain regions 108 ... gate dielectric

[0024] 110...Polarization switching structure 112...First conductive structure

[0025] 114... ferroelectric structure 116... second conductive structure

[0026] 118...gate electrode 120...device gate stack

[0027] 122...interlayer dielectric structure 122a...first interlayer dielectric structure

[0028] 122b...second interlayer dielectric structure 124...conductive contact

[0029] 402...conductive line 402bl...bit line

[0030] 402pl...board line 402sl...source line

[0031] 402wl...word line 404...conductive via

[0032] 502 ... sidewall spacers 504a, 504b ... lightly doped source / drain extensions

[0033] 700 ... second integrated chip 702 ... semiconductor device

[0034] 704...lower interlayer dielectric structure 706...middle interlayer dielectric structure

[0035] 708...upper interlayer dielectric structure 902...first electrode

[0036] 904...second electrode 1202...dielectric layer

[0037] 1204...first conductive layer 1206...ferroelectric layer

[0038] 1208...second conductive layer 1210...processing layer

[0039] 1302 ... initial gate stack 1304 ... sacrificial gate

[0040] 1306...masking layer 1702...opening

[0041] 1802...Gate electrode layer 2100...Flowchart

[0042] 2102, 2104, 2106, 2108, 2110, 2112, 2114...action

[0043] 2200...Flowchart

[0044] 2202, 2204, 2206, 2208, 2210...Action

[0045] L 1 ...the first length L 2 ...second length

[0046] L 3 ...the third length T 1 ...First thickness

[0047] T 2 ...Second thickness T 3 ...Third thickness

[0048] T4 ...The fourth thickness T 5 ...Fifth Thickness

[0049] T 6 ...The sixth thickness W 1 ...first width

[0050] W 2 ...second width W 3 ...third width. DETAILED DESCRIPTION

[0051] The following disclosure provides many different embodiments or examples to achieve different features of the subject matter provided. Specific embodiments of components and arrangements are described below to simplify the present disclosure. Of course, these embodiments are only embodiments and are not intended to be restrictive. For example, the formation of a first feature above or on a second feature in the subsequent description may include an embodiment in which the first and second features are formed as direct contacts, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in each embodiment. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0052] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature(s) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in different ways (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted similarly.

[0053] Some ferroelectric memories (e.g., ferroelectric random access memory (FeRAM)) include a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric structure disposed between a first electrode and a second electrode. In other embodiments, the ferroelectric structure may be disposed between a gate electrode and a semiconductor substrate (e.g., a ferroelectric field-effect transistor (FeFET)). The ferroelectric structure is configured to switch between polarization states to store data (e.g., binary "0" and binary "1"). Ferroelectric memories are typically disposed on an integrated chip (IC) that includes other types of semiconductor devices (e.g., metal-oxide semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), high-electron-mobility transistors (HEMTs), etc.).

[0054] The challenge of the above-mentioned ferroelectric memory is that a wake-up procedure needs to be performed on the ferroelectric memory cell to improve the memory window of the ferroelectric memory cell. For example, after the ferroelectric memory cell has been turned off (e.g., powered off) for a given period of time, the memory window of the ferroelectric memory cell may degrade to an unsatisfactory condition. Therefore, each time the ferroelectric memory cell is turned on, a wake-up procedure needs to be performed to improve the memory window of the ferroelectric memory cell so that the ferroelectric memory cell can operate normally (e.g., read, write, erase). The wake-up procedure includes providing multiple voltage pulses to the ferroelectric memory cell, which voltage pulses may consist of different voltage amplitudes and pulse widths.

[0055] In order to perform the wake-up procedure, the wake-up circuit system is arranged on the integrated chip to provide a voltage pulse to the ferroelectric memory cell. Since the wake-up procedure increases the power consumption of the ferroelectric memory, the wake-up procedure may negatively affect the performance of the ferroelectric memory. In addition, the wake-up circuit system occupies space on the integrated chip, which space may be utilized to increase the density / number of ferroelectric memory cells.

[0056] In some embodiments, the present disclosure is related to a wake-up-free ferroelectric memory device. The wake-up-free ferroelectric memory device includes a polarization switching structure. The polarization switching structure includes a ferroelectric structure disposed between a first conductive structure and a second conductive structure. Both the first conductive structure and the second conductive structure have an overall negative charge, which is greater than or equal to the overall negative charge of the ferroelectric structure. Because the overall negative charge of both the first conductive structure and the second conductive structure is greater than the overall negative charge of the ferroelectric structure, a wake-up procedure is not required to improve the memory window of the wake-up-free ferroelectric memory device. For example, because the overall negative charge of both the first conductive structure and the second conductive structure is greater than the overall negative charge of the ferroelectric structure, the memory window of the wake-up-free ferroelectric memory device may not degrade to an unsatisfactory condition after power is removed from the polarization switching structure. In other words, the wake-up-free ferroelectric memory device does not require a wake-up procedure to improve the memory window of the wake-up-free ferroelectric memory device for normal operation (e.g., reading, writing, erasing). Accordingly, a wake-up-free ferroelectric memory may consume less power and / or have a greater number (greater density) of ferroelectric memory devices on a given integrated chip than a non-wake-up-free ferroelectric memory.

[0057] Figure 1 A cross-sectional view of some embodiments of a first integrated chip (IC) 100 including a first wake-up-free ferroelectric memory device 101a is shown. In some embodiments, Figure 1 The first wake-up-free ferroelectric memory device 101a shown in the figure may be referred to as a wake-up-free ferroelectric field effect transistor (FeFET) and / or a front-end-of-line wake-up-free ferroelectric memory device. In further embodiments, the first wake-up-free ferroelectric memory device 101a may be a portion of a random access memory (RAM) device (e.g., a ferroelectric random access memory (FeRAM) device). It should be understood that in some embodiments, Figure 1 The first non-wake-up ferroelectric memory device 101a may be implemented in a fin type design (eg, a fin field effect transistor (FinFET) type design). It should be further understood that in some embodiments, the first integrated chip 100 may include a plurality of first non-wake-up ferroelectric memory devices 101a arranged in an array.

[0058] like Figure 1As shown, the first integrated chip 100 includes an isolation structure 104 disposed in a semiconductor substrate 102. A pair of source / drain regions 106a to 106b are disposed in the semiconductor substrate 102 and are spaced apart. A device gate stack 120 is disposed above the semiconductor substrate 102 and between the source / drain regions 106a to 106b. In some embodiments, the first wake-up-free ferroelectric memory device 101a includes a device gate stack 120 and source / drain regions 106a to 106b. An interlayer dielectric (ILD) structure 122 is disposed above the semiconductor substrate 102 and the device gate stack 120. A plurality of conductive contacts 124 are disposed in the interlayer dielectric (ILD) structure 122. The conductive contacts 124 extend through the interlayer dielectric structure 122 to contact the source / drain regions 106a to 106b and the device gate stack 120, respectively.

[0059] In some embodiments, the device gate stack 120 includes a gate dielectric 108 disposed on the semiconductor substrate 102. The polarization switching structure 110 is disposed between the gate dielectric 108 and the gate electrode 118. The polarization switching structure 110 is configured to store a bit of data. For example, the polarization switching structure 110 can be switched between a first polarization state (e.g., a negative remnant (-Pr) polarization state) (which corresponds to a binary value "1") and a second polarization state (e.g., a positive remnant (+Pr) polarization state) (which corresponds to a binary value "0", or vice versa). In some embodiments, a positive voltage pulse is applied to the gate electrode 118 to switch to the first polarization state, and a negative voltage pulse is applied to the gate electrode 118 to switch to the second polarization state, or vice versa.

[0060] The polarization switching structure 110 includes a ferroelectric structure 114 disposed between a first conductive structure 112 and a second conductive structure 116. The first conductive structure 112 has an overall negative charge, which is greater than or equal to the overall negative charge of the ferroelectric structure 114. The second conductive structure 116 has an overall negative charge, which is greater than or equal to the overall negative charge of the ferroelectric structure 114. More specifically, both the overall negative charge of the first conductive structure 112 and the overall negative charge of the second conductive structure 116 are greater than or equal to the overall negative charge of the ferroelectric structure 114.

[0061] "Overall negative charge" (X 化合物(或元素) ) depends on the chemical composition of the compound (or element), the percentage of atoms in the chemical composition, and the electronegativity of the element measured by the Pauling scale. x B y …N z ) is given by:

[0062]

[0063] Where X AxBy…Nz Compound A x B y …N z The overall electronegativity of A is the first element, B is the second element, N is the Nth element, and X rA is the electronegativity of the first element measured by the Pauling scale, X rB is the electronegativity of the second element measured by the Pauling scale, X rN is the electronegativity of the Nth element measured by the Pauling scale, and x is the electronegativity of the compound A x B y …N z The number of atoms of the first element in the compound A. x B y …N z The number of atoms of the second element in the compound A x B y …N z The number of atoms of the Nth element in .

[0064] Some non-limiting examples are provided below, illustrating the calculation of the "overall electronegativity" of various elements / compounds.

[0065] Example 1 - Tungsten (X W )'s overall electronegativity

[0066] The electronegativity of W (tungsten) measured by the Pauling scale (X rW )–2.36

[0067]

[0068] X W =2.36

[0069] Example 2 - Overall electronegativity of hafnium oxide (X HfO2 )

[0070] The electronegativity of Hf measured by the Pauling scale (X rHf )–1.3

[0071] The electronegativity of O measured by the Pauling scale (X rO )–3.44

[0072]

[0073] Example 3 - Overall electronegativity of hafnium-zirconium-oxide (X HfZrO4 )

[0074] The electronegativity of Hf measured by the Pauling scale (X rHf )–1.3

[0075] The electronegativity of Zr measured by the Pauling scale (X rZr )–1.33

[0076] The electronegativity of O measured by the Pauling scale (X rO )–3.44

[0077]

[0078] Because the overall negativity of the first conductive structure 112 and the overall negativity of the second conductive structure 116 are greater than or equal to the overall negativity of the ferroelectric structure 114, the memory window of the first non-wake-up ferroelectric memory device 101a may not degrade to an unsatisfactory condition after power is removed from the polarization switching structure 110. In other words, the first non-wake-up ferroelectric memory device 101a does not require a wake-up procedure to improve the memory window of the first non-wake-up ferroelectric memory device 101a for normal operation (e.g., reading, writing, erasing). Accordingly, compared to a non-wake-up ferroelectric memory, the first non-wake-up ferroelectric memory 101a may consume less power and / or the first integrated chip 100 may include a greater number (or a greater density) of first non-wake-up ferroelectric memory devices 101a.

[0079] Figure 2 Draw Figure 1 An enlarged cross-sectional view of some embodiments of a device gate stack 120 .

[0080] The gate electrode 118 may include, for example, doped polysilicon (e.g., N-type / P-type polysilicon), a metal (e.g., tungsten (W), aluminum (Al), titanium (Ti), molybdenum (Mo), nickel silicide (NiSi), or the like), some other conductive material, or a combination thereof. In some embodiments, a capping structure (not shown) (e.g., titanium nitride (TiN), tantalum nitride (TaN), or the like) may be disposed between the gate electrode 118 and the second conductive structure 116. In further embodiments, the gate electrode 118 and / or the capping structure have an overall negative charge that is less than the overall negative charge of the ferroelectric structure 114. In still further embodiments, when the gate electrode 118 includes a metal, the gate electrode 118 (and the capping structure) may be referred to as a metal gate electrode.

[0081] In some embodiments, the gate dielectric 108 may include, for example, an oxide (eg, silicon dioxide (SiO 2 )), high dielectric constant dielectric materials (e.g., hafnium oxide (HfO2 )、ZrO 2 ), or some other dielectric material having a dielectric constant greater than about 3.9), or some other dielectric material, or a combination thereof. In further embodiments, the overall electronegativity of the gate dielectric 108 is less than the overall electronegativity of the ferroelectric structure 114.

[0082] In some embodiments, the first conductive structure 112 may include, for example, a metal (e.g., aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), platinum (Pt), tungsten (W), nickel (Ni), iridium (Ir), etc.), a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), a metal oxide (e.g., iridium oxide (IrO 2 ), doped polysilicon (e.g., N-type / P-type polysilicon), or the like. In further embodiments, the ferroelectric structure 114 may include one or more of the following layers: for example, a metal oxide (e.g., hafnium oxide (HfXO Y )), metal oxide components (e.g., hafnium silicon oxide (Hf X Si Y O Z ), hafnium aluminum oxide (Hf X Al Y O Z ), Hafnium Gadolinium Oxide (Hf X G Y O Z ), hafnium zirconium oxide (Hf X Zr Y O Z ), Hafnium Lanthanum Oxide (Hf X La Y O Z ), hafnium strontium oxide (Hf X Sr Y O Z ), hafnium yttrium oxide (Hf X Y Y O Z ), strontium titanate (STO), etc.), metal oxynitrides (e.g., hafnium oxynitride (Hf X O Y N Z In a further embodiment, the second conductive structure 116 may include, for example, a metal (e.g., Al, Ti, Ta, Au, Pt, W, Ni, Ir, etc.), a metal nitride (e.g., TiN, TaN, etc.), a metal oxide (e.g., IrO 2 ), doped polysilicon (e.g., N-type / P-type polysilicon)), or the like.

[0083] The first conductive structure 112 and the second conductive structure 116 may have the same chemical composition. In other embodiments, the chemical composition of the first conductive structure 112 may be different from the chemical composition of the second conductive structure 116. The overall electronegativity of the first conductive structure 112 may be greater than the overall electronegativity of the gate dielectric 108. In further embodiments, the overall electronegativity of the second conductive structure 116 may be greater than the overall electronegativity of the gate electrode 118 (or capping structure).

[0084] In some embodiments, the first conductive structure 112 contacts both the gate dielectric 108 and the ferroelectric structure 114, the second conductive structure 116 contacts both the ferroelectric structure 114 and the gate electrode 118, and the gate electrode 118 contacts one of the conductive contacts 124. In further embodiments, the sidewalls of the gate dielectric 108, the sidewalls of the first conductive structure 112, the sidewalls of the ferroelectric structure 114, the sidewalls of the second conductive structure 116, and the sidewalls of the gate electrode 118 may be substantially aligned in a vertical direction. In such embodiments, the area (e.g., length (span)) of the gate dielectric 108 may be substantially aligned with respect to the gate dielectric 108. Figure 2 of pages) multiplied by the width (in / out Figure 2 ), the area of ​​the first conductive structure 112, the area of ​​the ferroelectric structure 114, the area of ​​the second conductive structure 116, and the area of ​​the gate electrode 118 may be substantially the same. In other embodiments, the sidewalls of the first conductive structure 112 may be disposed between the sidewalls of the gate dielectric 108, the sidewalls of the ferroelectric structure 114 may be disposed between the sidewalls of the first conductive structure 112, the sidewalls of the second conductive structure 116 may be disposed between the sidewalls of the ferroelectric structure 114, and / or the sidewalls of the gate electrode 118 may be disposed between the sidewalls of the second conductive structure 116. In such embodiments, the area of ​​the first conductive structure 112 may be smaller than the area of ​​the gate dielectric 108, the area of ​​the ferroelectric structure 114 may be smaller than the area of ​​the first conductive structure 112, the area of ​​the second conductive structure 116 may be smaller than the area of ​​the ferroelectric structure 114, and / or the area of ​​the gate electrode 118 may be smaller than the area of ​​the second conductive structure 116.

[0085] In some embodiments, the gate dielectric 108 may have an area between about 1 square nanometer (nm) and about 1 square nanometer (nm). 2 ) and about 100 square micrometers (μm 2 In a further embodiment, the area of ​​the polarization switching structure 110 is between about 1 square nanometer (nm 2 ) and about 100 square micrometers (μm 2). In yet further embodiments, the area of ​​the gate dielectric 108 may be substantially the same as the area of ​​the polarization switching structure 110. In other embodiments, the area of ​​the gate dielectric 108 may be different from the area of ​​the polarization switching structure 110.

[0086] The polarization switching structure 110 has a first thickness T 1 In some embodiments, the first thickness T 1 The first conductive structure 112 has a second thickness T between about 1.2 nanometers (nm) and about 2,100 nanometers (nm). 2 The second thickness T 2 The ferroelectric structure 114 has a third thickness T 3 In some embodiments, the third thickness is between about 1 nanometer and about 100 nanometers. The second conductive structure 116 has a fourth thickness T 4 . The fourth thickness T 4 The gate dielectric 108 may have a fifth thickness T between about 0.1 nanometers and about 1,000 nanometers. 5 In a further embodiment, the first thickness T 1 With the fifth thickness T 5 The ratio between 1 Divide by T 2 ) is between about 100 / 1 and about 1 / 1.

[0087] In some embodiments, the second thickness T 2 , the third thickness T 3 , and the fourth thickness T 4 In a further embodiment, the second thickness T 2 and the fourth thickness T 4 may be substantially the same, and the third thickness T 3 In a further embodiment, the second thickness T 2 (or the fourth thickness T 4 ) and the third thickness T 3 may be substantially the same, and the fourth thickness T 4 (or the second thickness T 2 ) is different. In a further embodiment, the second thickness T 2 , the third thickness T 3 , and the fourth thickness T 4 May be different from each other.

[0088] Figure 3 A top view of some embodiments of a first conductive structure, a ferroelectric structure, and a second conductive structure is shown, wherein the first conductive structure, the ferroelectric structure, and the second conductive structure are moved from Figure 1 They are stacked in an orientation and arranged adjacent to each other.

[0089] like Figure 3 As shown, the first conductive structure 112 has a first length L 1 and the first width W 1 In some embodiments, the first length L 1 The first width W may be between about 1 nanometer (nm) and about 10 micrometers (μm). 1 The area of ​​the first conductive structure 112 (eg, L 1 Multiply by W 1 ) in the range of about 1 square nanometer (nm 2 ) and about 100 square micrometers (μm 2 )between.

[0090] The ferroelectric structure 114 has a second length L 2 and the second width W 2 In some embodiments, the second length L 2 The second width W may be between about 1 nanometer (nm) and about 10 micrometers (μm). 2 The area of ​​the ferroelectric structure 114 (eg, L 2 Multiply by W 2 ) in the range of about 1 square nanometer (nm 2 ) and about 100 square micrometers (μm 2 )between.

[0091] The second conductive structure 116 has a third length L 3 and the third width W 3 In some embodiments, the third length L 3 The third width W may be between about 1 nanometer (nm) and about 10 micrometers (μm). 3 The area of ​​the second conductive structure 116 (eg, L 3 Multiply by W 3 ) in the range of about 1 square nanometer (nm 2 ) and about 100 square micrometers (μm 2 )between.

[0092] Figure 4 Draw Figure 1FIG. 1 is a cross-sectional view of some more detailed embodiments of the first integrated chip 100 .

[0093] like Figure 4 As shown, a plurality of conductive lines 402 (e.g., metal lines) and a plurality of conductive vias 404 (e.g., metal vias) are disposed in the interlayer dielectric structure 122. The plurality of conductive lines 402, the plurality of conductive vias 404, and the plurality of conductive contacts 124 are electrically coupled together in a predetermined manner and are configured to provide electrical connections between different devices disposed throughout the first integrated chip 100. In some embodiments, the plurality of conductive lines 402 and the plurality of conductive vias 404 may include, for example, copper (Cu), aluminum (Al), or the like. In further embodiments, the conductive contacts 124 may include, for example, tungsten (W), copper (Cu), aluminum (Al), or the like. The plurality of conductive lines 402 have a sixth thickness T 6 In a further embodiment, the sixth thickness T 6 With T 1 The ratio between 6 Divide by T 1 ) is between about 200 / 1 and about 0.5 / 1. It should be understood that any number of conductive lines 402 and / or conductive vias 404 may be stacked alternately with each other in the interlayer dielectric structure 122. In yet further embodiments, the plurality of conductive lines 402, the plurality of conductive vias 404, the plurality of conductive contacts 124, and the interlayer dielectric structure 122 may be referred to as an interconnect structure.

[0094] The first of the plurality of conductive lines 402 is represented as 402wl and may be referred to as a word line. In some embodiments, the word line may be electrically coupled to the polarization switching structure 110 via an interconnect structure and a gate electrode 118. The second of the plurality of conductive lines 402 is represented as 402bl and may be referred to as a bit line. In further embodiments, the bit line may be electrically coupled to a first source / drain region 106a of source / drain regions 106a to 106b via an interconnect structure. The third of the plurality of conductive lines 402 is represented as 402sl and may be referred to as a source line. In yet further embodiments, the source line may be electrically coupled to a second source / drain region 106b of source / drain regions 106b to 106b via an interconnect structure.

[0095] In some embodiments, the semiconductor substrate 102 may include any type of semiconductor body (e.g., single crystal silicon / CMOS bulk, silicon germanium (SiGe), silicon on insulator (SOI), etc.). The isolation structure 104 may be, for example, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or the like. In further embodiments, the source / drain regions 106a-106b are doped regions of the semiconductor substrate 102 having a doping type (e.g., N-type or P-type) opposite to the doping type of adjacent regions of the semiconductor substrate 102, or the adjacent regions of the semiconductor substrate 102 may be intrinsic. The interlayer dielectric structure 122 may include one or more stacked interlayer dielectric layers, which may respectively include a low dielectric constant dielectric (e.g., a dielectric material having a dielectric constant less than 3.9), an oxide (e.g., SiO 2 ), or the like.

[0096] Figure 5 Draw Figure 4 FIG. 1 is a cross-sectional view of some other embodiments of the first integrated chip 100 .

[0097] like Figure 5 As shown, the interlayer dielectric structure 122 includes a first interlayer dielectric structure 122a and a second interlayer dielectric structure 122b. The second interlayer dielectric structure 122b is disposed above the first interlayer dielectric structure 122a and the device gate stack 120. In some embodiments, the upper surface of the first interlayer dielectric structure 122a may be substantially coplanar with the upper surface of the gate electrode 118. In further embodiments, the first interlayer dielectric structure 122a may include one or more stacked interlayer dielectric layers. In yet further embodiments, the second interlayer dielectric structure 122b may include one or more stacked interlayer dielectric layers.

[0098] A pair of lightly doped source / drain extensions (LDDs) 504a-504b are disposed in the semiconductor substrate 102 and spaced apart. The lightly doped source / drain extensions (LDDs) 504a-504b are doped regions of the semiconductor substrate 102 having the same doping type as the source / drain regions 106a-106b. The lightly doped source / drain extensions (LDDs) 504a-504b have a lower doping concentration than the source / drain regions 106a-106b. Sidewall spacers 502 are disposed above the semiconductor substrate 102 and along sidewalls of the gate dielectric 108, sidewalls of the polarization switching structure 110, and sidewalls of the gate electrode 118. In further embodiments, the sidewall spacers 502 may include, for example, a nitride (eg, silicon nitride (eg, SiN)), an oxynitride (eg, silicon oxynitride (SiO X N Y )), or the like.

[0099] Figure 6 Draw Figure 4 FIG. 1 is a cross-sectional view of some other embodiments of the first integrated chip 100 .

[0100] like Figure 6 As shown, one of the plurality of conductive contacts 124 contacts the second conductive structure 116. In such an embodiment, the device gate stack 120 may not include a gate electrode 118 (eg, see Figure 5 ).

[0101] Figure 7 A cross-sectional view of some embodiments of a second integrated chip 700 including a second wake-up-free ferroelectric memory device 101b is illustrated. In some embodiments, the second wake-up-free ferroelectric memory device 101b may be referred to as a back-end-of-line wake-up-free ferroelectric memory device. In further embodiments, the second wake-up-free ferroelectric memory device 101b may be part of a random access memory (RAM) device (e.g., a ferroelectric random access memory (FeRAM) device). It should be understood that in some embodiments, features of the second integrated chip 700 that share reference numbers with features of the first integrated chip 100 may have substantially similar properties (e.g., size, chemical composition, relationship, etc.) to the features of the first integrated chip 100 where they share reference numbers. It should be further understood that in some embodiments, the second integrated chip 700 may include a plurality of second wake-up-free ferroelectric memory devices 101b arranged in an array.

[0102] like Figure 7As shown, a semiconductor device 702 is disposed on a semiconductor substrate 102. In some embodiments, the semiconductor device 702 may be a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or any other front-end semiconductor device. In further embodiments, the semiconductor device 702 may include a gate dielectric 108, a gate electrode 118 disposed above the gate dielectric 108, and a pair of source / drain regions 106a-106b.

[0103] The lower interlayer dielectric structure 704 is disposed over the semiconductor substrate 102 and the semiconductor device 702. In some embodiments, a plurality of conductive contacts 124, a plurality of conductive lines 402, and a plurality of conductive vias 404 are disposed in the lower interlayer dielectric structure 704. An upper interlayer dielectric structure 708 is disposed over the lower interlayer dielectric structure 704. In further embodiments, a plurality of conductive lines 402 and / or a plurality of conductive vias 404 are disposed in the upper interlayer dielectric structure 708. An intermediate interlayer dielectric structure 706 is disposed between the upper interlayer dielectric structure 708 and the lower interlayer dielectric structure 704. In yet further embodiments, the lower interlayer dielectric structure 704, the middle interlayer dielectric structure 706, and the upper interlayer dielectric structure 708 may include one or more stacked interlayer dielectric layers, which may respectively include a low-k dielectric (e.g., a dielectric material having a dielectric constant of less than about 3.9), an oxide (e.g., SiO 2 ), or the like.

[0104] The second wake-up-free ferroelectric memory device 101b is disposed in the interlayer dielectric structure 706. The second wake-up-free ferroelectric memory device 101b includes a polarization switching structure 110. The polarization switching structure 110 includes a ferroelectric structure 114 disposed between a first conductive structure 112 and a second conductive structure 116. In some embodiments, an upper surface of the second conductive structure 116 is substantially coplanar with an upper surface of the interlayer dielectric structure 706. In further embodiments, a bottom surface of the first conductive structure 112 is substantially coplanar with a bottom surface of the interlayer dielectric structure 706.

[0105] In some embodiments, the polarization switching structure 110 is electrically coupled to the second source / drain region 106b of the semiconductor device 702 via a plurality of conductive lines 402, a plurality of conductive vias 404, and a plurality of conductive contacts 124 disposed in the lower interlayer dielectric structure 704. A fourth of the plurality of conductive lines 402 is denoted as 402pl and may be referred to as a plateline. In further embodiments, the plateline is electrically coupled to the polarization switching structure 110 via a plurality of conductive lines 402 and / or conductive vias 404 disposed in the upper interlayer dielectric structure 708. In yet further embodiments, one of the plurality of conductive vias 404 (or conductive lines 402) disposed in the lower interlayer dielectric structure 704 may contact the first conductive structure 112, and one of the plurality of conductive vias 404 (or conductive lines 402) disposed in the upper interlayer dielectric structure 708 may contact the second conductive structure 116.

[0106] The first conductive structure 112 has an overall negative charge, which is greater than or equal to the overall negative charge of the ferroelectric structure 114. The second conductive structure 116 has an overall negative charge, which is greater than or equal to the overall negative charge of the ferroelectric structure 114. More specifically, both the overall negative charge of the first conductive structure 112 and the overall negative charge of the second conductive structure 116 are greater than or equal to the overall negative charge of the ferroelectric structure 114.

[0107] Because the overall negativity of the first conductive structure 112 and the overall negativity of the second conductive structure 116 are greater than or equal to the overall negativity of the ferroelectric structure 114, the memory window of the second non-wake-up ferroelectric memory device 101b may not degrade to an unsatisfactory condition after power is removed from the polarization switching structure 110. In other words, the second non-wake-up ferroelectric memory device 101b does not require a wake-up procedure to improve the memory window of the second non-wake-up ferroelectric memory device 101b for normal operation (e.g., reading, writing, erasing). Accordingly, compared to a non-wake-up ferroelectric memory, the second non-wake-up ferroelectric memory 101b may consume less power and / or the second integrated chip 700 may include a greater number (greater density) of second non-wake-up ferroelectric memory devices 101b.

[0108] Figure 8 Draw Figure 7 FIG. 7 is a cross-sectional view of some other embodiments of the second integrated chip 700 .

[0109] like Figure 8 As shown, some of the plurality of conductive lines 402 , the plurality of conductive vias 404 , and the plurality of conductive contacts 124 disposed in the lower interlayer dielectric structure 704 electrically couple the second wake-up-free ferroelectric memory device 101 b to the gate electrode 118 of the semiconductor device 702 .

[0110] Fig. 9 Draw Figure 7 FIG. 7 is a cross-sectional view of some other embodiments of the second integrated chip 700 .

[0111] like Fig. 9 As shown, the first electrode 902 and the second electrode 904 are disposed on opposite sides of the polarization switching structure 110. In some embodiments, the first electrode 902 and / or the second electrode 904 are disposed in the middle interlayer dielectric structure 706. In other embodiments, the first electrode 902 is disposed in the lower interlayer dielectric structure 704, and / or the second electrode 904 is disposed in the upper interlayer dielectric structure 708.

[0112] The first electrode 902 contacts the first conductive structure 112 and is disposed between the first conductive structure 112 and the semiconductor substrate 102. The second electrode 904 contacts the second conductive structure 116, and the polarization switching structure 110 is disposed between the second electrode 904 and the semiconductor substrate 102. In some embodiments, one of the plurality of conductive vias 404 (or conductive lines 402) disposed in the lower interlayer dielectric structure 704 may contact the first electrode 902, and one of the plurality of conductive vias 404 (or conductive lines 402) disposed in the upper interlayer dielectric structure 708 may contact the second electrode 904. In further embodiments, the first electrode 902 may include, for example, Al, Ti, Ta, Au, Pt, W, Ni, Ir, TiN, TaN, some other conductive material, or a combination thereof. In yet further embodiments, the second electrode 904 may include, for example, Al, Ti, Ta, Au, Pt, W, Ni, Ir, TiN, TaN, some other conductive material, or a combination thereof.

[0113] In some embodiments, the first electrode 902 and the second electrode 904 may have the same chemical composition. In other embodiments, the chemical composition of the first electrode 902 may be different from the chemical composition of the second electrode 904. The overall electronegativity of the first conductive structure 112 may be greater than or equal to the overall electronegativity of the first electrode 902. In further embodiments, the overall electronegativity of the second conductive structure 116 may be greater than or equal to the overall electronegativity of the second electrode 904.

[0114] In some embodiments, the sidewalls of the first electrode 902, the sidewalls of the first conductive structure 112, the sidewalls of the ferroelectric structure 114, the sidewalls of the second conductive structure 116, and the sidewalls of the second electrode 904 may be substantially aligned in a vertical direction. In such embodiments, the area (e.g., length (span)) of the first electrode 902 Figure 2 of pages) multiplied by the width (in and out Figure 2), the area of ​​the first conductive structure 112, the area of ​​the ferroelectric structure 114, the area of ​​the second conductive structure 116, and the area of ​​the second electrode 904 may be substantially the same. In other embodiments, the sidewalls of the first conductive structure 112 may be disposed between the sidewalls of the first electrode 902, the sidewalls of the ferroelectric structure 114 may be disposed between the sidewalls of the first conductive structure 112, the sidewalls of the second conductive structure 116 may be disposed between the sidewalls of the ferroelectric structure 114, and / or the sidewalls of the second electrode 904 may be disposed between the sidewalls of the second conductive structure 116. In such an embodiment, the area of ​​the first conductive structure 112 may be smaller than the area of ​​the first electrode 902, the area of ​​the ferroelectric structure may be smaller than the area of ​​the first conductive structure 112, the area of ​​the second conductive structure 116 may be smaller than the area of ​​the ferroelectric structure 114, and / or the area of ​​the second electrode 904 may be smaller than the area of ​​the second conductive structure 116.

[0115] Fig.10 Draw Fig. 9 FIG. 7 is a cross-sectional view of some other embodiments of the second integrated chip 700 .

[0116] like Fig.10 As shown, some of the plurality of conductive lines 402 , the plurality of conductive vias 404 , and the plurality of conductive contacts 124 disposed in the lower interlayer dielectric structure 704 electrically couple the second wake-up-free ferroelectric memory device 101 b to the gate electrode 118 of the semiconductor device 702 .

[0117] Figures 11 to 20 Drawing for forming Figure 5 FIG. 1 is a series of cross-sectional views of some embodiments of a first integrated chip 100 .

[0118] like Fig.11 As shown, the isolation structure 104 is formed within the semiconductor substrate 102. In some embodiments, the isolation structure 104 may be formed by selectively etching the semiconductor substrate 102 to form a trench in the semiconductor substrate 102, and then filling the trench with a dielectric material. In further embodiments, the semiconductor substrate 102 may be selectively etched by forming a masking layer (not shown) over the semiconductor substrate 102, and then exposing the semiconductor substrate 102 to an etchant, which is used to selectively remove unmasked portions of the semiconductor substrate 102. In still further embodiments, the dielectric material may include an oxide (e.g., SiO 2 ), nitride, carbide, or the like.

[0119] like Fig.12As shown, dielectric layer 1202, first conductive layer 1204, ferroelectric layer 1206, second conductive layer 1208, and handle layer 1210 are formed over isolation structure 104 and semiconductor substrate 102. In some embodiments, dielectric layer 1202 is formed on semiconductor substrate 102 and isolation structure 104. First conductive layer 1204 may be formed on dielectric layer 1202. Ferroelectric layer 1206 is formed on first conductive layer 1204. Second conductive layer 1208 is formed on ferroelectric layer 1206. Handle layer 1210 may be formed on second conductive layer 1208.

[0120] In some embodiments, the process for forming the dielectric layer 1202 includes depositing or growing the dielectric layer 1202 on the semiconductor substrate 102. In further embodiments, the dielectric layer 1202 may include, for example, an oxide (e.g., SiO 2 ), high dielectric constant dielectric materials (e.g., HfO 2 、ZrO 2 , or some other dielectric material having a dielectric constant greater than about 3.9), some other dielectric material, or a combination thereof. In still further embodiments, the dielectric layer 1202 may be deposited or grown by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or some other deposition or growth process.

[0121] In some embodiments, the process for forming the first conductive layer 1204 includes depositing or growing the first conductive layer 1204 on the dielectric layer 1202. In further embodiments, the first conductive layer 1204 may include, for example, a metal (e.g., Al, Ti, Ta, Au, Pt, W, Ni, Ir, etc.), a metal nitride (e.g., TiN, TaN, etc.), a metal oxide (e.g., IrO 2 ), doped polysilicon (e.g., N-type / P-type polysilicon), or the like. In yet further embodiments, the first conductive layer 1204 may be deposited or grown by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), epitaxy, sol-gel, sputtering, electroplating, chemical plating, or some other deposition or growth process.

[0122] In some embodiments, the process for forming the ferroelectric layer 1206 includes depositing or growing the ferroelectric layer 1206 on the first conductive layer 1204. In further embodiments, the ferroelectric layer 1206 may include, for example, a metal oxide (e.g., Hf X O Y ), metal oxide components (e.g., Hf X Si Y OZ , Hf X Al Y O Z , Hf X G Y O Z , Hf X Zr Y O Z , Hf X La Y O Z , Hf X Sr Y O Z , Hf X Y Y O Z , STO, etc.), metal oxynitrides (e.g., Hf X O Y N Z ), or the like. In yet further embodiments, the ferroelectric layer 1206 may be deposited or grown by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), epitaxy, sol-gel, sputtering, electroplating, chemical plating, or some other deposition or growth process.

[0123] In some embodiments, the process for forming the second conductive layer 1208 includes depositing or growing the second conductive layer 1208 on the ferroelectric layer 1206. In further embodiments, the second conductive layer 1208 may include, for example, a metal (e.g., Al, Ti, Ta, Au, Pt, W, Ni, Ir, etc.), a metal nitride (e.g., TiN, TaN, etc.), a metal oxide (e.g., IrO2), doped polysilicon (e.g., N-type / P-type polysilicon), or the like. In still further embodiments, the second conductive layer 1208 may be deposited or grown by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), epitaxy, sol-gel, sputtering, electroplating, chemical plating, or some other deposition or growth process.

[0124] In some embodiments, the process for forming the treatment layer 1210 includes depositing or growing the treatment layer 1210 on the second conductive layer 1208. In further embodiments, the treatment layer 1210 may include, for example, polysilicon (doped or undoped), an oxide (e.g., SiO 2 ), or some other material that can be selectively etched with respect to the second conductive layer 1208. In still further embodiments, the treatment layer 1210 can be deposited or grown by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), epitaxy, sputtering, or some other deposition or growth process.

[0125] The first conductive layer 1204 has an overall negative charge, which is greater than or equal to the overall negative charge of the ferroelectric layer 1206. The second conductive layer 1208 has an overall negative charge, which is greater than or equal to the overall negative charge of the ferroelectric layer 1206. More specifically, both the overall negative charge of the first conductive layer 1204 and the overall negative charge of the second conductive layer 1208 are greater than or equal to the overall negative charge of the ferroelectric layer 1206.

[0126] In some embodiments, the overall electronegativity of the first conductive layer 1204 is greater than or equal to the overall electronegativity of the dielectric layer 1202. The overall electronegativity of the dielectric layer 1202 may be greater than or equal to the overall electronegativity of the ferroelectric structure 114. The first conductive layer 1204 and the second conductive layer 1208 may have the same chemical composition. In other embodiments, the chemical composition of the first conductive layer 1204 may be different from the chemical composition of the second conductive layer 1208.

[0127] In some embodiments, the first conductive layer 1204 is formed as a conformal layer having a thickness between about 0.1 nanometers (nm) and about 1,000 nanometers (nm). The ferroelectric layer 1206 may be formed as a conformal layer having a thickness between about 1 nanometer (nm) and about 100 nanometers (nm). In further embodiments, the second conductive layer 1208 may be formed as a conformal layer having a thickness between about 0.1 nanometers (nm) and about 1,000 nanometers (nm). The combined thickness of the first conductive layer 1204, the ferroelectric layer 1206, and the second conductive layer 1208 may be between about 1.2 nanometers (nm) and about 2,100 nanometers (nm). In yet further embodiments, the dielectric layer 1202 is formed as a conformal layer having a thickness between about 1 / 100 and about 1 / 1 of the combined thickness of the first conductive layer 1204, the ferroelectric layer 1206, and the second conductive layer 1208.

[0128] like Fig.13 As shown, a dielectric layer 1202, a first conductive layer 1204, a ferroelectric layer 1206, a second conductive layer 1208, and a handle layer 1210 (eg, see Fig.12 ) is patterned into an initial gate stack 1302. The initial gate stack 1302 includes a polarization switching structure 110 disposed between the gate dielectric 108 and the sacrificial gate 1304. The polarization switching structure 110 includes a ferroelectric structure 114 disposed between the first conductive structure 112 and the second conductive structure 116.

[0129] In some embodiments, the process for forming the initial gate stack 1302 includes forming a patterned masking layer 1306 (e.g., positive / negative photoresist) above / on the handling layer 1210. The patterned masking layer 1306 may be formed by a spin coating process and patterned using lithography. Thereafter, with the patterned masking layer 1306 in place, etching (e.g., wet / dry etching) is performed on the handling layer 1210, the second conductive layer 1208, the ferroelectric layer 1206, the first conductive layer 1204, and the dielectric layer 1202. The etching step removes unmasked portions of the handling layer 1210, the second conductive layer 1208, the ferroelectric layer 1206, the first conductive layer 1204, and the dielectric layer 1202, thereby forming the sacrificial gate 1304, the second conductive structure 116, the ferroelectric structure 114, the first conductive structure 112, and the gate dielectric 108, respectively. Subsequently, the patterned masking layer 1306 may be stripped off.

[0130] In some embodiments, the initial gate stack 1302 may be formed by a single patterning process. In other embodiments, the initial gate stack 1302 may be formed by multiple patterning processes, where each process patterns one (or a combination) of the handle layer 1210, the second conductive layer 1208, the ferroelectric layer 1206, the first conductive layer 1204, and the dielectric layer 1202. It should be understood that in some embodiments, one (or a combination) of the first conductive layer 1204, the ferroelectric layer 1206, the second conductive layer 1208, and the handle layer 1210 may be patterned before subsequently forming a layer thereon. For example, the dielectric layer 1202 may be deposited and then patterned into the gate dielectric 108, and then the first conductive layer 1204 is formed on the gate dielectric 108.

[0131] like Fig.14 As shown, a pair of lightly doped source / drain extensions (LDD) 504a-504b are formed in the semiconductor substrate 102. The lightly doped source / drain extensions (LDD) 504a-504b are formed on opposite sides of the initial gate stack 1302. In some embodiments, the lightly doped source / drain extensions (LDD) 504a-504b are formed by an ion implantation process, and a masking layer (not shown) may be used to selectively implant ions in the semiconductor substrate 102. In further embodiments, the initial gate stack 1302 may be used as a masking layer to form the lightly doped source / drain extensions (LDD) 504a-504b.

[0132] like Fig.15As shown, sidewall spacers 502 are formed over semiconductor substrate 102 and along the sides of initial gate stack 1302. In some embodiments, sidewall spacers 502 may be formed by depositing a spacer layer (not shown) over semiconductor substrate 102 and initial gate stack 1302. In further embodiments, the spacer layer may include nitride (e.g., SiN), oxynitride (e.g., SiO X N Y ), or the like. The spacer layer may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, or some other deposition process. The spacer layer is then etched to remove the spacer layer from the horizontal plane, thereby leaving the spacer layer as sidewall spacers 502 along the sides of the initial gate stack 1302. In yet further embodiments, the sidewall spacers 502 may be formed prior to forming the lightly doped source / drain extensions (LDD) 504a-504b. In such an embodiment, the lightly doped source / drain extensions (LDD) 504a-504b may be formed using an angled ion implantation process.

[0133] like Fig.16 As shown, a pair of source / drain regions 106a-106b are formed in the semiconductor substrate 102. The source / drain regions 106a-106b are formed on opposite sides of the sidewall spacer 502. In some embodiments, the source / drain regions 106a-106b are formed by an ion implantation process, and a masking layer (not shown) may be used to selectively implant ions into the semiconductor substrate 102. In further embodiments, the initial gate stack 1302 and the sidewall spacer 502 may be used as a masking layer to form the source / drain regions 106a-106b.

[0134] like Fig.17 As shown, a first interlayer dielectric (ILD) structure 122a is formed over the semiconductor substrate 102 and the isolation structure 104. The first interlayer dielectric structure 122a can be formed to have a substantially flat upper surface that is coplanar with the upper surface of the sidewall spacer 502. In some embodiments, the process for forming the first interlayer dielectric structure 122a includes forming a first interlayer dielectric structure 122a on the semiconductor substrate 102, the isolation structure 104, the sidewall spacer 502, and the sacrificial gate 1304 (e.g., see Fig.16) is deposited on the first interlayer dielectric structure 122a. The interlayer dielectric layer may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or some other deposition process. Thereafter, a planarization process (e.g., chemical-mechanical planarization (CMP)) may be performed on the interlayer dielectric layer to form a first interlayer dielectric structure 122a.

[0135] like Fig.17 As shown in FIG. 1 , sacrificial gate 1304 is removed (eg, see Fig.16 ), thereby forming an opening 1702 defined by the inner sidewalls of the sidewall spacers 502 and the upper surface of the second conductive structure 116. In some embodiments, the process for removing the sacrificial gate 1304 includes performing an etch (e.g., a dry or wet etch) to selectively remove the sacrificial gate 1304. In further embodiments, prior to etching, a masking layer (not shown) may be formed to cover the first ILD structure 122a and the sidewall spacers 502 while leaving the sacrificial gate 1304 exposed. Thereafter, etching is performed with the masking layer in place to selectively remove the sacrificial gate 1304. Subsequently, the masking layer may be stripped off.

[0136] like Fig.18 As shown, a gate electrode layer 1802 is formed, which fills the opening 1702 and is above the second conductive structure 116, the sidewall spacer 502, and the first interlayer dielectric structure 122a. The gate electrode layer 1802 is conductive and may include, for example, metal W, Al, Ti, Mo, or the like. In some embodiments, the gate electrode layer 1802 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, electroplating, chemical plating, or some other deposition process.

[0137] In some embodiments, prior to forming the gate electrode layer 1802, a capping layer (not shown) may be formed that lines the opening 1702 and is above the second conductive structure 116, the sidewall spacers 502, and the first interlayer dielectric structure 122a. In such embodiments, the gate electrode layer 1802 may be formed on the capping layer. The capping layer may include, for example, TiN, TaN, or the like. In further embodiments, the capping layer may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or some other deposition process. In yet further embodiments, the gate electrode layer 1802 and / or the capping layer have an overall negative charge that is less than the overall negative charge of the ferroelectric structure 114.

[0138] like Fig.19As shown, the gate electrode 118 is formed on the second conductive structure 116 and between the inner sidewalls of the sidewall spacers 502. In some embodiments, the process for forming the gate electrode 118 includes: Fig.18 ) performs a planarization process (e.g., CMP). The planarization process removes the upper portion of the gate electrode layer 1802, thereby forming the gate electrode 118. In a further embodiment, after forming the gate electrode 118, the formation of the device gate stack 120 is completed, which can also complete the formation of the first wake-up-free ferroelectric memory device 101a. In a further embodiment, the process of forming the device gate stack 120 can be referred to as a gate-last high-k / metal gate (HKMG) process.

[0139] It should be understood that in some embodiments, the device gate stack 120 may be formed by other processes. For example, the device gate stack 120 may be formed by a gate-first HKMG process (e.g., forming a metal gate electrode before source / drain formation), a fully silicided (FUSI) metal gate process (e.g., fully silicided polysilicon gate), or a doped polysilicon gate process (e.g., self-aligned polysilicon gate process). Depending on the process used to form the device gate stack 120, the process layer may include, for example, doped polysilicon (e.g., N-type / P-type polysilicon), undoped polysilicon, metal (e.g., W, Al, Ti, Mo, or the like), metal nitride (e.g., TiN, TaN, or the like), some other conductive material, or a combination thereof.

[0140] like Fig. 20 As shown, a second interlayer dielectric structure 122b, a plurality of conductive contacts 124, a plurality of conductive lines 402, and a plurality of conductive vias 404 are formed above the first interlayer dielectric structure 122a and the first wake-up-free ferroelectric memory device 101a. The second interlayer dielectric structure 122b may be formed to have a substantially flat upper surface. In some embodiments, the process for forming the second interlayer dielectric structure 122b includes depositing a plurality of interlayer dielectric layers over the first interlayer dielectric structure 122a and the first wake-up-free ferroelectric memory device 101a, the interlayer dielectric layers being stacked on top of each other. The interlayer dielectric layers may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or some other deposition process. In further embodiments, a planarization process (e.g., a chemical mechanical planarization process (CMP)) may be performed on one or more of the plurality of interlayer dielectric layers.

[0141] In some embodiments, a process for forming a plurality of conductive contacts 124 includes forming a first interlayer dielectric layer on the first interlayer dielectric structure 122a, the sidewall spacers 502, and the gate electrode 118. Thereafter, the first interlayer dielectric layer and the first interlayer dielectric structure 122a are selectively etched to form contact openings (not shown), the contact openings corresponding to the plurality of conductive contacts 124. A conductive material (e.g., W) is then deposited on the first interlayer dielectric layer and fills the contact openings. Subsequently, a planarization process (e.g., chemical mechanical planarization (CMP)) is performed on the conductive material and the first interlayer dielectric layer to form a plurality of conductive contacts 124 extending through the first interlayer dielectric structure 122a. In further embodiments, the conductive material may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, electroplating, electroless plating, or some other deposition process.

[0142] In some embodiments, the process for forming the plurality of conductive lines 402 and the plurality of conductive vias 404 includes forming a second interlayer dielectric layer over the plurality of conductive contacts 124 and the first interlayer dielectric layer. The second interlayer dielectric layer is selectively etched to form a first set of conductive line openings (not shown), which correspond to the first set of conductive lines of the plurality of conductive lines 402. A conductive material (e.g., Cu) is deposited on the second interlayer dielectric layer and fills the first set of conductive line openings. A planarization process (e.g., chemical mechanical planarization (CMP)) is performed on the conductive material and the second interlayer dielectric layer to form the first set of conductive lines.

[0143] Thereafter, a third interlayer dielectric layer is formed over the first set of conductive lines and the second interlayer dielectric layer. The third interlayer dielectric layer is selectively etched to form a first set of conductive via openings (not shown), which correspond to the first set of conductive vias of the plurality of conductive vias 404. A conductive material (e.g., Cu) is deposited on the third interlayer dielectric layer and fills the first set of conductive via openings. A planarization process (e.g., CMP) is performed on the conductive material and the third interlayer dielectric layer to form the first set of conductive vias. This process is repeated (e.g., alternately forming conductive lines and vias) until a plurality of conductive lines 402 and a plurality of conductive vias 404 are formed.

[0144] although Figures 11 to 20 Drawing for forming Figure 5 However, it should be understood that in some embodiments, the first integrated chip 100 can be formed by a substantially similar process. Fig.10For example, the first electrode 902 and the second electrode 904 can be formed by one (some) processes, which are substantially similar to the above-mentioned processes for forming a plurality of conductive contacts 124, a plurality of conductive lines 402, and / or a plurality of conductive vias 404 (e.g., see Fig. 20 ) described in the process. In addition, the second conductive structure 116, the ferroelectric structure 114, and the first conductive structure 112 of the second integrated chip 700 can be formed by one (some) processes, which are substantially similar to the above-mentioned processes for forming the second conductive structure 116, the ferroelectric structure 114, and / or the first conductive structure 112 (for example, see Figure 12 to Figure 13 ) described in the process. In addition, the lower interlayer dielectric structure 704, the middle interlayer dielectric structure 706, and / or the upper interlayer dielectric structure 708 may be formed by one (some) processes that are substantially similar to the above-mentioned processes for forming the first interlayer dielectric structure 122a and / or the second interlayer dielectric structure 122b (for example, see Fig.17 and Fig. 20 ) described in the process.

[0145] Fig.21 A flowchart 2100 is shown of some embodiments of a method for forming an integrated chip (IC) including a front-end non-wake-up ferroelectric memory device. The front-end non-wake-up ferroelectric memory device may be the first non-wake-up ferroelectric memory device 101a. Fig.21 The flowchart 2100 is depicted and described as a series of actions or events, but it should be understood that the order of such actions or events should not be interpreted as limiting. For example, in addition to those illustrated and / or described herein, some actions can be performed in a different order from other actions and / or synchronously with other actions. In addition, not all of the actions shown may be necessary to implement one or more aspects or embodiments described herein, and one or more actions depicted herein may be performed in one or more separate actions and / or stages.

[0146] At act 2102, an initial gate stack including a polarization switch between a sacrificial gate and a gate dielectric is formed over a semiconductor substrate. The polarization switch structure includes a ferroelectric structure between a first conductive structure and a second conductive structure, wherein both an overall electronegativity of the first conductive structure and an overall electronegativity of the second conductive structure are greater than or equal to an overall electronegativity of the ferroelectric structure. Figures 11 to 13 A series of cross-sectional views corresponding to some implementations of act 2102 are depicted.

[0147] At act 2104, lightly doped source / drain extensions are formed in the semiconductor substrate and on opposite sides of the initial gate stack. Fig.14 A cross-sectional view corresponding to some implementations of act 2104 is depicted.

[0148] At activity 2106, sidewall spacers are formed over the semiconductor substrate and along sidewalls of the initial gate stack. Fig.15 A cross-sectional view corresponding to some implementations of act 2106 is depicted.

[0149] At activity 2108, source / drain regions are formed in the semiconductor substrate and on opposite sides of the sidewall spacers. Fig.16 A cross-sectional view corresponding to some implementations of act 2108 is depicted.

[0150] At act 2110, the sacrificial gate is removed, thereby forming an opening. Fig.17 Cross-sectional views corresponding to some implementations of act 2110 are depicted.

[0151] At activity 2112, a gate electrode is formed in the opening, thereby forming a device gate stack. Figure 18 to Figure 19 A series of cross-sectional views corresponding to some implementations of act 2112 are depicted.

[0152] At act 2114, an interconnect structure is formed over the semiconductor substrate and the device gate stack. Fig. 20 Cross-sectional views corresponding to some implementations of act 2114 are depicted.

[0153] Fig. 22 A flowchart 2200 is shown of some embodiments of a method for forming an integrated chip (IC) including a back-end no-wake-up ferroelectric memory device. The back-end no-wake-up ferroelectric memory device may be the second no-wake-up ferroelectric memory device 101b. Fig. 22 Flowchart 2200 is depicted and described as a series of actions or events, but it should be understood that the order in which such actions or events are shown should not be interpreted as limiting. For example, some actions may be performed in a different order than other actions and / or synchronously with other actions, in addition to those illustrated and / or described herein. In addition, not all illustrated actions are necessary to implement one or more aspects or embodiments described herein, and one or more of the actions depicted herein may be performed in one or more separate actions and / or stages.

[0154] In act 2202, a front-end semiconductor device is formed on a semiconductor substrate.

[0155] In some embodiments, the front-end semiconductor device may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or any other front-end semiconductor device. In some embodiments, the front-end semiconductor device may be formed by a process substantially similar to that described above with respect to forming the first wake-up-free ferroelectric memory device 101a (e.g., see Figures 11 to 19 For example, the process forms the isolation structure 104, the gate dielectric 108, the lightly doped source / drain extensions 504a-504b, the sidewall spacers 502, the source / drain regions 106a-106b, and / or the gate electrode 118.

[0156] At act 2204, a first portion of an interconnect structure is formed over a front-end semiconductor device and a semiconductor substrate, wherein the first portion of the interconnect structure includes a first plurality of conductive features disposed in an underlying inter-layer dielectric (ILD) structure.

[0157] In some embodiments, the first plurality of conductive features may be substantially similar to one or more of the plurality of conductive contacts 124, the plurality of conductive lines 402, and / or the plurality of conductive vias 404. In further embodiments, the lower interlayer dielectric structure may be substantially similar to a portion of the interlayer dielectric structure 122. In still further embodiments, the first portion of the interconnect structure may be formed by a process substantially similar to that described above with respect to forming the first interlayer dielectric structure 122a, the second interlayer dielectric structure 122b, the plurality of conductive contacts 124, the plurality of conductive lines 402, and / or the plurality of conductive vias 404 (e.g., see Fig.17 and / or Fig. 20 ) described in the process.

[0158] In action 2206, a polarization switching structure including a ferroelectric structure is formed above a first portion of an interconnect structure between a first conductive structure and a second conductive structure, wherein both an overall negative charge of the first conductive structure and an overall negative charge of the second conductive structure are greater than or equal to an overall negative charge of the ferroelectric structure, and wherein the first portion of the interconnect structure electrically couples the polarization switching structure to a front-end semiconductor device.

[0159] In some embodiments, the polarization switching structure 110 may be formed over a portion of the interconnect structure by a process substantially similar to that described above with respect to forming the first wake-up-free ferroelectric memory device 101a (eg, see Figures 11 to 13 ) of the polarization switching structure 110. For example, the process forms the first conductive structure 112, the ferroelectric structure 114, and / or the second conductive structure 116.

[0160] At act 2208, an intermediate interlayer dielectric structure is formed over the first portion of the interconnect structure and around the polarization switching structure.

[0161] In some embodiments, the intermediate interlayer dielectric structure may be substantially similar to a portion of the interlayer dielectric structure 122. In further embodiments, the intermediate interlayer dielectric structure may be formed by a process substantially similar to that described above with respect to forming the first interlayer dielectric structure 122a and / or the second interlayer dielectric structure 122b (e.g., see Fig.17 and / or Fig. 20 ) described in the process.

[0162] At act 2210, a second portion of the interconnect structure is formed over the intermediate ILD structure and the polarization switching structure, wherein the second portion of the interconnect structure includes a second plurality of conductive features disposed in the upper interlayer dielectric structure.

[0163] In some embodiments, the second plurality of conductive features may be substantially similar to one or more of the plurality of conductive contacts 124, the plurality of conductive lines 402, and / or the plurality of conductive vias 404. In further embodiments, the upper interlayer dielectric structure may be substantially similar to a portion of the interlayer dielectric structure 122. In further embodiments, the second portion of the interconnect structure may be formed by a process substantially similar to that described above with respect to forming the first interlayer dielectric structure 122a, the second interlayer dielectric structure 122b, the plurality of conductive contacts 124, the plurality of conductive lines 402, and / or the plurality of conductive vias 404 (e.g., see Fig.17 and / or Fig. 20 ) described in the process.

[0164] In some embodiments, the present application provides a ferroelectric memory device. The ferroelectric memory device includes a pair of source / drain regions disposed in a semiconductor substrate. A gate dielectric is disposed above the semiconductor substrate and between the source / drain regions. A first conductive structure is disposed on the gate dielectric. A first ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, wherein both the first conductive structure and the second conductive structure have an overall negative charge, and the overall negative charge is greater than or equal to the overall negative charge of the ferroelectric structure.

[0165] In some embodiments, the present application provides an integrated chip (IC). The integrated chip includes a semiconductor device disposed on a semiconductor substrate. A first interlayer dielectric (ILD) structure is disposed above the semiconductor device and the semiconductor substrate. A first conductive via is disposed in the first interlayer dielectric structure and is electrically coupled to the semiconductor device. A polarization switching structure is disposed above the first interlayer dielectric structure and is electrically coupled to the first conductive via, wherein the polarization switching structure includes a ferroelectric structure disposed between the first conductive structure and the second conductive structure, and wherein both the first conductive structure and the second conductive structure have an overall negative charge, and the overall negative charge is greater than or equal to the overall negative charge of the ferroelectric structure.

[0166] In some embodiments, the present application provides a method for forming a ferroelectric memory device. The method includes the following steps: forming a dielectric layer above a semiconductor substrate. A first conductive layer is formed above the dielectric layer, wherein the first conductive layer has a first overall negative charge. A ferroelectric layer is formed on the first conductive layer, wherein the ferroelectric layer has a second overall negative charge that is less than or equal to the first overall negative charge. A second conductive layer is formed on the ferroelectric layer, wherein the second conductive layer has a third overall negative charge that is greater than or equal to the second negative charge. Etching the second conductive layer, the ferroelectric layer, and the first conductive layer to form a polarization switching structure above the semiconductor substrate. A first conductive via is formed above the polarization switching structure and is electrically coupled to the polarization switching structure.

[0167] Some embodiments of the present disclosure provide a ferroelectric memory device comprising: a pair of source / drain regions, a gate dielectric, a first conductive structure, a ferroelectric structure, and a second conductive structure. The pair of source / drain regions are disposed in a semiconductor substrate. The gate dielectric is disposed above the semiconductor substrate and between the source / drain regions. The first conductive structure is disposed on the gate dielectric. The ferroelectric structure is disposed on the first conductive structure. The second conductive structure is disposed on the ferroelectric structure, wherein both the first conductive structure and the second conductive structure have an overall negative charge, and the overall negative charge is greater than or equal to the overall negative charge of the ferroelectric structure.

[0168] In some embodiments, the ferroelectric memory device further includes a gate electrode disposed on the second conductive structure.

[0169] In some embodiments, in the ferroelectric memory device, the gate electrode has an overall negative charge that is less than or equal to an overall negative charge of the second conductive structure.

[0170] In some embodiments, in the ferroelectric memory device, the overall electronegativity of the first conductive structure is the same as the overall electronegativity of the second conductive structure.

[0171] In some embodiments, in a ferroelectric memory device: the relative outermost walls of the first conductive structure are spaced apart by a first distance; the relative outermost walls of the ferroelectric structure are spaced apart by a second distance, and the second distance is substantially the same as the first distance; and the relative outermost walls of the second conductive structure are spaced apart by a third distance, and the third distance is substantially the same as the second distance.

[0172] In some embodiments, in a ferroelectric memory device: the second conductive structure has a first thickness, the first thickness is between about 0.1 nanometers (nm) and about 1000 nanometers; the first conductive structure has a second thickness, the second thickness is between about 0.1 nanometers and about 1000 nanometers; and the ferroelectric structure has a third thickness, the third thickness is between about 0.1 nanometers and about 1000 nanometers.

[0173] In some embodiments, in a ferroelectric memory device, the ferroelectric structure comprises a metal-based oxide.

[0174] In some embodiments, in the ferroelectric memory device, a distance between a bottom surface of the first conductive structure and an upper surface of the second conductive structure is greater than or equal to a distance between an upper surface of the gate dielectric and a bottom surface of the gate dielectric.

[0175] Some embodiments of the present disclosure provide an integrated chip comprising: a semiconductor device, a first interlayer dielectric (ILD) structure, a first conductive via, and a polarization switching structure. The semiconductor device is disposed on a semiconductor substrate. The first interlayer dielectric (ILD) structure is disposed above the semiconductor device and the semiconductor substrate. The first conductive via is disposed in the first interlayer dielectric structure and is electrically coupled to the semiconductor device. The polarization switching structure is disposed above the first interlayer dielectric structure and is electrically coupled to the first conductive via, wherein the polarization switching structure comprises a ferroelectric structure disposed between the first conductive structure and the second conductive structure, and wherein both the first conductive structure and the second conductive structure have an overall negative charge, and the overall negative charge is greater than or equal to the overall negative charge of the ferroelectric structure.

[0176] In some embodiments, in the integrated chip, the overall electronegativity of the first conductive via is less than or equal to the overall electronegativity of both the first conductive structure and the second conductive structure.

[0177] In some embodiments, the integrated chip further comprises: a second interlayer dielectric structure, and a second conductive via. The second interlayer dielectric structure is disposed above the polarization switching structure and the first interlayer dielectric structure. The second conductive via is disposed in the second interlayer dielectric structure and electrically coupled to the polarization switching structure, wherein the polarization switching structure separates the first conductive via from the second conductive via, and wherein the overall negative charge of the second conductive via is less than or equal to the overall negative charge of both the first conductive structure and the second conductive structure.

[0178] In some embodiments, the integrated chip further comprises: a first electrode and a second electrode disposed on opposite sides of the polarization switching structure, wherein the first electrode contacts both the first conductive structure and the first conductive via, and wherein the second electrode contacts the second conductive structure.

[0179] In some embodiments, in an integrated chip: the relative outermost walls of the first conductive structure are separated by a first distance; the relative outermost walls of the ferroelectric structure are separated by a second distance, and the second distance is less than or equal to the first distance; and the relative outermost walls of the second conductive structure are separated by a third distance, and the third distance is less than or equal to the second distance.

[0180] In some embodiments, in the integrated chip, opposite sidewalls of the first conductive via are spaced apart by a fourth distance, and the fourth distance is smaller than the third distance.

[0181] In some implementations, in the integrated chip, the first distance, the second distance, and the third distance are substantially the same.

[0182] In some embodiments, in an integrated chip: the semiconductor device includes a pair of source / drain regions and a gate dielectric, the pair of source / drain regions are arranged in a semiconductor substrate, and the gate dielectric is arranged above the semiconductor substrate and between the source / drain regions; the bottom surface of the gate dielectric is spaced apart from the upper surface of the gate dielectric by a first distance; the upper surface of the polarization switching structure is spaced apart from the bottom surface of the polarization switching structure by a second distance; and the ratio between the second distance and the first distance is between 100 and 1.

[0183] In some embodiments, in an integrated chip, a ferroelectric structure comprises a hafnium-based oxide.

[0184] Some embodiments of the present disclosure provide a method for forming a ferroelectric memory device, the method comprising: forming a dielectric layer above a semiconductor substrate; forming a first conductive layer above the dielectric layer, wherein the first conductive layer has a first overall negative charge; forming a ferroelectric layer on the first conductive layer, wherein the ferroelectric layer has a second overall negative charge, the second overall negative charge being less than or equal to the first overall negative charge; forming a second conductive layer on the ferroelectric layer, wherein the second conductive layer has a third overall negative charge, the third overall negative charge being greater than or equal to the second negative charge; etching the second conductive layer, the ferroelectric layer, and the first conductive layer to form a polarization switching structure above the semiconductor substrate; and forming a first conductive via, the first conductive via being above the polarization switching structure and electrically coupled to the polarization switching structure.

[0185] In some embodiments, the method further includes: forming a polysilicon layer on the second conductive layer; etching the polysilicon layer to form a sacrificial gate, the sacrificial gate being disposed on the polarization switching structure; etching the dielectric layer to form a gate dielectric, the gate dielectric being disposed between the polarization switching structure and the semiconductor substrate; forming a pair of source / drain regions in the semiconductor substrate, wherein the source / drain regions of the pair of source / drain regions are disposed on opposite sides of the gate dielectric and on opposite sides of the polarization switching structure; and replacing the sacrificial gate with a metal gate electrode.

[0186] In some embodiments, the method further includes: forming a second conductive via, the second conductive via extending through a dielectric layer, wherein the dielectric layer is a first interlayer dielectric (ILD) layer, and wherein the second conductive via electrically couples the polarization switching structure to a semiconductor device, the semiconductor device being disposed on a semiconductor substrate; forming a second interlayer dielectric layer above the polarization switching structure and the first interlayer dielectric layer; and forming a third conductive via, the third conductive via being above the polarization switching structure and extending through the second interlayer dielectric layer, wherein the third conductive via is electrically coupled to the polarization switching structure, and wherein the polarization switching structure separates the third conductive via from the second conductive via.

[0187] The features or embodiments of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same benefits of the embodiments or embodiments described herein. Those skilled in the art should also recognize that such equal constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and modifications of the present disclosure can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A ferroelectric memory device, characterized in that Include: A pair of source / drain regions are disposed in a semiconductor substrate; a gate dielectric disposed above the semiconductor substrate and between the source / drain regions; a first conductive structure disposed on the gate dielectric; a ferroelectric structure disposed on the first conductive structure; a second conductive structure disposed on the ferroelectric structure, wherein both the first conductive structure and the second conductive structure have an overall negative charge, and the overall negative charge is greater than or equal to an overall negative charge of the ferroelectric structure; a gate electrode disposed on the second conductive structure, wherein sidewalls of the gate dielectric, sidewalls of the first conductive structure, sidewalls of the ferroelectric structure, sidewalls of the second conductive structure, and sidewalls of the gate electrode are aligned in a vertical direction; as well as A sidewall spacer is disposed above the semiconductor substrate and along the sidewall of the gate dielectric, the sidewall of the first conductive structure, the sidewall of the ferroelectric structure, the sidewall of the second conductive structure, and the sidewall of the gate electrode.

2. The ferroelectric memory device according to claim 1, wherein The gate electrode has an overall negative charge, which is less than or equal to the overall negative charge of the second conductive structure.

3. The ferroelectric memory device according to claim 1, wherein The overall negative charge of the first conductive structure is the same as the overall negative charge of the second conductive structure.

4. The ferroelectric memory device according to claim 1, wherein: in: The outermost sidewalls of the first conductive structure are spaced apart by a first distance; The opposite outermost sidewalls of the ferroelectric structure are spaced apart by a second distance, the second distance being the same as the first distance; as well as The opposite outermost sidewalls of the second conductive structure are spaced apart by a third distance, and the third distance is the same as the second distance.

5. The ferroelectric memory device according to claim 4, characterized in that in: The second conductive structure has a first thickness, and the first thickness is between 0.1 nanometers and 1000 nanometers; The first conductive structure has a second thickness, and the second thickness is between 0.1 nanometers and 1000 nanometers; and The ferroelectric structure has a third thickness between 0.1 nanometers and 1000 nanometers.

6. The ferroelectric memory device according to claim 1, wherein The ferroelectric structure includes a metal-based oxide.

7. The ferroelectric memory device according to claim 1, wherein: A distance between a bottom surface of the first conductive structure and an upper surface of the second conductive structure is greater than or equal to a distance between an upper surface of the gate dielectric and a bottom surface of the gate dielectric.

8. An integrated chip, characterized in that: Include: A semiconductor device is disposed on a semiconductor substrate; a first interlayer dielectric structure disposed above the semiconductor device and the semiconductor substrate; a first conductive via disposed in the first interlayer dielectric structure and electrically coupled to the semiconductor device; a polarization switching structure disposed above the first interlayer dielectric structure and electrically coupled to the first conductive via, wherein the polarization switching structure includes a ferroelectric structure disposed between a first conductive structure and a second conductive structure, and wherein both the first conductive structure and the second conductive structure have an overall negative charge that is greater than or equal to an overall negative charge of the ferroelectric structure; a gate electrode disposed on the second conductive structure, wherein the sidewalls of the first conductive structure, the sidewalls of the ferroelectric structure, the sidewalls of the second conductive structure, and the sidewalls of the gate electrode are aligned in a vertical direction; as well as A sidewall spacer is disposed above the semiconductor substrate and along a sidewall of the polarization switching structure and a sidewall of the gate electrode.

9. The integrated chip according to claim 8, characterized in that: The first conductive via has an overall negative charge less than or equal to the overall negative charge of the first conductive structure and the second conductive structure.

10. The integrated chip according to claim 9, characterized in that: Also includes: a second interlayer dielectric structure disposed above the polarization switching structure and the first interlayer dielectric structure; and A second conductive via is disposed in the second interlayer dielectric structure and electrically coupled to the polarization switching structure, wherein the polarization switching structure separates the first conductive via from the second conductive via, and wherein an overall negative charge of the second conductive via is less than or equal to the overall negative charge of both the first conductive structure and the second conductive structure.

11. The integrated chip according to claim 8, characterized in that: Also includes: A first electrode and a second electrode are disposed on opposite sides of the polarization switching structure, wherein the first electrode contacts both the first conductive structure and the first conductive via, and wherein the second electrode contacts the second conductive structure.

12. The integrated chip according to claim 8, characterized in that: in: The outermost sidewalls of the first conductive structure are spaced apart by a first distance; The opposite outermost sidewalls of the ferroelectric structure are spaced apart by a second distance, the second distance being less than or equal to the first distance; as well as The outermost sidewalls of the second conductive structure are spaced apart by a third distance, and the third distance is less than or equal to the second distance.

13. The integrated chip according to claim 12, characterized in that: The opposite side walls of the first conductive via are spaced apart by a fourth distance, and the fourth distance is smaller than the third distance.

14. The integrated chip according to claim 13, characterized in that: The first distance, the second distance, and the third distance are the same.

15. The integrated chip according to claim 8, characterized in that: in: The semiconductor device comprises a pair of source / drain regions and a gate dielectric, the pair of source / drain regions are disposed in the semiconductor substrate, and the gate dielectric is disposed above the semiconductor substrate and between the source / drain regions; A bottom surface of the gate dielectric is spaced apart from an upper surface of the gate dielectric by a first distance; An upper surface of the polarization switching structure is spaced apart from a bottom surface of the polarization switching structure by a second distance; and A ratio between the second distance and the first distance is between 100 and 1.

16. The integrated chip according to claim 8, characterized in that: The ferroelectric structure includes a hafnium-based oxide.

17. A method for forming a ferroelectric memory device, characterized in that The method includes: forming a dielectric layer over a semiconductor substrate; forming a first conductive layer above the dielectric layer, wherein the first conductive layer has a first overall negative charge; Forming a ferroelectric layer on the first conductive layer, wherein the ferroelectric layer has a second overall negative charge, and the second overall negative charge is less than or equal to the first overall negative charge; Forming a second conductive layer on the ferroelectric layer, wherein the second conductive layer has a third overall negative charge, and the third overall negative charge is greater than or equal to the second overall negative charge; etching the second conductive layer, the ferroelectric layer, and the first conductive layer to form a polarization switching structure above the semiconductor substrate; forming a metal gate electrode on the polarization switching structure, wherein the sidewalls of the dielectric layer, the sidewalls of the first conductive layer, the sidewalls of the ferroelectric layer, the sidewalls of the second conductive layer, and the sidewalls of the metal gate electrode are aligned in a vertical direction; forming a sidewall spacer disposed along a sidewall of the dielectric layer, a sidewall of the polarization switching structure, and a sidewall of the metal gate electrode; as well as A first conductive via is formed above the polarization switching structure and electrically coupled to the polarization switching structure.

18. The method according to claim 17, characterized in that Forming the metal gate electrode on the polarization switching structure comprises: forming a polysilicon layer on the second conductive layer; etching the polysilicon layer to form a sacrificial gate, the sacrificial gate being disposed on the polarization switching structure; etching the dielectric layer to form a gate dielectric disposed between the polarization switching structure and the semiconductor substrate; forming a pair of source / drain regions in the semiconductor substrate, wherein the source / drain regions of the pair of source / drain regions are disposed on opposite sides of the gate dielectric and on opposite sides of the polarization switching structure; and The sacrificial gate is replaced with the metal gate electrode.

19. The method according to claim 17, characterized in that Also includes: forming a second conductive via extending through the dielectric layer, wherein the dielectric layer is a first interlayer dielectric layer, and wherein the second conductive via electrically couples the polarization switching structure to a semiconductor device disposed on the semiconductor substrate; forming a second interlayer dielectric layer over the polarization switching structure and the first interlayer dielectric layer; as well as A third conductive via is formed above the polarization switching structure and extending through the second interlayer dielectric layer, wherein the third conductive via is electrically coupled to the polarization switching structure, and wherein the polarization switching structure separates the third conductive via from the second conductive via.

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